Imaging system, imaging method, and computer program

Abstract

To provide an imaging system capable of correcting image quality deterioration caused by noise generated by batch drive control.SOLUTION: An imaging system including a plurality of pixels, each of the pixels including a photoelectric conversion unit configured to generate a charge by photoelectric conversion, two or more charge holding units configured to hold the charge, a transfer unit configured to transfer the charge from the photoelectric conversion unit to the charge holding unit, a charge discharging unit configured to discharge the charge accumulated in the photoelectric conversion unit, and a readout unit configured to read out a signal corresponding to an amount of the charge transferred from the charge holding unit, the imaging system being configured to perform collective drive control of simultaneously driving at least one of the transfer unit and the charge discharging unit for the plurality of pixels, and a control unit configured to perform photoelectric conversion in two or more different exposure periods during one frame period, and perform control such that one of timings at which signals corresponding to the charges accumulated in the respective exposure periods are read out does not overlap a timing of the collective drive control.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an imaging system, an imaging method, a computer program, and the like. [Background technology]

[0002] Among so-called CMOS sensors, there are so-called GS sensors that have a global shutter (hereafter referred to as GS) function by having a memory section in each pixel. That is, each pixel of a GS sensor has a gate that transfers the signal charge accumulated in the photoelectric conversion section to the charge storage section, and by transferring the signal charge from the photoelectric conversion section to the charge storage section simultaneously for all pixels, the timing of starting and ending signal accumulation in the photoelectric conversion section can be made the same for all pixels.

[0003] Furthermore, by providing multiple charge storage units for one photoelectric conversion unit and transferring signal charges to each charge storage unit multiple times during one frame, signal charges of different accumulation periods can be stored in each charge storage unit, enabling images with different dynamic ranges to be acquired. Furthermore, by combining these images, a single image with a high dynamic range can be obtained. Patent Document 1 describes the configuration of such a GS pixel. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2013 / 0135486 [Patent Document 2] Japanese Patent Application Publication No. 2017-55322 Summary of the Invention [Problem to be solved by the invention]

[0005] On the other hand, Patent Document 2 describes a configuration for controlling the exposure period in which pixel signals from multiple rows are read out by transferring charges all at once, and a configuration for performing batch transfer drive for multiple rows and batch reset drive for multiple rows. However, because multiple rows are transferred all at once, there is a possibility that the potential of the batch transfer drive wiring or batch reset drive wiring may change during the readout of pixel signals.

[0006] As a result, potential fluctuations are propagated to, for example, pixel readout lines, power supply lines, etc. due to capacitive coupling between the batch transfer drive wiring or batch reset drive wiring and other wiring, causing noise in the pixel signals of the row being read out at that time, which causes horizontal lines and reduces image quality.

[0007] An object of the present invention is to provide an imaging system capable of correcting degradation in image quality caused by noise generated by collective drive control. [Means for solving the problem]

[0008] An imaging system according to one aspect of the present invention comprises: A plurality of pixels, each pixel having: a photoelectric conversion unit that generates electric charges by photoelectric conversion; two or more charge holding units that hold the charges; a transfer unit that transfers the charges from the photoelectric conversion unit to the charge storage unit; a charge discharging section that discharges the charge accumulated in the photoelectric conversion section; a readout unit that reads out a signal corresponding to the amount of charge transferred from the charge holding unit, The present invention is characterized by having a control unit that performs collective drive control to drive at least one of the transfer unit and the charge discharge unit simultaneously for the plurality of pixels, and performs photoelectric conversion using two or more different exposure periods during one frame period, and controls one of the timings for reading out signals corresponding to the charges accumulated in each exposure period so that it does not overlap with the timing of the collective drive control. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide an imaging system capable of correcting degradation in image quality caused by noise generated by collective drive control. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a circuit block diagram showing an example of a schematic configuration of a photoelectric conversion device according to a first embodiment of the present invention. [Figure 2] 1 is an equivalent circuit diagram showing an example of the configuration of each pixel of a photoelectric conversion device according to a first embodiment of the present invention. [Figure 3] FIG. 3 is a timing chart showing an example of a basic driving method for an exposure period of the photoelectric conversion device according to the first embodiment of the present invention. [Figure 4] FIG. 4 is a timing chart showing an example of a driving method for reading out the photoelectric conversion device according to the first embodiment of the present invention. [Figure 5] FIG. 4 is an equivalent circuit diagram showing an example of the configuration of each pixel of a photoelectric conversion device according to a second embodiment of the present invention. [Figure 6] FIG. 10 is a timing chart showing an example of a driving method for reading out the photoelectric conversion device according to the second embodiment of the present invention. [Figure 7] FIG. 10 is an equivalent circuit diagram showing an example of the configuration of each pixel of a photoelectric conversion device according to a third embodiment of the present invention. [Figure 8] FIG. 10 is a timing chart showing an example of a basic driving method for the exposure time of a photoelectric conversion device according to a third embodiment of the present invention. [Figure 9A] FIG. 10 is a timing chart showing an example of a driving method for reading out a photoelectric conversion device according to a third embodiment of the present invention. [Figure 9B] FIG. 10 is a timing chart showing an example of a driving method for reading out a photoelectric conversion device according to a third embodiment of the present invention. [Figure 10] FIG. 10 is an equivalent circuit diagram showing an example of the configuration of each pixel of a photoelectric conversion device according to a fourth embodiment of the present invention. [Figure 11] FIG. 10 is a timing chart showing an example of a basic driving method for the exposure time of a photoelectric conversion device according to a fourth embodiment of the present invention. [Figure 12]FIG. 10 is a timing chart showing an example of a driving method for reading out a photoelectric conversion device according to a fourth embodiment of the present invention. [Figure 13] FIG. 10 is a timing chart showing an example of a basic driving method for the exposure time of a photoelectric conversion device according to a fifth embodiment of the present invention. [Figure 14] FIG. 10 is a functional block diagram showing an example of a schematic configuration of an imaging system according to a sixth embodiment of the present invention. [Figure 15] FIG. 10 is a functional block diagram showing a detailed configuration example of a signal processing unit of an imaging system according to a sixth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following embodiment. In each drawing, the same members or elements are given the same reference numerals, and duplicated descriptions will be omitted or simplified.

[0012] In the following embodiments, an example will be described in which a CMOS (Complementary Metal Oxide Semiconductor) image sensor is used as the photoelectric conversion device. However, the photoelectric conversion device may also be, for example, a distance measurement device using TOF (Time Of Flight), a photometric device for measuring the amount of incident light, or the like, and includes these.

[0013] <Embodiment 1> A photoelectric conversion device and a driving method thereof according to a first embodiment of the present invention will be described below with reference to Fig. 1 to Fig. 4. Fig. 1 is a circuit block diagram showing an example of the schematic configuration of a photoelectric conversion device according to the first embodiment of the present invention.

[0014] As shown in FIG. 1, the photoelectric conversion device 100 according to this embodiment includes a pixel section 10, a vertical scanning circuit 20, a readout circuit 30, a horizontal scanning circuit 40, an output circuit 50, and a drive control circuit 60.

[0015] The pixel unit 10 is connected to a vertical scanning circuit 20 and a readout circuit 30. The readout circuit 30 is connected to a horizontal scanning circuit 40 and an output circuit 50. The drive control circuit 60 is connected to the vertical scanning circuit 20, the readout circuit 30, and the horizontal scanning circuit 40.

[0016] The pixel section 10 has a plurality of pixels 12 arranged in a matrix to form a plurality of rows and a plurality of columns. Each of the plurality of pixels 12 includes a photoelectric conversion unit made up of a photoelectric conversion element such as a photodiode, and the photoelectric conversion unit generates electric charges through photoelectric conversion, thereby outputting a pixel signal corresponding to the amount of incident light.

[0017] There is no particular limitation on the number of rows and columns of the pixel array arranged in the pixel section 10. In addition to effective pixels that output pixel signals according to the amount of incident light, the pixel section 10 may also include optical black pixels that are light-shielded photoelectric conversion sections and dummy pixels that do not output signals.

[0018] In each column of the pixel section 10, vertical output lines 16 and 17 are arranged, extending in a second direction (vertical direction in FIG. 1) intersecting with a first direction (horizontal direction in FIG. 1, also called a row direction or horizontal direction). Each of the vertical output lines 16 and 17 is connected to a plurality of pixels 12 aligned in the second direction, and serves as a common signal line for these plurality of pixels 12.

[0019] The second direction in which the vertical output lines 16 and the vertical output lines 17 extend is sometimes called the column direction or the vertical direction. The vertical output lines 16 and the vertical output lines 17 are connected to a readout circuit 30. The vertical scanning circuit 20 has a function of receiving a drive control signal from a drive control circuit 60, generating a control signal for driving the pixels 12, and outputting the control signal to the pixel section 10 via the control line 14. The vertical scanning circuit 20 uses logic circuits such as a shift register and an address decoder.

[0020] The vertical scanning circuit 20 sequentially outputs control signals to the control lines 14 of each row, and sequentially drives the plurality of pixels 12 of the pixel section 10 row by row. The signals read out from the plurality of pixels 12 row by row are input to a readout circuit 30 via vertical output lines 16 and 17 arranged in each column of the pixel section 10.

[0021] The readout circuit 30 has a function of performing predetermined processing, such as amplification processing, addition processing, etc., on signals read out from the pixels 12. The readout circuit 30 has a function of performing predetermined processing, such as amplification processing, addition processing, etc., on signals read out from the pixels 12. The readout circuit 30 may further include other processing circuits, such as an A / D (analog / digital) conversion circuit.

[0022] The horizontal scanning circuit 40 has a function of receiving a drive control signal from the drive control circuit 60, generating a control signal for transferring the signals processed by the readout circuit 30 to the output circuit 50 sequentially for each column, and outputting the control signal to the readout circuit 30. The horizontal scanning circuit 40 uses logic circuits such as a shift register and an address decoder.

[0023] The output circuit 50 is a circuit section that is composed of a buffer amplifier, a differential amplifier, etc., and that amplifies and outputs signals of columns selected by the horizontal scanning circuit 40. The output circuit 50 may further include a signal processing section that performs predetermined signal processing on pixel signals, such as correction processing or HDR (High Dynamic Range) synthesis processing. In this embodiment, the output circuit 50 corrects image quality degradation caused by potential fluctuations associated with global electronic shutter operation.

[0024] The drive control circuit 60 supplies drive control signals to the vertical scanning circuit 20, the readout circuit 30, and the horizontal scanning circuit 40 based on the vertical synchronization signal VD and the horizontal synchronization signal HD to control their operations and timings. In other words, it functions as an exposure control unit and a readout control unit for the pixels 12.

[0025] At least some of the drive control signals supplied to the vertical scanning circuit 20, the readout circuit 30, and the horizontal scanning circuit 40 may be supplied from outside the photoelectric conversion device 100. Furthermore, the vertical synchronization signal VD and the horizontal synchronization signal HD may be generated internally or may be supplied externally.

[0026] 2 is an equivalent circuit diagram showing an example of the configuration of each pixel of the photoelectric conversion device according to Embodiment 1 of the present invention. As shown in FIG. 2, each pixel 12 has a photoelectric conversion unit PD, and transfer transistors M1L1, M1S1, M2L1, M2S1, M3L1, and M3S1.

[0027] Each pixel 12 further includes reset transistors M4 and M8, amplification transistors M5 and M9, selection transistors M6 and M10, and a charge drain transistor M7. Here, the charge drain transistor M7 functions as a charge drain unit that drains charges accumulated in the photoelectric conversion unit.

[0028] The photoelectric conversion unit PD is composed of a photoelectric conversion element, for example, a photodiode. When electrons are used as signal charges, each transistor is composed of an N-type MOS transistor. However, each transistor does not necessarily have to be an N-type MOS transistor, and each transistor may be composed of a P-type MOS transistor and holes may be used as signal charges.

[0029] The photoelectric conversion unit PD has an anode connected to the ground node and a cathode connected to the source of the transfer transistor M1L1, the source of the transfer transistor M1S1, and the source of the charge discharging transistor M7.

[0030] The drain of the transfer transistor M1L1 is connected to the source of the transfer transistor M2L1. The connection node between the drain of the transfer transistor M1L1 and the source of the transfer transistor M2L1 includes a capacitance component and functions as a charge holding unit (charge holding unit MEM_L1).

[0031] The drain of the transfer transistor M1S1 is connected to the source of the transfer transistor M2S1. The connection node between the drain of the transfer transistor M1S1 and the source of the transfer transistor M2S1 includes a capacitance component and functions as a charge holding unit (charge holding unit MEM_S1).

[0032] The drain of the transfer transistor M2L1 is connected to the source of the transfer transistor M3L1. The connection node between the drain of the transfer transistor M2L1 and the source of the transfer transistor M3L1 includes a capacitance component and functions as a charge holding unit (charge holding unit MEM_L2).

[0033] The drain of the transfer transistor M2S1 is connected to the source of the transfer transistor M3S1. The connection node between the drain of the transfer transistor M2S1 and the source of the transfer transistor M3S1 includes a capacitance component and functions as a charge holding unit (charge holding unit MEM_S2).

[0034] Here, the charge holding units MEM_L1, MEM_L2, MEM_S1, and MEM_S2 function as four charge holding units that hold charges from the photoelectric conversion units, and the transfer transistors M1L1, M1S1, M2L1, and M2S1 function as transfer units that transfer charges from the photoelectric conversion units to the charge holding units.

[0035] That is, in this embodiment, as shown in FIG. 2, two charge holding units can be connected to the photoelectric conversion unit, and each of the two charge holding units can be connected in series to another charge holding unit.

[0036] The drain of the transfer transistor M3L1 is connected to the source of the reset transistor M4 and the gate of the amplification transistor M5. The connection node between the drain of the transfer transistor M3L1, the source of the reset transistor M4, and the gate of the amplification transistor M5 constitutes a floating diffusion portion FD_L. The floating diffusion portion FD_L includes a capacitance component (floating diffusion capacitance) and functions as a charge storage portion.

[0037] The drain of the transfer transistor M3S1 is connected to the source of the reset transistor M8 and the gate of the amplification transistor M9. The connection node between the drain of the transfer transistor M3S1, the source of the reset transistor M8, and the gate of the amplification transistor M9 constitutes a floating diffusion portion FD_S. The floating diffusion portion FD_S includes a capacitance component (floating diffusion capacitance) and functions as a charge storage portion.

[0038] The drain of the reset transistor M4, the drain of the reset transistor M8, the drain of the amplifying transistor M5, the drain of the amplifying transistor M9, and the drain of the charge discharging transistor M7 are connected to the power supply voltage line (voltage VDD).

[0039] The drain voltages of the reset transistor M4 and the reset transistor M8, the drain voltages of the amplifying transistor M5 and the amplifying transistor M9, and the drain voltage of the charge discharging transistor M7 may be at least partially different.

[0040] The source of the amplification transistor M5 is connected to the drain of the selection transistor M6, and the source of the amplification transistor M9 is connected to the drain of the selection transistor M10. The source of the selection transistor M6 is connected to the vertical output line 16, and the source of the selection transistor M10 is connected to the vertical output line 17.

[0041] Here, the transfer transistor M3L1, the reset transistor M4, the amplification transistor M5, and the selection transistor M6 function as a readout section that reads out a signal according to the amount of charge transferred from the charge holding section.

[0042] The transfer transistor M3S1, reset transistor M8, amplifier transistor M9, and selection transistor M10 also function as a readout unit that reads out a signal corresponding to the amount of charge transferred from the charge storage unit. Note that these readout units perform a readout operation during the exposure operation of the photoelectric conversion unit.

[0043] Each of the control lines 14 includes 11 signal lines, six of which are connected to the transfer transistor M1L1, the transfer transistor M1S1, the transfer transistor M2L1, the transfer transistor M2S1, the transfer transistor M3L1, and the transfer transistor M3S1, respectively.

[0044] The remaining five signal lines are connected to the gates of the reset transistor M4, the reset transistor M8, the selection transistor M6, the selection transistor M10, and the charge discharging transistor M7.

[0045] A signal line connected to the gate of the transfer transistor M1L1 is supplied with a control signal GS_L1 from the vertical scanning circuit 20. A signal line connected to the gate of the transfer transistor M2L1 is supplied with a control signal GS_L2 from the vertical scanning circuit 20. A signal line connected to the gate of the transfer transistor M3L1 is supplied with a control signal TX_L1 from the vertical scanning circuit 20.

[0046] A signal line connected to the gate of the transfer transistor M1S1 is supplied with a control signal GS_S1 from the vertical scanning circuit 20. A signal line connected to the gate of the transfer transistor M2S1 is supplied with a control signal GS_S2 from the vertical scanning circuit 20. A signal line connected to the gate of the transfer transistor M3S1 is supplied with a control signal TX_S1 from the vertical scanning circuit 20.

[0047] A signal line connected to the gate of the reset transistor M4 is supplied with a control signal RES_L from the vertical scanning circuit 20. A signal line connected to the gate of the reset transistor M8 is supplied with a control signal RES_S from the vertical scanning circuit 20.

[0048] A signal line connected to the gate of the selection transistor M6 is supplied with a control signal SEL_L from the vertical scanning circuit 20. A signal line connected to the gate of the selection transistor M10 is supplied with a control signal SEL_S from the vertical scanning circuit 20. A signal line connected to the gate of the charge discharging transistor M7 is supplied with a control signal OFG from the vertical scanning circuit 20.

[0049] When each transistor is an N-type transistor, when a high-level control signal is supplied from the vertical scanning circuit 20, the corresponding transistor turns on, and when a low-level control signal is supplied from the vertical scanning circuit 20, the corresponding transistor turns off.

[0050] The photoelectric conversion unit PD photoelectrically converts incident light into electric charges in an amount corresponding to the amount of light, and accumulates the generated electric charges.

[0051] The transfer transistor M1L1 functions as a transfer unit that transfers the charge held in the photoelectric conversion unit PD to the charge holding unit MEM_L1 when turned on. The transfer transistor M2L1 functions as a transfer unit that transfers the charge held in the charge holding unit MEM_L1 to the charge holding unit MEM_L2 when turned on.

[0052] The transfer transistor M3L1 functions as a transfer unit that, when turned on, transfers the charge held in the charge holding unit MEM_L2 to the floating diffusion unit FD_L.

[0053] The transfer transistor M1S1 functions as a transfer unit that transfers the charge held in the photoelectric conversion unit PD to the charge holding unit MEM_S1 when turned on. The transfer transistor M2S1 functions as a transfer unit that transfers the charge held in the charge holding unit MEM_S1 to the charge holding unit MEM_S2 when turned on.

[0054] The transfer transistor M3S1 functions as a transfer unit that, when turned on, transfers the charge held in the charge holding unit MEM_S2 to the floating diffusion unit FD_S.

[0055] The amplifier transistors M5 and M9 each have a drain supplied with a voltage VDD and a source supplied with a bias current from a current source (not shown) via a selection transistor M6 or a selection transistor M10. The amplifier transistors M5 and M9 form an amplifier section (source follower circuit) with their gates serving as input nodes.

[0056] As a result, the amplification transistor M5 outputs a signal corresponding to the potential of the floating diffusion region FD_L to the vertical output line 16 via the selection transistor M6. In addition, the amplification transistor M9 outputs a signal corresponding to the potential of the floating diffusion region FD_S to the vertical output line 17 via the selection transistor M10.

[0057] That is, the floating diffusion FD_L, the amplification transistor M5, and the selection transistor M6 constitute an output section that outputs a signal corresponding to the amount of charge held by the floating diffusion. Similarly, the floating diffusion FD_S, the amplification transistor M9, and the selection transistor M10 constitute an output section that outputs a signal corresponding to the amount of charge held by the floating diffusion.

[0058] 2 shows a configuration in which the two charge retention units (charge retention unit MEM_L2 and charge retention unit MEM_S2) each have a different transfer unit and output unit. However, it is sufficient if signals based on the charges of the two charge retention units can be output to the vertical output line independently, and for example, the two charge retention units may have a common output unit.

[0059] The reset transistor M4 and the reset transistor M8 function as reset units that reset the floating diffusion units FD_L and FD_S to voltages corresponding to the voltage VDD when they are turned on.

[0060] When the charge drain transistor M7 is off, it functions as an overflow drain that drains excess charge from the photoelectric conversion unit PD. When the charge drain transistor M7 is on, it functions as a reset unit that resets the photoelectric conversion unit PD to a voltage corresponding to the voltage VDD.

[0061] The selection transistor M6 and the selection transistor M10 function as a selection unit that selects whether or not to output a signal corresponding to the source voltage of the amplification transistor M5 and the amplification transistor M9 as a pixel signal to the vertical output line 16 or the vertical output line 17, respectively.

[0062] Next, a method for driving the photoelectric conversion device according to this embodiment will be described with reference to Fig. 3 and Fig. 4. Fig. 3 is a timing chart showing an example of a basic driving method for the exposure period of the photoelectric conversion device according to the first embodiment of the present invention.

[0063] 3 shows an example of temporal changes in the control signals GS_L1 and GS_L2 supplied to the transfer transistors M1L1 and M2L1 in the Nth frame. It also shows an example of temporal changes in the control signals GS_S1, GS_S2, and OFG supplied to the transfer transistors M1S1, M2S1, and charge discharging transistor M7, as well as the vertical synchronization signal VD and horizontal synchronization signal HD.

[0064] In the first embodiment, the falling edge of the vertical synchronization signal VD is the frame start timing, and each control signal is controlled based on the falling edge of the horizontal synchronization signal HD. That is, at time t10 shown in Fig. 3, the (N-1)th frame ends and the Nth frame begins, and at time t20, the Nth frame ends and the (N+1)th frame begins. Here, N is an integer greater than or equal to 1.

[0065] 3 are synchronized with the falling edge of the horizontal synchronization signal HD. When each control signal is at a high level, the corresponding transistor is active (turned on). In this embodiment, since GS driving is performed, the driving and timing related to the exposure operation are the same for all rows of pixels 12.

[0066] In the first embodiment, in each frame, multiple (Ks) accumulation periods Ts and multiple (Kl) accumulation periods Tl are executed, i.e., photoelectric conversion is performed in two or more different exposure periods during one frame period.

[0067] The accumulation period Ts is a period for accumulating signal charges in the charge holding unit MEM_S1 or the charge holding unit MEM_S2, and the accumulation period Tl is a period for accumulating signal charges in the charge holding unit MEM_L1 or the charge holding unit MEM_L2.

[0068] Below, the operation of the i-th accumulation period Tsi and the (i+1)-th accumulation period Tsi+1 out of the Ks accumulations, and the operation of the j-th accumulation period Tlj and the (j+1)-th accumulation period Tlj+1 out of the Kl accumulations will be explained using Figure 3.

[0069] Here, i is an integer greater than or equal to 1 and less than Ks-1, and j is an integer greater than or equal to 1 and less than Kl-1. Note that the numbers Ks and Kl can be set according to the total accumulation period within one frame period, and the numbers Ks and Kl may be the same or different.

[0070] The control signal OFG is changed from low to high by the horizontal synchronization signal HD immediately before time t11. The charge discharging transistor M7 is turned on in response to the high-level control signal OFG, and the photoelectric conversion unit PD is reset to a potential corresponding to the voltage VDD.

[0071] At time t11, the vertical scanning circuit 20 changes the control signal OFG from high level to low level, which turns off the charge discharging transistor M7 and releases the reset state of the photoelectric conversion unit PD.

[0072] That is, the timing when the control signal OFG transitions from high to low is the start time of the signal charge accumulation period Tsi. The signal charge generated by the incidence of photons on the photoelectric conversion unit PD while the charge discharging transistor M7 is off is accumulated in the photoelectric conversion unit PD.

[0073] In the next horizontal synchronization signal HD immediately before time t12, the vertical scanning circuit 20 changes the control signal GS_S1 from low to high, thereby turning on the transfer transistor M1S1 and transferring the signal charge accumulated in the photoelectric conversion unit PD to the charge holding unit MEM_S1.

[0074] The time t12 when the transfer transistor M1S1 turns off is the end time of the signal charge accumulation period Tsi. That is, the period from time t11 to time t12 is the signal charge accumulation period Tsi. At time t12, the vertical scanning circuit 20 changes the control signal OFG from low to high. This turns on the charge discharging transistor M7, and the photoelectric conversion unit PD is reset to a potential corresponding to the voltage VDD.

[0075] At the next time t13, the vertical scanning circuit 20 changes the control signal OFG from high to low. This turns off the charge discharging transistor M7, and the reset state of the photoelectric conversion unit PD is released. That is, the timing when the control signal OFG changes from high to low is the start time of the signal charge accumulation period Tlj.

[0076] In this example, the photoelectric conversion unit PD is reset by turning on the charge drain transistor M7. However, in the case of a configuration in which complete transfer is performed so that no signal charge remains in the photoelectric conversion unit PD during transfer, resetting the photoelectric conversion unit PD by the charge drain transistor M7 may be omitted.

[0077] In this case, the timing (time t12) when the transfer transistor (here, transfer transistor M1S1) turns off is the start time of the signal charge accumulation period Tlj. Note that complete transfer of signal charge from the photoelectric conversion unit to the charge storage unit can be achieved by potential design of the photoelectric conversion unit, transfer transistor, charge storage unit, etc.

[0078] In the next horizontal synchronization signal HD immediately before time t14, the vertical scanning circuit 20 changes the control signal GS_L1 from low to high. This turns on the transfer transistor M1L1, and the signal charge accumulated in the photoelectric conversion unit PD is transferred to the charge holding unit MEM_L1. Time t14, when the transfer transistor M1L1 turns off, marks the end of the signal charge accumulation period Tlj.

[0079] After that, the accumulation period Ts and the accumulation period Tl are repeated a predetermined number of times in the same manner as in the driving from time t11 to time t12 and from time t13 to time t14. For example, as shown in Fig. 3, the accumulation period Tsi+1 is performed from time t15 to time t16, and the accumulation period Tlj+1 is performed from time t17 to time t18.

[0080] In this way, Ks accumulation periods Ts and Kl accumulation periods Tl are executed, whereby the signal charge generated in the photoelectric conversion unit PD is held in the charge holding unit MEM_S1 for an accumulation period Tshort, which is the total length of the Ks accumulation periods Ts from accumulation period Ts1 to accumulation period TsKs.

[0081] Furthermore, the charge holding unit MEM_L1 holds the signal charge generated in the photoelectric conversion unit PD for an accumulation period Tlong, which is the total length of Kl accumulation periods Tl from accumulation period Tl1 to accumulation period TlKl.

[0082] Time t19 is the end time of the accumulation period TsKs in embodiment 1. Furthermore, from the following time t19 to time t20, the vertical scanning circuit 20 controls the control signals GS_S2 and GS_L2 to a high level.

[0083] This turns on the transfer transistor M2S1, transferring the signal charge held in the charge holding unit MEM_S1 to the charge holding unit MEM_S2. Also, the transfer transistor M2L1 turns on, transferring the signal charge held in the charge holding unit MEM_L1 to the charge holding unit MEM_L2. Here, the transfer transistors M2S1 and M2L1 are turned on simultaneously, but they may be turned on separately after the accumulation period ends and before the frame ends.

[0084] That is, the transfer transistor M2S1 may be turned on from the end of the accumulation period TsKs until time t20, which is the end time of the Nth frame, and the transfer transistor M2L1 may be turned on from the end of the accumulation period TlKl until time t20, which is the end time of the Nth frame.

[0085] In this embodiment, the control signals OFG, GS_L1, GS_S1, GS_L2, and GS_S2 are controlled so that the accumulation period Ts and the accumulation period Tl are each an odd number of periods of the horizontal synchronization signal HD.

[0086] In addition, the control signal OFG becomes high level at the even-numbered horizontal synchronization signal HD within the frame, and the control signals GS_L1, GS_S1, GS_L2, and GS_S2 become high level at the odd-numbered horizontal synchronization signal HD within the frame.

[0087] In the following description, the horizontal synchronization signal HD immediately before time t12 is referred to as the 2mth horizontal synchronization signal HD(2m) of the Nth frame, and the horizontal synchronization signal HD at time t12 is referred to as the (2m+1)th horizontal synchronization signal HD(2m+1) of the Nth frame, where m is an integer equal to or greater than 1.

[0088] In this way, charge accumulation is performed during each accumulation period Tlong and Tshort in each frame. As a result, the signal charge generated by the photoelectric conversion unit PD during the accumulation period Tlong is held in the charge holding unit MEM_L2. Also, the signal charge generated by the photoelectric conversion unit PD during the accumulation period Tshort is held in the charge holding unit MEM_S2.

[0089] 4 is a timing chart showing an example of a driving method for readout of the photoelectric conversion device according to Embodiment 1 of the present invention, which illustrates control signals supplied to the transfer transistor M3L1, the transfer transistor M3S1, the selection transistor M6, the selection transistor M10, the reset transistor M4, and the reset transistor M8.

[0090] That is, it shows the changes over time of the control signals TX_L1, TX_S1, SEL_L, SEL_S, RES_L, and RES_S. Note that in Figure 4, n is an integer equal to or greater than 1. When each control signal is at a high level, the corresponding transistor is active (on).

[0091] 4 shows control signals supplied to the pixels 12 in the nth row and control signals supplied to the pixels 12 in the (n+1)th row, among the control signals corresponding to each of the rows constituting the pixel unit 10. The control signals supplied to the pixels 12 in the nth row are indicated by the symbol with (n) added, and the control signals supplied to the pixels 12 in the (n+1)th row are indicated by the symbol with (n+1) added.

[0092] In each frame, signals are sequentially read out based on the signal charges accumulated in the charge holding units MEM_L2 and MEM_S2 of the pixels 12 in each row. At the start time of the Nth frame, the signal charges accumulated during the accumulation period Tshort or Tlong of the (N-1)th frame are respectively held in the charge holding units MEM_L2 and MEM_S2 of each pixel 12.

[0093] Immediately before time t30, the control signal TX_L1(n) and the control signal SEL_L(n) are at a low level, and the control signal RES_L(n) is at a high level.

[0094] At time t30, the vertical scanning circuit 20 changes the control signal SEL_L(n) from low level to high level, thereby turning on the selection transistor M6 of the pixel 12 in the n-th row. As a result, the amplification transistor M5 of the pixel 12 in each column in the n-th row is connected to the vertical output line 16 of the corresponding column via the selection transistor M6, and the pixel is placed in a selected state where pixel signals can be read out.

[0095] At this time, the reset transistor M4 is on, and the floating diffusion portion FD_L is reset to a potential corresponding to the voltage VDD. That is, a signal corresponding to the reset potential of the floating diffusion portion FD_L is output to the vertical output line 16.

[0096] At the next time t31, the vertical scanning circuit 20 changes the control signal RES_L(n) from high to low. This turns off the reset transistor M4, and the reset state of the floating diffusion region FD_L is released. The voltage of the vertical output line 16 that settles after turning off the reset transistor M4 is the reset level voltage VRES_L of the floating diffusion region FD_L. In this way, the reset level voltage VRES_L is read out to the vertical output line 16.

[0097] At the next time t32, the vertical scanning circuit 20 changes the control signal TX_L1(n) from low to high, thereby turning on the transfer transistor M3L1 of the pixel 12 in the nth row, and transferring the signal charge held in the charge holding portion MEM_L2 to the floating diffusion portion FD_L.

[0098] The floating diffusion portion FD_L then has a potential corresponding to the amount of signal charge transferred from the charge holding portion MEM_L2, and a voltage corresponding to the potential of the floating diffusion portion FD_L is output to the vertical output line 16.

[0099] At time t33, the voltage of the vertical output line 16 that settles after the transfer transistor M3L1 is turned off is the signal level voltage VSIG_L. In this way, the signal level voltage VSIG_L of the pixel 12 based on the signal charge held in the charge holding unit MEM_L2 is read out to the vertical output line 16.

[0100] The difference between the reset level voltage VRES_L and the signal level voltage VSIG_L obtained in this way, i.e., |VSIG_L-VRES_L|, becomes the pixel signal, which is a physical quantity corresponding to the amount of signal charge held in the charge holding unit MEM_L2.

[0101] At the next time t34, the vertical scanning circuit 20 changes the control signal RES_L(n) from low to high, thereby turning on the reset transistors M4 of the pixels 12 in the nth row and resetting the floating diffusion regions FD_L to a potential corresponding to the voltage VDD.

[0102] At subsequent time t35, the vertical scanning circuit 20 changes the control signal SEL_L(n) from high level to low level, thereby turning off the selection transistors M6 of the pixels 12 in the nth row and deselecting the nth row.

[0103] Here, the operation of reading out pixel signals from the charge holding unit MEM_L2 described in the period from time t30 to time t35 functions as a first readout operation that reads out pixel signals according to the amount of charge accumulated during the first exposure period (accumulation period Tlong).

[0104] Immediately before the next time t36, the control signal TX_S1(n) and the control signal SEL_S(n) are at a low level, and the control signal RES_S(n) is at a high level.

[0105] At time t36, the vertical scanning circuit 20 changes the control signal SEL_S(n) from low level to high level, thereby turning on the selection transistor M10 of the pixel 12 in the n-th row. As a result, the amplification transistor M9 of the pixel 12 in each column in the n-th row is connected to the vertical output line 17 of the corresponding column via the selection transistor M10, and the pixel enters a selected state in which pixel signals can be read out.

[0106] At this time, the reset transistor M8 is on, and the floating diffusion region FD_S is reset to a potential corresponding to the voltage VDD, so that a signal corresponding to the reset potential of the floating diffusion region FD_S is output to the vertical output line 17.

[0107] At the next time t37, the vertical scanning circuit 20 changes the control signal RES_S(n) from high to low. This turns off the reset transistor M8, and the reset state of the floating diffusion region FD_S is released. The voltage of the vertical output line 17 that settles after turning off the reset transistor M8 is the reset level voltage VRES_S of the floating diffusion region FD_S. In this way, the reset level voltage VRES_S is read out to the vertical output line 17.

[0108] At subsequent time t38, the vertical scanning circuit 20 changes the control signal TX_S1(n) from low to high, thereby turning on the transfer transistor M3S1 of the pixel 12 in the nth row and transferring the signal charge held in the charge holding unit MEM_S2 to the floating diffusion unit FD_S.

[0109] The floating diffusion region FD_S then has a potential corresponding to the amount of signal charge transferred from the charge storage region MEM_S2, and a voltage corresponding to the potential of the floating diffusion region FD_S is output to the vertical output line 17. At time t39, the voltage of the vertical output line 17 that settles after the transfer transistor M3S1 is turned off is the signal level voltage VSIG_S.

[0110] In this way, the signal level voltage VSIG_S of the pixel 12 based on the signal charge held in the charge holding unit MEM_S2 is read out to the vertical output line 17. The difference between the reset level voltage VRES_S obtained in this way and the signal level voltage VSIG_S, i.e., |VSIG_S-VRES_S|, becomes the pixel signal, which is a physical quantity corresponding to the amount of signal charge held in the charge holding unit MEM_S2.

[0111] At the next time t40, the vertical scanning circuit 20 changes the control signal RES_S(n) from low to high, thereby turning on the reset transistor M8 of the pixel 12 in the nth row and resetting the floating diffusion FD_S to a potential corresponding to the voltage VDD.

[0112] At subsequent time t41, the vertical scanning circuit 20 changes the control signal SEL_S(n) from high to low, thereby turning off the selection transistors M10 of the pixels 12 in the nth row and deselecting the nth row.

[0113] Here, the operation of reading out pixel signals from the charge holding unit MEM_S2 described in the period from time t36 to time t41 functions as a second readout operation that reads out pixel signals according to the amount of charge accumulated during the second exposure period (accumulation period Tshort).

[0114] The first and second readout operations described above are started based on the falling edge of the horizontal synchronization signal HD, and are completed by the time the next horizontal synchronization signal HD falls.

[0115] Furthermore, during the period from time t42 to time t43, a first readout operation is performed from the pixels 12 in the (n+1)th row, similar to the period from time t30 to time t35. Furthermore, during the period from time t44 to time t45, a second readout operation is performed from the pixels 12 in the (n+1)th row, similar to the period from time t36 to time t41. The readout operations for the pixels 12 in the other rows are similar.

[0116] In this embodiment, the read timing is controlled so that the first read operation of pixel 12 is performed at the timing of an odd-numbered horizontal synchronization signal HD within a frame, and the second read operation of pixel 12 is performed at the timing of an even-numbered horizontal synchronization signal HD within a frame.

[0117] That is, the readout timing is controlled so that the horizontal synchronization signal HD(2m) occurs immediately before time t36, which is the timing for starting the second readout operation of the nth row, and the readout timing is controlled so that the horizontal synchronization signal HD(2m+1) occurs immediately before time t42, which is the timing for starting the first readout operation of the (n+1)th row.

[0118] In this embodiment, after accumulation starts in the accumulation period Ts, the accumulation periods Ts and Tl are alternately performed, and finally accumulation in the accumulation period Ts is performed, but the order of the accumulation periods Ts and Tl may be reversed. Also, in the readout operation, reading from the charge holding unit MEM_L2 is performed after reading from the charge holding unit MEM_S2, but the order may be reversed as long as the readings are performed at different timings.

[0119] 3 and 4, the lengths of the accumulation periods Tlong and Tshort may be the same, but are preferably different. By changing the lengths of the accumulation periods Tlong and Tshort, it becomes possible to acquire two types of images with different effective exposure amounts in the same frame.

[0120] By correcting the signal of one of the two types of images acquired in this way according to the ratio of the lengths of the accumulation periods and combining it with the signal of the other image to create a single image, an image with a wide dynamic range (HDR image) can be obtained. The HDR image synthesis process can be performed in a signal processing unit within the photoelectric conversion device or in an external signal processing device.

[0121] As described above, in this embodiment, GS driving is performed, and therefore driving related to the exposure operation, i.e., transfer driving and reset driving, is performed collectively on all rows of pixels 12. In this embodiment, the control signals GS_L1, GS_L2, GS_S1, and GS_S2 in FIG. 3 correspond to the collective transfer driving control, and the control signal OFG corresponds to the collective reset driving control.

[0122] Incidentally, collective drive control for simultaneously driving at least one of the transfer section and the charge discharging section for a plurality of pixels is performed by, for example, a control section 218 (see FIG. 14) described later.

[0123] In the first embodiment, if the potential fluctuation due to the batch drive control is propagated through the power supply line or the like, noise is superimposed on the pixel signals read out at the same timing, causing horizontal lines to appear on the screen. At the timing of the horizontal synchronization signal HD(2m) shown in Figures 3 and 4, batch transfer drive is performed by the control signal GS_S1, and at the same time, the second readout of the pixels in the nth row is performed.

[0124] That is, for example, potential fluctuation noise due to the control signal GS_S1 is superimposed on the nth row of an image acquired during the accumulation period Tshort. Furthermore, at the timing of the horizontal synchronization signal HD(2m+1), a collective reset operation is performed by the control signal OFG, and simultaneously, the first readout of the pixels in the (n+1)th row is performed. That is, potential fluctuation noise due to the control signal OFG is superimposed on the (n+1)th row of an image acquired during the accumulation period Tlong.

[0125] In this embodiment, a predetermined process is carried out to correct the degradation of image quality due to the noise superimposition that accompanies such collective driving, as will be described below.

[0126] In the following description, the pixel unit 10 is assumed to be a photoelectric conversion device having pixels 12 arranged in v rows and h columns, and a pixel signal read out in a first readout operation is represented as Plong[x,y], and a pixel signal read out in a second readout operation is represented as Pshort[x,y], where x and y are integers satisfying 1≦x≦v and 1≦y≦h. For example, the pixel signal in the 64th column of the row that is first output in the Nth frame is represented as Plong[1,64] and Pshort[1,64].

[0127] 3 and 4, the pixel signal for the nth row of the image acquired during the accumulation period Tshort is Pshort[n,y], where n is an integer satisfying 1≦n≦v. In this case, the pixel signal Plong[n,y] read out from the same pixel at a different timing than the pixel signal Pshort[n,y] does not have noise superimposed thereon due to the collective drive control signal, but there is a difference in brightness due to the difference in accumulation period.

[0128] That is, if C[n,y]=Plong[n,y]×(Tshort / Tlong), the correction signal C[n,y] can be obtained based on the pixel signal Plong[n,y] that is not superimposed with noise due to the collective drive control signal. That is, by replacing the pixel signal Pshort[n,y] that is superimposed with noise with the correction signal C[n,y], it is possible to correct the noise caused by the collective drive control.

[0129] On the other hand, the pixel signal of the (n+1)th row of the image acquired during the accumulation period Tlong is Plong[n+1,y], which has noise superimposed thereon due to the collective drive control. At this time, the pixel signal Pshort[n+1,y] read out from the same pixel at a different timing than the pixel signal Plong[n+1,y] does not have noise superimposed thereon due to the collective drive control signal, but there is a difference in brightness due to the difference in accumulation period.

[0130] Therefore, the correction signal C[n+1,y] is calculated as C[n+1,y] = Pshort[n+1,y] × (Tlong / Tshort), and the pixel signal Plong[n+1,y] with noise superimposed thereon is corrected by being replaced with this correction signal C[n+1,y].

[0131] In this manner, in this embodiment, control is performed so that noise is superimposed on only one of the two pixel signals read out from a given pixel 12. That is, in the imaging method of this embodiment, the charge discharge unit, transfer unit, and readout unit are controlled so that one of the first readout operation and the second readout operation is performed at the same timing as the collective drive control.

[0132] Furthermore, the timing for reading out signals corresponding to the charges accumulated during each exposure period is controlled so that it does not overlap with the timing of the collective drive control. That is, the charge discharge unit, the transfer unit, and the readout unit are controlled so that one of the first readout operation and the second readout operation is performed at a timing different from the timing of the collective drive control. Therefore, the pixel signals on which noise has been superimposed can be corrected by the correction process described above.

[0133] Note that the correction process of this embodiment as described above is just one example, and other correction processes may be performed. For example, a pixel signal Plong[n,y] with noise superimposed thereon is compared with a correction signal C[n,y] that has been corrected for brightness differences according to differences in exposure periods. Then, the noise component Cn[n,y] generated by collective drive control may be calculated and subtracted from the pixel signal Plong[n,y] to perform correction.

[0134] Furthermore, to reduce the influence of random noise components, correction may be performed by subtracting noise components Cn'[n,y], which are obtained by taking a horizontal moving average of the noise components Cn[n,y], from the pixel signal Plong[n,y]. Furthermore, if either the pixel signal Plong[n,y] or the pixel signal Pshort[n,y] is saturated, correction processing may not be performed.

[0135] In this embodiment, both the exposure timing and the readout timing are controlled so that noise associated with the collective control signal is superimposed on only one of the two pixel signals read out from the pixel 12. However, it is also possible to control only the exposure timing or only the readout timing.

[0136] In other words, it is possible to prevent the batch reset by the control signal OFG and the batch transfer by the control signal GS_L1, the control signal GS_S1, the control signal GS_L2, the control signal GS_S2, the control signal TX_L1 or the control signal TX_S1 from occurring at consecutive HD timings.

[0137] Alternatively, the first readout and second readout of the nth row may not be performed at the timing of consecutive horizontal synchronization signals HD. That is, the readout timing may be controlled so that the readout order is the first readout of the nth row, the first readout of the (n+1)th row, the second readout of the nth row, and the second readout of the (n+1)th row. Note that the correction processing in this embodiment may be performed by a signal processing unit within the photoelectric conversion device or by an external signal processing device.

[0138] In this embodiment, accumulation operations are performed during a first exposure period and a second exposure period during one frame period. Furthermore, either the first readout operation, which reads out pixel signals corresponding to the amount of charge accumulated during the first exposure period, or the second readout operation, which reads out pixel signals corresponding to the amount of charge accumulated during the second exposure period, is performed at a timing that does not overlap with the timing of collective drive control. Therefore, it is possible to obtain an image in which the degradation in image quality due to the global electronic shutter operation has been corrected.

[0139] <Embodiment 2> A photoelectric conversion device and a driving method thereof according to a second embodiment of the present invention will be described with reference to Figures 5 and 6. In the following description, the same configurations and processes as those of the first embodiment will be denoted by the same reference numerals, and detailed description thereof will be omitted.

[0140] This embodiment differs from embodiment 1 in that one pixel has multiple photoelectric conversion units. In embodiment 1, one pixel has one photoelectric conversion unit, but in this embodiment, one pixel has multiple photoelectric conversion units, which can improve functionality such as phase difference detection for focusing and ranging.

[0141] 5 is an equivalent circuit diagram showing an example of the configuration of each pixel of the photoelectric conversion device according to Embodiment 2 of the present invention. As shown in FIG. 2, each pixel 12 has a photoelectric conversion unit PD, and transfer transistors M1L1, M1S1, M2L1, M2S1, M3L1, and M3S1.

[0142] Each pixel 12 also includes reset transistors M4 and M8, amplifier transistors M5 and M9, select transistors M6 and M10, and a charge drain transistor M7.

[0143] The pixel 12 also has a photoelectric conversion unit PD', a transfer transistor M1L1', a transfer transistor M1S1', a transfer transistor M2L1', a transfer transistor M2S1', a transfer transistor M3L1', a transfer transistor M3S1', and a charge discharging transistor M7'.

[0144] The photoelectric conversion unit PD' is configured by a photoelectric conversion element, for example, a photodiode. The photoelectric conversion units PD (first photoelectric conversion unit) and PD' (second photoelectric conversion unit) are arranged in the same pixel and receive light via a common light-collecting microlens (not shown).

[0145] In other words, PD and PD' receive light from different exit pupils of the same imaging lens. Therefore, the distance to the subject can be calculated by detecting the phase difference between the image signals obtained from multiple PDs and the image signals obtained from multiple PD's.

[0146] The photoelectric conversion unit PD' has an anode connected to the ground node and a cathode connected to the source of the transfer transistor M1L1', the source of the transfer transistor M1S1', and the source of the charge discharging transistor M7'.

[0147] The drain of the transfer transistor M1L1′ is connected to the source of the transfer transistor M2L1′. The connection node between the drain of the transfer transistor M1L1′ and the source of the transfer transistor M2L1′ includes a capacitance component and functions as a charge holding unit (charge holding unit MEM_L1′).

[0148] The drain of the transfer transistor M1S1' is connected to the source of the transfer transistor M2S1'. The connection node between the drain of the transfer transistor M1S1' and the source of the transfer transistor M2S1' includes a capacitance component and functions as a charge holding unit (charge holding unit MEM_S1').

[0149] The drain of the transfer transistor M2L1′ is connected to the source of the transfer transistor M3L1′. The connection node between the drain of the transfer transistor M2L1′ and the source of the transfer transistor M3L1′ includes a capacitance component and functions as a charge holding unit (charge holding unit MEM_L2′).

[0150] The drain of the transfer transistor M2S1′ is connected to the source of the transfer transistor M3S1′. The connection node between the drain of the transfer transistor M2S1′ and the source of the transfer transistor M3S1′ includes a capacitance component and functions as a charge holding unit (charge holding unit MEM_S2′).

[0151] Here, the charge holding unit MEM_L1', the charge holding unit MEM_L2', the charge holding unit MEM_S1', and the charge holding unit MEM_S2' function as two or more charge holding units that hold charges from the photoelectric conversion unit.

[0152] The transfer transistors M1L1', M1S1', M2L1', and M2S1' function as a transfer unit that transfers charges from the photoelectric conversion unit to the charge storage unit. The drain of the transfer transistor M3L1' is connected to the drain of the transfer transistor M3L1, the source of the reset transistor M4, and the gate of the amplification transistor M5.

[0153] The connection node of the drain of the transfer transistor M3L1, the drain of the transfer transistor M3L1′, the source of the reset transistor M4, and the gate of the amplification transistor M5 forms a floating diffusion portion FD_L.

[0154] The drain of the transfer transistor M3S1' is connected to the drain of the transfer transistor M3S1, the source of the reset transistor M8, and the gate of the amplification transistor M9. The connection node between the drain of the transfer transistor M3S1, the drain of the transfer transistor M3S1', the source of the reset transistor M8, and the gate of the amplification transistor M9 forms a floating diffusion portion FD_S.

[0155] The drain of the reset transistor M4, the drain of the reset transistor M8, the drain of the amplifying transistor M5, the drain of the amplifying transistor M9, and the drain of the charge discharging transistor M7' are connected to the power supply voltage line (voltage VDD).

[0156] The drain voltages of the reset transistor M4 and the reset transistor M8, the drain voltages of the amplifying transistor M5 and the amplifying transistor M9, and the drain voltage of the charge discharging transistor M7' may be at least partially different.

[0157] Each of the control lines 14 includes eleven signal lines, six of which are connected to the gates of the transfer transistor M1L1', the transfer transistor M1S1', the transfer transistor M2L1', the transfer transistor M2S1', the transfer transistor M3L1', and the transfer transistor M3S1', respectively.

[0158] Furthermore, five signal lines are connected to the gates of the reset transistor M4, the reset transistor M8, the selection transistor M6, the selection transistor M10, and the charge ejection transistor M7'.

[0159] A signal line connected to the gate of the transfer transistor M1L1′ is supplied with a control signal GS_L1 from the vertical scanning circuit 20. A signal line connected to the gate of the transfer transistor M2L1′ is supplied with a control signal GS_L2 from the vertical scanning circuit 20. A signal line connected to the gate of the transfer transistor M3L1′ is supplied with a control signal TX_L1′ from the vertical scanning circuit 20.

[0160] A control signal GS_S1 is supplied from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M1S1′. A control signal GS_S2 is supplied from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M2S1′.

[0161] A signal line connected to the gate of the transfer transistor M3S1′ is supplied with a control signal TX_S1′ from the vertical scanning circuit 20. A signal line connected to the gate of the charge discharging transistor M7′ is supplied with a control signal OFG from the vertical scanning circuit 20.

[0162] The transfer transistor M1L1' functions as a transfer unit that, when turned on, transfers the charges held in the photoelectric conversion unit PD' to the charge holding unit MEM_L1'. The transfer transistor M2L1' functions as a transfer unit that, when turned on, transfers the charges held in the charge holding unit MEM_L1' to the charge holding unit MEM_L2'.

[0163] The transfer transistor M3L1' functions as a transfer unit that, when turned on, transfers the charges held in the charge holding unit MEM_L2' to the floating diffusion unit FD_L. The transfer transistor M1S1' functions as a transfer unit that, when turned on, transfers the charges held in the photoelectric conversion unit PD' to the charge holding unit MEM_S1'.

[0164] The transfer transistor M2S1' functions as a transfer unit that, when turned on, transfers the charge held in the charge holding unit MEM_S1' to the charge holding unit MEM_S2'. The transfer transistor M3S1' functions as a transfer unit that, when turned on, transfers the charge held in the charge holding unit MEM_S2' to the floating diffusion unit FD_S.

[0165] 5, two charge holding units (charge holding unit MEM_L2 and charge holding unit MEM_L2') have a common output unit, and two other charge holding units (charge holding unit MEM_S2 and charge holding unit MEM_S2') have a common output unit and output pixel signals to vertical output lines.

[0166] However, it is sufficient that the configuration is such that signals based on the respective charges from the four charge holding units are output to vertical output lines. For example, the vertical output lines to which pixel signals are output from the four charge holding units may all be different, or the four charge holding units may have a common output unit.

[0167] The charge drain transistor M7' functions as an overflow drain unit that drains excess charge from the photoelectric conversion unit PD' when it is off. It can also be said that the charge drain transistor M7' functions as a reset unit that performs a reset operation to reset the photoelectric conversion unit PD' to a voltage corresponding to the voltage VDD when it is on.

[0168] Next, a method for driving the photoelectric conversion device according to this embodiment will be described with reference to Fig. 6. Fig. 6 is a timing chart showing an example of a method for driving the photoelectric conversion device according to the second embodiment in relation to readout.

[0169] The temporal changes of the control signals GS_L1, GS_L2, GS_S1, GS_S2, and OFG, as well as the vertical and horizontal synchronization signals VD and HD, are the same as those in FIG. 3, and therefore will not be described.

[0170] However, in this embodiment, the transfer control by the control signals GS_L1, GS_L2, GS_S1 and GS_S2 and the subsequent reset control by the control signal OFG are performed at the timing of successive horizontal synchronization signals HD.

[0171] Moreover, the accumulation period Ts and the accumulation period Tl are both controlled to be longer than two horizontal synchronization signals HD. That is, the drive control circuit 60 controls so that the collective control signal that causes noise superposition is not performed at intervals equal to one horizontal synchronization signal HD. That is, the collective drive control is controlled so that the interval between the collective drive controls is less than a predetermined period. Also, the collective drive control is controlled so that the interval between the collective drive controls is equal to or longer than a predetermined period.

[0172] FIG. 6 shows control signals supplied to the transfer transistor M3L1, the transfer transistor M3L1', the transfer transistor M3S1, the transfer transistor M3S1', the selection transistor M6, the selection transistor M10, the reset transistor M4, and the reset transistor M8.

[0173] That is, it shows the changes over time of the control signals TX_L1, TX_L1', TX_S1, TX_S1', SEL_L, SEL_S, RES_L, and RES_S. Here, n is an integer greater than or equal to 1. When each control signal is at a high level, the corresponding transistor is active (on).

[0174] 6 shows the control signals supplied to the pixels 12 in the nth row and the control signals supplied to the pixels 12 in the (n+1)th row, among the control signals corresponding to each of the multiple rows constituting the pixel unit 10. The control signals supplied to the pixels 12 in the nth row are indicated by the symbol with (n) added, and the control signals supplied to the pixels 12 in the (n+1)th row are indicated by the symbol with (n+1) added.

[0175] In each frame, signals based on the signal charges stored in the charge holding units MEM_L2, MEM_L2', MEM_S2, and MEM_S2' of the pixels 12 in each row are read out sequentially.

[0176] At the start time of the Nth frame, the signal charges accumulated during the accumulation period Tlong of the (N-1)th frame are respectively held in the charge holding units MEM_L2 and MEM_L2' of each pixel 12. Also, the signal charges accumulated during the accumulation period Tshort of the (N-1)th frame are respectively held in the charge holding units MEM_S2 and MEM_S2'.

[0177] Immediately before time t50, the control signals TX_L1(n), TX_L1'(n), and SEL_L(n) are at low level, and the control signal RES_L(n) is at high level.

[0178] At time t50, the vertical scanning circuit 20 changes the control signal SEL_L(n) from low to high, thereby selecting the pixel 12 in each column of the nth row so that the pixel signal can be read from the charge holding unit MEM_L2 or MEM_L2′.

[0179] At the next time t51, the vertical scanning circuit 20 changes the control signal RES_L(n) from high to low, thereby turning off the reset transistor M4. The voltage of the vertical output line 16 that settles after the reset transistor M4 turns off is the reset level voltage VRES_L.

[0180] At the next time t52, the vertical scanning circuit 20 changes the control signal TX_L1(n) from low to high, thereby turning on the transfer transistor M3L1 of the pixel 12 in the nth row, and a voltage corresponding to the potential of the floating diffusion FD_L is output to the vertical output line 16.

[0181] The voltage of the vertical output line 16 that settles after the transfer transistor M3L1 is turned off is the signal level voltage VSIG_L. In this way, a pixel signal |VSIG_L-VRES_L|, which is a physical quantity corresponding to the amount of signal charge held in the n-th row charge holding unit MEM_L2 in the N-th frame, is obtained.

[0182] At subsequent time t53, the vertical scanning circuit 20 changes the control signal RES_L(n) from low level to high level, thereby resetting the floating diffusion portions FD_L of the pixels 12 in the nth row to a potential corresponding to the voltage VDD.

[0183] At the next time t54, the vertical scanning circuit 20 changes the control signal RES_L(n) from high to low. The voltage of the vertical output line 16 that settles after the reset transistor M4 is turned off is the reset level voltage VRES_L'.

[0184] At the next time t55, the vertical scanning circuit 20 changes the control signal TX_L1′(n) from low to high, thereby transferring the signal charges held in the charge holding unit MEM_L2′ of the nth row to the floating diffusion unit FD_L.

[0185] The floating diffusion portion FD_L then has a potential corresponding to the amount of signal charge transferred from the charge holding portion MEM_L2′, and a voltage corresponding to the potential of the floating diffusion portion FD_L is output to the vertical output line 16.

[0186] Subsequently, the voltage of the vertical output line 16 that settles after the transfer transistor M3L1' is turned off is the signal level voltage VSIG_L'. In this way, a pixel signal |VSIG_L'-VRES_L'|, which is a physical quantity corresponding to the amount of signal charge held in the charge holding unit MEM_L2', is obtained.

[0187] By the following time t56, the vertical scanning circuit 20 changes the control signal RES_L(n) from low level to high level, and at time t56 changes the control signal SEL_L(n) from high level to low level, thereby deselecting the nth row.

[0188] Here, the operation of reading pixel signals from the charge holding units MEM_L2 and MEM_L2' described in the period from time t50 to time t56 functions as a first read operation that reads pixel signals according to the amount of charge accumulated during the first exposure period.

[0189] The first read operation from the charge holding unit MEM_L2 and the first read operation from the charge holding unit MEM_L2' described above are each started based on the falling edge of the horizontal synchronization signal HD and are completed by the time the next horizontal synchronization signal HD falls.

[0190] Also, from time t57 to time t58, similarly to time t50 to time t56, pixel signals |VSIG_S-VRES_S| and pixel signals |VSIG_S'-VRES_S'| are read out from the charge holding units MEM_S2 and MEM_S2' of the pixels 12 in the (n)th row, respectively.

[0191] These operations function as a second readout operation for reading out pixel signals according to the amount of charge accumulated in the second exposure period.

[0192] Furthermore, from time t59 to time t60, similarly to time t50 to time t56, the first readout operation is performed from the charge holding units MEM_L2 and MEM_L2′ of the pixels 12 in the (n+1)th row.

[0193] Furthermore, during the period from time t61 to time t62, a second readout operation is performed from the charge holding units MEM_S2 and MEM_S2′ of the pixels 12 in the (n+1)th row. The readout operation is similar for the pixels 12 in the other rows.

[0194] In this embodiment, the pixel signal based on the charge generated in the photoelectric conversion unit PD and the pixel signal based on the charge generated in the photoelectric conversion unit PD' are read out as independent pixel signals, but they may also be added together in the floating diffusion unit FD and read out.

[0195] Here, in the photoelectric conversion unit PD and photoelectric conversion unit PD' of pixel 12 in the nth row, the pixel signals obtained by the first readout are Plong[n,y] and Plong'[n,y], respectively, and the pixel signals obtained by the second readout are Pshort[n,y] and Pshort'[n,y], respectively.

[0196] When Plong'[n,y] is read out at the timing of the horizontal synchronization signal HD(2m), noise due to the collective control signal is superimposed on Plong'[n,y] and Pshort[n,y].

[0197] In this embodiment, the read timing is controlled so that noise due to the collective control signal is not superimposed on both the pixel signals read from the charge holding unit MEM_L2 and the pixel signals read from the charge holding unit MEM_S2, or the read timing is controlled so that noise due to the collective control signal is not superimposed on both the pixel signals read from the charge holding unit MEM_L2' and the pixel signals read from the charge holding unit MEM_S2'.

[0198] Therefore, noise due to the collective control signal is not superimposed on Plong[n,y] and Pshort'[n,y]. In other words, Plong'[n,y] and Pshort[n,y] can be corrected using Plong[n,y] or Pshort'[n,y].

[0199] In this way, according to this embodiment, it is possible to acquire an image in which the degradation in image quality caused by the global electronic shutter operation has been corrected.

[0200] <Embodiment 3> A photoelectric conversion device and a driving method thereof according to a third embodiment of the present invention will be described with reference to Figs. 7 to 9. Fig. 7 is an equivalent circuit diagram showing an example of the configuration of each pixel of the photoelectric conversion device according to the third embodiment of the present invention. In the following description, the same configurations and processes as those already described will be assigned the same reference numerals, and detailed description thereof will be omitted.

[0201] This embodiment differs from embodiment 1 in that two charge storage units are connected in parallel between each of the photoelectric conversion unit PD and two floating diffusion units FD. That is, in this embodiment, four charge storage units can be connected in parallel to the photoelectric conversion unit.

[0202] 7, each pixel 12 has a photoelectric conversion unit PD and a transfer transistor M1L1, a transfer transistor M1L2, a transfer transistor M1S1, and a transfer transistor M1S2. Also, each pixel 12 has a transfer transistor M3L1, a transfer transistor M3L2, a transfer transistor M3S1, and a transfer transistor M3S2.

[0203] Each pixel 12 also includes reset transistors M4 and M8, amplifier transistors M5 and M9, select transistors M6 and M10, and a charge drain transistor M7.

[0204] The drain of the transfer transistor M1L1 is connected to the source of the transfer transistor M3L1. The connection node between the drain of the transfer transistor M1L1 and the source of the transfer transistor M3L1 includes a capacitance component and functions as a charge holding unit (charge holding unit MEM1_L).

[0205] The drain of the transfer transistor M1L2 is connected to the source of the transfer transistor M3L2. The connection node between the drain of the transfer transistor M1L2 and the source of the transfer transistor M3L2 includes a capacitance component and functions as a charge holding unit (charge holding unit MEM2_L).

[0206] The drain of the transfer transistor M1S1 is connected to the source of the transfer transistor M3S1. The connection node between the drain of the transfer transistor M1S1 and the source of the transfer transistor M3S1 includes a capacitance component and functions as a charge holding unit (charge holding unit MEM1_S).

[0207] The drain of the transfer transistor M1S2 is connected to the source of the transfer transistor M3S2. The connection node between the drain of the transfer transistor M1S2 and the source of the transfer transistor M3S2 includes a capacitance component and functions as a charge holding unit (charge holding unit MEM2_S).

[0208] Here, the charge holding units MEM1_L, MEM2_L, MEM1_S, and MEM2_S function as two or more charge holding units that hold charges from the photoelectric conversion units, and the transfer transistors M1L1, M1L2, M1S1, and M1S2 function as transfer units that transfer charges from the photoelectric conversion units to the charge holding units.

[0209] The drains of the transfer transistors M3L1 and M3L2 are connected to the source of the reset transistor M4 and the gate of the amplification transistor M5. The connection node between the drains of the transfer transistors M3L1 and M3L2, the source of the reset transistor M4, and the gate of the amplification transistor M5 forms a floating diffusion portion FD_L.

[0210] The drains of the transfer transistors M3S1 and M3S2 are connected to the source of the reset transistor M8 and the gate of the amplification transistor M9. The connection node between the drains of the transfer transistors M3S1 and M3S2, the source of the reset transistor M8, and the gate of the amplification transistor M9 forms a floating diffusion portion FD_S.

[0211] Here, the transfer transistor M3L1, the transfer transistor M3L2, the reset transistor M4, the amplification transistor M5, and the selection transistor M6 function as a readout unit that reads out a signal according to the amount of charge transferred from the charge storage unit.

[0212] The transfer transistor M3S1, transfer transistor M3S2, reset transistor M8, amplification transistor M9, and selection transistor M10 function as a readout section that reads out a signal according to the amount of charge transferred from the charge storage section.

[0213] Each of the control lines 14 includes 13 signal lines, six of which are connected to the gates of the transfer transistor M1L1, the transfer transistor M1L2, the transfer transistor M1S1, the transfer transistor M1S2, the transfer transistor M3L1, and the transfer transistor M3L2, respectively.

[0214] The remaining seven signal lines are connected to the gates of the transfer transistor M3S1, transfer transistor M3S2, reset transistor M4, reset transistor M8, selection transistor M6, selection transistor M10, and charge discharging transistor M7.

[0215] A control signal GS1_L is supplied from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M1L1. A control signal GS2_L is supplied from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M1L2.

[0216] A control signal TX1_L is supplied from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M3L1. A control signal TX2_L is supplied from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M3L2.

[0217] A control signal GS1_S is supplied from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M1S1. A control signal GS2_S is supplied from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M1S2.

[0218] A control signal TX1_S is supplied from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M3S1. A control signal TX2_S is supplied from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M3S2.

[0219] The transfer transistor M1L1 functions as a transfer unit that, when turned on, transfers the charge held in the photoelectric conversion unit PD to the charge holding unit MEM1_L. The transfer transistor M1L2 functions as a transfer unit that, when turned on, transfers the charge held in the photoelectric conversion unit PD to the charge holding unit MEM2_L.

[0220] The transfer transistor M1S1 functions as a transfer unit that, when turned on, transfers the charge held in the photoelectric conversion unit PD to the charge holding unit MEM1_S. The transfer transistor M1S2 functions as a transfer unit that, when turned on, transfers the charge held in the photoelectric conversion unit PD to the charge holding unit MEM2_S.

[0221] The transfer transistor M3L1 functions as a transfer unit that, when turned on, transfers the charge held in the charge holding unit MEM1_L to the floating diffusion unit FD_L. The transfer transistor M3L2 functions as a transfer unit that, when turned on, transfers the charge held in the charge holding unit MEM2_L to the floating diffusion unit FD_L.

[0222] The transfer transistor M3S1 functions as a transfer unit that transfers the charge held in the charge holding unit MEM1_S to the floating diffusion unit FD_S when turned on. The transfer transistor M3S2 functions as a transfer unit that transfers the charge held in the charge holding unit MEM2_S to the floating diffusion unit FD_S when turned on.

[0223] Note that Figure 7 shows a configuration in which two charge holding units (charge holding unit MEM1_L and charge holding unit MEM2_L) have a common output unit, and two other charge holding units (charge holding unit MEM1_S and charge holding unit MEM2_S) have a common output unit.

[0224] However, it is sufficient that the configuration is such that signals based on the charges of the four charge holding units are output to the vertical output lines independently. For example, the four charge holding units may each have a different output unit, or the four charge holding units may have a common output unit.

[0225] Next, a method for driving the photoelectric conversion device according to this embodiment will be described with reference to FIGS.

[0226] Fig. 8 is a timing chart showing an example of a basic driving method for an exposure period of a photoelectric conversion device according to embodiment 3 of the present invention. Fig. 8 shows an example of temporal changes in the control signals GS1_L and GS2_L supplied to the transfer transistor M1L1 and the transfer transistor M1L2, respectively, in the Nth frame and the N+1th frame.

[0227] FIG. 8 also shows an example of temporal changes in the control signals GS1_S, GS2_S, and OFG supplied to the transfer transistor M1S1, transfer transistor M1S2, and charge discharging transistor M7, as well as the vertical synchronization signal VD and horizontal synchronization signal HD.

[0228] In the third embodiment, the falling edge of the vertical synchronization signal VD is the frame start timing, and each control signal is controlled based on the falling edge of the horizontal synchronization signal HD. In the third embodiment, in each frame, multiple (Ks) accumulation periods Ts and multiple (Kl) accumulation periods Tl are executed.

[0229] In the Nth frame of FIG. 8, the accumulation period Ts is a period for accumulating signal charges in the charge holding unit MEM1_S, and the accumulation period Tl is a period for accumulating signal charges in the charge holding unit MEM1_L.

[0230] In the (N+1)th frame of FIG. 8, the accumulation period Ts is a period for accumulating signal charges in the charge holding unit MEM2_S, and the accumulation period Tl is a period for accumulating signal charges in the charge holding unit MEM2_L.

[0231] Below, the operation of the i-th accumulation period Tsi and the (i+1)-th accumulation period Tsi+1 out of the Ks accumulations, and the operation of the j-th accumulation period Tlj and the (j+1)-th accumulation period Tlj+1 out of the Kl accumulations will be explained using Figure 8.

[0232] In the Nth frame, just before time t71, the vertical scanning circuit 20 changes the control signal OFG from low to high. Then, at time t71, the vertical scanning circuit 20 changes the control signal OFG from high to low. This turns off the charge discharging transistor M7, and the reset state of the photoelectric conversion unit PD is released.

[0233] Subsequently, in the horizontal synchronization signal HD immediately before time t72, the vertical scanning circuit 20 changes the control signal GS1_S from low to high, thereby turning on the transfer transistor M1S1 and transferring the signal charge accumulated in the photoelectric conversion unit PD to the charge holding unit MEM1_S.

[0234] At the following time t72, the transfer transistor M1S1 is turned off. That is, the period from time t71 to time t72 is the signal charge accumulation period Tsi for the Nth frame. At time t72, the vertical scanning circuit 20 changes the control signal OFG from low to high. This turns on the charge discharging transistor M7, and the photoelectric conversion unit PD is reset to a potential corresponding to the voltage VDD.

[0235] At subsequent time t73, the vertical scanning circuit 20 changes the control signal OFG from high level to low level, thereby turning off the charge discharging transistor M7 and releasing the reset state of the photoelectric conversion unit PD.

[0236] In the next horizontal synchronization signal HD immediately before time t74, the vertical scanning circuit 20 changes the control signal GS1_L from low to high, thereby turning on the transfer transistor M1L1 and transferring the signal charge accumulated in the photoelectric conversion unit PD to the charge holding unit MEM1_L.

[0237] At the following time t74, the transfer transistor M1L1 is turned off. That is, the period from time t73 to time t74 is the signal charge accumulation period Tlj for the Nth frame. At time t74, the vertical scanning circuit 20 changes the control signal OFG from low to high. This turns on the charge discharging transistor M7, and the photoelectric conversion unit PD is reset to a potential corresponding to the voltage VDD.

[0238] Thereafter, the accumulation period Ts and the accumulation period Tl are repeated a predetermined number of times in the same manner as in the driving from time t71 to time t72 or from time t73 to time t74. For example, as shown in Fig. 8, the signal charge accumulation period Tsi+1 is performed from time t75 to time t76, and the signal charge accumulation period Tlj+1 is performed from time t77 to time t78.

[0239] In this way, Ks accumulation periods Ts and Kl accumulation periods Tl are executed in the Nth frame, whereby the signal charges generated in the photoelectric conversion unit PD are held in the charge holding unit MEM1_S for an accumulation period Tshort having a length equal to the total length of the Ks periods from accumulation period Ts1 to accumulation period TsKs.

[0240] The charge holding unit MEM1_L holds the signal charge generated in the photoelectric conversion unit PD for an accumulation period Tlong having a length equal to the total length of Kl periods from accumulation period Tl1 to accumulation period TlKl.

[0241] In the subsequent (N+1)th frame, just before time t79, the vertical scanning circuit 20 changes the control signal OFG from low to high. Then, at time t79, the vertical scanning circuit 20 changes the control signal OFG from high to low. This turns off the charge discharging transistor M7, and the reset state of the photoelectric conversion unit PD is released.

[0242] Subsequently, in the horizontal synchronization signal HD immediately before time t80, the vertical scanning circuit 20 changes the control signal GS2_S from low to high, which turns on the transfer transistor M1S2 and transfers the signal charge accumulated in the photoelectric conversion unit PD to the charge holding unit MEM2_S.

[0243] At the following time t80, the transfer transistor M1S2 is turned off. That is, the period from time t79 to time t80 is the signal charge accumulation period Tsi for the (N+1)th frame. At time t80, the vertical scanning circuit 20 changes the control signal OFG from low to high. This turns on the charge discharging transistor M7, and the photoelectric conversion unit PD is reset to a potential corresponding to the voltage VDD.

[0244] At subsequent time t81, the vertical scanning circuit 20 changes the control signal OFG from high level to low level, thereby turning off the charge discharging transistor M7 and releasing the reset state of the photoelectric conversion unit PD.

[0245] In the next horizontal synchronization signal HD immediately before time t82, the vertical scanning circuit 20 changes the control signal GS2_L from low to high, thereby turning on the transfer transistor M1L2 and transferring the signal charge accumulated in the photoelectric conversion unit PD to the charge holding unit MEM2_L.

[0246] At the following time t82, the transfer transistor M1L2 is turned off. That is, the period from time t81 to time t82 is the accumulation period Tlj of the signal charges in the (N+1)th frame.

[0247] Thereafter, the accumulation periods Ts and Tl are repeated a predetermined number of times in the same manner as in the driving from time t79 to time t80 or from time t81 to time t82.

[0248] For example, as shown in FIG. 8, a signal charge accumulation period Tsi+1 is carried out from time t83 to time t84, and a signal charge accumulation period Tlj+1 is carried out from time t85 to time t86.

[0249] In this way, Ks accumulation periods Ts and Kl accumulation periods Tl are executed in the (N+1)th frame. As a result, the signal charge generated by the photoelectric conversion unit PD is held in the charge holding unit MEM2_S during the accumulation period Tshort. Also, the signal charge generated by the photoelectric conversion unit PD is held in the charge holding unit MEM2_L during the accumulation period Tlong.

[0250] Here, the horizontal synchronization signal HD immediately before time t72 is the 2mth horizontal synchronization signal HD(2m) of the Nth frame, and the horizontal synchronization signal HD at time t72 is the (2m+1)th horizontal synchronization signal HD(2m+1) of the Nth frame, where m is an integer equal to or greater than 1.

[0251] 9A and 9B are timing charts showing an example of a driving method for readout of the photoelectric conversion device according to the third embodiment of the present invention. Fig. 9 shows control signals supplied to the transfer transistors M3L1, M3L2, M3S1, and M3S2. It also shows control signals supplied to the select transistor M6, select transistor M10, reset transistor M4, and reset transistor M8.

[0252] That is, it shows the time changes of the control signals TX1_L, TX2_L, TX1_S, TX2_S, SEL_L, SEL_S, RES_L, and RES_S.

[0253] 9A and 9B show control signals supplied to the pixels 12 in the nth row and control signals supplied to the pixels 12 in the (n+1)th row, among the control signals corresponding to each of the multiple rows constituting the pixel unit 10. The control signals supplied to the pixels 12 in the nth row have (n) added to their reference numerals, and the control signals supplied to the pixels 12 in the (n+1)th row have (n+1) added to their reference numerals.

[0254] 9A and 9B, signals are sequentially read out based on the signal charges accumulated in the charge holding units MEM2_L and MEM2_S of the pixels 12 in each row. At the start of the Nth frame, the signal charges accumulated during the accumulation period Tshort or Tlong of the (N-1)th frame are respectively held in the charge holding units MEM2_L and MEM2_S of each pixel 12.

[0255] 9A and 9B, signals are sequentially read out based on the signal charges accumulated in the charge holding units MEM1_L and MEM1_S of the pixels 12 in each row. At the start of the N+1th frame, the signal charges accumulated during the accumulation period Tshort or Tlong of the Nth frame are respectively held in the charge holding units MEM1_L and MEM1_S of each pixel 12.

[0256] Immediately before time t90, the control signals TX1_L(n), TX2_L(n), and SEL_L(n) are at low level, and the control signal RES_L(n) is at high level.

[0257] At time t90, the vertical scanning circuit 20 changes the control signal SEL_L(n) from low to high, thereby enabling pixel signals to be read out from the charge holding unit MEM1_L or MEM2_L of the pixel 12 in each column of the nth row.

[0258] At the next time t91, the vertical scanning circuit 20 changes the control signal RES_L(n) from high to low, thereby turning off the reset transistor M4. The voltage of the vertical output line 16 that settles after turning off the reset transistor M4 is the reset level voltage VRES_L.

[0259] At subsequent time t92, the vertical scanning circuit 20 changes the control signal TX2_L(n) from low to high, thereby turning on the transfer transistor M3L2 of the pixel 12 in the nth row, and transferring the signal charge held in the charge holding portion MEM2_L to the floating diffusion portion FD_L.

[0260] A voltage corresponding to the potential of the floating diffusion region FD_L is output to the vertical output line 16. The voltage of the vertical output line 16 that settles after the transfer transistor M3L2 is turned off is the signal level voltage VSIG_L. In this way, a pixel signal |VSIG_L-VRES_L|, which is a physical quantity corresponding to the amount of signal charge held in the charge holding unit MEM2_L of the nth row in the Nth frame, is obtained.

[0261] Between the time when the transfer transistor M3L2 is turned off and time t93, the vertical scanning circuit 20 changes the control signal RES_L(n) from low to high. This resets the floating diffusion FD_L of the pixel 12 in the nth row to a potential corresponding to the voltage VDD. At time t93, the vertical scanning circuit 20 changes the control signal SEL_L(n) from high to low. This deselects the pixel 12 in the nth row.

[0262] Here, the operation of reading out pixel signals from the charge holding unit MEM2_L described in the period from time t90 to time t93 functions as a first readout operation that reads out pixel signals according to the amount of charge accumulated during the first exposure period.

[0263] Immediately before the next time t94, the control signals TX1_S(n), TX2_S(n) and SEL_S(n) are at low level, and the control signal RES_S(n) is at high level.

[0264] At time t94, the vertical scanning circuit 20 changes the control signal SEL_S(n) from low to high, thereby selecting the charge holding unit MEM1_S or MEM2_S of the pixel 12 in the nth row so that pixel signals can be read from the charge holding unit MEM1_S or MEM2_S.

[0265] During the period from time t94 to the subsequent time t95, similar to the period from time t90 to time t93, the pixel signal |VSIG_S-VRES_S| is read out from the charge holding unit MEM2_S of the nth row in the Nth frame. These operations function as a second readout operation that reads out pixel signals according to the amount of charge accumulated during the second exposure period.

[0266] During the period from time t96 to time t97, similar to the period from time t90 to time t93, pixel signals |VSIG_L-VRES_L| are read out from the charge holding unit MEM2_L in the (n+1)th row in the Nth frame. These operations function as a first readout operation that reads out pixel signals according to the amount of charge accumulated during the first exposure period.

[0267] Furthermore, during the period from time t98 to time t99, similar to the period from time t94 to time t95, pixel signals |VSIG_S-VRES_S| are read out from the charge storage unit MEM2_S in the (n+1)th row in the Nth frame. These operations function as a second readout operation that reads out pixel signals corresponding to the amount of charge accumulated during the second exposure period. The readout operations for the pixels 12 in the other rows are similar.

[0268] During the period from time t100 to time t101, similar to the period from time t90 to time t93, the pixel signal |VSIG_L-VRES_L| is read out from the charge holding unit MEM1_L of the nth row in the (N+1)th frame. These operations function as a first readout operation that reads out a pixel signal according to the amount of charge accumulated during the first exposure period.

[0269] Furthermore, during the period from time t102 to time t103, similar to the period from time t94 to time t95, the pixel signal |VSIG_S-VRES_S| is read out from the charge holding unit MEM1_S in the nth row in the (N+1)th frame. These operations function as a second readout operation that reads out pixel signals according to the amount of charge accumulated during the second exposure period.

[0270] Furthermore, during the period from time t104 to time t105, similar to the period from time t96 to time t97, a pixel signal |VSIG_L-VRES_L| is read out from the charge holding unit MEM1_L of the (n+1)th row in the (N+1)th frame. These operations function as a first readout operation that reads out a pixel signal according to the amount of charge accumulated during the first exposure period.

[0271] Furthermore, during the period from time t106 to time t107, similar to the period from time t98 to time t99, pixel signals |VSIG_S-VRES_S| are read out from the charge storage unit MEM1_S of the (n+1)th row in the (N+1)th frame. These operations function as a second readout operation that reads out pixel signals corresponding to the amount of charge accumulated during the second exposure period. The readout operations for the pixels 12 of the other rows are similar.

[0272] As described above, in this embodiment, GS driving is performed, and therefore driving related to the exposure operation, i.e., transfer driving and reset driving, is performed collectively on all rows of pixels 12. In this embodiment, the control signals GS1_L, GS2_L, GS1_S, and GS2_S in FIG. 8 correspond to the collective transfer driving control, and the control signal OFG corresponds to the collective reset driving control.

[0273] In this embodiment, the read timing is controlled so that the first read operation of pixel 12 is performed at the timing of an odd-numbered horizontal synchronization signal HD within a frame, and the second read operation of pixel 12 is performed at the timing of an even-numbered horizontal synchronization signal HD within a frame.

[0274] That is, the readout timing is controlled so that the horizontal synchronization signal HD(2m) occurs just before time t94, which is the timing to start the second readout operation of the nth row in the Nth frame. Also, the readout timing is controlled so that the horizontal synchronization signal HD(2m+1) occurs just before time t96, which is the timing to start the first readout operation of the (n+1)th row. The same is true for the N+1th frame.

[0275] According to this embodiment, it is possible to perform the same correction as that described in the first embodiment, and it is possible to obtain an image in which the degradation in image quality due to the global electronic shutter operation has been corrected.

[0276] <Embodiment 4> A photoelectric conversion device and a driving method thereof according to a fourth embodiment of the present invention will be described with reference to Figures 10 to 12. In the following description, the same configurations and processes as those already described will be assigned the same reference numerals, and detailed description will be omitted. This embodiment differs from the first embodiment in that one charge storage section is connected in parallel between each of the photoelectric conversion section PD and two floating diffusion sections FD.

[0277] 10 is an equivalent circuit diagram showing an example of the configuration of each pixel of the photoelectric conversion device according to Embodiment 4 of the present invention. As shown in FIG. 10, each pixel 12 has a photoelectric conversion unit PD, and transfer transistors M1L1, M1S1, M3L1, and M3S1.

[0278] Each pixel 12 further includes reset transistors M4 and M8, amplification transistors M5 and M9, selection transistors M6 and M10, and a charge drain transistor M7. The charge drain transistor M7 functions as a charge drain unit that drains charges accumulated in the photoelectric conversion unit.

[0279] The photoelectric conversion unit PD has an anode connected to the ground node and a cathode connected to the source of the transfer transistor M1L1, the source of the transfer transistor M1S1, and the source of the charge discharging transistor M7.

[0280] The drain of the transfer transistor M1L1 is connected to the source of the transfer transistor M3L1. The connection node between the drain of the transfer transistor M1L1 and the source of the transfer transistor M3L1 includes a capacitance component and functions as a charge holding unit (charge holding unit MEM_L1).

[0281] The drain of the transfer transistor M1S1 is connected to the source of the transfer transistor M3S1. The connection node between the drain of the transfer transistor M1S1 and the source of the transfer transistor M3S1 includes a capacitance component and functions as a charge holding unit (charge holding unit MEM_S1).

[0282] Here, the charge holding unit MEM_L1 and the charge holding unit MEM_S1 function as a first charge holding unit and a second charge holding unit that hold charges from the photoelectric conversion unit, and the transfer transistor M1L1 and the transfer transistor M1S1 function as transfer units that transfer charges from the photoelectric conversion unit to the charge holding units.

[0283] The transfer transistor M3L1, reset transistor M4, amplifier transistor M5, and select transistor M6, as well as the transfer transistor M3S1, reset transistor M8, amplifier transistor M9, and select transistor M10, function as a readout unit, which reads out a signal corresponding to the amount of charge transferred from the charge storage unit.

[0284] Each of the control lines 14 includes nine signal lines, five of which are connected to the gates of the transfer transistor M1L1, transfer transistor M1S1, transfer transistor M3L1, transfer transistor M3S1, and reset transistor M4, respectively, and the remaining four signal lines are connected to the gates of the reset transistor M8, select transistor M6, select transistor M10, and charge ejection transistor M7.

[0285] The transfer transistor M3L1 functions as a transfer unit that, when turned on, transfers the charge held in the charge holding unit MEM_L1 to the floating diffusion unit FD_L. The transfer transistor M3S1 functions as a transfer unit that, when turned on, transfers the charge held in the charge holding unit MEM_S1 to the floating diffusion unit FD_S.

[0286] 10 shows a configuration in which the two charge retention units (charge retention unit MEM_L1 and charge retention unit MEM_S1) each have a different transfer unit and output unit. However, it is sufficient if the two charge retention units are configured to output signals based on their respective charges to the vertical output lines independently, and for example, the two charge retention units may have a common output unit.

[0287] Next, a method for driving the photoelectric conversion device according to this embodiment will be described with reference to FIGS.

[0288] 11 is a timing chart showing an example of a basic driving method for an exposure period of a photoelectric conversion device according to Embodiment 4 of the present invention. Fig. 11 shows an example of temporal changes in the control signals GS_L1, GS_S1, and OFG supplied to the transfer transistor M1L1, the transfer transistor M1S1, and the charge discharging transistor M7 in the Nth frame.

[0289] In the fourth embodiment, the accumulation period Tlong and the accumulation period Tshort are each performed once in each frame. The accumulation period Tlong is a period for accumulating signal charge in the charge holding unit MEM_L1, and the accumulation period Tshort is a period for accumulating signal charge in the charge holding unit MEM_S1. The operation of the accumulation period Tlong and the accumulation period Tshort will be described below with reference to FIG. 11.

[0290] It is assumed that the control signal OFG is at a high level immediately before time t110. At time t110, the vertical scanning circuit 20 changes the control signal OFG from a high level to a low level. That is, time t110 is the start time of the accumulation period Tlong in the photoelectric conversion unit PD.

[0291] During the period from a predetermined timing after time t110 to time t111, the vertical scanning circuit 20 controls the control signal GS_L1 to a high level. This turns on the transfer transistor M1L1, and the signal charge accumulated in the photoelectric conversion unit PD is transferred to the charge holding unit MEM_L1. Time t111, when the transfer transistor M1L1 turns off, marks the end of the accumulation period Tlong in the photoelectric conversion unit PD.

[0292] After time t111, the vertical scanning circuit 20 changes the control signal OFG from low to high. At the following time t112, the vertical scanning circuit 20 changes the control signal OFG from high to low. That is, time t112 is the start time of the accumulation period Tshort in the photoelectric conversion unit PD.

[0293] During the period from a predetermined timing after time t112 to time t113, the vertical scanning circuit 20 controls the control signal GS_S1 to high level. This turns on the transfer transistor M1S1, and the signal charge accumulated in the photoelectric conversion unit PD is transferred to the charge holding unit MEM_S1. Time t113, when the transfer transistor M1S1 turns off, marks the end of the accumulation period Tshort in the photoelectric conversion unit PD.

[0294] In this way, the accumulation period Tlong and the accumulation period Tshort are executed in each frame. As a result, the signal charge generated by the photoelectric conversion unit PD is held in the charge holding unit MEM_L1 during the accumulation period Tlong. Also, the signal charge generated by the photoelectric conversion unit PD is held in the charge holding unit MEM_S1 during the accumulation period Tshort.

[0295] The signal charge accumulated in the photoelectric conversion unit PD can be transferred to the charge holding unit MEM_L1 or the charge holding unit MEM_S1 after the readout of the pixel signal based on the signal charge of the N-1th frame accumulated in the charge holding unit MEM_L1 and the charge holding unit MEM_S1 is completed.

[0296] In this embodiment, it is assumed that the readout of pixel signals based on the signal charges of the N-1th frame accumulated in the charge holding units MEM_L1 and MEM_S1 is completed by the time the control signal OFG is controlled to a high level just before time t110.

[0297] Fig. 12 is a timing chart showing an example of a driving method for readout of the photoelectric conversion device according to the fourth embodiment of the present invention, which shows control signals supplied to the transfer transistor M3L1, the transfer transistor M3S1, the selection transistor M6, the selection transistor M10, the reset transistor M4, and the reset transistor M8.

[0298] That is, it shows the time changes of the control signal TX_L1, the control signal TX_S1, the control signal SEL_L, the control signal SEL_S, the control signal RES_L, and the control signal RES_S.

[0299] Figure 12 shows the control signals supplied to the pixels 12 in the nth row and the control signals supplied to the pixels 12 in the (n+1)th row, among the control signals corresponding to each of the multiple rows that make up the pixel section 10.

[0300] In each frame, pixel signals are sequentially read out based on the signal charges accumulated in the charge storage units MEM_L1 and MEM_S1 of each row. At the start time of the Nth frame, the charge storage units MEM_L1 and MEM_S1 of each pixel 12 respectively store the signal charges accumulated during the accumulation period Tlong or Tshort of the (N-1)th frame.

[0301] Immediately before time t120, the control signal TX_L1(n) and the control signal SEL_L(n) are at a low level, and the control signal RES_L(n) is at a high level.

[0302] At time t120, the vertical scanning circuit 20 changes the control signal SEL_L(n) from low level to high level, thereby placing the pixels 12 in the n-th row and each column in a selected state in which pixel signals accumulated therein can be read out.

[0303] At the next time t121, the vertical scanning circuit 20 changes the control signal RES_L(n) from high to low, thereby releasing the reset state of the floating diffusion region FD_L. Thus, the reset level voltage VRES_L is read out to the vertical output line 16.

[0304] At the next time t122, the vertical scanning circuit 20 changes the control signal TX_L1(n) from low to high, thereby turning on the transfer transistor M3L1 of the pixel 12 in the nth row, and transferring the signal charge held in the charge holding portion MEM_L1 to the floating diffusion portion FD_L.

[0305] The floating diffusion portion FD_L then has a potential corresponding to the amount of signal charge transferred from the charge holding portion MEM_L1, and a voltage corresponding to the potential of the floating diffusion portion FD_L is output to the vertical output line 16.

[0306] After time t122, the control signal TX_L1(n) is set to low level, turning off the transfer transistor M3L1 of the pixel 12 in the nth row. The voltage of the vertical output line 16 that settles after the transfer transistor M3L1 is turned off is the signal level voltage VSIG_L. In this way, the signal level voltage VSIG_L of the pixel 12 based on the signal charge held in the charge holding unit MEM_L1 is read out to the vertical output line 16.

[0307] The difference between the reset level voltage VRES_L and the signal level voltage VSIG_L obtained in this way, i.e., |VSIG_L-VRES_L|, becomes the pixel signal, which is a physical quantity corresponding to the amount of signal charge held in the charge holding unit MEM_L1.

[0308] During the period from when the transfer transistor M3L1 is turned off until time t123, the vertical scanning circuit 20 controls the control signal RES_L(n) to change from low level to high level.

[0309] At the following time t123, the vertical scanning circuit 20 changes the control signal SEL_L(n) from low level to high level.

[0310] Here, the operation of reading out pixel signals from the charge holding unit MEM_L1 described in the period from time t120 to time t123 functions as a first readout operation.

[0311] Immediately before time t123, the control signal TX_S1(n) and the control signal SEL_S(n) are at a low level, and the control signal RES_S(n) is at a high level.

[0312] At time t123, the vertical scanning circuit 20 changes the control signal SEL_S(n) from low level to high level, thereby bringing the pixels 12 in the n-th row and each column into a selected state in which pixel signals can be read out.

[0313] At the next time t124, the vertical scanning circuit 20 changes the control signal TX_S1(n) from low to high, thereby releasing the reset state of the floating diffusion region FD_S, and a signal corresponding to the reset potential of the floating diffusion region FD_S is output to the vertical output line 17.

[0314] At subsequent time t125, the vertical scanning circuit 20 changes the control signal TX_S1(n) from low to high, thereby turning on the transfer transistor M3S1 of the pixel 12 in the nth row, and transferring the signal charge held in the charge holding portion MEM_S1 to the floating diffusion portion FD_S.

[0315] The floating diffusion portion FD_S then has a potential corresponding to the amount of signal charge transferred from the charge holding portion MEM_S1, and a voltage corresponding to the potential of the floating diffusion portion FD_S is output to the vertical output line 17.

[0316] After time t125, the control signal TX_S1(n) is set to low level, turning off the transfer transistor M3S1 of the pixel 12 in the nth row. The voltage of the vertical output line 17 that settles after the transfer transistor M3S1 is turned off is the signal level voltage VSIG_S. In this way, the signal level voltage VSIG_S of the pixel 12 based on the signal charge held in the charge holding unit MEM_S1 is read out to the vertical output line 17.

[0317] The difference between the reset level voltage VRES_S and the signal level voltage VSIG_S obtained in this way, i.e., |VSIG_S-VRES_S|, becomes the pixel signal, which is a physical quantity corresponding to the amount of signal charge held in the charge holding unit MEM_S1.

[0318] During the period from when the transfer transistor M3S1 is turned off until time t126, the vertical scanning circuit 20 changes the control signal RES_S(n) from low level to high level.

[0319] At the following time t126, the vertical scanning circuit 20 changes the control signal SEL_S(n) from low level to high level.

[0320] Here, the operation of reading out pixel signals from the charge holding unit MEM_S1 described in the period from time t123 to time t126 functions as a second readout operation.

[0321] During the period from time t126 to time t127, a first readout operation is performed from the pixels 12 in the (n+1)th row, similar to the period from time t120 to time t123. Furthermore, during the period from time t128 to time t129, a second readout operation is performed from the pixels 12 in the (n+1)th row, similar to the period from time t123 to time t126. The readout operations for the pixels 12 in the other rows are similar.

[0322] In this embodiment, the exposure operation for the accumulation period Tshort is performed after the exposure operation for the accumulation period Tlong, but the order may be reversed.

[0323] As described above, in this embodiment, GS driving is performed, and therefore driving related to the exposure operation, i.e., transfer driving and reset driving, is performed collectively on all rows of pixels 12. That is, in this embodiment, the control signals GS_L1 and GS_S1 in FIG. 11 correspond to the collective transfer driving control, and the control signal OFG corresponds to the collective reset driving control.

[0324] The collective drive control for simultaneously driving at least one of the transfer section and the charge discharging section for a plurality of pixels is performed by, for example, the control section 218 described later.

[0325] As described above, in the fourth embodiment, the readout operation from each pixel 12 is completed before the control signal GS_L1 is controlled. That is, in the fourth embodiment, the collective drive control signal that causes degradation in image quality is only the control signal OFG among the collective drive control signals described above.

[0326] 12, it is possible to correct noise caused by collective drive control by performing the first readout operation and the second readout operation from each pixel 12 at different timings. In this way, according to this embodiment, it is possible to obtain an image in which degradation in image quality due to the global electronic shutter operation has been corrected.

[0327] <Embodiment 5> Fig. 13 is a timing chart showing an example of a basic driving method relating to the exposure time of a photoelectric conversion device according to embodiment 5 of the present invention, and the photoelectric conversion device according to embodiment 5 and its driving method will be described with reference to Figs. 1, 2, 4, and 13. In the following description, the same configurations and processes as those already described will be assigned the same reference numerals, and detailed description thereof will be omitted.

[0328] This embodiment differs from embodiment 1 in that the output circuit 50 does not have a correction processing unit for correcting image quality degradation caused by potential fluctuations associated with GS operation, but has a signal processing unit that performs HDR synthesis processing. Another difference from embodiment 1 is that the drive control circuit 60 controls the collective drive control timing so that noise associated with collective drive control is superimposed only on pixel signals based on the accumulation period Tshort.

[0329] An example of the schematic configuration of a photoelectric conversion device according to embodiment 5 of the present invention is shown in Fig. 1, similar to embodiment 1. An example of the configuration of each pixel of the photoelectric conversion device according to embodiment 5 of the present invention is shown in Fig. 2, similar to embodiment 1.

[0330] Next, a method for driving the photoelectric conversion device according to the fifth embodiment of the present invention will be described with reference to FIG.

[0331] 13 shows an example of the control signals GS_L1 and GS_L2 supplied to the transfer transistor M1L1 and the transfer transistor M2L1, and the transfer transistor M1S1 in the Nth frame. Also shown in FIG. 13 is an example of temporal changes in the control signals GS_S1, GS_S2, and OFG supplied to the transfer transistor M2S1 and the charge discharging transistor M7, the vertical synchronization signal VD, and the horizontal synchronization signal HD.

[0332] 13 are the same as those in the first embodiment, and therefore will not be described further. However, the timing of the accumulation periods Tsi, Tlj, Tsi+1, and Tlj+1, as well as the time t19 to the time t20, is controlled so as to provide an even number of horizontal synchronization signals HD in the accumulation periods Ts and Tl in this embodiment.

[0333] After the transfer transistor M1L1 or M1S1 is turned off, the charge discharging transistor M7 is turned on by the control signal OFG at a timing that is one horizontal synchronization signal HD away.

[0334] In FIG. 13, noise accompanying the control signal GS_S1 in the accumulation period Tsi occurs at the timing of the horizontal synchronization signal HD(2m), and noise accompanying the control signal OFG immediately before the accumulation period Tlj occurs at the timing of the horizontal synchronization signal HD(2m+2).

[0335] Similarly, noise associated with the control signal GS_L1 in the accumulation period Tlj occurs at the timing of the horizontal synchronization signal HD(2m+8), and noise associated with the control signal OFG immediately before the accumulation period Tsj+1 occurs at the timing of the horizontal synchronization signal HD(2m+10).

[0336] In this embodiment, the length of the accumulation period Tlong is controlled to be longer than the length of the accumulation period Tshort, which makes it possible to acquire two types of images with different effective exposure amounts in the same frame, and an HDR image can be obtained by performing HDR compositing processing in the output circuit 50.

[0337] A driving method for readout of a photoelectric conversion device according to embodiment 5 of the present invention is shown in Fig. 4, similar to embodiment 1. However, a first readout operation for reading out pixel signals based on an accumulation period Tlong and a second readout operation for reading out pixel signals based on an accumulation period Tshort are performed alternately for each horizontal synchronization signal HD, and the second readout operation is performed with horizontal synchronization signal HD(2a), where a is an integer greater than or equal to 1.

[0338] As described above, in this embodiment, noise caused by collective drive control is superimposed at the timing of the horizontal synchronization signal HD(2a). Also, only images acquired during the accumulation period Tshort (short-second images) are read out using the horizontal synchronization signal HD(2a).

[0339] In other words, noise caused by collective drive control is superimposed only on short-period images, and is not superimposed on images acquired during the accumulation period Tlong (long-period images). In the HDR image obtained by HDR compositing the long-period and short-period images obtained in this way, noise caused by collective drive control is superimposed only on high-brightness areas.

[0340] In addition, since optical shot noise is dominant in high-brightness areas, noise caused by collective drive control is difficult to see. In other words, by controlling the collective drive control so that noise caused by collective drive control is limited to short-time images, it is possible to acquire images with reduced image quality degradation due to noise caused by collective drive control without performing correction processing.

[0341] In this embodiment, the exposure timing is controlled so that noise caused by the collective control signal is superimposed only on the short-time image, but the readout timing may also be controlled. For example, when collective drive control is performed using the horizontal synchronization signal HD(2m+1) shown in Figure 4, the second readout of the nth row and the first readout of the n+1th row may be interchanged.

[0342] In this embodiment, accumulation operations are performed during a first exposure period and a second exposure period during one frame period. The first exposure period is longer than the second exposure period, and the second readout is controlled to occur at the same timing as the collective drive control. The two images obtained by the above operations are then combined to obtain an HDR image. This makes it possible to obtain an image with reduced image quality degradation due to noise caused by the collective drive control.

[0343] <Embodiment 6> An imaging system according to a sixth embodiment of the present invention will be described with reference to Fig. 14. Fig. 14 is a functional block diagram showing an example of the schematic configuration of the imaging system according to the sixth embodiment of the present invention.

[0344] 14 is realized by causing a CPU or the like serving as a computer (not shown) included in the imaging system to execute a computer program stored in a memory (not shown) serving as a storage medium. However, some or all of these functions may be realized by hardware. Examples of hardware that can be used include a dedicated circuit (ASIC) and a processor (reconfigurable processor, DSP).

[0345] Furthermore, the functional blocks shown in Fig. 14 do not have to be housed in the same housing, but may be configured as separate devices connected to each other via signal paths. The above explanation regarding Fig. 14 also applies to Fig. 15.

[0346] The photoelectric conversion device 100 described in the first embodiment can be applied to various imaging systems, such as digital still cameras, digital video cameras, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites.

[0347] Furthermore, a camera module equipped with an optical system such as a lens and a photoelectric conversion device is also included in the imaging system. Fig. 14 shows a block diagram of a digital video camera as an example of an imaging system.

[0348] 14 includes a photoelectric conversion device 100, a lens 202 that forms an optical image of a subject on the light receiving surface of the photoelectric conversion device 100, and an aperture 204 that varies the amount of light that passes through the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light on the photoelectric conversion device 100. The photoelectric conversion device 100 is the photoelectric conversion device 100 configured as described in the first to fifth embodiments, and converts the optical image formed by the lens 202 into image data.

[0349] The imaging system 200 also includes a signal processing unit 208 that processes signals output from the photoelectric conversion device 100. The signal processing unit 208 generates video data from the digital signals output from the photoelectric conversion device 100. The signal processing unit 208 also performs various corrections, compression, etc. as necessary, and outputs image data.

[0350] The photoelectric conversion device 100 generates a digital signal to be processed by the signal processing unit 208. The AD conversion unit and the signal processing unit 208 may be formed in multiple layers on a semiconductor substrate separate from the semiconductor layer on which the photoelectric conversion unit of the photoelectric conversion device 100 is formed.

[0351] The imaging system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit 212 for communicating with an external computer or the like.

[0352] Furthermore, the imaging system 200 has a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control I / F (interface) unit 216 for recording or reading out data from the recording medium 214. The recording medium 214 may be built into the imaging system 200 or may be detachable.

[0353] The imaging system 200 further includes a control unit 218 that performs various calculations and controls the entire imaging system 200 , and a timing generation unit 220 that outputs various timing signals to the photoelectric conversion device 100 and the signal processing unit 208 .

[0354] The control unit 218 has a built-in CPU and the like as a computer, and functions as a control means for controlling the operation of each unit of the entire imaging system based on a computer program stored in a memory as a storage medium.

[0355] In addition, in embodiment 6, the control unit 218 controls the exposure settings (accumulation period settings and aperture value settings) of the photoelectric conversion device 100 and the aperture 204, focus adjustment by the lens 202, etc., based on the results of analyzing the video signal obtained by the signal processing unit 208.

[0356] In addition, timing signals and the like may be input from outside, and the imaging system 200 only needs to have at least the photoelectric conversion device 100 and a signal processing unit 208 that processes the output signal output from the photoelectric conversion device 100.

[0357] The photoelectric conversion device 100 outputs a video signal to the signal processing unit 208, and the signal processing unit 208 performs predetermined signal processing on the video signal output from the photoelectric conversion device 100 and outputs video data. In the sixth embodiment, the process of correcting image quality degradation due to the global electronic shutter operation in the signal processing unit 208 will be described with reference to FIG.

[0358] FIG. 15 is a functional block diagram showing a detailed example configuration of a signal processing unit of an imaging system according to embodiment 6 of the present invention, and shows an example configuration for correcting image quality degradation caused by global electronic shutter operation in the signal processing unit 208 shown in FIG.

[0359] As described above, the photoelectric conversion device 100 has the configuration described in Embodiments 1 to 5. That is, as a characteristic drive, when correcting image quality degradation due to global electronic shutter operation, two pixel signals with a luminance difference that are read out at different timings are obtained from the photoelectric conversion device 100.

[0360] In the following description, it is assumed that the photoelectric conversion device 100 has pixels in v rows and h columns. A pixel signal during the accumulation period Tlong will be represented as Plong[x,y], and a pixel signal during the accumulation period Tshort will be represented as Pshort[x,y], where x and y are integers satisfying 1≦x≦v and 1≦y≦h.

[0361] 15, the signal processing unit 208 has a correction position determination unit 300, a correction value generation unit 301, and a correction unit 302 as blocks that correct the degradation in image quality that accompanies the global electronic shutter operation described in the first to fourth embodiments. Note that this correction processing is not performed in the configuration of the fifth embodiment.

[0362] However, other image corrections, signal processing, etc. may be performed before or after the correction of the image quality degradation caused by the global electronic shutter operation. Here, the correction unit 302 uses the correction value generated by the correction value generation unit 301 to perform correction processing of noise caused by the global electronic shutter operation.

[0363] As described above, the correction unit 302 uses one of the first signal read out in the first readout operation and the second signal read out in the second readout operation to correct the other signal. That is, of the first and second signals, the signal on which noise generated by collective drive control is superimposed is corrected by the signal on which noise is not superimposed.

[0364] The correction position determination unit 300 acquires the setting value for the exposure period (accumulation period) of the photoelectric conversion device 100 from the exposure settings calculated by the control unit 218, and determines the correction position of the video signal where correction processing is performed to correct the degradation in image quality associated with the global electronic shutter operation.

[0365] For example, when the photoelectric conversion device 100 has the configuration described in the first embodiment, the video signal read out at time t11 when the control signal OFG is set to high level is set to the correction position.

[0366] Also, if time t11 is the timing for reading out pixel signals during the accumulation period Tlong of pixels in the Cpth row, for example, Plong[Cp,k] is set as the correction position where noise is superimposed. Hereinafter, the correction position (correction row) determined by the correction position determination unit 300 is set as Cp. Cp is an integer equal to or greater than 0.

[0367] The correction value generation unit 301 generates a correction value corresponding to the pixel signal Plong[Cp,k] at the correction position. That is, as described in the first embodiment, for example, a correction signal C[Cp,y] for correcting the pixel signal Plong[Cp,y] on which noise is superimposed is obtained by, for example, setting C[Cp,y]=Pshort[Cp,y]×(Tlong / Tshort).

[0368] This correction signal C[Cp,y] is then input to the correction unit 302, which then corrects the pixel signal Plong[Cp,y] on which noise is superimposed by replacing it with the correction signal C[Cp,y]. As described in the first to fourth embodiments, the method of generating the correction signal is not limited to this.

[0369] The present invention has been described above in detail based on its preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and combinations of the above embodiments are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0370] The present invention also includes those that realize the functions of the above embodiments using, for example, at least one processor such as a CPU, memory, or circuit (for example, ASIC). Also, multiple processors may be used to perform distributed processing.

[0371] In order to realize part or all of the control in the above-described embodiments, a computer program that realizes the functions of the above-described embodiments may be supplied to an imaging system or the like via a network or various storage media. Then, a computer (or a CPU, MPU, or the like) in the imaging system or the like may read and execute the program. In this case, the program and the storage medium storing the program constitute the present invention. The present invention also includes the following combinations.

[0372] (Configuration 1) An imaging system having a plurality of pixels, each pixel having a photoelectric conversion unit that generates an electric charge through photoelectric conversion, two or more charge holding units that hold the electric charge, a transfer unit that transfers the electric charge from the photoelectric conversion unit to the charge holding unit, a charge discharge unit that discharges the electric charge accumulated in the photoelectric conversion unit, and a readout unit that reads out a signal corresponding to the amount of electric charge transferred from the charge holding unit, and further having a control unit that performs collective drive control to drive at least one of the transfer units and the charge discharge units simultaneously for the plurality of pixels, and performs photoelectric conversion using two or more different exposure periods during one frame period, and controls so that one of the timings for reading out the signals corresponding to the electric charge accumulated in each exposure period does not overlap with the timing of the collective drive control.

[0373] (Configuration 2) The imaging system described in Configuration 1, characterized in that the control unit performs accumulation operations for a first exposure period and a second exposure period during one frame period, and controls one of a first readout operation that reads out pixel signals corresponding to the amount of charge accumulated during the first exposure period and a second readout operation that reads out pixel signals corresponding to the amount of charge accumulated during the second exposure period to be performed at a timing that does not overlap with the timing of the collective drive control.

[0374] (Configuration 3) The imaging system according to Configuration 2, wherein the control unit controls to perform one of the first readout operation and the second readout operation at the same timing as the collective drive control.

[0375] (Configuration 4) The imaging system described in Configuration 2 or 3, characterized in that the control unit controls the charge discharge unit, the transfer unit, and the readout unit to perform one of the first readout operation and the second readout operation at the same timing as the collective drive control.

[0376] (Configuration 5) An imaging system described in any one of configurations 2 to 4, characterized in that the control unit controls the charge discharge unit, the transfer unit, and the readout unit to perform one of the first readout operation and the second readout operation at a timing different from the collective drive control.

[0377] (Configuration 6) The imaging system according to Configuration 5, further comprising a correction unit that uses one of the first signal read out in the first readout operation and the second signal read out in the second readout operation to correct the other signal.

[0378] (Configuration 7) The imaging system described in Configuration 6, wherein the correction unit corrects, of the first signal and the second signal, the signal on which noise generated by the collective drive control is superimposed, by the signal on which the noise is not superimposed.

[0379] (Configuration 8) An imaging system described in any one of configurations 2 to 7, characterized in that the first exposure period is longer than the second exposure period, and the charge discharge unit, the transfer unit, and the readout unit are controlled so that the second readout operation is performed at the same timing as the collective drive control.

[0380] (Configuration 9) An imaging system described in any one of configurations 1 to 8, characterized in that two of the charge holding units can be connected to the photoelectric conversion unit, and each of the two charge holding units can be connected in series to another charge holding unit.

[0381] (Configuration 10) The imaging system according to any one of configurations 1 to 9, wherein four of the charge holding units can be connected in parallel to the photoelectric conversion unit.

[0382] (Configuration 11) The imaging system according to any one of configurations 1 to 10, wherein the control unit controls the collective drive control so that the interval between the collective drive controls is equal to or longer than a predetermined period.

[0383] (Configuration 12) The imaging system according to any one of configurations 1 to 11, wherein the control unit controls the collective drive control so that the interval between the collective drive controls is less than a predetermined period.

[0384] (Configuration 13) The imaging system according to any one of configurations 1 to 12, wherein the readout section performs the readout operation during an exposure operation of the photoelectric conversion section.

[0385] (Method) An imaging method for controlling an imaging system having a plurality of pixels, each pixel having a photoelectric conversion unit that generates charge through photoelectric conversion, two or more charge holding units that hold the charge, a transfer unit that transfers the charge from the photoelectric conversion unit to the charge holding unit, a charge discharge unit that discharges the charge accumulated in the photoelectric conversion unit, and a readout unit that reads out a signal corresponding to the amount of charge transferred from the charge holding unit, characterized in that the imaging method performs a collective drive control to drive at least one of the transfer units and the charge discharge units simultaneously for the plurality of pixels, and performs photoelectric conversion using two or more different exposure periods during one frame period, and controls so that one of the timings for reading out the signals corresponding to the charge accumulated in each exposure period does not overlap with the timing of the collective drive control.

[0386] (Program) A computer program for controlling each unit of the imaging system according to any one of configurations 1 to 13 by a computer. [Explanation of symbols]

[0387] PD: Photoelectric conversion unit M1, M2, M3: Transfer transistors M4, M8: Reset transistors M5, M9: Amplifying transistors M6, M10: Select transistor M7: Charge discharge transistor MEM: Charge storage unit FD: Floating diffusion unit 10: Pixel unit 12: Pixel 14: Control line 16, 17: Vertical output line 20: Vertical scanning circuit 30: Readout circuit 40: Horizontal scanning circuit 50: Output circuit 60: Drive control circuit 100: Photoelectric conversion device 200: Imaging system 202: Lens 204: Aperture 208: Signal processing unit 210: Memory unit 212: External I / F unit 214: Recording medium 216: Recording medium control I / F unit 218: Control unit 220: Timing generation unit 300: Correction position determination unit 301: Correction value generation unit 302: Correction unit

Claims

1. A plurality of pixels, each pixel having: a photoelectric conversion unit that generates electric charges by photoelectric conversion; two or more charge holding units that hold the charges; a transfer unit that transfers the charges from the photoelectric conversion unit to the charge storage unit; a charge discharging section that discharges the charge accumulated in the photoelectric conversion section; a readout unit that reads out a signal corresponding to the amount of charge transferred from the charge holding unit, a control unit that performs collective drive control to drive at least one of the transfer unit and the charge discharge unit simultaneously for the plurality of pixels, and performs photoelectric conversion using two or more different exposure periods during one frame period, and controls one of the timings for reading out signals corresponding to the charges accumulated in each exposure period so that it does not overlap with the timing of the collective drive control.

2. 2. The imaging system according to claim 1, wherein the control unit performs accumulation operations for a first exposure period and a second exposure period during one frame period, and controls one of a first readout operation for reading out pixel signals corresponding to the amount of charge accumulated during the first exposure period and a second readout operation for reading out pixel signals corresponding to the amount of charge accumulated during the second exposure period to be performed at a timing that does not overlap with the timing of the collective drive control.

3. 3. The imaging system according to claim 2, wherein the control unit controls so that one of the first readout operation and the second readout operation is performed at the same timing as the collective drive control.

4. The imaging system according to claim 2, wherein the control unit controls the charge discharge unit, the transfer unit, and the readout unit to perform one of the first readout operation and the second readout operation at the same timing as the collective drive control.

5. The imaging system according to claim 2, wherein the control unit controls the charge discharge unit, the transfer unit, and the readout unit to perform one of the first readout operation and the second readout operation at a timing different from that of the collective drive control.

6. 6. The imaging system according to claim 5, further comprising a correction unit that uses one of a first signal read out in the first readout operation and a second signal read out in the second readout operation to correct the other signal.

7. The imaging system according to claim 6, wherein the correction unit corrects one of the first signal and the second signal, on which noise caused by the collective drive control is superimposed, by the other signal on which the noise is not superimposed.

8. 3. The imaging system according to claim 2, wherein the first exposure period is longer than the second exposure period, and the charge discharge unit, the transfer unit, and the readout unit are controlled so that the second readout operation is performed at the same timing as the collective drive control.

9. 2. The imaging system according to claim 1, wherein two of the charge holding units can be connected to the photoelectric conversion unit, and another charge holding unit can be connected in series to each of the two charge holding units.

10. 2. The imaging system according to claim 1, wherein four of the charge holding units can be connected in parallel to the photoelectric conversion unit.

11. 2. The imaging system according to claim 1, wherein the control unit controls the simultaneous drive control so that the interval between the simultaneous drive controls is equal to or longer than a predetermined period.

12. 2. The imaging system according to claim 1, wherein the control unit controls the collective drive control so that the interval between the collective drive controls is less than a predetermined period.

13. 2. The imaging system according to claim 1, wherein the readout section performs the readout operation during an exposure operation of the photoelectric conversion section.

14. A plurality of pixels, each pixel having: a photoelectric conversion unit that generates electric charges by photoelectric conversion; two or more charge holding units that hold the charges; a transfer unit that transfers the charges from the photoelectric conversion unit to the charge storage unit; a charge discharging section that discharges the charge accumulated in the photoelectric conversion section; a readout unit that reads out a signal corresponding to an amount of charge transferred from the charge holding unit, an imaging method characterized by performing collective drive control to drive at least one of the transfer unit and the charge discharge unit simultaneously for the plurality of pixels, and performing photoelectric conversion using two or more different exposure periods during one frame period, and controlling one of the timings for reading out signals corresponding to the charges accumulated in each exposure period so that it does not overlap with the timing of the collective drive control.

15. A computer program for controlling each unit of the imaging system according to any one of claims 1 to 13 by a computer.

Images