Semiconductor device

Abstract

To provide a transistor structure which achieves a so-called normally-off switching element having a positive threshold voltage in an n-channel transistor using an oxide semiconductor for a channel formation region.SOLUTION: In the transistor, an oxide semiconductor stack is provided between a first gate electrode layer and a second gate electrode layer with an insulating layer interposed therebetween, and the thickness of a channel formation region is smaller than that of the other region in the oxide semiconductor stack. In the above transistor, one of the gate electrode layers is provided as a so-called back gate for controlling the threshold voltage. By controlling the level of the potential supplied to the back gate, the threshold voltage of the transistor can be controlled; thus, the transistor can be easily kept normally off.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The invention disclosed in this specification relates to a semiconductor device and a manufacturing method thereof.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general category of semiconductor devices, including electro-optical devices, light-emitting displays, semiconductor circuits, and electronic equipment. be. [Background technology]

[0003] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is The transistor is being used in integrated circuits (ICs) and image display devices (simply called display devices). It is widely applied to semiconductor electronic devices such as transistors. Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used for this purpose. Oxide semiconductors are attracting attention.

[0004] For example, zinc oxide or In-Ga-Zn oxide is used as the oxide semiconductor to produce a transistor. Techniques for producing a transistor have been disclosed (see Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0006] The transistors applied to semiconductor devices have a positive threshold voltage whose gate voltage is as close to 0V as possible. It is desirable that the channel is formed at a threshold voltage (Vth). A transistor is a so-called normal transistor, in which current flows between the source and drain even when the gate voltage is 0V. It is difficult to control the transistor as a circuit, so the threshold A transistor with a negative value of the voltage is not suitable for application to an integrated circuit of a semiconductor device.

[0007] In view of this, in one embodiment of the present invention, an n-channel semiconductor device using an oxide semiconductor for a channel formation region is In the transistor, a normally-off switching element having a positive threshold voltage is realized. It is an object of the present invention to provide a transistor structure and a manufacturing method thereof.

[0008] In addition, depending on the material and manufacturing conditions, the manufactured transistor may not be normally off. Even in this case, it is important to approach the normally-off characteristics. The threshold voltage is negative, so even if the transistor is normally on, the threshold voltage is zero. It is also an object of the present invention to provide a structure and a manufacturing method thereof that approach the above.

[0009] One embodiment of the present invention is to solve at least one of the above problems. [Means for solving the problem]

[0010] In one embodiment of the present invention, a first gate electrode layer and a second gate electrode layer are provided with an insulating layer therebetween. a channel formation region in the oxide semiconductor stack having a thickness of The transistor is configured to be smaller than the other regions. One of the gate electrode layers is provided as a so-called back gate for controlling the threshold voltage. By controlling the potential applied to the back gate, the threshold voltage of the transistor can be controlled. Since the value voltage can be controlled, it is easy to keep the transistor normally off. More specifically, for example, the following configuration can be adopted.

[0011] One aspect of the present invention is a semiconductor device comprising a first gate electrode layer on an insulating surface and a first gate electrode layer on the first gate electrode layer. an insulating layer and a first oxide semiconductor layer overlapping with the first gate electrode layer with the first insulating layer interposed therebetween; and an oxide semiconductor stack including a second oxide semiconductor layer and a second oxide semiconductor layer on or in contact with the second oxide semiconductor layer. A source electrode layer and a drain electrode layer, a part of the oxide semiconductor stack, the source electrode layer and the drain electrode layer, a second insulating layer in contact with the oxide semiconductor layer and a second insulating layer overlapping the oxide semiconductor stack with the second insulating layer interposed therebetween; a second gate electrode layer having a first insulating layer and a second insulating layer formed on the first insulating layer; The thickness of the region of the semiconductor device is smaller than the thickness of the region in contact with the source electrode layer and the drain electrode layer. It is a location.

[0012] Another embodiment of the present invention is a method for manufacturing a semiconductor device including: a first gate electrode layer on an insulating surface; a first insulating layer, a first oxide semiconductor layer overlapping the first gate electrode layer with the first insulating layer interposed therebetween; an oxide semiconductor stack including a conductor layer and a second oxide semiconductor layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a part of the oxide semiconductor stack, the source electrode layer and the drain electrode layer a second insulating layer in contact with the drain electrode layer and the oxide semiconductor stacked layer through the second insulating layer; a second gate electrode layer overlapping the first oxide semiconductor layer and the second oxide semiconductor layer; The insulating layer has the same constituent elements but a different composition, and is the second insulating layer in the oxide semiconductor stack. The thickness of the region in contact with the insulating layer is larger than the thickness of the region in contact with the source and drain electrode layers. It is a small semiconductor device.

[0013] In the semiconductor device, the first oxide semiconductor layer contains at least indium and gallium. the first oxide semiconductor layer contains indium and the first oxide semiconductor layer contains gallium; Larger is preferable.

[0014] Alternatively, in the above semiconductor device, the second oxide semiconductor layer contains at least indium and and gallium, and in the second oxide semiconductor layer, the composition of indium is It is preferable that the composition is equal to or less than that.

[0015] In the semiconductor device, at least the first gate electrode layer and the second gate electrode layer In either case, it is preferable to use a conductive layer having a work function of 5 electron volts or more. For example, it is preferable to provide a conductive layer using an In-Ga-Zn-O film containing nitrogen.

[0016] The effects of the above-described configuration, which is one embodiment of the disclosed invention, can be explained as follows. Please note that the following explanation is merely a consideration.

[0017] Oxide semiconductor transistors are Nch accumulation type transistors that use electrons as majority carriers. It can be considered as an OSFET. It is an Nch inversion MOSFET using silicon. By applying a gate voltage, an inversion layer is formed near the surface of the active layer (here, silicon). On the other hand, in an accumulation-type MOSFET, the active The electrons, which are the majority carriers, are accumulated on the surface of the conductive layer (here, the oxide semiconductor layer) to allow the current to flow. A channel is formed. Also, in the off state, a negative gate voltage is applied to completely deplete the entire film.

[0018] In an accumulation-type MOSFET, in addition to the first current flowing through the surface (accumulation) as the on-current, there is a significant difference from an inversion-type MOSFET in that there is a second current flowing through the entire film thickness direction of the active layer. Here, let the threshold voltage of the first current be Vth , and the threshold voltage of the second current be Vth . Then, when the gate voltage Vg is lower than the threshold voltage of the second current ( _2 Vg < Vth _2 ), the entire film thickness direction of the active layer is depleted (completely depleted), and the transistor is in the off state. When the gate voltage Vg is increased and the gate voltage Vg is higher than the threshold voltage of the second current Vth _2 and lower than the threshold voltage of the first current Vth _1 _2 <Vg < Vth _1 _1 (Vth _2 <Vg < Vth _1 ), the depletion layer width becomes narrow (partial depletion state), and the second current flows from the back channel side, and the transistor is in the on state. When the gate voltage Vg is further increased and the gate voltage Vg exceeds the threshold voltage of the first current (Vth _1 _1 <Vg), the depletion layer disappears, carriers (electrons) are accumulated on the surface of the active layer, and the first current flows.

[0019] [[ID=S47]]The threshold voltage Vth _2 of the second current and the threshold voltage of the first current Vth _1 in an Nch accumulation-type MOSFET can be expressed as in the following equations (1 ) and equation (2) using the gradual channel approximation.

[0020]

number

[0021] In addition, V FB denotes the flat band voltage, and C s denotes the capacitance of the active layer, and C ox Gate indicates the capacitance of the insulating layer, N d denotes the donor density, and t s indicates the film thickness of the active layer.

[0022] From the above equation (1), the donor density (N d ) and the thickness of the active layer (t s ) becomes larger. , the threshold voltage Vth of the second current _2 It can be seen that the value fluctuates (shifts) in the negative direction. Furthermore, from equations (1) and (2), the flat band voltage (V FB ) to increase the That is, increasing the work function of the gate electrode layer is the key to the improvement of Nch accumulation type MOSFETs. Threshold voltage (Vth _1 and Vth _2 ) is important for the positive shift of Light.

[0023] Next, the relationship between the thickness of the oxide semiconductor layer ( T OS ) and donor density (N d ) dependence was calculated by device simulation.

[0024] The transistor structure assumed in the calculation is shown in Figure 9. The conditions used in the calculation are shown in Table 1. .

[0025] As shown in FIG. 9, in this calculation, the oxide film formed on the insulating layer 302 having a thickness of 300 nm is The oxide semiconductor layer 306 is connected to a source electrode layer 308a and a drain electrode layer 308b on the oxide semiconductor layer 306. The source electrode layer 308a and the drain electrode layer 308b are covered with an oxide semiconductor. A gate insulating layer 310 is partially in contact with the semiconductor layer 306, and an oxide semiconductor is formed through the gate insulating layer 310. A transistor 320 including a gate electrode layer 112 overlapping with a conductor layer 306 was used.

[0026] [Table 1]

[0027] The calculated IdVg characteristics (Vd=0.1V) are shown in Figures 10(A) to 10(C). 10A to 10C show the donor densities assumed to be contained in the oxide semiconductor layer. (N d ) are 1×10 18 cm -3 (Figure 10(A)), 1 × 10 17 cm -3 (figure 10(B)), 1×10 16 cm -3 The transistor characteristics in the case of (Figure 10(C)) are shown. .

[0028] As shown in Figure 10(A), the donor density (N d ) is high, the thickness of the oxide semiconductor layer When the thickness is thin (for example, 10 nm), good electrical properties are obtained. As the thickness of the body layer increases, the body becomes normally on.

[0029] On the other hand, as shown in Figure 10(B), the donor density (N d ) to 1×10 17 cm -3 reduced to By doing so, the negative shift in characteristics caused by the thickening of the oxide semiconductor layer is reduced. In addition, the on-current (Ion ) is independent of the thickness of the oxide semiconductor layer and provides almost constant results. In addition, as shown in FIG. 10(C), the donor density (N d ) to 1×10 16 cm -3 By further reducing the thickness of the oxide semiconductor layer, the negative shift in characteristics due to the thickening of the oxide semiconductor layer can be prevented. The to is rarely confirmed.

[0030] From the above calculation results, it is considered that in order to achieve a normally-off transistor, an oxide semiconductor It was confirmed that it is important to thin the layer and reduce the donor density contained in the oxide semiconductor layer. do.

[0031] In a transistor according to one embodiment of the present invention, the thickness of the channel formation region is larger than that of the other region (e.g., a region in contact with the source electrode layer and the drain electrode layer) This allows the threshold voltage of the transistor to shift in the negative direction. It can be suppressed.

[0032] Next, we considered the causes of normally-on transistors. In the case of the oxide semiconductor layer having the characteristics shown in FIG. 10A, the thickness of the oxide semiconductor layer is 50 nm and the donor density is high. Degrees are 1 x 10 18 cm -3 The transistor used was:

[0033] As mentioned above, in an accumulation-type MOSFET, the on-current flows through the active layer surface (accumulation). There is a first current and a second current that flows through the entire active layer in the film thickness direction. By taking the second derivative of the Vg characteristic, it is possible to distinguish between the first current and the second current. It is known that the oxide semiconductor layer has a thickness of 50 nm and the donor density is 1×1. 0 18 cm -3 The IdVg characteristics of a transistor (solid line) and its second derivative (bold line) are A graph of the obtained values ​​is shown.

[0034] As shown in Figure 11(A), the line obtained by second-order differentiation of the IdVg characteristics has two peaks. From here, the gate voltage Vg is swept from -3V to the positive direction, and Vg reaches the first line. At the peak (Vg = -1.52 (V)), a second current begins to flow, and the second peak ( It can be assumed that the first current begins to flow when Vg is near 0.30 (V). is expressed as the equations (1) and (2) using the gradual channel approximation shown above, and the equations shown in Table 1. Calculation result after substituting parameter values ​​(Vth _2 =-1.56V, Vth _1 =0. 36V) is almost the same.

[0035] Therefore, in order to make the transistor normally off, the lower of the first and second currents is It is effective to suppress the second current that flows at a low gate voltage.

[0036] Figure 11(B) shows the current density distribution in the film thickness direction at each gate voltage. When -3V is applied to g, the transistor is in the off state and the channel region is When the gate voltage Vg is equal to or greater than Vth, the electrons are repelled and the state becomes fully depleted. _2 When it gets bigger, The channel region becomes partially depleted, and a second current begins to flow through the back channel. Voltage Vg is Vth _2 <Vg<Vth _1 At this time, the second current is dominant in the on-state current. However, the gate voltage Vg is Vth _1If it is larger, the second current does not increase and the gate The current density at the interface of the insulating layer is increased, and the current density of the second current is higher than that of the first current. The current density is two orders of magnitude smaller. That is, when the transistor is in the on state, the first current is dominant. You will realize something.

[0037] A transistor according to one embodiment of the present invention has a structure in which an oxide semiconductor layer including a channel formation region is sandwiched between two semiconductor layers. The device has a first gate electrode layer and a second gate electrode layer, and a bias voltage is applied to one of the gate electrode layers. By applying this voltage, the generation of the second current on the back channel side is suppressed. This makes it possible to shift the threshold voltage of the capacitor in the positive direction.

[0038] In addition, a conductive layer with a large work function (for example, 5 electron volts or more) is used as the gate electrode layer. By using this, it is possible to shift the threshold voltage in a more positive direction. As a large conductive layer, for example, a layer containing nitrogen at a concentration higher than that of the oxide semiconductor layer An In-Ga-Zn-O film can be used.

[0039] The gate insulating layer (the insulating layer provided between the gate electrode layer and the oxide semiconductor layer) is When positive ions such as thorium are included, a positive bias voltage is applied to the gate electrode layer. When the gate insulating layer is applied, positive ions move to the interface between the gate insulating layer and the oxide semiconductor layer. This causes the threshold voltage of the transistor to shift in the negative direction. By using a material with a large work function for the gate electrode layer, This allows the positive ions at the interface to move to the gate electrode layer side.

[0040] In Fig. 12, the oxide semiconductor layer is an In-Ga-Zn-O film, and the gate electrode layer is an I-type film containing nitrogen. An example of a schematic diagram of the band structure in an OSFET model with an n-Ga-Zn-O film is shown. Here, an oxide semiconductor layer (represented as OS in FIG. 12) of In-Ga-Zn-O The electron affinity of the film is set to 4.6 eV, the band gap is set to 3.2 eV, and the gate voltage is set to The work function of the nitrogen-containing In-Ga-Zn-O film, which is the electrode layer (denoted as GE in Fig. 12), is The energy density is 5.6 eV and the band gap is 1.8 eV. The oxide semiconductor layer is n-type, and its Fermi level E F is higher than the center of the band gap Located at the top.

[0041] As shown in Figure 12, the energy band of the In-Ga-Zn-O film is The junction bends upward at the interface (denoted as GI in Fig. 12), and the flat band voltage is V FB >0 and Therefore, in the gate insulating layer, the interface between the oxide semiconductor layer and the gate electrode layer An electric field is generated toward the oxide semiconductor layer, and the interface with the gate electrode layer is positively charged. Therefore, the positive ions at the interface with the oxide semiconductor layer are The electrons move toward the port electrode layer.

[0042] As described above, it is possible to use a material with a large work function (e.g., In-Ga- containing nitrogen) for the gate electrode layer. By using a Zn-O film, positive ions at the oxide semiconductor layer interface can be transferred to the gate electrode. It also has the effect of attracting the particles to the layer side. [Effects of the Invention]

[0043] According to one embodiment of the present invention, a normally-off transistor can be realized. Even if the transistor is normally on, the threshold voltage of the transistor is made close to 0V. It is possible. [Brief explanation of the drawings]

[0044] [Figure 1] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 2] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device. [Figure 3] 1A and 1B are a cross-sectional view and a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 4] 1A and 1B are a circuit diagram and a perspective view illustrating one embodiment of a semiconductor device. [Figure 5] 1A and 1B are a block diagram illustrating one embodiment of a semiconductor device and a partial circuit diagram thereof; [Figure 6] 1A to 1C illustrate electronic devices. [Figure 7] 1A to 1C illustrate electronic devices. [Figure 8] 1A to 1C illustrate electronic devices. [Figure 9] FIG. 10 shows the structure of a transistor used in calculations. [Figure 10] FIG. 10 is a graph showing the IdVg characteristics obtained by calculation. [Figure 11] (A) IdVg characteristics and their second derivatives. (B) Current density distribution in the film thickness direction at each gate voltage. [Figure 12] Schematic diagram of the band structure in the OSFET model. [Figure 13] 1A and 1B are a cross-sectional view and a circuit diagram illustrating one embodiment of a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0045] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Therefore, the present invention should not be construed as being limited to the description of the following embodiments. It is not something that can be done.

[0046] In the configuration of the present invention described below, the same parts or parts having similar functions are The same reference numerals are used in common between different drawings, and repeated explanations thereof will be omitted. When referring to a part with the same function, the hatch pattern is the same, and when no symbol is given, There is a match.

[0047] In each drawing described in this specification, the size of each component, the thickness of the film, or the area is not clearly indicated. The figures may be exaggerated for clarity and are not necessarily limited to that scale.

[0048] In this specification, ordinal numbers such as first, second, etc. are used for convenience. It does not indicate the order of processes or stacking layers. It does not indicate a specific name for the purpose of identification.

[0049] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. refers to the state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This includes cases where the angle is between 85° and 95°.

[0050] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. . (Embodiment 1) In this embodiment mode, one mode of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. In this embodiment, a transistor having an oxide semiconductor stack will be described as an example of a semiconductor device. A transistor is shown.

[0051] 1A and 1B show examples of the structure of a transistor 120. 1(B) is a plan view of the transistor 120, and FIG. 1(B) is a plan view of the transistor 120 along the chain line X1-Y1 in FIG. 1(A). Cross-sectional view.

[0052] As shown in FIG. 1B, which is a cross-sectional view in the channel length direction, the transistor 120 has an insulating surface. A gate electrode layer 102, an insulating layer 104, and an oxide semiconductor layer 105 are formed on a substrate 100 having a surface. The oxide semiconductor stack 106 includes the oxide semiconductor layer 106a and the oxide semiconductor layer 106b, and the source electrode layer 10 8a, a drain electrode layer 108b, an insulating layer 110, and a gate electrode layer 112. It is composed.

[0053] In the transistor 120, the gate electrode layer 102 is connected to an oxide semiconductor layer via an insulating layer 104. The gate electrode layer 112 is formed on the oxide semiconductor stack 106 via the insulating layer 110 . The oxide semiconductor layer 106b is on and in contact with the oxide semiconductor layer 106a. The source electrode layer 108a and the drain electrode layer 108b are formed on the oxide semiconductor layer 10 The insulating layer 110 is in contact with the oxide semiconductor stack 106 at the region 6b. A part of the layer 106 is provided on and in contact with the source electrode layer 108a and the drain electrode layer 108b. In addition, the thickness of the oxide semiconductor stack 106 in the region in contact with the insulating layer 110 is The thickness is smaller than that of a region in contact with the electrode layer 108a and the drain electrode layer 108b.

[0054] In the oxide semiconductor stack 106, the thin region is the source electrode layer 108a and the drain electrode layer 108b. When processing the conductive film that will become the inner electrode layer 108b, a part of the conductive film is etched, and After the source electrode layer 108a and the drain electrode layer 108b are formed, the oxide semiconductor stack 106 The exposed areas are formed by etching the The oxide semiconductor stack 106 is a region that functions as a channel formation region of the transistor 120. Since the film thickness of the channel forming region is small, oxygen vacancies that may be contained in the channel forming region are not contained in other regions. Therefore, by reducing the film thickness, It is also possible to reduce the donor density in the

[0055] In addition, by reducing the thickness of the channel formation region in the oxide semiconductor stack 106, The resistance of the region in contact with the source electrode layer 108a and the drain electrode layer 108b is calculated as Therefore, the source electrode layer 108a and the drain electrode layer 108b can be reduced in comparison with the region. This makes it possible to reduce the contact resistance with 108b.

[0056] As described above, in a transistor using an oxide semiconductor layer, the oxide semiconductor of the active layer Thinning the semiconductor layer and reducing the donor density achieved a normally-off transistor. The transistor 120 described in this embodiment has a channel formation region Since the oxide semiconductor stack 106 having a small thickness is included, the threshold voltage of the transistor It is possible to suppress fluctuations in the negative voltage direction.

[0057] In this embodiment, the oxide semiconductor layer 106b in the oxide semiconductor stack 106 By etching the part of the oxide semiconductor stack 106, the oxide semiconductor stack 106 is thin. However, the embodiment of the present invention is not limited to this, and the oxide A partial region of the semiconductor layer 106a is etched to form a region with a small film thickness. Alternatively, a part of the oxide semiconductor layer 106a and the oxide semiconductor layer 106b may be etched. By this, a region with a small film thickness may be formed.

[0058] The oxide semiconductor layer 106b included in the oxide semiconductor stack 106 is made of indium (In an oxide semiconductor containing at least In and gallium (Ga), the content of which satisfies the following relationship: In≦Ga It is preferable to use Ga. Compared with In, the formation energy of oxygen vacancies is higher, and Since defects are unlikely to occur, oxides with a composition of In≦Ga are less likely to occur than oxides with a composition of In>Ga. By applying such oxide semiconductor materials, The reliability of the transistor can be improved.

[0059] The oxide semiconductor layer 106a included in the oxide semiconductor stack 106 is made of In and Ga. It is preferable to use an oxide semiconductor containing at least In and Ga, and the content of In is greater than Ga. In oxide semiconductors, the s orbitals of heavy metals mainly contribute to carrier conduction, and the inclusion of In Increasing the proportion of s orbitals tends to increase the overlap, so In>G An oxide having a composition of a has a higher mobility than an oxide having a composition of In≦Ga. Therefore, when a channel is formed in the oxide semiconductor layer 106a, the mobility of the transistor can be improved.

[0060] The thickness of the oxide semiconductor layer 106a is preferably 3 nm to 15 nm. It is more preferable that the thickness of the source electrode layer 108a and the drain electrode layer 108b is 100 nm or more and 12 nm or less. The thickness of the oxide semiconductor layer 106b in the region in contact with the oxide electrode layer 108b is 3 nm to 15 nm. It is preferable that the thickness is 5 nm or less and more preferable that the thickness is 5 nm or more and 12 nm or less. In the oxide semiconductor stack 106, a region that functions as a channel formation region (a source electrode layer The thickness of the region between the drain electrode layer 108a and the drain electrode layer 108b is 3 nm or more and less than 20 nm. It is preferable to set the thickness to 5 nm or more and less than 15 nm.

[0061] The insulating layer 104 in contact with the oxide semiconductor layer 106a contains oxygen in excess of the stoichiometric composition. It is preferable that the oxide semiconductor layer 10 includes a region containing oxygen (hereinafter also referred to as an oxygen excess region). The insulating layer 104 in contact with the oxide semiconductor layer 106a includes an oxygen-excess region, so that oxygen is Therefore, oxygen can be prevented from being released from the oxide semiconductor layer 106a. Similarly, the oxide semiconductor layer 106b and the oxide semiconductor layer 106c can be formed by the same method. The adjacent insulating layer 110 also preferably contains an oxygen excess region.

[0062] The gate electrode layer 102 is formed by insulating the insulating layer 104 and the oxide semiconductor layer 106. a material having a work function greater than that of a, preferably greater than 1 electron volt or more Similarly, the gate electrode layer 112 is preferably made of a material having a work function of at least At least the surface in contact with the insulating layer 110 is made of a material having a work function larger than that of the oxide semiconductor layer 106b. A material having a work function, more preferably a material having a work function greater than 1 electron volt, is used. It is desirable that the material is, for example, an In-Ga-Zn-O film containing nitrogen, Nitrogen-containing In-Sn-O film, nitrogen-containing In-Ga-O film, nitrogen-containing In-Zn-O film film, Sn-O film containing nitrogen, In-O film containing nitrogen, metal nitride film (indium nitride film, Zinc nitride film, tantalum nitride film, tungsten nitride film, etc.) can be used. The film has a work function of 5 electron volts or more, which makes the threshold voltage of the transistor positive. For example, nitrogen can be used to realize a normally-off switching transistor. When an In—Ga—Zn—O film containing In—Ga—Zn—O is used, at least the oxide semiconductor layer 106a and the oxide It is preferable to use an In-Ga-Zn-O film containing nitrogen at a higher concentration than the compound semiconductor layer 106b. stomach.

[0063] In this embodiment, the gate electrode layer 102 is an electrode layer that functions as a back gate. The potential can be set appropriately to a fixed potential, GND, or the like. By controlling the gate voltage applied to the transistor 120, the threshold voltage of the transistor 120 is controlled. Therefore, the transistor 120 can be a normally-off type.

[0064] Furthermore, when a negative bias voltage is applied to the gate electrode layer 102, an insulator layer 104 Positive ions that can be contained as pure substances (e.g., Na + etc.) to the gate electrode layer 102 side It can be done.

[0065] An example of a method for manufacturing the transistor 120 will be described below with reference to FIGS.

[0066] First, a gate electrode layer 102 is formed over a substrate 100 having an insulating surface.

[0067] There are no major restrictions on the substrate that can be used for the substrate 100 having an insulating surface, but at least In either case, it is necessary to have heat resistance to the extent that it can withstand subsequent heat treatment. Glass substrates such as borosilicate glass and aluminoborosilicate glass, ceramic substrates, and quartz substrates A substrate such as a silicon substrate or a sapphire substrate can be used. crystalline semiconductor substrate, polycrystalline semiconductor substrate, compound semiconductor substrate such as silicon germanium, SOI A substrate or the like can be applied, and a substrate having a semiconductor element mounted thereon is called a substrate 100. It may also be used as.

[0068] The material of the gate electrode layer 102 is molybdenum, titanium, tantalum, tungsten, aluminum, or the like. Metallic materials such as aluminum, copper, chromium, neodymium, scandium, etc., or alloys containing these as the main components The gate electrode layer 102 can be formed using an impurity source such as phosphorus. Semiconductor films, such as polycrystalline silicon films doped with silicon, and silicon films such as nickel silicide The gate electrode layer 102 may have a single layer structure or a stacked layer structure. The gate electrode layer 102 may have a tapered shape, for example, with a taper angle of 30° or more. The taper angle is the angle between the side surface of the layer having the tapered shape and the surface of the layer. This refers to the angle between the bottom surface of the layer.

[0069] The material of the gate electrode layer 102 includes indium oxide, tin oxide, and tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium oxide, indium tin oxide with titanium oxide, indium oxide zinc oxide, acid Conductive materials such as silicon dioxide doped indium tin oxide can also be applied.

[0070] The gate electrode layer 102 is insulated at least on the side that comes into contact with the insulating layer 104 to be formed later. The oxide semiconductor layer 104 has a work function larger than that of the oxide semiconductor layer 106. It is preferable to use a material having a work function larger than 1 electron volt, more preferably a material having a work function larger than 1 electron volt. As a conductive material with a large work function, for example, a metal oxide containing nitrogen is used. It is possible.

[0071] Next, an insulating layer 103 is formed on the gate electrode layer 102 so as to cover the gate electrode layer 102. The insulating layer 103 is formed by depositing silicon oxide by plasma CVD, sputtering, or the like. silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, A single layer or a laminated structure of a film containing gallium oxide, zinc gallium oxide, or a mixture of these materials is provided. It can be done.

[0072] The insulating layer 103 is a layer that will be processed later to become the insulating layer 104 that is in contact with the oxide semiconductor stack 106. Therefore, the insulating layer 103 preferably has an oxygen excess region. To provide the oxygen excess region, for example, the insulating layer 103 may be formed in an oxygen atmosphere. Alternatively, oxygen is introduced into the insulating layer 103 after the film formation to form an oxygen-excess region in the insulating layer 103. Good too.

[0073] In this embodiment, the insulating layer 103 is provided with oxygen 400 (at least oxygen radicals, oxygen oxygen atoms or oxygen ions) are introduced to form an oxygen-excess region 402 (FIG. 2( A)). The oxygen introduction method includes ion implantation, ion doping, plasma ion implantation, etc. Possible methods include ion implantation, plasma treatment, and the like.

[0074] In FIG. 2A, the peak position of oxygen introduced into the insulating layer 103 is clearly indicated by a dotted line. This region is illustrated as an oxygen excess region 402. The depth of oxygen introduction and the amount of introduced oxygen are The distribution of elements is not limited to the structure shown in FIG.

[0075] Next, the surface of the insulating layer 103 is planarized to form an insulating layer 104 (FIG. 2(B)). The planarization process is not particularly limited, but may be a polishing process (for example, chemical mechanical polishing The method includes dry etching, plasma treatment, etc., and a combination of these methods can be used. It is also acceptable to do so.

[0076] Note that the planarization treatment of the insulating layer 103 is performed without removing the oxygen excess region 402. The introduction depth of the oxygen 400 and the thickness of the insulating layer 103 to be removed are set appropriately.

[0077] In addition, the insulating layer is made of a material that reduces impurities such as hydrogen (including water and hydroxyl groups) and is free from excessive oxygen. To achieve this state, the insulating layer 104 (or the insulating layer 103 before planarization treatment) is subjected to hydrogen or hydrogenated treatment. A heat treatment may be carried out to remove (dehydrate or dehydrogenate) the compound.

[0078] Next, an oxide semiconductor film and an oxide semiconductor film to be the oxide semiconductor layer 106a are formed on the insulating layer 104. An oxide semiconductor film that will become the conductor layer 106b is stacked and processed into an island shape to form the oxide semiconductor layer 106a. and the oxide semiconductor layer 106b are formed (see FIG. 2C). ).

[0079] The oxide semiconductor layer 106a and the oxide semiconductor layer 106b may each have an amorphous structure. The oxide semiconductor layer 106a or 106b may have an amorphous structure or a crystalline structure. In the case of the above structure, the oxide semiconductor stack 106 is subjected to heat treatment in a later manufacturing step. The amorphous oxide semiconductor layer may be crystallized by the heat treatment. The treatment temperature is 250° C. or higher and 700° C. or lower, preferably 400° C. or higher, more preferably The temperature is set to 500° C. or higher, and more preferably 550° C. or higher. It is also possible to combine this with other heat treatments in the process.

[0080] The oxide semiconductor films to be the oxide semiconductor layers 106a and 106b are formed by the following method. , sputtering method, MBE (Molecular Beam Epitaxy) method, C VD method, pulsed laser deposition method, ALD (Atomic Layer Deposition n) Method etc. can be used as appropriate.

[0081] When forming an oxide semiconductor film, the hydrogen concentration in the oxide semiconductor film is reduced as much as possible. In order to reduce the hydrogen concentration, for example, a film is formed by using a sputtering method. When performing the above, hydrogen, water, etc. are used as the atmospheric gas to be supplied into the film formation chamber of the sputtering device. High-purity rare gas (typically argon) from which impurities such as hydroxyl groups or hydrides have been removed , oxygen, and a mixed gas of a rare gas and oxygen are used as appropriate.

[0082] In addition, the residual moisture in the film formation chamber is removed and sputtering gas from which hydrogen and moisture have been removed is introduced. By forming the oxide semiconductor film in this manner, the hydrogen concentration in the formed oxide semiconductor film can be reduced. To remove residual moisture in the deposition chamber, an adsorption type vacuum pump, such as a cryopump, is used. It is preferable to use a turbo pump, an ion pump, or a titanium sublimation pump. A molecular pump with a cold trap may be used. , hydrogen molecules, water (H2O), and other compounds containing hydrogen atoms (preferably compounds containing carbon atoms) Since the pumping capacity of the film deposition chamber is high, the film deposition chamber is evacuated using a cryopump. The concentration of impurities contained in the nitride semiconductor film can be reduced.

[0083] In addition, when the oxide semiconductor film is formed by a sputtering method, the metal oxide substrate used for the film formation The relative density (filling rate) of the get is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. % or less. By using a metal oxide target with a high relative density, the oxide film The compound semiconductor layer can be made into a dense film.

[0084] In addition, the oxide semiconductor film can be formed while the substrate 100 is maintained at a high temperature. This is effective in reducing the concentration of impurities that may be contained in the film. The substrate temperature is preferably 150°C or higher and 450°C or lower, and more preferably 200°C or higher and 300°C or lower. The temperature should be 50°C or less. In addition, by heating the substrate at a high temperature during film formation, the crystalline oxide semiconductor A conductive film can be formed.

[0085] The structure of the oxide semiconductor film will be described below.

[0086] Oxide semiconductor films are roughly classified into single-crystal oxide semiconductor films and non-single-crystal oxide semiconductor films. The single-crystal oxide semiconductor film includes an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, and a polycrystalline oxide semiconductor film. Physical semiconductor film, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor films, etc.

[0087] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and is an oxide film that does not contain a crystalline component. The film is a compound semiconductor film. It does not have any crystalline parts even in the microscopic areas, and the entire film has a completely amorphous structure. A typical example is an oxide semiconductor film.

[0088] The microcrystalline oxide semiconductor film is made up of, for example, microcrystals (nanocrystals) having a size of 1 nm or more and less than 10 nm. Therefore, the microcrystalline oxide semiconductor film has a lower atomic number than the amorphous oxide semiconductor film. Therefore, the microcrystalline oxide semiconductor film has a higher order of molecular arrangement than the amorphous oxide semiconductor film. The defect level density is also low.

[0089] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts. The crystal part is so large that it fits inside a cube with a side length of less than 100 nm. The crystals contained in the S film are cubic with sides of less than 10 nm, 5 nm, or 3 nm. The CAAC-OS film has a smaller defect density than the microcrystalline oxide semiconductor film. The CAAC-OS film has a low density of recessed states. .

[0090] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a crystalline microscope, clear boundaries between the crystals, i.e., crystal boundaries, are clearly visible. It is not possible to confirm the grain boundary. It can be said that the AC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0091] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). ) It can be confirmed that the metal atoms are arranged in layers in the crystalline part. Each layer has a surface on which the CAAC-OS film is formed (also referred to as a surface on which the CAAC-OS film is formed) or an uneven surface on which the CAAC-OS film is formed. The shape reflects this and is aligned parallel to the surface on which the CAAC-OS film is formed or the top surface.

[0092] On the other hand, the CAAC-OS film was observed by TEM from a direction approximately perpendicular to the sample surface (planar TEM). When observed, it was found that the metal atoms were arranged in triangular or hexagonal shapes in the crystals. However, there is no regularity in the arrangement of metal atoms between different crystal parts. stomach.

[0093] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It turns out that there are.

[0094] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was found by structural analysis using the device. In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0095] On the other hand, in-pl X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is In contrast, in the case of the CAAC-OS film, 2θ is set to 5 Even when the φ is fixed at around 6° and scanned, no clear peak appears.

[0096] From the above, it is concluded that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. Although it is regular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. Therefore, the layered arrangement confirmed by the cross-sectional TEM observation mentioned above is consistent with the above. Each layer of aligned metal atoms is a plane parallel to the ab plane of the crystal.

[0097] The crystalline part is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed or the surface on which the CAAC-OS film is formed. The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it may not be parallel to the normal vector of the upper surface.

[0098] The crystallinity of the CAAC-OS film may not be uniform. When the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface, The area near the surface may have a higher degree of crystallinity than the area near the surface to be formed. When impurities are added to a C-OS film, the crystallinity of the region where the impurities are added changes, resulting in partial In some cases, regions of different crystallinity may be formed.

[0099] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ around 31°, a peak also appeared at 2θ around 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferable that the peak is exhibited at 2θ of around 36° and that the peak is not exhibited at 2θ of around 36°.

[0100] The electrical characteristics of a transistor using a CAAC-OS film change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0101] The oxide semiconductor layer 106a and the oxide semiconductor layer 106b are each an amorphous oxide semiconductor. The structure may be any of a conductive film, a microcrystalline oxide semiconductor film, or a CAAC-OS film. It may also be a mixed film of two or more kinds. The film may be a stacked film having two or more of a semiconductor film and a CAAC-OS film.

[0102] A CAAC-OS film is used as the oxide semiconductor layer 106a and / or the oxide semiconductor layer 106b. When using a fluorine-containing compound, the CAAC-OS film can be obtained by, for example, setting the film formation temperature at 200° C. or higher. A method in which an oxide semiconductor film is formed at 450°C or less and the c-axis is oriented approximately perpendicular to the surface. Alternatively, after forming a thin oxide semiconductor film, a Alternatively, a thin film may be used as the first layer to orient the c-axis approximately perpendicular to the surface by heat treatment. After forming the film, heat treatment is performed at 200°C to 700°C, and the second layer is formed on the surface. The c-axis may be oriented approximately vertically.

[0103] The oxide semiconductor layer 106a and the oxide semiconductor layer 106b contain at least indium (In In particular, an oxide semiconductor containing indium and zinc (Zn) is used. In addition, it is preferable to use the oxide semiconductor. In addition to these, it contains gallium (Ga) as a stabilizer to reduce the As a stabilizer, tin (Sn), hafnium (Hf), aluminum (Al), etc. are preferable. It is preferable that the alloy contains one or more of aluminum (Al) and zirconium (Zr). stomach.

[0104] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Tetrium) (Lu).

[0105] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxides, In-Mg oxides, In-Ga oxides, and ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides oxides, In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides , In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, I n-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide, which is an oxide of a quaternary metal, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al -Zn-based oxides, In-Sn-Hf-Zn-based oxides, In-Hf-Al-Zn-based oxides It can be used.

[0106] For example, an In-Ga-Zn oxide is an oxide having In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn is not important. Metal elements may also be included.

[0107] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) It is also possible to use a material represented by the formula: where M is selected from Ga, Fe, Mn and Co. In2SnO 5(ZnO) n A material expressed as (n>0 and n is an integer) may be used.

[0108] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3), In:Ga:Z n=2:2:1 (=2 / 5:2 / 5:1 / 5), or In:Ga:Zn=3:1:2 In-Ga-Zn oxides with atomic ratios of (=1 / 2:1 / 6:1 / 3) and their neighboring compositions Alternatively, an oxide of In:Sn:Zn=1:1:1 (=1 / 3: 1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In-Sn with an atomic ratio of In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8) It is preferable to use a -Zn-based oxide or an oxide having a composition close to that.

[0109] However, the transistor using an oxide semiconductor containing indium is not limited to these. The appropriate composition is selected according to the required electrical characteristics (field effect mobility, threshold value, variation, etc.). In addition, in order to obtain the required electrical characteristics, the carrier concentration and impurity concentration can be adjusted. The degree of crystallization, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. must be appropriate. is preferred.

[0110] For example, transistors using In-Sn-Zn oxide semiconductors can be easily fabricated with high current. However, the field effect mobility of transistors using In-Ga-Zn oxide semiconductors is In transistors, the field-effect mobility can also be increased by reducing the defect density in the bulk. Cut.

[0111] For example, when the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with c=1) is In:Ga:Zn=A:B:C (A+B+C = 1), the oxide composition is close to (aA) 2 +(bB) 2 + (cC) 2 ≦r 2 The value of r can be set to, for example, 0.05. The same applies to other oxides.

[0112] Note that the oxide semiconductor layer 106a and the oxide semiconductor layer 106b are formed by using oxide semiconductors having different crystallinity. That is, a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, A suitable combination of a crystalline semiconductor, an amorphous oxide semiconductor, or a CAAC-OS is also possible. good.

[0113] In addition, the oxide semiconductor stack 106 is subjected to the treatment of excess hydrogen ( It is preferable to carry out a heat treatment to remove (dehydrate or dehydrogenate) the organic compounds (including water and hydroxyl groups). The temperature of the heat treatment should be between 300°C and 700°C, or below the distortion point of the substrate. This heat treatment can be carried out under reduced pressure or in a nitrogen atmosphere. Hydrogen, which is an impurity that imparts hydrogen, can be removed from the oxide semiconductor.

[0114] Note that the heat treatment for dehydration or dehydrogenation can be performed after the formation of the oxide semiconductor layer. This may be done at any time during the manufacturing process of the star 120. The heat treatment for curing may be carried out multiple times, or may be carried out in combination with other heat treatments.

[0115] Note that the heat treatment for dehydration or dehydrogenation is performed before the oxide semiconductor film is processed into an island shape. This can prevent oxygen contained in the insulating layer 104 from being released by heat treatment. Therefore, it is preferable.

[0116] In heat treatment, nitrogen or rare gases such as helium, neon, and argon are mixed with water, hydrogen, etc. It is preferable that nitrogen, helium, or neon introduced into the heat treatment device is not included. The purity of the rare gas such as argon is 6N (99.9999%) or more, preferably 7N (99. 99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm or less) It is preferable to do so.

[0117] Furthermore, the oxide semiconductor stack 106 (or the oxide semiconductor film before being processed into an island shape) is heated by heat treatment. After that, high purity oxygen gas is added to the same furnace while maintaining the heating temperature or slowly cooling from the heating temperature. , high purity nitrous oxide gas, or ultra dry air (CRDS (cavity ring down lathe) When measured using a dew point meter using the laser spectroscopy method, the moisture content was 20 ppm (-5 ppm in terms of dew point). 5°C or less, preferably 1 ppm or less, more preferably 10 ppb or less) It is preferable that the oxygen gas or nitrous oxide gas does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas or nitrous oxide gas introduced into the heat treatment device is preferably 6N or more. or 7N or more (i.e., the impurity concentration in oxygen gas or nitrous oxide gas is 1 ppm or less, preferably It is preferable to set the concentration to 0.1 ppm or less. By using this method, the impurities are simultaneously removed by dehydration or dehydrogenation treatment. By supplying oxygen, which is the main component material that makes up the oxide semiconductor, The body layer can be highly purified and made i-type (intrinsic).

[0118] Furthermore, the dehydration or dehydrogenation treatment can remove oxygen, which is a main component material of the oxide semiconductor. Since there is a risk that the amount of The oxide semiconductor layer is doped with oxygen (at least one of oxygen radicals, oxygen atoms, and oxygen ions). ) may be introduced to supply oxygen into the film.

[0119] Oxygen is introduced into the oxide semiconductor layer that has been subjected to dehydration or dehydrogenation treatment to supply oxygen into the film. By this, the oxide semiconductor layer can be highly purified and made to be i-type (intrinsic). A transistor having a purified i-type (intrinsic) oxide semiconductor has low fluctuations in electrical characteristics. It is controlled and electrically stable.

[0120] When oxygen is introduced into the oxide semiconductor layer, it may be introduced directly into the oxide semiconductor layer or into a layer formed later. Oxygen may be introduced into the oxide semiconductor layer through another film such as the insulating layer 110. When introducing the material through the membrane, ion implantation, ion doping, plasma imaging, A direct ion implantation method or the like may be used. When oxygen is introduced, plasma treatment or the like can be used in addition to the above methods.

[0121] As the oxygen supply gas, a gas containing O may be used, for example, O2 gas, N2O Gas, CO2 gas, CO gas, NO2 gas, etc. can be used. The gas may contain a rare gas (for example, Ar).

[0122] For example, when oxygen ions are implanted into an oxide semiconductor layer by ion implantation, the dose is set to 1× 10 13 ions / cm 2 5x10 or more 16 ions / cm 2 The following would suffice.

[0123] Alternatively, the insulating layer in contact with the oxide semiconductor layer (the insulating layer 104 or the insulating layer 110) is heated to a temperature of 1000° C. or 1000° C. by heating the insulating layer in an atmosphere containing an excess of oxygen. and performing heat treatment in a state where the insulating layer and the oxide semiconductor layer are in contact with each other. The oxygen contained in the insulating layer in excess is diffused into the oxide semiconductor layer, and oxygen is supplied to the oxide semiconductor layer. This heat treatment may be performed in combination with other heat treatments in the manufacturing process of the transistor 120. It is also possible.

[0124] The timing of supplying oxygen to the oxide semiconductor layer is not particularly limited as long as it is after the oxide semiconductor layer is formed. The introduction of oxygen into the oxide semiconductor layer may be performed multiple times. The heat treatment and / or oxygen supply for hydration or dehydrogenation may be performed separately for each oxide semiconductor layer. Alternatively, the oxide semiconductor stack 106 may be subjected to the thermal treatment after the stack structure is formed. good.

[0125] The insulating layer 104 and the oxide semiconductor film that will become the oxide semiconductor layer 106a are continuously formed without being exposed to the air. It is preferable that the insulating layer 104 and the oxide semiconductor film are formed successively. This can prevent impurities such as hydrogen and moisture from being adsorbed on the surface of the insulating layer 104. .

[0126] Next, the source electrode layer 108a and the drain electrode layer 108b are formed over the oxide semiconductor stack 106. The conductive film 108 is formed as follows (see FIG. 2(D)). a metal film containing an element selected from the group consisting of I, Cr, Cu, Ta, Ti, Mo, and W, or the above-mentioned Metal nitride films containing elements (titanium nitride film, molybdenum nitride film, tungsten nitride film) ) or the like can be used. In addition, either the upper or lower side of a metal film such as Al or Cu can be used. Both are made of high-melting metal films such as Ti, Mo, W, etc. or their metal nitride films (titanium nitride film, A layered structure of a molybdenum nitride film, a tungsten nitride film, etc. may also be used. The conductive film used for the electrode layer 108a and the drain electrode layer 108b is a conductive metal oxide film. Conductive metal oxides include indium oxide (In2O3), Tin (SnO2), zinc oxide (ZnO), indium oxide tin oxide (In2O3-SnO 2) Indium oxide zinc oxide (In2O3-ZnO) or these metal oxide materials A material containing silicon oxide can be used.

[0127] The conductive film 108 may be an In—Ga—Zn—O film containing nitrogen, an In—Sn— O film, In-Ga-O film containing nitrogen, In-Zn-O film containing nitrogen, Sn-O film containing nitrogen Metal nitride films such as oxide films and nitrogen-containing In-O films can be used. Since the oxide semiconductor layer 106b contains the same constituent elements as the oxide semiconductor layer 106b, the interface with the oxide semiconductor layer 106b is stabilized. For example, the conductive film 108 can be formed by A stacked structure of an In-Ga-Zn-O film containing nitrogen and a tungsten film can be applied from the side. can.

[0128] Next, the conductive film 108 is selectively etched to form the source electrode layer 108a and the drain electrode layer 108b. The source electrode layer 108a and the drain electrode layer 108b are formed (see FIG. 2(E)). The source electrode layer 108a and the drain electrode layer 108b may have a tapered shape. If 8b has a tapered shape, it is possible to reduce the concentration of the electric field between the source and the drain. Therefore, it is preferable.

[0129] Furthermore, this etching process also etches a portion of the oxide semiconductor layer 106b. A thin region is formed between the source electrode layer 108a and the drain electrode layer 108b. Alternatively, after the source electrode layer 108a and the drain electrode layer 108b are formed, the exposed The oxide semiconductor layer 106b is subjected to etching treatment (for example, wet etching treatment). A thin region may be formed by forming the source electrode layer 108a and the drain electrode layer 108b. Thinning of the pole layer 108b by processing and / or subsequent etching The thickness of the oxide semiconductor layer 106b in the recessed region can be set to 1 nm or more and 2 nm or less. preferable.

[0130] Then, the exposed oxide semiconductor layer 106b, the source electrode layer 108a, and the drain electrode layer 108b are An insulating layer 110 is formed to cover the gate insulating layer 08b. On the insulating layer 110, a gate electrode layer 112 (which is a wiring formed in the same layer) is formed. A conductive film serving as a gate electrode layer 112 is formed by selectively etching the conductive film. (See Figure 2(F)).

[0131] The insulating layer 110 can be made of the same material and by the same film formation method as the insulating layer 104. The thickness of the insulating layer 110 is preferably 5 nm or more and 30 nm or less. It is more preferable that the thickness is between 100 nm and 22 nm.

[0132] The gate electrode layer 112 is formed using the same material and film formation method as the gate electrode layer 102. Note that the gate electrode layer 112 can be formed by forming a gate electrode layer 113 on a layer in contact with at least the insulating layer 110. The surface side is preferably made of a material having a work function larger than that of the oxide semiconductor layer 106b. It is preferable to use a material having a work function greater than 1 electron volt.

[0133] In this manner, the transistor 120 of this embodiment can be formed.

[0134] In the transistor 120 described in this embodiment, the thickness of the channel formation region is For example, the region in contact with the source electrode layer 108a and the drain electrode layer 108b, which is an oxide semiconductor, The oxide semiconductor laminate 106 is smaller than the thickness of the conductive layer 101 (excluding the tapered portion at the end of the conductive layer). This suppresses the negative shift of the threshold voltage of the transistor 120. It is possible.

[0135] The transistor 120 described in this embodiment includes an oxide semiconductor including a channel formation region. The gate electrode layer 102 and the gate electrode layer 112 are sandwiched between the stacked layers 106. By applying a negative bias voltage to 2, a second current is generated on the back channel side. Therefore, the threshold voltage of the transistor 120 can be shifted in the positive direction. It becomes possible.

[0136] As described above, the structures, methods, etc. described in this embodiment are applicable to the structures, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0137] (Embodiment 2) In this embodiment, as an example of a semiconductor device to which the transistor described in Embodiment 1 is applied, It is possible to retain memory contents even when power is not supplied, and there is no limit to the number of times it can be written. The semiconductor device without the above-mentioned structure will be described with reference to the drawings.

[0138] FIG. 3 shows an example of the configuration of a semiconductor device. FIG. 3(A) shows a cross-sectional view of the semiconductor device, and FIG. B) shows the circuit diagram of the semiconductor device.

[0139] The semiconductor device shown in FIG. 3A includes a transistor 160 using a first semiconductor material in the lower part. The transistor 162 is made of a second semiconductor material. The transistor of one embodiment of the present invention described in Embodiment 1 is used as the transistor 162. It is possible.

[0140] Here, the first and second semiconductor materials have different bandgaps. For example, it is desirable to use a semiconductor material other than an oxide semiconductor (silicon The second semiconductor material may be an oxide semiconductor. Transistors using oxide semiconductors can easily operate at high speed. The transistor's characteristics allow it to retain charge for a long period of time.

[0141] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that p-channel transistors can also be used. In order to retain the capacitance, the transistor using an oxide semiconductor as described in Embodiment 1 is used. In addition to being used as a resistor 162, the semiconductor device is also used in semiconductor devices, such as materials and structures of semiconductor devices. The specific configuration of the conductor device need not be limited to that shown here.

[0142] The transistor 160 in FIG. 3A includes a semiconductor material (e.g., silicon). A channel forming region 216 is provided on the substrate 200, and a The impurity region 214 and the high concentration impurity region 220 (together referred to as simply an impurity region) are provided in the The intermetallic compound region 224 is in contact with the high concentration impurity region 220. A gate insulating layer 208 is provided on the panel forming region 216, and a gate insulating layer 209 is provided on the gate insulating layer 208. The gate electrode layer 210 is formed by insulating a gate electrode layer 210 with a sidewall insulating film provided on the side of the gate electrode layer 210. It has an edge layer 218, an electrode layer 212a, and an electrode layer 212b.

[0143] The electrode layer 212a and the electrode layer 212b function as a source electrode layer or a drain electrode layer. The gate electrode layer 210 is a functional electrode layer, and a contact hole is provided in the insulating layer 228 on the gate electrode layer 210. The insulating layer 228 is electrically connected to the intermetallic compound region 224 through the insulating layer 228. The insulating film may have a laminated structure, and may be a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or the like. Aluminum oxide nitride film, silicon nitride film, aluminum nitride film, silicon oxide nitride film An inorganic insulating film such as an aluminum nitride oxide film or an aluminum oxide film can be used.

[0144] An element isolation insulating layer 206 is provided on the substrate 200 so as to surround the transistor 160. do.

[0145] The transistor 160 using a single crystal semiconductor substrate can operate at high speed. By using this transistor as a readout transistor, it is possible to read out information at high speed. can be done.

[0146] The transistor 162 illustrated in FIG. 3A is a transistor in which an oxide semiconductor is used for a channel formation region. A transistor using an oxide semiconductor for the channel formation region is extremely small. Note that the oxide semiconductor included in the transistor 162 can achieve good off-state characteristics. The layer is preferably a highly purified oxide semiconductor. This allows the transistor 162 to have better off-state characteristics.

[0147] The transistor 162 has a small off-state current, and therefore, by using this transistor, it is possible to achieve long-term recording. It is possible to retain the memory contents, i.e., no refresh operation is required, or , it is possible to realize a semiconductor memory device in which the frequency of refresh operations is extremely low. Power consumption can be reduced sufficiently.

[0148] The transistor 162 includes an oxide semiconductor layer 244a and an oxide semiconductor layer 244b. The thickness of the channel forming region is different from that of the other layer (for example, the electrode layer 268a or the electrode layer 268b). The oxide semiconductor stack 244 is smaller than the oxide semiconductor stack 244 (the area adjacent to the oxide semiconductor stack 244). The oxide semiconductor stack 244 included in the second semiconductor layer 2 has a thinned channel formation region and a thinned threshold voltage. The negative shift of the voltage can be suppressed. a gate electrode layer 262 overlapping with the oxide semiconductor stack 244 with the gate insulating layer 260 interposed therebetween; In addition, a gate electrode overlapping with the oxide semiconductor stack 244 with the insulating layer 203 and the insulating layer 204 interposed therebetween is formed. The gate electrode layer 202b is used as a back gate electrode. By applying a negative bias voltage to the gate electrode layer 202b, The second current is prevented from flowing on the transistor side, and the threshold voltage of the transistor 162 is increased. These allow transistor 162 to be normally-off. The transistor can be a flip-chip transistor.

[0149] The insulating layer 203 and the insulating layer 204 may be formed of silicon oxide, silicon oxynitride, or aluminum oxide. aluminum oxide nitride, hafnium oxide, gallium oxide, zinc gallium oxide, or A film containing a mixture of these materials can be used. Specifically, the insulating layer 204 in contact with the oxide semiconductor layer 244a) has an oxygen excess region. It is preferable.

[0150] If a film having a barrier property against oxygen is used as the insulating layer 203, the insulating layer 20 It is preferable because it can prevent oxygen from being released from 4. As the film, a film having a permeability to oxygen lower than that of the insulating layer 204 may be used. Specifically, for example, aluminum, aluminum with magnesium addition, titanium An oxide film or nitride film of aluminum, magnesium, titanium, or the like to which The insulating layer 203 may be formed of a single layer or a laminated layer. It is more preferable to use a membrane that is not only porous but also has low permeability to impurities such as hydrogen and moisture. An aluminum oxide film can be suitably used as such a film. By using an aluminum oxide film as the oxide layer, not only is oxygen desorption prevented, but also the Suppresses the inclusion of impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of transistor 162. It is possible.

[0151] Note that when the gate electrode layer 202b and the electrode layer 202a have a tapered shape, the insulating layer The taper angle is preferably 30° or more and 70° or less because it can improve the coverage of 203. It is preferable to set it to 1° or less.

[0152] An insulating layer 232 and an insulating layer 236 are provided over the transistor 162 as a single layer or a stacked layer. The insulating layer 232 or the insulating layer 236 may be formed using the same material as the insulating layer 203 or the insulating layer 204. If necessary, after forming the insulating layer 236, a film containing C The surface of the insulating layer 236 may be planarized by performing a planarization process such as MP processing. As the insulating layer 236, a planarizing insulating film is formed to reduce surface irregularities caused by the transistor. Alternatively, an inorganic insulating film and a planarizing insulating film may be laminated. It can be used with organic materials such as polyimide resin, acrylic resin, and benzocyclobutene resin. Alternatively, in addition to the organic materials, low-dielectric-constant materials (low-k materials) can be used. This can be done.

[0153] A wiring layer 256 is provided on the insulating layer 236. The wiring layer 256 is connected to the transistor 16. The wiring layer 256 is a wiring for connecting the insulating layer 236, The electrodes are connected to the insulating layer 232 through contact holes formed in the gate insulating layer 260. In addition, a separate electrode layer is formed in the contact hole, and the electrode layer is electrically connected to the contact hole. The wiring layer 256 and the electrode layer 268b may be electrically connected via the electrode layer.

[0154] In addition, a region overlapping with the electrode layer 268a of the transistor 162 with the gate insulating layer 260 interposed therebetween The conductive layer 253 is provided in the region, and the electrode layer 268a, the gate insulating layer 260, and the conductive layer 253 are connected to each other. The capacitor element 164 is formed by the conductive layer 253. The electrode layer 268a functions as one electrode of the capacitor 164, and the conductive layer 253 functions as one electrode of the capacitor 164. It functions as the other electrode of the capacitor element 164. If capacitance is not required, the capacitor element 164 can be Alternatively, the capacitor 164 may be provided separately from the transistor 162. It may be provided above the

[0155] In this embodiment, the conductive layer 253 is the same as the gate electrode layer 262 of the transistor 162. It can be formed in a single manufacturing process.

[0156] The electrode layer 268a is electrically connected to the electrode layer 202a formed in the same layer as the gate electrode layer 202b. The electrode layer 202a is connected to a contact hole provided in the insulating layer 234. Although not shown in FIG. 3A, the electrode layer 222a is electrically connected to the electrode layer 222a. 222a is electrically connected to the gate electrode layer 210 of the transistor 160. The electrode layer 268a of the transistor 162 is connected to the gate electrode layer 210 of the transistor 160. Electrically connected.

[0157] The insulating layer 230 and the insulating layer 234 can have the same structure as the insulating layer 228. The insulating layers 228, 230, and 234 may be subjected to a planarization process if necessary. In addition, the electrode layer 268a of the transistor 162 and the gate electrode layer 268b of the transistor 160 The electrical connection with 210 is not limited to the configuration shown in FIG. 3(A), and may be made by an electrode layer (or The configuration of the electrode layer 202a and the insulating layer can be set appropriately. A separate electrode layer may be provided between the electrode layer 268a and the gate electrode layer 21. 0 may be directly connected.

[0158] When the insulating layer 204 has an oxygen-excess region, the excess oxygen contained in the insulating layer 204 , may be released when opening the contact hole, so the contact hole It is preferable that the insulating film 242 be provided in a region that does not overlap with the oxide semiconductor stack 244. In the edge layer 204, a contact provided in a region that does not overlap with the oxide semiconductor stack 244 The electrode layer 202a and the electrode layer 268a are electrically connected through the hole. The contact hole provided below 204 (on the transistor 160 side) is made of oxide semiconductor. The gate of the transistor 162 may overlap with the conductor stack 244. The electrode layer 202b is electrically connected to the wiring layer 222b provided in the same layer as the electrode layer 222a. The following example shows:

[0159] In FIG. 3A, the transistor 160 and the transistor 162 are at least partially The transistor 162 and the capacitor 164 are provided so as to overlap each other. It is preferable that the transistor 160 is provided so as to overlap at least a part of the transistor 160. For example, the conductive layer 253 of the capacitor 164 is slightly different from the gate electrode layer 210 of the transistor 160. By adopting such a planar layout, This allows the area occupied by the semiconductor device to be reduced, thereby enabling higher integration. .

[0160] Next, an example of a circuit configuration corresponding to FIG. 3(A) is shown in FIG. 3(B).

[0161] In FIG. 3B, the first wiring (1st Line) and the source voltage of the transistor 160 The electrode layer is electrically connected to the second wiring (2nd Line) and the transistor 160. The drain electrode layer is electrically connected to the third wiring (3rd Line). and one of the source electrode layer and the drain electrode layer of the transistor 162 are electrically connected to each other. The fourth line and the gate electrode layer of the transistor 162 are electrically connected to each other. The gate electrode layer of the transistor 160 and the gate electrode layer of the transistor 16 The other of the source electrode layer and the drain electrode layer of the capacitor 164 is electrically connected to one of the electrodes of the capacitor 164. , and the fifth wiring (5th Line) and the other electrode of the capacitor element 164 are electrically connected to is connected to.

[0162] In the semiconductor device illustrated in FIG. 3B, the potential of the gate electrode layer of the transistor 160 can be maintained. By taking advantage of this feature, it is possible to write, store, and read information as follows: .

[0163] The writing and retention of data will be explained. First, the potential of the fourth wiring is applied to the transistor The potential is set to a level at which the transistor 162 is turned on, thereby turning on the transistor 162. The potential of the third wiring is applied to the gate electrode layer of the transistor 160 and the capacitor 164. That is, a predetermined charge is applied to the gate electrode layer of the transistor 160. (Write). Here, charges that give two different potential levels (hereinafter referred to as Low-level charges) , High level charge) is given. Then, the fourth wiring The potential of the transistor 162 is set to a potential at which the transistor 162 is turned off. By setting the transistor 160 in this state, the charge applied to the gate electrode layer of the transistor 160 is held. (hold).

[0164] Since the off-state current of the transistor 162 is extremely small, the gate electrode layer of the transistor 160 The charge is retained for a long time.

[0165] Next, we will explain how to read information. When a predetermined potential (constant potential) is applied to the first wiring, When an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 160 The second wiring has a different potential depending on the amount of charge held in the electrode layer. If the transistor 160 is an n-channel type, a high level is applied to the gate electrode layer of the transistor 160. The apparent threshold voltage V for a given charge th_H The gate of transistor 160 The apparent threshold voltage V when a low-level charge is applied to the gate electrode layer th_L twist Here, the apparent threshold voltage is the voltage at which the transistor 160 is turned on. This refers to the potential of the fifth wiring required to achieve the "state." The potential of V th_H and V th_L By setting the potential V0 between For example, in writing, the charge given to the gate electrode layer can be determined. If a Bell charge is applied, the potential of the fifth wire is V0 (>V th_H ) then When a low level charge is applied, the transistor 160 is in the "on state." The potential of the fifth wire is V0( <V th_L ), transistor 160 remains "off" Therefore, by observing the potential of the second wiring, the stored information It can be read out.

[0166] When memory cells are arranged in an array, only the information in the desired memory cell can be read. In this way, if the information is not read out, the state of the gate electrode layer The potential at which transistor 160 is in the "off state" regardless of V th_H Alternatively, a lower potential may be applied to the fifth wiring regardless of the state of the gate electrode layer. The potential at which transistor 160 is "on," i.e., V th_L Larger power Just give the position to the fifth wire.

[0167] In the semiconductor device described in this embodiment, an oxide semiconductor is used in the channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation becomes unnecessary or the refresh operation is This allows the frequency of operations to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is desirable that the potential is fixed), Even if the transistor 1 is turned on, the stored contents can be retained for a long period of time. By making 62 a normally-off transistor, when there is no power supply, the transistor The gate of the transistor 162 (gate electrode layer 262) is configured to receive a ground potential. Thus, when there is no power supply, the transistor 162 is in an off state. can be maintained, and the memory contents can be maintained.

[0168] Furthermore, the semiconductor device described in this embodiment mode does not require a high voltage for writing data. There is no problem of degradation of the capacitor. For example, unlike conventional non-volatile memory, the floating gate There is no need to inject electrons into the floating gate or extract electrons from the floating gate. The problem of deterioration of the gate insulating layer does not occur at all. In semiconductor devices, there is no limit to the number of times that data can be rewritten, which is a problem with conventional nonvolatile memories. Furthermore, the on / off state of the transistor Since information is written in the memory, high-speed operation can be easily achieved.

[0169] As described above, semiconductor devices that have achieved miniaturization and high integration and are endowed with high electrical characteristics have been developed. It is possible to provide a semiconductor device and a method for manufacturing the semiconductor device.

[0170] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0171] (Embodiment 3) In this embodiment mode, the transistor described in Embodiment 1 is used, and a A semiconductor device that can retain memory contents even in a difficult situation and has no limit on the number of times it can be written. Regarding this, the configuration different from that shown in the second embodiment will be described with reference to FIG.

[0172] FIG. 4(A) shows an example of a circuit configuration of a semiconductor device, and FIG. 4(B) shows an example of the semiconductor device. First, the semiconductor device shown in FIG. 4(A) will be explained, followed by the semiconductor device shown in FIG. The semiconductor device shown in B) will be described below.

[0173] In the semiconductor device shown in FIG. 4A, the bit line BL and the source electrode of the transistor 162 The layer or drain electrode layer is electrically connected to the word line WL and the gate electrode layer of the transistor 162. The source electrode layer or the drain electrode layer of the transistor 162 is electrically connected to the and the first terminal of the capacitor 254 are electrically connected to each other.

[0174] Next, data is written and stored in the semiconductor device (memory cell 250) shown in FIG. This section explains how to do this.

[0175] First, the potential of the word line WL is set to a potential at which the transistor 162 is turned on. The transistor 162 is turned on. As a result, the potential of the bit line BL is changed to the potential of the capacitor 254. The potential of the word line WL is then applied to the first terminal (write). By setting the potential at which the transistor 62 is turned off, the transistor 162 is turned off. The potential of the first terminal of the capacitance element 254 is held (held).

[0176] The transistor 162 including an oxide semiconductor has an extremely low off-state current. For this reason, when the transistor 162 is turned off, the first The potential of the terminal (or the charge stored in the capacitance element 254) is kept constant for an extremely long time. In addition, the transistor 162 can be configured as a normally-off transistor. By doing so, when there is no power supply, the gate of the transistor 162 is at ground potential. In this way, when there is no power supply, The transistor 162 can remain in the off state, and the memory contents can continue to be retained. .

[0177] Next, the reading of information will be described. When the transistor 162 is turned on, the floating The bit line BL and the capacitance element 254 are electrically connected to each other. As a result, the potential of the bit line BL changes. The amount of change in potential is determined by the potential of the first terminal of the capacitance element 254 (or the potential stored in the capacitance element 254). It takes on different values ​​depending on the charge.

[0178] For example, the potential of the first terminal of the capacitance element 254 is V, the capacitance of the capacitance element 254 is C, and the bit line The capacitance component of BL (hereinafter also referred to as bit line capacitance) is CB, and the capacitance before charge redistribution is If the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB×VB0+C×V) / (CB+C). Therefore, the state of memory cell 250 is Therefore, if the potential of the first terminal of the capacitance element 254 takes two states, V1 and V0 (V1>V0), Then, the potential of the bit line BL when the potential V1 is maintained is (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the bit line BL when the potential V0 is maintained (=(CB× VB0+C×V0) / (CB+C)).

[0179] Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out. do.

[0180] As described above, in the semiconductor device illustrated in FIG. 4A, the off-state current of the transistor 162 is extremely small. Therefore, the charge stored in the capacitance element 254 can be maintained for a long time. In other words, refresh operations are not required, or the frequency of refresh operations can be reduced. Since it is possible to make the power consumption extremely low, it is possible to reduce the power consumption sufficiently. Even if there is no power supply, the memory contents can be retained for a long period of time. do.

[0181] Next, the semiconductor device shown in FIG. 4B will be described.

[0182] The semiconductor device shown in FIG. 4B has the memory cell 2 shown in FIG. 4A as a memory circuit on the upper part. 50, and at the bottom, The peripheral circuits required to operate the array 251 (memory cell arrays 251a and 251b) The peripheral circuit 258 is electrically connected to the memory cell array 251. It is being done.

[0183] By configuring as shown in FIG. 4B, the peripheral circuit 258 is connected to the memory cell array 251 ( Since it can be provided directly under the memory cell arrays 251a and 251b, It is possible to achieve miniaturization.

[0184] The transistors provided in the peripheral circuit 258 are made of a different semiconductor material from the transistor 162. It is more preferable to use silicon, germanium, silicon germanium, Silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor can also be used. Alternatively, organic semiconductor materials may be used. The transistor is capable of sufficiently high speed operation. It is possible to realize various circuits (logic circuits, drive circuits, etc.) that require operation. do.

[0185] In the semiconductor device shown in FIG. 4B, two memory cell arrays 251 (memory cell Although the configuration in which the memory cell array 251a and the memory cell array 251b are stacked has been illustrated, The number of memory cell arrays to be stacked is not limited to this. It may also be configured as

[0186] As described above, semiconductor devices that have achieved miniaturization and high integration and are endowed with high electrical characteristics have been developed. It is possible to provide a semiconductor device and a method for manufacturing the semiconductor device.

[0187] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0188] (Fourth embodiment) In this embodiment, as another example of a semiconductor device using the transistor described in this specification, NOR type circuits and NAND type circuits, which are logic circuits, are shown in Figures 13(A) to 13(C). 13(B) is a NOR type circuit, and FIG. 13(C) is a NAND type circuit. The structure of the transistor 802 and the transistor 803 in the NOR type circuit of FIG. FIG.

[0189] In the NOR type circuit and the NAND type circuit shown in FIGS. 13(B) and 13(C), p-channel transistors The transistors 801, 802, 811, and 814 are the same as those shown in the second embodiment. The transistor 160 can have the same structure as the transistor 160. In this embodiment, A substrate 800 (for example, an n-type single crystal silicon substrate) made of a semiconductor material having The impurity elements to be added include boron (B), aluminum (Al), and gallium (Ga). or the like to form a p-channel transistor having a p-type impurity region.

[0190] In addition, the transistors 803, 804, 812, and 813, which are n-channel transistors, The channel formation region has a structure similar to that of the transistor 120 described in Embodiment 1. A transistor using a compound semiconductor film is applied.

[0191] In the NOR type circuits and NAND type circuits shown in FIGS. 13(A) to 13(C), The transistors 803, 804, 812, and 813 have thin channel formation regions in the oxide semiconductor stacks. Since the transistor is made into a thin film, the negative shift of the threshold voltage of the transistor is suppressed. In addition, the first gate electrode and the second gate electrode are formed so as to sandwich the oxide semiconductor stack with an insulating layer interposed therebetween. a layer and a second gate electrode layer are provided, one of the gate electrode layers being used as a back gate; By using this, the potential is appropriately controlled, for example, to GND, and the transistors 803, 804, and 8 12,813 threshold voltage is made more positive to make it a normally-off transistor. can be done.

[0192] In this embodiment, in the NOR circuit, the transistor 803 and the transistor 8 The gate electrode layers, which can function as back gates, are electrically connected to each other, and N In the AND circuit, a back-transistor is provided in the transistor 812 and the transistor 813. An example in which gate electrode layers functioning as gates are electrically connected to each other is shown. However, this is not limitative. The gate electrode layers functioning as back gates are electrically controlled independently. The structure may be such that

[0193] The semiconductor device shown in FIG. 13A uses a single crystal silicon substrate as a substrate 800. A transistor 802 is formed on a silicon substrate, and an oxide semiconductor layer is formed on the transistor 802. This is an example in which a transistor 803 using a layer as a channel formation region is stacked on a substrate 800. An element isolation insulating layer 806 is provided to surround the transistor 802 .

[0194] The electrode layer 841b electrically connected to the gate electrode layer 841a of the transistor 803 is The gate electrode is connected to the gate insulating layer 843 through a contact hole provided in the insulating layer 839. The layer 840 is electrically connected to the electrode layer 835, which is an electrode layer provided in the same layer as the layer 840. The layer 835 is electrically connected to the insulating layer 836 through contact holes formed in the insulating layer 833. 13A, the wiring layer 832 is electrically connected to the wiring layer 832. 32 is connected to the transistor 810 via contact holes provided in the insulating layer 830 and the insulating layer 826. The gate electrode layer 821 of the transistor 802 is electrically connected to the gate electrode layer 821 of the transistor 80. The gate electrode layer 841a of the third transistor is electrically connected to the gate electrode layer 821 of the transistor 802. is doing.

[0195] Although not explicitly shown in FIG. 13A, the electrode layer 825 of the transistor 802 is The wiring layer 834 is electrically connected to the transistor through the electrode layer 831. The electrode layer 845 of the transistor 802 is electrically connected to the electrode layer 845 of the transistor 803. The layer 825 and the electrode layer 845 of the transistor 803 are electrically connected.

[0196] Note that the electrode layer (or gate electrode layer) of the transistor 802 and the electrode layer of the transistor 803 The electrical connection between the gate electrode layer and the insulating layer is not limited to the structure shown in FIG. The configuration of the intervening electrode layer (or wiring layer) and insulating layer can be set appropriately.

[0197] As shown in FIG. 13A, even if a transistor 802 and a transistor 803 are stacked, By providing the semiconductor device, the area occupied by the semiconductor device can be reduced, and therefore high integration can be achieved. The transistor 802 is a transistor that can be normally off. Therefore, the logic circuit can be controlled accurately.

[0198] As described above, semiconductor devices that have achieved miniaturization and high integration and are endowed with high electrical characteristics have been developed. It is possible to provide a semiconductor device and a method for manufacturing the semiconductor device.

[0199] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0200] (Embodiment 5) In this embodiment, the transistor disclosed in the first embodiment is used as an example of a semiconductor device. CPU (Central Processing Unit) that uses at least a portion of This article explains:

[0201] Fig. 5(A) is a block diagram showing a specific configuration of the CPU. On the board 1190, an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), ALU controller 1192, instruction decoder 11 93, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface 1189 (ROM The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in Figure 5(A) is just an example of a simplified configuration. Actual CPUs have a wide variety of configurations depending on their applications.

[0202] The instructions input to the CPU via the bus interface 1198 are After being input to the decoder 1193 and decoded, the ALU controller 1192 Rupture controller 1194, register controller 1197, timing controller It is entered into 1195.

[0203] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates a response and reads or writes to register 1196 depending on the state of the CPU.

[0204] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal that controls the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal C based on the reference clock signal CLK1. The internal clock signal CLK2 is generated by an internal clock generator. Supply to the seed circuit.

[0205] In the CPU shown in FIG. 5A, a memory cell is provided in the register 1196. The memory cells of the first 1196 are the same as those disclosed in the second or third embodiment. Good too.

[0206] In the CPU shown in FIG. 5A, the register controller 1197 In accordance with the instruction from the register 1196, the holding operation is selected. In the memory cell of 1196, the logic (value) is inverted by a logic element. Select whether to hold the data by using the capacitor or by using the logic (value). If the logic element that holds the data is selected, the memory cell in register 1196 When data retention in the capacitor element is selected, the power supply voltage is supplied to the capacitor. When this occurs, data is rewritten to the capacitance element, and the power supply to the memory cell in the register 1196 is turned off. The voltage supply can be stopped.

[0207] Regarding the power supply stop, as shown in FIG. 5(B) or FIG. 5(C), the memory cell group and the power supply A switching element is provided between nodes to which the potential VDD or power supply potential VSS is applied. The circuits in Figures 5(B) and 5(C) will be explained below.

[0208] In FIG. 5B and FIG. 5C, a switching element that controls the supply of a power supply potential to a memory cell is shown. An example of the structure of a memory circuit including the transistor disclosed in Embodiment 1 is shown as an element.

[0209] The memory device shown in FIG. 5B includes a switching element 1141 and a plurality of memory cells 1142. Specifically, each memory cell 1142 has a memory cell group 1143 having a real The memory cells described in the second or third embodiment can be used. Each memory cell 1142 of the memory cell 43 is connected to a high level through a switching element 1141. Furthermore, the power supply potential VDD of each memory cell in the memory cell group 1143 is supplied to the The cell 1142 is supplied with the potential of the signal IN and the potential of the low-level power supply potential VSS. There are.

[0210] In FIG. 5B, the switching element 1141 is the transistor disclosed in the first embodiment. The transistor is driven by a signal SigA applied to its gate electrode layer. This allows for better control of switching.

[0211] In FIG. 5B, the switching element 1141 has only one transistor. However, there is no particular limitation, and a plurality of transistors may be included. When the element 1141 has a plurality of transistors that function as switching elements, The plurality of transistors may be connected in parallel or in series. Alternatively, the circuits may be connected in series and parallel in combination.

[0212] In FIG. 5B, the switching element 1141 controls the memory cell group 1143. The supply of a high-level power supply potential VDD to each memory cell 1142 is controlled. The supply of the low-level power supply potential VSS is controlled by the switching element 1141. Good too.

[0213] In addition, in FIG. 5C, each memory cell 1142 included in the memory cell group 1143 is A low-level power supply potential VSS is supplied via a switching element 1141. The switching element 1141 switches each memory cell in the memory cell group 1143. The supply of the low-level power supply potential VSS to the recell 1142 can be controlled.

[0214] A switch is provided between the memory cell group and a node to which the power supply potential VDD or VSS is applied. When a switching element is installed to temporarily stop CPU operation and cut off the supply of power voltage It is possible to retain data even in this state, and power consumption can be reduced. Specifically, for example, a user of a personal computer inputs information into an input device such as a keyboard. You can stop the CPU from operating while you are no longer entering information, which will save you money. Power consumption can be reduced.

[0215] Here, we have taken the CPU as an example, but the same can be said for DSP (Digital Signal Processor) processor), custom LSI, FPGA (Field Programmable Gate Array) It can also be applied to LSIs such as MOS gate arrays.

[0216] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0217] In addition, spin-MRAM (spin transfer magnetization reversal) is known as a spintronics device. Table 2 shows a comparison between MRAM and memory using oxide semiconductors.

[0218] [Table 2]

[0219] Combining oxide semiconductor transistors and silicon transistors As shown in Table 2, compared to spintronics devices, the drive method and writing principle of the The theory and materials are very different.

[0220] In addition, a transistor using an oxide semiconductor and a transistor using silicon can be combined. As shown in Table 2, the memory used in this study has advantages over spintronic devices in terms of heat resistance, 3D design, and It has many advantages, including a laminated structure of three or more layers and magnetic field resistance. The overhead is the power consumed to write to the memory in the processor. This refers to the amount of electricity consumed by

[0221] As such, oxide semiconductor-based metal-oxide devices have many advantages over spintronic devices. By using memory, it is possible to reduce CPU power consumption.

[0222] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0223] (Sixth embodiment) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic devices include televisions, monitors, and other display devices, lighting devices, and desktop Or a laptop computer, word processor, DVD (Digital Playing still images or videos stored on recording media such as a Versatile Disc image playback devices, portable CD players, radios, tape recorders, headphone stereos Audio, stereos, cordless telephone handsets, transceivers, portable radios, mobile phones, car phones , portable game consoles, calculators, personal digital assistants, electronic organizers, e-books, electronic translators, voice input devices High-frequency heating equipment such as electric appliances, video cameras, digital still cameras, electric shavers, and microwave ovens Electric rice cookers, electric washing machines, electric vacuum cleaners, air conditioning equipment such as air conditioners, tableware Washing machines, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerated freezers These include refrigerators, freezers for storing DNA, smoke detectors, radiation detectors, dialysis machines and other medical equipment. In addition, it is used in emergency lights, traffic lights, conveyor belts, elevators, escalators, industrial Examples include industrial equipment such as robots and power storage systems. Also, vehicles propelled by electric motors using power from non-aqueous secondary batteries are included in the category of electrical equipment. The above-mentioned mobile units include, for example, electric vehicles (EVs), internal combustion engines, and Hybrid electric vehicles (HEV) and plug-in hybrid electric vehicles (PHEV) , tracked vehicles in which these tires and wheels are converted into tracks, and motorized vehicles including electrically assisted bicycles. Bicycles, motorcycles, electric wheelchairs, golf carts, small or large boats, submarines, helicopters Examples include robots, aircraft, rockets, satellites, space probes, planetary rovers, and spacecraft. Specific examples of these electronic devices are shown in Figure 6.

[0224] FIG. 6A shows a table 9000 having a display unit. A display unit 9003 is built into the body 9001, and images are displayed on the display unit 9003. It is possible to support the housing 9001 with four legs 9002. The housing 9001 also has a power cord 9005 for power supply.

[0225] The transistor described in Embodiment 1 can be used in the display portion 9003 and This can give the device high reliability.

[0226] The display unit 9003 has a touch input function, and the display unit 9003 of the table 9000 By touching the displayed display button 9004 with a finger or the like, the screen can be operated or information can be input. It can also communicate with other home appliances or control them, making it possible to It may also be used as a control device to control other home appliances by operation. For example, If a semiconductor device having a sensor function is used, the display portion 9003 can have a touch input function. This can be done.

[0227] In addition, the screen of the display unit 9003 can be vertically fixed to the floor by a hinge provided in the housing 9001. It can also be set upright and used as a television set. If you install a large screen television, the free space will be narrow, but it is possible to install it on a table. If the display unit is built in, the space in the room can be used more effectively.

[0228] FIG. 6B shows a portable music player, which has a main body 3021 with a display unit 3023 and a headset 3024 attached to the ear. A fixing portion 3022 for fixing the device, an operation button 3024, an external connection port 3025, etc. are provided. The transistor or the real device according to the first embodiment may also have a speaker. The memories and logic circuits shown in the second to fourth embodiments are incorporated in the main body 3021. By applying it to PUs, it will become a more power-efficient portable music player (PDA). It is possible.

[0229] Furthermore, the portable music player shown in FIG. 6(B) is equipped with an antenna, a microphone function, and a wireless function. If you connect it to your mobile phone, you can enjoy wireless hands-free driving while driving a car. Conversations are also possible.

[0230] FIG. 6C shows a computer, which includes a main body 9201 including a CPU, a housing 9202, a display unit 9 203, keyboard 9204, external connection port 9205, pointing device 920 The computer displays a semiconductor device manufactured using one embodiment of the present invention. By using the CPU shown in the fifth embodiment, This makes it possible to make the computer power-saving.

[0231] Figures 7(A) and 7(B) show tablet terminals that can be folded in half. The tablet terminal is in a state where the display unit 9631a is in a housing 9630. 1b, display mode switch 9034, power switch 9035, power saving mode switch It has a replacement switch 9036, a fastener 9033, and an operating switch 9038.

[0232] In the portable devices shown in FIGS. 7(A) and 7(B), image data is temporarily stored. For example, in the second or third embodiment, an SRAM or a DRAM is used as the memory. The semiconductor device described in the previous embodiment can be used as a memory. By adopting semiconductor devices in memory, information can be written and read at high speeds. It is possible to retain data for a long period of time and to reduce power consumption sufficiently.

[0233] In addition, a part of the display portion 9631a can be used as a touch panel area 9632a. By touching the operation keys 9638 shown, data can be input. In the example of 9631a, half of the area has a display function, and the other half The area shown in FIG. 1 has a touch panel function, but is not limited to this. The entire area of ​​9631a may have a touch panel function. The entire surface of the display section 9631a is used as a touch panel by displaying keyboard buttons, and the display section 9631b can be used as a display screen.

[0234] In addition, in the display unit 9631b, as in the display unit 9631a, a part of the display unit 9631b The area 9632b of the touch panel can be used as the keyboard of the touch panel. By touching the area where the display switch button 9639 is displayed with your finger or a stylus, A keyboard can be displayed on the display portion 9631b.

[0235] In addition, touch panel area 9632a and touch panel area 9632b can be touched simultaneously. You can also input characters using the touchpad.

[0236] A display mode changeover switch 9034 is used to change the display orientation between portrait and landscape. You can select between black and white and color display. The 9036 is a tablet device that detects external light during use using a built-in light sensor. The display brightness can be optimized according to the amount of light. In addition, other detection devices such as gyro, acceleration sensor, etc. that detect tilt are also included. It may be stored.

[0237] FIG. 7A shows an example in which the display area of ​​the display portion 9631b is the same as that of the display portion 9631a. However, there is no particular limitation, and one size may be different from the other size. The quality may also be different. For example, one display panel may be capable of displaying images with higher resolution than the other. You may do so.

[0238] FIG. 7B shows the tablet terminal in a closed state. The tablet terminal includes a housing 9630 and a solar cell 963 3. Includes a charge / discharge control circuit 9634, a battery 9635, and a DC / DC converter 9636 7B, a battery 9635, a D A configuration including a CDC converter 9636 is shown.

[0239] In addition, since the tablet device can be folded in half, the housing 9630 can be folded when not in use. Therefore, the display portions 9631a and 9631b can be protected, and thus the display portions 9631a and 9631b can be withstood. This makes it possible to provide a tablet terminal that is highly durable and reliable even from the perspective of long-term use.

[0240] In addition, the tablet terminals shown in Fig. 7(A) and Fig. 7(B) can also display various information ( Functions that display still images, videos, text images, etc., calendars, dates, or times, etc. A function to display information on the display unit, and a touch input device to operate or edit the information displayed on the display unit by touch input. It can have functions such as the ability to control processing by various software (programs), etc. can.

[0241] The solar cell 9633 attached to the surface of the tablet terminal supplies power to the touch panel, The solar cell 9633 can be supplied to a display unit, a video signal processor, or the like. The battery 9635 can be efficiently charged by the battery 9630. The battery 9635 may be a lithium-ion battery. This has the advantage of enabling miniaturization.

[0242] The configuration and operation of the charge / discharge control circuit 9634 shown in FIG. 7B will be described with reference to FIG. A block diagram is shown and explained. In FIG. 7(C), a solar cell 9633, a battery 9635, DC-DC converter 9636, converter 9637, switches SW1 to SW3, display unit The figure shows the 9631, the battery 9635, the DC-DC converter 9636, 7B. This corresponds to 4.

[0243] First, an example of operation when power is generated by the solar cell 9633 using external light will be described. The power generated by the solar cell is converted to a voltage to charge the Battery 9635. The voltage is increased or decreased by a C converter 9636. When power is being used from the battery 9633, the switch SW1 is turned on and the converter 96 37 increases or decreases the voltage to the voltage required for the display unit 9631. When not displaying in 31, turn SW1 off and SW2 on to charge the battery. 35 charging configuration.

[0244] The solar cell 9633 is shown as an example of a power generating means, but is not particularly limited thereto. Other power generation methods such as piezoelectric elements (piezoelectric elements) and thermoelectric elements (Peltier elements) For example, it may be configured to transmit and receive power wirelessly (contactlessly). A wireless power transmission module that charges by transmitting power, or a configuration that combines other charging methods It may also be possible to use the following.

[0245] In FIG. 8A, a television set 8000 includes a housing 8001 and a display unit 8002. The display unit 8002 displays images and the speaker unit 8003 outputs sounds. The transistor described in Embodiment 1 can be used in the display portion 8002. It is possible to do so.

[0246] The display unit 8002 is a light-emitting device having a light-emitting element such as a liquid crystal display device or an organic EL element in each pixel. Device, electrophoretic display, DMD (Digital Micromirror Device) e), PDP (Plasma Display Panel), and other semiconductor display devices It can be used.

[0247] The television device 8000 may include a receiver, a modem, and the like. The device 8000 can receive general television broadcasts using a receiver, and also has a modem. By connecting to a wired or wireless communication network via Recipient) or two-way (between sender and recipient, or between recipients) information communication It is also possible.

[0248] The television device 8000 also includes a CPU and memory for performing information communication. The television device 8000 may include the memory described in any one of Embodiments 2 to 5. It is possible to use a logic circuit or a CPU.

[0249] In FIG. 8(A), an air conditioner having an indoor unit 8200 and an outdoor unit 8204 is an example of an electrical device using the CPU of the fifth embodiment. Specifically, the indoor unit 8200 is 8A, the C Although the PU 8203 is provided in the indoor unit 8200, 3 may be provided in the outdoor unit 8204. Alternatively, the indoor unit 8200 and the outdoor unit 8204 The CPU 8203 may be provided in both the CPU 8203 and the CPU 8204. The CPU uses a compound semiconductor, which makes it highly heat-resistant and highly reliable. This can be achieved.

[0250] In FIG. 8A, an electric refrigerator-freezer 8300 includes a CPU using an oxide semiconductor. Specifically, the electric refrigerator-freezer 8300 includes a housing 8301, a refrigerator compartment The freezer compartment door 8302, the freezer compartment door 8303, the CPU 8304, etc. The CPU shown in the fifth embodiment is electrically By using it in the CPU 8304 of the refrigerator-freezer 8300, power saving can be achieved.

[0251] 8(B) and 8(C) show an example of an electric vehicle, which is an example of an electric device. A secondary battery 9701 is mounted on the automobile 9700. The power of the secondary battery 9701 is The output is adjusted by the control circuit 9702 and supplied to the driving device 9703. 702 is controlled by a processing unit 9704 having a ROM, RAM, CPU, etc. (not shown). By using the CPU shown in the fifth embodiment as the CPU of the electric vehicle 9700, This allows for power savings.

[0252] The driving device 9703 is a DC motor or an AC motor alone, or a combination of a motor and an internal combustion engine. The processing device 9704 is configured in combination with the electric vehicle 9700. (acceleration, deceleration, stopping, etc.) and driving information (uphill and downhill slopes, etc., load on the drive wheels) Based on input information (such as cargo information), the control circuit 9702 outputs a control signal. 702 is supplied with electric energy from a secondary battery 9701 in response to a control signal from a processing unit 9704. It adjusts the energy and controls the output of the drive unit 9703. When an AC motor is installed Although not shown, the inverter for converting direct current to alternating current is also built in.

[0253] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination. [Explanation of symbols]

[0254] 100 boards 102 gate electrode layer 103 Insulating layer 104 Insulating layer 106 Oxide semiconductor stack 106a Oxide semiconductor layer 106b Oxide semiconductor layer 108 Conductive film 108a Source electrode layer 108b Drain electrode layer 110 Insulating layer 112 gate electrode layer 120 transistors 160 transistors 162 transistors 164 Capacitor 200 boards 202a Electrode layer 202b gate electrode layer 203 Insulating layer 204 Insulation layer 206 Element isolation insulating layer 208 Gate insulating layer 210 gate electrode layer 212a Electrode layer 212b Electrode layer 214 Impurity region 216 Channel formation region 218 Sidewall insulating layer 220 High concentration impurity region 222a Electrode layer 222b wiring layer 224 Intermetallic compound area 228 Insulating Layer 230 Insulating layer 232 Insulating layer 234 Insulating Layer 236 Insulating Layer 244 Oxide Semiconductor Stack 244a Oxide semiconductor layer 244b Oxide semiconductor layer 250 memory cells 251 Memory Cell Array 251a Memory Cell Array 251b memory cell array 253 Conductive Layer 254 Capacitor 256 wiring layer 258 Peripheral Circuits 260 Gate insulating layer 262 gate electrode layer 268a Electrode layer 268b Electrode layer 302 Insulation layer 306 Oxide semiconductor layer 308a Source electrode layer 308b Drain electrode layer 310 Gate insulating layer 320 transistors 402 Oxygen excess region 400 oxygen 800 boards 801 transistors 802 transistors 803 Transistor 804 transistor 806 Element isolation insulating layer 811 Transistor 812 transistors 813 Transistor 814 transistors 821 Gate electrode layer 825 Electrode layer 826 Insulating layer 830 Insulation layer 831 Electrode layer 832 Wiring layer 833 Insulation layer 834 Wiring layer 835 Electrode layer 836 Insulation Layer 839 Insulation Layer 840 gate electrode layer 841a Gate electrode layer 841b Electrode layer 843 Gate insulating layer 845 Electrode layer 1141 Switching element 1142 memory cells 1143 memory cell group 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 3021 Main Unit 3022 Fixed part 3023 Display section 3024 Operation button 3025 External connection port 8000 Television Equipment 8001 Case 8002 Display section 8003 Speaker section 8200 indoor unit 8201 Housing 8202 Ventilation outlet 8203 CPU 8204 Outdoor unit 8300 Electric refrigerator-freezer 8301 Housing 8302 Refrigerator door 8303 Freezer door 8304 CPU 9000 tables 9001 Case 9002 Legs 9003 Display section 9004 Display button 9005 Power Cord 9033 Fasteners 9034 Switch 9035 Power Switch 9036 Switch 9038 Operation switch 9201 Main Unit 9202 Housing 9203 Display section 9204 keyboard 9205 External connection port 9206 Pointing Device 9630 chassis 9631 Display section 9631a Display section 9631b Display section 9632a area 9632b area 9633 Solar Cells 9634 Charge / Discharge Control Circuit 9635 Battery 9636 DC / DC Converter 9637 Converter 9638 Operation Key 9639 Button 9700 Electric Vehicle 9701 Secondary battery 9702 Control circuit 9703 Drive unit 9704 Processing equipment

Claims

1. a first oxide semiconductor layer; a second oxide semiconductor layer having a region in contact with an upper surface of the first oxide semiconductor layer; a first conductive layer having a region in contact with a top surface of the second oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of a transistor; a second conductive layer having a region in contact with a top surface of the second oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the transistor; a third conductive layer having regions overlapping with the first oxide semiconductor layer and the second oxide semiconductor layer and functioning as a gate electrode of the transistor; a fourth conductive layer having the same material as the third conductive layer and having an area overlapping the first conductive layer; a first insulating layer having a region in contact with an upper surface of the first conductive layer, a region in contact with an upper surface of the third conductive layer, and a region in contact with an upper surface of the second oxide semiconductor layer; a second insulating layer having a region in contact with an upper surface of the third conductive layer and a region in contact with an upper surface of the fourth conductive layer; a fifth conductive layer having a region located above the first insulating layer and a region in contact with the second conductive layer; the first oxide semiconductor layer contains indium and gallium; the second oxide semiconductor layer contains indium and gallium, an atomic ratio of gallium in the second oxide semiconductor layer is equal to or greater than an atomic ratio of indium in the second oxide semiconductor layer; an atomic ratio of indium to gallium in the first oxide semiconductor layer is greater than an atomic ratio of indium to gallium in the second oxide semiconductor layer; the second oxide semiconductor layer has a region that does not overlap with the second conductive layer and does not overlap with the third conductive layer in a cross-sectional view of the transistor in a channel length direction, and a thickness of the second oxide semiconductor layer in the region is smaller than a thickness of the first oxide semiconductor layer; the second oxide semiconductor layer has a crystal part oriented in a c-axis direction.

2. a first oxide semiconductor layer; a second oxide semiconductor layer having a region in contact with an upper surface of the first oxide semiconductor layer; a first conductive layer having a region in contact with a top surface of the second oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of a transistor; a second conductive layer having a region in contact with a top surface of the second oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the transistor; a third conductive layer having regions overlapping with the first oxide semiconductor layer and the second oxide semiconductor layer and functioning as a gate electrode of the transistor; a fourth conductive layer having the same material as the third conductive layer and having an area overlapping the first conductive layer; a first insulating layer having a region in contact with an upper surface of the first conductive layer, a region in contact with an upper surface of the third conductive layer, and a region in contact with an upper surface of the second oxide semiconductor layer; a second insulating layer having a region in contact with an upper surface of the third conductive layer and a region in contact with an upper surface of the fourth conductive layer; a fifth conductive layer having a region located above the first insulating layer and a region in contact with the second conductive layer; the first oxide semiconductor layer contains indium and gallium; the second oxide semiconductor layer contains indium and gallium, an atomic ratio of gallium in the second oxide semiconductor layer is equal to or greater than an atomic ratio of indium in the second oxide semiconductor layer; an atomic ratio of indium to gallium in the first oxide semiconductor layer is greater than an atomic ratio of indium to gallium in the second oxide semiconductor layer; the second oxide semiconductor layer has a region that does not overlap with the second conductive layer and does not overlap with the third conductive layer in a cross-sectional view of the transistor in a channel length direction, and a thickness of the second oxide semiconductor layer in the region is smaller than a thickness of the first oxide semiconductor layer; the first oxide semiconductor layer includes a microcrystalline oxide semiconductor; the second oxide semiconductor layer has a crystal part oriented in a c-axis direction.

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