Imaging apparatus

Abstract

To provide an imaging apparatus capable of performing high dynamic range photographing.SOLUTION: An imaging device includes a first photoelectric conversion unit configured to convert incident light into electric charge, a capacitor electrically connected to the first photoelectric conversion unit, and a second photoelectric conversion unit configured to convert incident light into electric charge, wherein at least a part of the capacitor overlaps a region between the first photoelectric conversion unit and the second photoelectric conversion unit in a plan view.SELECTED DRAWING: Figure 15

Description

[Technical Field]

[0001] The present disclosure relates to an imaging device. [Background technology]

[0002] The dynamic range of subjects in nature is wide. For example, in-vehicle imaging devices are required to simultaneously capture bright and dark subjects (high dynamic range) because the brightness of the subject changes from moment to moment. To achieve a high dynamic range, Patent Documents 1 and 2 propose the following methods.

[0003] The imaging devices disclosed in Patent Documents 1 and 2 use silicon photodiodes. In Patent Document 1, a wide dynamic range can be obtained by combining images with different exposure times (hereinafter sometimes referred to as "accumulation times"). This method has already been put to practical use. In Patent Document 2, the dynamic range is expanded by combining images obtained from multiple imaging cells with different sensitivities arranged within one pixel.

[0004] Patent Document 3 proposes a stacked sensor having a photoelectric conversion film instead of a silicon photodiode that inhibits a high dynamic range. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 62-108678 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-99073 [Patent Document 3] Japanese Patent Application Laid-Open No. 2007-59465 [Patent Document 4] Japanese Patent Application Laid-Open No. 2012-19167 Summary of the Invention [Problem to be solved by the invention]

[0006] The conventional imaging devices described above have been required to further improve their high dynamic range imaging capabilities. One non-limiting exemplary embodiment of the present application provides an imaging device capable of performing high dynamic range imaging and a driving method thereof. [Means for solving the problem]

[0007] In order to solve the above problem, an imaging device according to one embodiment of the present disclosure includes a first imaging cell having a first photoelectric conversion unit, a first charge detection circuit electrically connected to the first photoelectric conversion unit via a connection portion, and a first capacitance element one end of which is electrically connected to the connection portion, and a second imaging cell having a second photoelectric conversion unit and a second charge detection circuit electrically connected to the second photoelectric conversion unit.

[0008] The general and specific aspects described above can be realized using a driving method for an imaging device. [Effects of the Invention]

[0009] According to one aspect of the present disclosure, it is possible to provide an imaging device capable of performing high dynamic range imaging and a driving method thereof. [Brief explanation of the drawings]

[0010] [Figure 1] 10A and 10B are diagrams for explaining the difference between conventional imaging cell characteristics and desirable imaging cell characteristics. [Figure 2] 10A and 10B are diagrams for explaining the difference between conventional imaging cell characteristics and more desirable imaging cell characteristics. [Figure 3] 10 is a schematic diagram showing the relationship between the capacitance of a charge storage node and the number of saturated electrons (ele) and random noise (ele). FIG. [Figure 4] 1 is a schematic diagram showing an example of the structure of an imaging device 100 according to a first exemplary embodiment. [Figure 5] 2 is a schematic diagram showing the circuit configuration of a unit pixel 30. FIG. [Figure 6]2 is a cross-sectional view showing a device configuration of a unit pixel 30. FIG. [Figure 7] 2 is a schematic diagram showing the planar shape of a pixel electrode in a unit pixel 30 when viewed from the vertical direction of a P-type silicon substrate 1. FIG. [Figure 8] 10 is a graph showing the characteristics of the light collection rate of the first pixel electrode 7 when the radius of the first pixel electrode 7 is changed, when the light collection rate of the entire unit pixel 30 is normalized to 100%. [Figure 9] 2 is a schematic diagram showing the areas occupied by a first charge detection circuit 51 and a second charge detection circuit 51′ in a unit pixel 30. FIG. [Figure 10] 1 is an operation sequence diagram showing exposure and readout operations in one cycle period in the imaging device 100. FIG. [Figure 11A] FIG. 10 is a schematic diagram showing the planar shape of a donut-shaped first pixel electrode 7 as a modified example of the pixel electrode. [Figure 11B] FIG. 10 is a schematic diagram showing the planar shape of a cross-shaped first pixel electrode 7 as a modified example of the pixel electrode. [Figure 11C] FIG. 10 is a schematic diagram showing the planar shape of a first pixel electrode 7 having a notched shape, as a modified example of the pixel electrode. [Figure 12A] FIG. 10 is a schematic diagram showing an example of the shape of a pixel electrode when a microlens 12 is eliminated. [Figure 12B] FIG. 10 is a schematic diagram showing another example of the shape of the pixel electrode when the microlens 12 is eliminated. [Figure 13] FIG. 10 is a cross-sectional view illustrating a device configuration of a unit pixel 30A according to a second exemplary embodiment. [Figure 14] FIG. 10 is a schematic diagram illustrating the layout of a 3×3 unit pixel 30B in an image pickup device 100 according to a modified example of the second embodiment. [Figure 15] FIG. 10 is a cross-sectional view schematically illustrating a device configuration of a unit pixel 30B according to a modified example of the second embodiment. [Figure 16] 15 is a schematic cross-sectional view showing a cross section of a unit pixel 30B taken along line AA' shown in FIG. 14. FIG. [Figure 17] FIG. 10 is a cross-sectional view schematically illustrating a device configuration of a unit pixel 30C according to another modified example of the second embodiment. [Figure 18] FIG. 10 is a diagram schematically illustrating functional blocks of an imaging module 200 incorporating an imaging device 100 according to an exemplary third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] First, the problems of the prior art that the inventors of the present invention have considered will be explained.

[0012] In the image synthesis disclosed in Patent Document 1, multiple image data are acquired in chronological order. Therefore, it takes several times longer than normal image capture time to obtain one synthesized image. Furthermore, since images with a time lag are synthesized, the simultaneity of the images is lost, resulting in distortion in images of moving subjects.

[0013] In Patent Document 2, multiple photodiodes of the same size with the same sensitivity and saturation electron number are used. Each photodiode is equipped with an on-chip top lens that divides the amount of light incident on it into two types, large and small. With this configuration, there is no actual difference between the multiple imaging cells. This effectively makes it appear as though the sensitivities are different. Since two cells are mounted on one pixel, images can be captured simultaneously, ensuring the simultaneity of the images.

[0014] On the other hand, since two cells must be placed within one pixel, the area of ​​the photodiode must be reduced to half or less compared to conventional devices. The area of ​​the photodiode and the sensitivity or number of saturation electrons are roughly proportional. As a result, if the area of ​​the photodiode is reduced to half or less, the sensitivity and number of saturation electrons will also be reduced to half or less compared to conventional devices.

[0015] Figure 1 shows a schematic diagram of conventional and desirable imaging cell characteristics. The horizontal axis indicates sensitivity, and the vertical axis indicates the number of saturated electrons. Sensitivity here is one of the indicators that indicate the characteristics of an imaging device (image sensor), and refers to the number of charges (electron-hole pairs) generated in the imaging cell in response to incident light. Sensitivity is generally expressed in units (e - / Lux sec) The saturation electron number refers to the allowable number of electrons that can be stored in the imaging cell, and is expressed in units (e - ) In principle, the sensitivity and number of saturated electrons are proportional to the effective area of ​​the photoelectric conversion element. However, the sensitivity also depends on the design of the microlens.

[0016] Unlike a normal cell (hereinafter referred to as a "normal cell") that has one imaging cell within a single pixel, high dynamic range (HDR) imaging uses two imaging cells within a single pixel. These two imaging cells preferably have (a) imaging cell characteristics with sensitivity and saturation electron count similar to those of a normal cell, and (b) imaging cell characteristics with saturation electron count similar to that of a normal cell but lower sensitivity than that of a normal cell. "a" and "b" in the figure indicate the desired combinations.

[0017] "a'" and "b'" in FIG. 1 indicate the combination of two imaging cells in Patent Document 2. As mentioned above, the area of ​​each imaging cell (photodiode) is half or less that of a normal cell. This reduces the sensitivity of each imaging cell, and also reduces the number of saturated electrons. This means that the characteristics deviate from the desired characteristics. Thus, the characteristics of the imaging cell in Patent Document 2 are significantly inferior to the required characteristics.

[0018] Figure 2 shows a schematic diagram of conventional and more desirable imaging cell characteristics. As shown in "b" in Figure 2, reducing the sensitivity alleviates saturation, which can occur when the amount of incident light is high. In addition, if the number of saturation electrons can be increased, the dynamic range can be further expanded.

[0019] Table 1 below compares a conventional Si sensor having a photodiode with a stacked sensor having a photoelectric conversion film disclosed in Patent Document 3, and shows the factors that determine element function and sensor performance. As can be seen from Table 1, in a conventional Si sensor, both the sensitivity and the number of saturated electrons are determined by the performance of the photodiode. In contrast, in a stacked sensor having a photoelectric conversion film, the sensitivity depends on the area and quantum efficiency of the photoelectric conversion film, and the number of saturated electrons depends on the capacitance of the charge storage node. Therefore, if the capacitance of the charge storage node is increased, the number of saturated electrons increases. In this way, in a stacked sensor, the number of saturated electrons does not depend on the performance of the photoelectric conversion film, so it is essentially possible to increase the number of saturated electrons. However, increasing the capacitance of the charge storage node can have significant side effects.

[0020] [Table 1]

[0021] Figure 3 shows the relationship between the capacitance of the charge storage node and the number of saturated electrons (e - ) and random noise (e - ) is shown in the figure. The horizontal axis represents the capacitance of the charge storage node, and the vertical axis represents the number of saturated electrons and random noise. Increasing the capacitance of the charge storage node can increase the number of saturated electrons, but at the same time, this also increases the random noise, which is a problem.

[0022] Random noise mainly includes noise that occurs when the charge detection circuit reads out, or transfers, the charge accumulated in the charge storage node, and noise that occurs when the charge detection circuit resets the charge accumulated in the charge storage node (hereafter referred to as "reset noise"). Increasing the capacity of the charge storage node increases the number of saturated electrons, but the ratio of the change in the number of stored charges to the change in the charge storage node voltage also increases. The noise generated by the charge detection circuit is voltage noise, and as a result, the noise converted into the number of stored charges becomes large.

[0023] Furthermore, in sensors that use silicon photodiodes for photoelectric conversion, complete charge transfer is achieved, making CDS (Correlated Double Sampling) effective in suppressing reset noise. In contrast, stacked sensors that use photoelectric conversion films cannot achieve complete charge transfer, making it impossible to cancel reset noise using CDS. Therefore, as will be described in detail later, noise cancellation using feedback, such as that proposed in Patent Document 4, is necessary. However, as mentioned above, increasing the capacity of the charge storage node reduces the ratio of the change in charge storage node voltage to the change in the number of stored charges, making it impossible to achieve sufficient reset noise suppression through feedback.

[0024] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the present disclosure is not limited to the following embodiments. Furthermore, appropriate modifications are possible within the scope of the effects of the present invention. Furthermore, one embodiment can be combined with another embodiment. In the following description, identical or similar components are designated by the same reference numerals. Furthermore, duplicated descriptions may be omitted.

[0025] (First embodiment) The structure, function and driving method of the imaging device 100 according to this embodiment will be described with reference to Figs. 4 to 12B. An example in which a P-type silicon substrate is used as the semiconductor substrate will be described below. An example in which holes are used as signal charges will also be shown. Note that electrons may also be used as signal charges. No.

[0026] (Structure of imaging device 100) First, the structure of the imaging device 100 will be described with reference to FIG.

[0027] FIG. 4 schematically illustrates an example of the structure of an imaging device 100. The imaging device 100 includes a plurality of unit pixels 30 arranged two-dimensionally. In reality, several million unit pixels 30 may be arranged two-dimensionally, but FIG. 4 illustrates some of the unit pixels 30 arranged in a 2×2 matrix. The imaging device 100 may be a line sensor. In this case, the plurality of unit pixels 30 may be arranged one-dimensionally (in the row or column direction).

[0028] Each unit pixel 30 includes a first imaging cell 31 and a second imaging cell 31'. The first imaging cell 31 is an imaging cell that supports high saturation, and the second imaging cell 31' is an imaging cell that supports low noise. Typically, the first imaging cell 31 functions as an imaging cell for low sensitivity, and the second imaging cell 31' functions as an imaging cell for high sensitivity. The imaging device 100 includes, for the first imaging cell 31, a plurality of reset signal lines 47 and a plurality of address signal lines 48 arranged for each row, and a plurality of vertical signal lines 45, power supply wiring 46, and a plurality of feedback signal lines 49 arranged for each column. The imaging device 100 also includes, for the second imaging cell 31', a plurality of reset signal lines 47' and a plurality of address signal lines 48' arranged for each row, and a plurality of vertical signal lines 45', power supply wiring 46', and a plurality of feedback signal lines 49' arranged for each column.

[0029] The image pickup device 100 is provided with a first peripheral circuit that processes signals from the first imaging cell 31 and a second peripheral circuit that processes signals from the second imaging cell 31'. The first peripheral circuit includes a first vertical scanning circuit 52, a first horizontal scanning circuit 53, and a first column AD conversion circuit 54, while the second peripheral circuit includes a second vertical scanning circuit 52', a second horizontal scanning circuit 53', and a second column AD conversion circuit 54'. However, the address signal lines for the first imaging cell 31 and the second imaging cell 31' may be common depending on the pixel configuration.

[0030] Focusing on the first imaging cell 31, a first vertical scanning circuit 52 controls a plurality of reset signal lines 47 and a plurality of address signal lines 48. The vertical signal lines 45 are connected to a first horizontal scanning circuit 53 and transmit pixel signals to the first horizontal scanning circuit 53. A power supply wiring 46 supplies a power supply voltage to all unit pixels 30. A feedback signal line 49 transmits a feedback signal from a feedback amplifier 50 (described later) to the first imaging cell 31 of the unit pixel 30. The second imaging cell 31′ is also wired with various signal lines similar to the first imaging cell 31, and each signal line is controlled by a respective circuit.

[0031] (Circuit configuration of first and second imaging cells 31, 31′) Next, an example of the circuit configuration of the first and second imaging cells 31, 31' will be described with reference to Fig. 5. The first and second imaging cells 31, 31' each have an independent but substantially identical circuit configuration.

[0032] FIG. 5 is an enlarged view of a unit pixel 30, and schematically shows the circuit configurations of the first and second imaging cells 31, 31'. The first imaging cell 31 includes a capacitive element, a first photoelectric conversion unit 43, and a first charge detection circuit 51, while the second imaging cell 31' includes a second photoelectric conversion unit 43' and a second charge detection circuit 51'. The capacitive element is, for example, a MOM capacitor 6, which will be described later. The circuit configuration will be described below, focusing on the first imaging cell 31.

[0033] The first charge detection circuit 51 includes an amplifying transistor 40, a reset transistor 41, and and an address transistor 42.

[0034] The first photoelectric conversion unit 43 is electrically connected to the drain electrode of the reset transistor 41 and the gate electrode of the amplification transistor 40, and performs photoelectric conversion on light (incident light) incident on the first imaging cell 31. The first photoelectric conversion unit 43 generates signal charges according to the amount of incident light. The generated signal charges are accumulated by the charge accumulation node 44.

[0035] The power supply wiring 46 is connected to the source electrode of the amplifying transistor 40. The power supply wiring 46 is wired in the column direction for the following reason: the first imaging cells 31 are selected row by row. Therefore, if the power supply wiring 46 were wired in the row direction, all of the pixel drive current for one row would flow through one power supply wiring 46, resulting in a large voltage drop. A common source follower power supply voltage is applied to the amplifying transistors 40 in all of the first imaging cells 31 in the imaging device 100 by the power supply wiring 46.

[0036] The amplifier transistor 40 amplifies the signal voltage according to the amount of signal charge stored in the charge storage node 44 .

[0037] The gate electrode of the reset transistor 41 is connected to the first vertical scanning circuit 52 via a reset signal line 47, and the source electrode is connected to a feedback signal line 49. The reset transistor 41 resets (initializes) the charge stored in the charge storage node 44. In other words, the reset transistor 41 resets the potential of the gate electrode of the amplification transistor 40.

[0038] The gate electrode of the address transistor 42 is connected to a first vertical scanning circuit 52 via an address signal line 48, and the drain electrode is connected to a first horizontal scanning circuit 53 via a vertical signal line 45. The address transistor 42 selectively outputs the output voltage of the amplifying transistor 40 to the vertical signal line 45.

[0039] The first vertical scanning circuit 52 applies a row selection signal that controls the on / off of the address transistor 42 to the gate electrode of the address transistor 42. This causes the row to be read out to be scanned in the vertical direction (column direction) and selected. A signal voltage is read out to the vertical signal line 45 from the unit pixels 30 in the selected row. The first vertical scanning circuit 52 also applies a reset signal that controls the on / off of the reset transistor 41 to the gate electrode of the reset transistor 41. This selects the row of the first imaging cells 31 in the unit pixels 30 that are the target of the reset operation.

[0040] The first column AD conversion circuit 54 performs noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion (AD conversion), on the signals read out from the first imaging cells 31 for each row to the vertical signal lines 45. The first horizontal scanning circuit 53 drives the readout of the signals processed by the first column AD conversion circuit 54.

[0041] (Device structure of unit pixel 30) FIG. 6 is a schematic cross-sectional view of the device structure of a unit pixel 30 in the imaging device 100 according to this embodiment.

[0042] Each unit pixel 30 typically includes a P-type silicon substrate 1, a first imaging cell 31, a second imaging cell 31', a photoelectric conversion film 9, an upper electrode 10, a color filter 11, and a microlens 12. However, if only monochrome imaging is performed, the color filter 11 may not be provided. Also, if light collection by a microlens is not performed, the microlens 12 may not be provided.

[0043] The photoelectric conversion unit is formed by a photoelectric conversion film 9, an upper electrode 10, a first pixel electrode 7, and a second pixel electrode 8. The photoelectric conversion unit has a first photoelectric conversion unit 43 of the first imaging cell 31 and a second photoelectric conversion unit 43' of the second imaging cell 31'. The photoelectric conversion film 9 includes a first photoelectric conversion region 33 for the first imaging cell 31 and a second photoelectric conversion region 33' for the second imaging cell 31'. The first photoelectric conversion region 33 is in contact with the first pixel electrode 7. The second photoelectric conversion region 33' is in contact with the second pixel electrode 8. In this embodiment, the sensitivity of the first imaging cell 31 is lower than that of the second imaging cell 31'. Furthermore, the capacitance of the charge storage node of the first imaging cell 31 is larger than the capacitance of the charge storage node of the second imaging cell 31'.

[0044] From the cross-sectional view of Figure 6, the first pixel electrode 7 appears to be divided into two with the second pixel electrode 8 in between. However, in reality, the two first pixel electrodes 7 in Figure 6 are electrically equipotential and are a single pixel electrode.

[0045] The microlens 12 is supported by the P-type silicon substrate 1 so as to cover the entire photoelectric conversion section. In this manner, the first imaging cell 31 and the second imaging cell 31′ have a common microlens 12. The microlens 12 focuses light incident on the unit pixel 30 onto the center of the unit pixel 30 (the second pixel electrode 8). The second pixel electrode 8 may be disposed on the optical axis of the microlens 12.

[0046] The photoelectric conversion film 9 is stacked above the P-type silicon substrate 1. The photoelectric conversion film 9 may be formed of, for example, an organic material or amorphous silicon. The photoelectric conversion film 9 photoelectrically converts incident light from the outside. The first pixel electrode 7 and the second pixel electrode 8 are in contact with the surface of the photoelectric conversion film 9 on the P-type silicon substrate 1 side. In other words, the first pixel electrode 7 and the second pixel electrode 8 are disposed between the P-type silicon substrate 1 and the photoelectric conversion film 9. The first pixel electrode 7 collects signal charges generated in the first photoelectric conversion region 33. The second pixel electrode 8 collects signal charges generated in the second photoelectric conversion region 33'.

[0047] The upper electrode 10 is a transparent electrode and is formed in contact with the surface of the photoelectric conversion film 9 that faces the first pixel electrode 7 and the second pixel electrode 8. A positive constant voltage is applied to the upper electrode 10, and a negative constant voltage is applied to the first pixel electrode 7 and the second pixel electrode 8. As a result, electron-hole pairs are generated in the photoelectric conversion film 9 by photoelectric conversion. Holes generated in the first photoelectric conversion region 33 on the first pixel electrode 7 move to the first pixel electrode 7. Holes generated in the second photoelectric conversion region 33' on the second pixel electrode 8 move to the second pixel electrode 8.

[0048] The first imaging cell 31 includes the area of ​​the unit pixel 30 other than the second imaging cell 31′. The first imaging cell 31 includes a first photoelectric conversion region 33, a first pixel electrode 7, a first charge storage node 32, a first charge detection circuit 51, and an STI (Shallow Trench Isolation) separation layer 2.

[0049] The first charge detection circuit 51 is formed on a P-type silicon substrate 1. The first charge detection circuit 51 is electrically connected to the first pixel electrode 7 via a first charge storage node 32. The first diffusion layer 22 in the figure is an N-type source region of the first reset transistor 41 (see FIG. 5). The arrow indicates the gate width of the first amplification transistor 40 (see FIG. 5). The drain and source regions of the first amplification transistor 40 are arranged in a direction perpendicular to the paper surface and are not shown.

[0050] The first charge accumulation node 32 accumulates the charges (holes) that have moved to the first pixel electrode 7. In addition to the first charge accumulation node 32, the first pixel electrode 7, the first diffusion layer 22, the first amplification transistor The gate electrode 3 of the transistor 40 and the wiring (not shown) electrically connecting them can also function as a charge storage node for storing holes. These elements functioning as charge storage nodes are collectively referred to as "charge storage node 44" (see FIG. 5). The gate electrode 3 can be formed from polysilicon.

[0051] The first imaging cell 31 further includes a MOM (Metal Oxide Metal) capacitor 6, one end of which is electrically connected between the first charge detection circuit 51 and the first pixel electrode 7. The MOM capacitor 6 increases the capacitance of the charge storage node 44. As a result, the number of saturation electrons in the first imaging cell 31 can be increased, as shown in FIG. 3. The first imaging cell 31 functions as an imaging cell capable of high saturation.

[0052] The second imaging cell 31 ′ includes a second photoelectric conversion region 33 ′, a second pixel electrode 8 , a second charge storage node 32 ′, a second charge detection circuit 51 ′, and an STI isolation layer 2 .

[0053] The second charge detection circuit 51' is formed on the P-type silicon substrate 1. The second charge detection circuit 51' is electrically connected to the second pixel electrode 8 via the second charge storage node 32'. The second diffusion layer 23 in the figure is an N-type source region of the second reset transistor 41' (see FIG. 5).

[0054] The second charge storage node 32' stores holes that have moved to the second pixel electrode 8. In addition to the second charge storage node 32', the second pixel electrode 8, the second diffusion layer 23, the gate electrode 3 of the second amplification transistor 40', and wiring (not shown) electrically connecting these elements can also function as charge storage nodes that store holes. These are collectively referred to as "charge storage node 44'" (see FIG. 5).

[0055] The second imaging cell 31' does not include a capacitive element such as an MOM capacitor. As shown in Fig. 3, random noise can be suppressed by relatively reducing the capacitance of the charge storage node 44' in the second imaging cell 31'. The second imaging cell 31' functions as an imaging cell capable of low noise.

[0056] The first charge storage node 32 and the second charge storage node 32' are connected to a local wiring 4 via a contact plug 5. The first charge storage node 32 is electrically connected to the gate electrode 3 and the first diffusion layer 22 via the local wiring 4. The second charge storage node 32' is electrically connected to the gate electrode 3 and the second diffusion layer 23 via the local wiring 4. The local wiring 4 may be made of polysilicon.

[0057] FIG. 7 shows the planar shapes of the pixel electrodes (first pixel electrode 7 and second pixel electrode 8) in a unit pixel 30 when viewed from the normal direction of the P-type silicon substrate 1. The second pixel electrode 8 is disposed in the center of the unit pixel 30 and has a substantially circular shape. Its radius is, for example, 0.75 μm. The first pixel electrode 7 is disposed with a gap therebetween so as to surround the second pixel electrode 8. The area of ​​the second pixel electrode 8 is smaller than the area of ​​the first pixel electrode 7.

[0058] The length W of one side of the unit pixel 30 is, for example, 3 μm. The unit pixel 30 includes three-layer Cu wiring. The length W corresponds to the distance between the centers of adjacent unit pixels 30 (pixel pitch).

[0059] In this embodiment, the area of ​​the first pixel electrode 7 is larger than the area of ​​the second pixel electrode 8. In addition, the second pixel electrode 8 is disposed in the area where light is collected by the microlens 12 (near the center of the unit pixel 30). The pixel electrodes 8 are arranged in this manner. By arranging them in this manner, the second imaging cell 31' having a smaller area functions as a high-sensitivity imaging cell, and the first imaging cell 31 functions as a low-sensitivity imaging cell, by utilizing the light collection of the microlenses 12. As a result, a low-sensitivity image can be captured by the first imaging cell 31, and a high-sensitivity image can be captured by the second imaging cell 31'. For example, a high-sensitivity image refers to an image of a dark subject obtained in a dark environment, and a low-sensitivity image refers to an image of a bright subject obtained in a bright environment.

[0060] Now, with reference to FIG. 8, the sensitivities of the first imaging cell 31 and the second imaging cell 31' will be explained in more detail.

[0061] 8 shows the relationship between the radius of the second pixel electrode 8 and the light collection efficiency of the second pixel electrode 8, when the light collection efficiency of the entire unit pixel 30 is normalized to 100%. The horizontal axis represents the radius (μm) of the second pixel electrode 8, and the vertical axis represents the light collection efficiency (%) of the second pixel electrode 8.

[0062] When the radius of the second pixel electrode 8 is 0.75 μm, its area is approximately 20% of the area of ​​the entire pixel unit 30. Even in this case, it can be seen that a high light collection efficiency of 90% or more can be obtained. This is because the incident light is mainly collected at the center of the pixel by the microlens 12. The light collection efficiency is proportional to the number of charges (holes) generated in the photoelectric conversion film on the pixel electrode. As long as light is collected by the microlens 12, a high sensitivity of 90% or more can be maintained even if the area of ​​the second pixel electrode 8 is small.

[0063] In contrast, the area of ​​the first pixel electrode 7 occupies 80% of the entire area of ​​the unit pixel 30. However, since only 10% or less of the incident light is incident on the first photoelectric conversion region 33 on the first pixel electrode 7, the sensitivity of the first imaging cell 31 drops to 10% or less. In this way, a sensitivity difference of approximately one digit can be generated between the first imaging cell 31 and the second imaging cell 31'.

[0064] The electrodes and wiring of the unit pixel 30 can be made of a wide range of materials that are commonly used in the manufacture of silicon semiconductor devices.

[0065] Referring again to FIG.

[0066] Random noise may occur when transferring or resetting signal charges in the imaging device 100. However, the following will mainly describe random noise caused by reset noise that occurs when resetting signal charges.

[0067] If random noise remains at the time of reset, the remaining noise may be added to the signal charge that is next accumulated in the charge accumulation node 44. In that case, when the signal charge is read out, a signal on which random noise is superimposed is output.

[0068] The image pickup device 100 includes a feedback circuit to remove this random noise. The feedback operation of the feedback circuit will be described below.

[0069] The feedback circuit includes a feedback amplifier 50. A feedback amplifier 50 is provided corresponding to each column of unit pixels 30. The negative input terminal of the feedback amplifier 50 is connected to the corresponding vertical signal line 45. The output terminal of the feedback amplifier 50 and the source electrode of the reset transistor 41 are connected via a feedback signal line 49 via a switch. Therefore, the feedback amplifier 50 is connected to the amplifying transistor 40, the address transistor 42, the reset transistor 41, and When the amplifier transistor 40 is in a conductive state, the negative terminal of the amplifier receives the output value of the address transistor 42. The feedback amplifier 50 performs a feedback operation so that the gate potential of the amplifier transistor 40 becomes a predetermined feedback voltage.

[0070] In the imaging device 100, one row of unit pixels 30 is selected by a first vertical scanning circuit 52. Signal charges photoelectrically converted by first photoelectric conversion units 43 in the selected unit pixels 30 are amplified by amplification transistors 40. The signal charges in the unit pixels 30 are output to vertical signal lines 45 via address transistors 42.

[0071] The output signal charges are selected by the first horizontal scanning circuit 53 and output to the outside. The signal charges in the first imaging cell 31 are discharged by turning on the reset transistor 41. At this time, a large thermal noise (random noise) called kTC noise is generated from the reset transistor 41. This thermal noise remains in the charge storage node 44 even after the reset operation.

[0072] To suppress this thermal noise, the vertical signal line 45 is connected to the negative input terminal of the feedback amplifier 50. The voltage value at the negative input terminal is inverted and amplified by the feedback amplifier 50. When the charge in the charge storage node 44 is reset by the reset transistor 41, the three transistors become conductive. The inverted and amplified signal is fed back to the source electrode of the reset transistor 41 via the feedback signal line 49. Specifically, random noise generated in the charge storage node 44 is negatively fed back to the source electrode of the reset transistor 41 via the amplifier transistor 40, the address transistor 42, the vertical signal line 45, the feedback amplifier 50, and the feedback signal line 49. The noise component of the charge storage node 44 is canceled out, and the random noise can be suppressed by negative feedback control. The AC component of the thermal noise is fed back to the source electrode of the reset transistor 41. The DC component is a positive voltage near 0 V.

[0073] As described above, the number of saturated electrons is determined by the capacitance of the charge storage node 44 that stores the charges (holes) generated in the photoelectric conversion film 9.

[0074] Referring again to FIG.

[0075] The capacitance of the charge storage node 44 in the first imaging cell 31 mainly includes the capacitance between the first pixel electrode 7 and the upper electrode 10, the capacitance between the first pixel electrode 7 and the second pixel electrode 8, the capacitance between the first pixel electrode 7 and the first pixel electrode 7 of the adjacent unit pixel 30, the parasitic capacitance between the Cu wirings, the gate capacitance of the first amplification transistor 40, and the junction capacitance of the first diffusion layer 22. The capacitance of the charge storage node 44' in the second imaging cell 31' mainly includes the capacitance between the second pixel electrode 8 and the upper electrode 10, the capacitance between the first pixel electrode 7 and the second pixel electrode 8, the parasitic capacitance between the Cu wirings, the gate capacitance of the second amplification transistor 40', and the junction capacitance of the second diffusion layer 23. Of these, the components that account for a large proportion of the capacitance of each of the charge storage nodes 44 and 44' are the capacitance components related to the first pixel electrode 7 and the second pixel electrode 8.

[0076] The first imaging cell 31 functions as an imaging region for capturing an image of a bright subject with a high amount of light. A desirable characteristic required of the first imaging cell 31 is a high number of saturated electrons (high saturation). In this embodiment, as shown in FIG. 7 , the first pixel electrode 7 is disposed outside the central region of the unit pixel 30 where incident light is focused by the microlens 12 so as to avoid this region, thereby ensuring a sufficient area for the first pixel electrode 7. As a result, the capacitance of the charge storage node 44 in the first imaging cell 31 increases, thereby achieving desirable high saturation characteristics.

[0077] Furthermore, as shown in FIG. 6 , the capacitance of the charge storage node 44 of the first imaging cell 31 is further increased by electrically connecting the MOM capacitor 6 to the first pixel electrode 7. The capacitance of the charge storage node 44' of the second imaging cell 31' needs to be small to suppress noise. A small capacitance of the charge storage node 44' reduces the electrical capacitive coupling between adjacent charge storage nodes 44'. However, the mutual influence of the charge storage nodes 44' on the voltages of the charge storage nodes 44' increases. By placing the MOM capacitor 6 between the Cu wiring of the adjacent second imaging cell 31', the capacitive coupling between the adjacent charge storage nodes 44' can be suppressed, thereby suppressing color mixing. Note that the MOM capacitor 6 increases the capacitive coupling between the charge storage node 44 of the first imaging cell 31 and the charge storage node 44' of the second imaging cell 31'. However, because the capacitance of the charge storage node 44 of the first imaging cell 31 is large, the voltage swing of the charge storage node 44 is small, and the impact on color mixing is negligible.

[0078] On the other hand, the second imaging cell 31' functions as an imaging area for capturing images of dark subjects in low light. A desirable characteristic required of the second imaging cell 31' is low random noise. The number of saturation electrons may be low, i.e., low saturation.

[0079] 7 and 8, the second pixel electrode 8 can achieve high sensitivity in a relatively small area by utilizing light collection by the microlens 12. Furthermore, as shown in FIG. 3, by reducing the area of ​​the second pixel electrode 8, the capacitance of the charge storage node 44' in the second imaging cell 31' is reduced, ensuring a relatively large conversion gain in the amplifying transistor 40'. In the feedback circuit of FIG. 5, the greater the conversion gain, the more effective the feedback circuit operation becomes, enabling random noise to be effectively suppressed.

[0080] Furthermore, in the feedback circuit, increasing the mutual conductance gm of the amplifier transistor 40' improves the transistor's driving capability, making it easier to suppress random noise. In this embodiment, the area of ​​the second charge detection circuit 51' is made larger than the area of ​​the first charge detection circuit 51. Specifically, the gate width of the amplifier transistor 40' in the second imaging cell 31' is made larger than the gate width of the amplifier transistor 40 in the first imaging cell 31. As a result, the drain current flowing through the amplifier transistor 40' increases, thereby improving the driving capability of the amplifier transistor 40'. In the second imaging cell 31', low-noise imaging can be achieved.

[0081] Compared to the second imaging cell 31', the first imaging cell 31 has relatively large noise. However, in high dynamic range processing, the image obtained by the first imaging cell 31 and the image obtained by the second imaging cell 31' are combined. As a result, the S / N ratio after combination is improved, and noise caused by the first imaging cell 31 does not pose a problem in the combined image.

[0082] FIG. 9 schematically shows the areas occupied by the first charge detection circuit 51 and the second charge detection circuit 51′ in the unit pixel 30. Region 60 indicates the area of ​​the first charge detection circuit 51, and region 61 indicates the area of ​​the second charge detection circuit 51′. The areas of the first charge detection circuit 51 and the second charge detection circuit 51′ each represent the sum of the areas of the transistors formed on the P-type silicon substrate 1. By reducing the area occupied by the transistors constituting the first charge detection circuit 51, the area occupied by the transistors of the second charge detection circuit 51′ can be increased. As a result, the driving capability of the second charge detection circuit 51′ can be improved, and low-noise imaging can be achieved in the second imaging cell 31′.

[0083] (Method of driving the imaging device 100) An example of an operation sequence of the imaging device 100 will be described with reference to FIG.

[0084] FIG. 10 schematically shows exposure and readout operations for one cycle (one frame) in the imaging device 100. The horizontal axis indicates time, and the vertical axis indicates the readout row. FIG. 10 shows so-called rolling shutter readout. In the imaging device 100, if exposure and readout operations are performed at the same timing using the first imaging cell 31 and the second imaging cell 31′, the dynamic range can, in principle, be expanded.

[0085] In the device configuration shown in FIG. 6, a sensitivity difference of approximately one order of magnitude is created between the first imaging cell 31 and the second imaging cell 31′, and even when the same exposure and readout are performed, the dynamic range can be improved by approximately one order of magnitude compared to normal pixels.

[0086] In this embodiment, in order to further expand the dynamic range, the first imaging cell 31 and the second imaging cell 31' each have independent exposure and readout timings. In one cycle of imaging operation, the second imaging cell 31' is exposed for a first accumulation time T1, and the first imaging cell 31 is exposed for second accumulation times T2 and T3 that are shorter than the first accumulation time T1. This will be explained in detail below.

[0087] In this embodiment, one cycle is, for example, 1 / 60 seconds. First, the second imaging cells 31' are exposed for an accumulation time T1 that is close to one cycle, and after the accumulation time has elapsed, the charges in the second imaging cells 31' are read out row by row (readout 1). When the row-by-row readout is completed, the charges accumulated in the second imaging cells 31' in all of the readout-target rows are reset.

[0088] In the first imaging cell 31, so-called non-destructive readout is performed at least twice per cycle. For example, a first exposure is performed with an accumulation time T2 of 1 / 30 (1 / 1800 seconds) of one cycle period, and readout is performed after the exposure is complete (readout 2). Then, without resetting the accumulated charge, a second exposure is performed with an accumulation time T3 of 1 / 2 (1 / 120 seconds) of one cycle period, and readout is performed after the exposure is complete (readout 3). This operational sequence allows three sets of imaging data with different exposure times to be acquired in one cycle period. Performing the same exposure and readout operation would have improved the dynamic range by approximately one order of magnitude, but combining these imaging data allows for an image with a higher dynamic range by approximately one and a half orders of magnitude, for a total of approximately two and a half orders of magnitude.

[0089] Modifications of the imaging device 100 will be described below with reference to FIGS. 11A to 12B.

[0090] 11A to 11C each show modified examples of the planar shape of the second pixel electrode 8. As shown in the figures, the planar shape of the second pixel electrode 8 does not have to be circular; for example, it may be a donut shape as shown in FIG. 11A, a cross shape as shown in FIG. 11B, or a notched shape as shown in FIG. 11C. Furthermore, the notch may be circular instead of rectangular. Such a shape can suppress changes in the sensitivity of the first imaging cell 31 due to changes in the incident angle of light. Furthermore, even if the incident angle of light changes, the ratio between the sensitivity of the second imaging cell 31′ and the sensitivity of the first imaging cell 31 can be maintained constant.

[0091] In this embodiment, an example has been described in which incident light is focused at the center of the unit pixel 30 using the microlens 12, but the present disclosure is not limited to this. The imaging device 100 does not need to include the microlens 12. When light is not focused, the sensitivity and the number of saturated electrons depend only on the area of ​​the pixel electrode and are approximately proportional to it. Therefore, it is possible to eliminate the microlens 12 and set the sensitivity ratio based only on the area ratio of the pixel electrodes.

[0092] 12A and 12B show an example of the shape of the pixel electrode when the microlens 12 is eliminated. As shown in FIG. 12A, the second pixel electrode 8 is disposed at the center of the unit pixel 30. 12B , the first pixel electrode 7 may be disposed around the unit pixel 30 with a gap therebetween. Alternatively, as shown in FIG. 12B , the first pixel electrode 7 may be disposed at the center of the unit pixel 30, and the second pixel electrode 8 may be disposed around the unit pixel 30 with a gap therebetween. As long as the area of ​​the second pixel electrode 8 is larger than the area of ​​the first pixel electrode 7, the shape of the pixel electrode may be determined arbitrarily.

[0093] However, with this configuration, the area of ​​the first pixel electrode 7 is reduced, resulting in a decrease in both the cell sensitivity and capacitance. Therefore, by connecting the MOM capacitor 6 to the first pixel electrode 7, the capacitance of the charge storage node 44 in the first imaging cell 31 can be increased.

[0094] In this embodiment, the random noise and the number of saturated electrons are different between the first imaging cell 31 and the second imaging cell 31′. However, the present disclosure is not limited to this example, and at least one of the random noise and the capacitance may be different. In this embodiment, the capacitance of the charge storage node of the second imaging cell 31′ is reduced to suppress random noise using a feedback circuit, thereby increasing the conversion gain. As a result, the number of saturated electrons of the second imaging cell 31′ can be reduced. However, if random noise is canceled by taking the difference between data before and after imaging using an external memory, the capacitance of the charge storage node of the second imaging cell 31′ does not need to be reduced. Image synthesis can be facilitated by connecting a capacitive element (e.g., a metal-on-metal capacitor) to the second imaging cell 31′ to increase the number of saturated electrons. Furthermore, for example, in a configuration that does not include a microlens 12, if the areas of the first pixel electrode 7 and the second pixel electrode are the same, the sensitivity and capacitance will be approximately the same. Therefore, connecting a metal-on-metal capacitor to the first pixel electrode 7 increases the capacitance of the charge storage node 44 of the first imaging cell 31. In other words, only the capacitance can be made different between the first imaging cell 31 and the second imaging cell 31'. In this case, the sensitivity performance is deteriorated, but image synthesis can be facilitated.

[0095] In this disclosure, the term "storage capacitance" refers to all capacitance components connected to a pixel electrode. In this embodiment, the first storage capacitance is exemplified by the charge storage node 44 and the MOM capacitance 6. The second storage capacitance is exemplified by the charge storage node 44'. The capacitance element (capacitor) is exemplified by the MOM capacitance 6.

[0096] (Second embodiment) An imaging device 100 according to the second embodiment will be described with reference to FIGS.

[0097] The unit pixel 30A according to the second embodiment differs from the unit pixel 30 according to the first embodiment in that the first imaging cell 31 has a MIM (Metal Insulator Metal) capacitance element 13 as a capacitance element. The following description will focus on the differences from the unit pixel 30.

[0098] 13 is a schematic cross-sectional view of the device structure of a unit pixel 30A according to this embodiment. The first imaging cell 31 has a MIM capacitance element 13 as a capacitance element. The MIM capacitance element 13 has a layered structure including an upper electrode 14, a lower electrode 16, and an insulator 15 sandwiched between the upper electrode 14 and the lower electrode 16.

[0099] The insulator 15 is made of a high-dielectric-constant material such as silicon nitride film, hafnium oxide (HfO2), zirconium oxide (ZrO2), strontium titanate (SrTiO), and titanium oxide (TiO2). Silicon nitride film is generally used as a capacitor for analog circuits. Hafnium oxide (HfO2) and zirconium oxide (ZrO2) are used as a capacitive insulating film for DRAM (Dynamic Random Access Memory). When a leakage current occurs in the insulator 15, the charge contributed to the leakage current is stored as a charge accumulation film. As a result, the leakage current becomes a noise component in the dark.

[0100] The film composition of high-dielectric-constant materials is easily affected by heat treatment after film formation. For example, heat treatment at about 400°C can accelerate crystallization and degrade current leakage characteristics. Therefore, it is desirable to form the MIM capacitance element 13 after the pixel wiring arrangement is completed, or to form it as high up in the wiring layer as possible. Furthermore, wiring and contact plugs made of polysilicon or tungsten, which require film formation temperatures exceeding 400°C, should be formed before the MIM capacitance element 13 is formed.

[0101] The MIM capacitance element 13 can be made of a material and have a structure independent of the wiring. The MIM capacitance element 13 is formed from a material with a high dielectric constant. By using an insulator 15 several tens of nanometers thick, the MIM capacitance element 13 can achieve a capacitance significantly larger than that of the MOM capacitance element 6 described in the first embodiment. However, additional processes are required to form the MIM capacitance element. As a result, it should be noted that this increases manufacturing costs. In contrast, using the MOM capacitance element 6 as a capacitance element allows the use of the same wiring structure used for signal transmission within or between pixels. This reduces manufacturing costs. However, if the capacitance density of the MOM capacitance element 6 is limited by the wiring structure used, and if the wiring becomes congested, it may become difficult to secure space for the MOM capacitance element 6, resulting in insufficient capacitance. In such cases, it is desirable to use the MIM capacitance element 13, which allows for secure placement space regardless of wiring congestion, as the capacitance element. Ultimately, the optimal capacitance element can be selected appropriately based on design specifications, etc.

[0102] The MIM capacitance element 13 increases the capacitance of the charge storage node 44 of the first imaging cell 31. As a result, the number of saturated electrons in the first imaging cell 31 can be increased, as in the first embodiment. The first imaging cell 31 functions as an imaging cell capable of high saturation. Note that the second imaging cell 31' has the same structure as the second imaging cell 31' of the unit pixel 30 according to the first embodiment, and therefore functions as an imaging cell capable of low noise.

[0103] Fig. 14 focuses on a 3 × 3 unit pixel 30B according to a modification of this embodiment and schematically shows its layout in the imaging device 100. Fig. 15 schematically shows a cross section of the device structure of the unit pixel 30B. Fig. 16 schematically shows a cross section of the unit pixel 30B taken along line A-A' shown in Fig. 14.

[0104] Each unit pixel 30B has a first imaging cell 31 having a first pixel electrode 7 and a second imaging cell 31' having a second pixel electrode 8. Focusing on the 3×3 unit pixel 30B, three unit pixels 30B are arranged along line A-A' (a direction forming an angle of approximately 45° with the x-axis in the figure) shown in FIG. 14. One first pixel electrode 7 is located approximately at the center of the second pixel electrodes 8 arranged in a 2×2 matrix. The area of ​​the second pixel electrode 8 is larger than that of the first pixel electrode 7. In this way, the first imaging cells 31 and the second imaging cells 31' can be arranged closely together, thereby improving the efficiency of the layout.

[0105] As shown in FIG. 15 , unlike the first embodiment, the microlens 12 is supported by the P-type silicon substrate 1 so as to cover the second photoelectric conversion unit 43′. When viewed from the normal direction of the P-type silicon substrate 1, the MIM capacitance element 13 is disposed between the first photoelectric conversion unit 43 and the second photoelectric conversion unit 43′. In other words, the MIM capacitance element 13 is disposed between the first pixel electrode 7 and the second pixel electrode 8. As shown in the figure, the MIM capacitance element 13 may be formed so that at least a portion of the MIM capacitance element 13 overlaps both or one of the first pixel electrode 7 and the second pixel electrode 8. This increases the size of the MIM capacitance element 13, thereby increasing its capacitance.

[0106] According to this modification, similarly to the second embodiment, it is possible to increase the capacitance of the charge storage node 44 of the first imaging cell 31. As a result, the number of saturated electrons in the first imaging cell 31 increases, and the first imaging cell 31 can function as an imaging cell capable of high saturation.

[0107] 17 is a schematic cross-sectional view of a device structure of a unit pixel 30C according to another modification of this embodiment. Two microlenses 12 may be supported on the P-type silicon substrate 1 so as to cover the first photoelectric conversion unit 43 and the second photoelectric conversion unit 43′, respectively. In this case, the light-collecting area of ​​the microlens of the second imaging cell 31′ is larger than the light-collecting area of ​​the microlens of the first imaging cell 31. By providing a microlens in the first imaging cell 31 as well, the incident angle characteristics of the first imaging cell 31 and the second imaging cell 31′ can be made uniform, resulting in a more natural composite image.

[0108] The second imaging cell 31' may include an MIM capacitor 13' having a capacitance smaller than that of the MIM capacitor 13. The purpose of connecting the MIM capacitor 13' to the second charge storage node 44' is as follows: a control voltage is applied to a terminal 55 of the MIM capacitor 13' opposite to the terminal connected to the second charge storage node 44'. This allows capacitive coupling via the MIM capacitor 13' to be utilized to control the voltage of the second charge storage node 44', thereby suppressing random noise and leakage current.

[0109] For example, the capacitance of the second charge storage node 44' to which the MIM capacitance element 13' is not connected is 0.5 fF to 3 fF. However, the capacitance of the charge storage node is highly dependent on the pixel size. When the MIM capacitance element 13' is connected, the capacitance of the second charge storage node 44' is set to a value that can prevent an increase in random noise. The MIM capacitance element 13 is used to increase the capacitance of the first charge storage node 44. Therefore, its capacitance is set to a value that exceeds the capacitance of the first charge storage node 44 to which the MIM capacitance element 13 is not connected. For example, the capacitance of the first charge storage node 44 is 0.5 fF to 3 fF, similar to the capacitance of the second charge storage node 44' to which the MIM capacitance element 13' is not connected.

[0110] (Third embodiment) An imaging module 200 according to this embodiment will be described with reference to FIG.

[0111] FIG. 18 is a schematic diagram showing functional blocks of an imaging module 200 incorporating the imaging device 100. As shown in FIG.

[0112] The imaging module 200 includes the imaging device 100 according to the first embodiment and a DSP (Digital Signal Processor) 300. The imaging module 200 processes the signal obtained by the imaging device 100 and outputs the processed signal to the outside.

[0113] The DSP 300 functions as a signal processing circuit that processes the output signal from the image capture device 100. The DSP 300 receives the digital pixel signal output from the image capture device 100. The DSP 300 performs processes such as gamma correction, color interpolation, spatial interpolation, and auto white balance. Note that the signal processing circuit may also be realized by a microcomputer that controls the image capture device 100 in accordance with various settings specified by the user and integrates the overall operation of the image capture module 200.

[0114] The DSP 300 processes the digital pixel signals output from the image pickup device 100 to calculate optimal reset voltages (VRG, VRB, and VRR). The DSP 300 feeds back the reset voltages to the image pickup device 100. Here, VRG, VRB, and VRR are reset voltages for G pixels, B pixels, and R pixels, respectively. 1 shows a reset voltage related to the image pickup device 100. The reset voltage may be a feedback signal transmitted from the feedback signal line 49 or the vertical signal line 45. The image pickup device 100 and the DSP 300 can also be manufactured as a single semiconductor device (a so-called SoC (System on a Chip)). This allows for miniaturization of electronic devices using the image pickup device 100.

[0115] It is of course possible to commercialize only the imaging device 100 without modularizing it. In that case, a signal processing circuit may be externally connected to the imaging device 100, and signal processing may be performed outside the imaging device 100. Furthermore, in the first and second embodiments, an example has been shown in which a photoelectric conversion film is disposed on the front side of the silicon substrate 1 and incident light from the front side is detected. However, the present disclosure is not limited to this, and also includes an image sensor using a BSI (Backside Illumination) method in which a photoelectric conversion film is disposed on the back side of the silicon substrate 1 and incident light from the back side is detected. [Industrial Applicability]

[0116] The imaging device and the driving method thereof according to the present disclosure are useful for image sensors used in cameras such as digital cameras and vehicle-mounted cameras, and for driving methods thereof. [Explanation of symbols]

[0117] 1 p-type semiconductor substrate 2 STI separation layer 3. Gate electrode 4 Local Wiring 5 Contact plug 6 MOM capacity 7 First pixel electrode 8 Second pixel electrode 9 Photoelectric conversion film 10 Upper electrode 11 Color Filter 12 Microlenses 13, 13' MIM capacitor element 14 Upper electrode 15 Insulators 16 Lower electrode 22 First diffusion layer 23 Second diffusion layer 30, 30A, 30B, 30C unit pixel 31 First imaging cell 31' Second imaging cell 32 First charge storage node 32' Second charge storage node 33 First photoelectric conversion region 33' Second photoelectric conversion region 40, 40' Amplifying transistor 41, 41' Reset transistor 42, 42' Address transistor 43. First photoelectric conversion unit 43' Second photoelectric conversion unit 44, 44' charge storage node 45, 45' vertical signal line 46, 46' power wiring 47, 47' Reset signal line 48, 48' address signal lines 49, 49' Feedback signal line 50, 50' Feedback Amplifier 51 First charge detection circuit 51' Second charge detection circuit 52 First vertical scanning circuit 52' Second vertical scanning circuit 53 First horizontal scanning circuit 53' Second horizontal scanning circuit 54 First column AD conversion circuit 54' Second column AD conversion circuit 55 terminals 60 Area of ​​the first charge detection circuit 61 Area of ​​the second charge detection circuit 100 Imaging device 200 Imaging Module 300 DSP

Claims

1. a first photoelectric conversion unit that converts incident light into electric charges; a capacitance element electrically connected to the first photoelectric conversion unit; a second photoelectric conversion unit that converts incident light into electric charges; Equipped with In a plan view, at least a portion of the capacitive element overlaps a region between the first photoelectric conversion unit and the second photoelectric conversion unit. Imaging device.

2. a pixel including a first cell and a second cell; The first cell is a first photoelectric conversion unit that converts incident light into electric charges; a capacitance element electrically connected to the first photoelectric conversion unit; Including, The second electric cell is A second photoelectric conversion unit that converts incident light into electric charges Including, In a plan view, at least a portion of the capacitive element overlaps a region between the first photoelectric conversion unit and the second photoelectric conversion unit. Imaging device.

3. In a plan view, the second photoelectric conversion unit is adjacent to the first photoelectric conversion unit without any other photoelectric conversion unit therebetween.

3. The imaging device according to claim 1.

4. In a plan view, the area of ​​the second photoelectric conversion unit is larger than the area of ​​the first photoelectric conversion unit. The imaging device according to claim 1 .

5. In a plan view, at least a portion of the capacitive element overlaps with the second photoelectric conversion unit. The imaging device according to claim 1 .

6. the capacitance element has a laminated structure including a lower electrode, an upper electrode, and an insulator sandwiched between the lower electrode and the upper electrode; The imaging device according to claim 1 .

7. The capacitance element is an MIM capacitance element. The imaging device according to claim 1 .

Images