Battery monitoring device

Abstract

The circuit area is kept small, and the synchronization of voltage detection by the main voltage detection section and the sub-voltage detection section is improved. [Solution] A battery monitoring device 1 includes a main voltage detection unit 6 provided corresponding to each of a plurality of battery cells Cb and detecting the voltages of the plurality of battery cells Cb, sub-voltage detection units 7 provided corresponding to two or more of the plurality of battery cells Cb and detecting the voltages of the two or more battery cells Cb in a time-division manner, and a detection control unit 9. When detecting the voltage of a detection target battery cell, which is a battery cell Cb selected as a detection target by the sub-voltage detection unit 7, the detection control unit 9 controls the operation of the main voltage detection unit 6 and the sub-voltage detection unit 7 so that the difference in the start timing of A / D conversion and the difference in the conversion period of A / D conversion between the second A / D converter 14 of the sub-voltage detection unit 7 and the first A / D converter 11 of the main voltage detection unit 6 that detects the voltage of the detection target battery cell are within a predetermined tolerance.

Description

[Technical Field]

[0001] The present invention relates to a battery monitoring device that monitors a battery pack in which a plurality of battery cells are connected in series. [Background technology]

[0002] As disclosed in Patent Document 1, a battery monitoring device mounted on a vehicle such as an automobile is required to have the function of diagnosing failures in various paths and components related to voltage detection. To achieve this function, a battery monitoring device has traditionally been provided with a sub-voltage detection unit for diagnostic purposes in addition to a main voltage detection unit that detects the voltages of multiple battery cells. In such a configuration, to reduce the number of external filter components at the cell input, both the main voltage detection unit and the sub-voltage detection unit must be configured with an A / D converter and a digital filter that functions as a low-pass filter.

[0003] In this case, the following two configurations are possible: A first conventional configuration is one in which a main voltage detection unit is provided corresponding to each of the plurality of battery cells, and a sub-voltage detection unit is provided corresponding to each of the plurality of battery cells; A second conventional configuration is one in which a main voltage detection unit is provided corresponding to each of the plurality of battery cells, and a sub-voltage detection unit is provided corresponding to two or more of the plurality of battery cells.

[0004] In the second prior art, the voltages of the two or more battery cells are detected in a time-division manner by the sub-voltage detection unit by switching between them using a selector or the like. Furthermore, in the second prior art, from the viewpoint of reducing circuit area and manufacturing costs, different types of A / D converters are often used for the main voltage detection unit and the sub-voltage detection unit. Specifically, for example, a ΔΣ A / D converter is used for the main voltage detection unit, and a successive approximation A / D converter is used for the sub-A / D converter. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 6174146 Summary of the Invention [Problem to be solved by the invention]

[0006] In the first conventional configuration, the sub-voltage detection unit requires A / D converters and digital filters in numbers corresponding to the number of battery cells, resulting in a problem of large circuit area. In the second conventional configuration, the main voltage detection unit and the sub-voltage detection unit have different transfer functions, resulting in poor synchronization. This poor synchronization leads to a decrease in the accuracy of fault diagnosis, which in turn reduces the energy available in the battery cells and may shorten the vehicle's driving distance.

[0007] The present invention has been made in consideration of the above circumstances, and its purpose is to provide a battery monitoring device that can reduce the circuit area and improve the synchronization of voltage detection by the main voltage detection unit and the sub-voltage detection unit. [Means for solving the problem]

[0008] The battery monitoring device described in claim 1 monitors an assembled battery (2) in which a plurality of battery cells (Cb) are connected in series, and includes: main voltage detection units (6) provided corresponding to each of the plurality of battery cells and detecting the voltages of the plurality of battery cells; sub-voltage detection units (7) provided corresponding to two or more of the plurality of battery cells and detecting the voltages of the two or more battery cells in a time-division manner; and a detection control unit (9) that controls the operation of the main voltage detection units and the sub-voltage detection units. The main voltage detection units include a first A / D converter (11) that receives an input voltage corresponding to the voltage of the corresponding battery cell, and a first digital filter (12) that receives a digital signal output from the first A / D converter and functions as a low-pass filter.

[0009] The sub-voltage detection unit includes a cell selection circuit (13, 41, 51) that selects one of the corresponding battery cells as a detection target, a second A / D converter (14) that receives an input voltage corresponding to the voltage of the battery cell selected by the cell selection circuit, and a second digital filter (15) that receives a digital signal output from the second A / D converter and functions as a low-pass filter. When detecting the voltage of a detection target battery cell that is the battery cell selected by the sub-voltage detection unit as a detection target, the detection control unit controls the operations of the main voltage detection unit and the sub-voltage detection unit so that the difference in A / D conversion start timing and the difference in A / D conversion period between the second A / D converter of the sub-voltage detection unit and the first A / D converter of the main voltage detection unit that detects the voltage of the detection target battery cell are within a predetermined allowable error.

[0010] With this configuration, the number of sub-voltage detection units can be reduced to half or more compared to a configuration in which a sub-voltage detection unit is provided for each of all battery cells, thereby reducing the circuit area. Furthermore, with this configuration, when the main voltage detection unit and the sub-voltage detection unit detect the voltage of the same battery cell, the difference in the start timing of A / D conversion and the difference in the conversion period of A / D conversion between the second A / D converter of the sub-voltage detection unit and the first A / D converter of the main voltage detection unit are kept within a predetermined tolerance, thereby improving the synchronization of voltage detection. Therefore, with this configuration, the circuit area can be reduced and the synchronization of voltage detection by the main voltage detection unit and the sub-voltage detection unit can be improved.

[0011] The battery monitoring device according to claim 2 further includes: a first filter circuit provided corresponding to each of the plurality of battery cells, receiving the voltage of the corresponding battery cell as an input and functioning as a low-pass filter; and a second filter circuit provided corresponding to each of the plurality of battery cells, receiving the voltage of the corresponding battery cell as an input and functioning as a low-pass filter. The first A / D converter of the main voltage detection unit receives the output voltage of the first filter circuit as the input voltage. The second A / D converter of the sub-voltage detection unit receives the output voltage of the second filter circuit as the input voltage.

[0012] The first A / D converter and the second A / D converter are ΔΣ A / D converters of the same order. The first digital filter and the second digital filter are digital filters having the same transfer function. The first filter circuit and the second filter circuit have the same circuit format. This configuration further improves the synchronization of voltage detection by the main voltage detection unit and the sub-voltage detection unit. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a battery monitoring device according to a first embodiment. [Figure 2] FIG. 1 is a diagram schematically illustrating a portion of the configuration related to voltage detection in a battery monitoring device according to a first embodiment. [Figure 3] 1 is a timing chart showing the operation of each part in the configuration related to voltage detection in the battery monitoring device according to the first embodiment; [Figure 4] FIG. 1 is a diagram illustrating a flow of operations related to voltage detection by the battery monitoring device according to the first embodiment. [Figure 5] FIG. 1 is a diagram showing an example of a specific configuration of a cell selection circuit according to a first embodiment; [Figure 6] FIG. 1 is a timing chart showing an example of clocks and selection signals used in the second A / D converter according to the first embodiment; [Figure 7]FIG. 10 is a diagram showing an example of a specific configuration of a cell selection circuit according to a second embodiment; [Figure 8] FIG. 10 is a timing chart showing an example of clocks and selection signals used in the second A / D converter according to the second embodiment; [Figure 9] FIG. 10 is a diagram showing an example of a specific configuration of a cell selection circuit according to a third embodiment; [Figure 10] FIG. 10 is a timing chart showing an example of clocks and selection signals used in the second A / D converter according to the third embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, a number of embodiments of the present invention will be described with reference to the drawings. Note that substantially the same components in the respective embodiments are designated by the same reference numerals, and the description thereof will be omitted. (First embodiment) The first embodiment will be described below with reference to FIGS.

[0015] <Overall structure> As shown in Fig. 1, the battery monitoring device 1 of this embodiment is a device that monitors the state of the battery pack 2 by detecting various conditions such as the voltage of the battery pack 2, and includes a battery monitoring IC 3, which is an integrated circuit that integrates circuits that perform various operations for battery monitoring, and multiple external elements provided outside the battery monitoring IC 3. Note that IC is an abbreviation for Integrated Circuit. The battery pack 2 is mounted on a vehicle such as an automobile, and is configured such that multiple, for example, 24 battery cells Cb are connected in series in multiple stages between a pair of DC power supply lines L1 and L2.

[0016] In this case, the battery cells Cb are, for example, secondary batteries such as lithium-ion batteries, fuel cells, etc. Note that Fig. 1 shows four of the 24 battery cells Cb, and numbers are added to the end of the reference symbols to distinguish between the four battery cells Cb. These numbers correspond to the arrangement of the battery cells Cb in the battery pack 2, with the battery cell Cb arranged on the lowest potential side being assigned the number 1, and the numbers assigned increasing toward the higher potential side are 2, 3, 4, ..., until the battery cell Cb arranged on the highest potential side is assigned the number 24.

[0017] 1 shows battery cell Cb1 arranged on the lowest potential side, battery cell Cb2 arranged on the second lowest potential side, battery cell Cb23 arranged on the second highest potential side, and battery cell Cb24 arranged on the highest potential side. The components provided in the battery monitoring device 1 corresponding to these four battery cells Cb1, Cb2, Cb23, and Cb24 may also be distinguished by adding the same numeral to the end of their reference numerals. However, when it is not necessary to distinguish between these components, the suffixes will be omitted and they will be referred to collectively.

[0018] <External element configuration> First, the configuration of external elements provided outside the battery monitoring IC 3 will be described. The high-potential terminal of battery cell Cb24 is connected to connection terminal S24 via resistor Rs, and is also connected to connection terminal V24 via resistor Rv. The low-potential terminal of battery cell Cb24 and the high-potential terminal of battery cell Cb23 are connected to connection terminal S23 via resistor Rs, and are also connected to connection terminal V23 via resistor Rv. A capacitor Cs is connected between connection terminal S24 and connection terminal S23. A capacitor Cv is connected between connection terminal V24 and connection terminal V23.

[0019] The low-potential terminal of battery cell Cb23 and the high-potential terminal of battery cell Cb22 (not shown) are connected to connection terminal S22 via resistor Rs and to connection terminal V22 via resistor Rv. A capacitor Cs is connected between connection terminal S23 and connection terminal S22. A capacitor Cv is connected between connection terminal V23 and connection terminal V22.

[0020] The low-potential terminal of battery cell Cb3 and the high-potential terminal of battery cell Cb2 (not shown) are connected to connection terminal S2 via resistor Rs and to connection terminal V2 via resistor Rv. The low-potential terminal of battery cell Cb2 and the high-potential terminal of battery cell Cb1 are connected to connection terminal S1 via resistor Rs and to connection terminal V1 via resistor Rv. A capacitor Cs is connected between connection terminal S2 and connection terminal S1. A capacitor Cv is connected between connection terminal V2 and connection terminal V1.

[0021] The low-potential terminal of battery cell Cb1 is connected to connection terminal S0 via resistor Rs and to connection terminal V0 via resistor Rv. A capacitor Cs is connected between connection terminal S1 and connection terminal S0. A capacitor Cv is connected between connection terminal V1 and connection terminal V0.

[0022] In this case, the resistor Rv and the capacitor Cv form a first filter circuit 4 that functions as a low-pass filter. In this specification, low-pass filter may be abbreviated as LPF. The first filter circuit 4 is a so-called L-type LPF. In the above configuration, the first filter circuit 4 is provided corresponding to each of the multiple battery cells Cb, and receives the voltage of the corresponding battery cell Cb as input.

[0023] In this case, the resistor Rs and the capacitor Cs form a second filter circuit 5 that functions as an LPF. The second filter circuit 5 is a so-called L-type LPF. In the above configuration, the second filter circuit 5 is provided corresponding to each of the multiple battery cells Cb, and receives the voltage of the corresponding battery cell Cb as input. Thus, in the above configuration, the first filter circuit 4 and the second filter circuit 5 have the same circuit format.

[0024] <Internal configuration of battery monitoring IC> Next, the internal configuration of the battery monitoring IC 3 will be described. The battery monitoring IC 3 includes a main voltage detection unit 6 provided corresponding to each of the plurality of battery cells Cb, and detecting the voltages of the plurality of battery cells Cb. In other words, the battery monitoring IC 3 includes 24 main voltage detection units 6, the same number as the number of battery cells Cb. Note that FIG. 1 shows four of the 24 main voltage detection units 6. In this case, the numbers added to the end of the four main voltage detection units 6 are shown in parentheses.

[0025] The battery monitoring IC 3 includes sub-voltage detection units 7 that correspond to two of the multiple battery cells Cb and detect the voltages of those two battery cells Cb in a time-division manner. In other words, the battery monitoring IC 3 includes 12 sub-voltage detection units 7, which is half the number of battery cells Cb. Note that FIG. 1 shows two of the 12 sub-voltage detection units 7, and to distinguish between these two sub-voltage detection units 7, the same numbers as those at the end of the reference numerals for the two corresponding battery cells Cb are indicated in parentheses. However, when it is not necessary to distinguish between the 12 sub-voltage detection units 7, the parentheses at the end are omitted and the units are referred to collectively.

[0026] The battery monitoring IC 3 includes a comparator 8 provided corresponding to each of the multiple battery cells Cb. In other words, it includes 24 comparators 8, the same number as the number of battery cells Cb. Note that FIG. 1 shows four of the 24 comparators 8. In this case, the numbers at the end of the four comparators 8 are shown in parentheses. The battery monitoring IC 3 includes a detection control unit 9. The detection control unit 9 includes a communication I / F for communicating with the outside world and registers for storing various data, and controls the overall operation of the battery monitoring IC 3. Note that I / F is an abbreviation for interface. The detection control unit 9 controls the operation of the main voltage detection unit 6 and the sub-voltage detection unit 7.

[0027] The main voltage detection unit 6 includes a first A / D converter 11 that receives an input voltage corresponding to the voltage of the corresponding battery cell Cb, and a first digital filter 12 that receives a digital signal output from the first A / D converter 11 and functions as an LPF. In this specification, the A / D converter is sometimes abbreviated as ADC. In FIG. 1, the digital filter is abbreviated as DF. In this case, the output voltage of the first filter circuit 4 is input to the first ADC 11 of the main voltage detection unit 6 as an input voltage.

[0028] That is, the first ADC 11 of the main voltage detection unit 6

[24] receives an input voltage corresponding to the voltage of the battery cell Cb24, specifically the output voltage of the first filter circuit 4 provided via the connection terminals V24 and V23. The first ADC 11 of the main voltage detection unit 6

[23] receives an input voltage corresponding to the voltage of the battery cell Cb23, specifically the output voltage of the first filter circuit 4 provided via the connection terminals V23 and V22.

[0029] The first ADC 11 of the main voltage detection unit 6[2] receives an input voltage corresponding to the voltage of the battery cell Cb2, specifically the output voltage of the first filter circuit 4 provided via the connection terminals V2 and V1. The first ADC 11 of the main voltage detection unit 6[1] receives an input voltage corresponding to the voltage of the battery cell Cb1, specifically the output voltage of the first filter circuit 4 provided via the connection terminals V1 and V0.

[0030] The sub-voltage detection unit 7 includes a cell selection circuit 13 that selects one of the two corresponding battery cells Cb as the detection target, a second A / D converter 14 that receives an input voltage corresponding to the voltage of the battery cell Cb selected by the cell selection circuit 13, and a second digital filter 15 that receives a digital signal output from the second A / D converter 14 and functions as an LPF. In this case, the output voltage of the second filter circuit 5 is input to the second A / D converter 14 of the sub-voltage detection unit 7 as an input voltage.

[0031] That is, the cell selection circuit 13 of the sub-voltage detection unit 7 [24, 23] selects either the voltage at the connection terminals S24, S23 or the voltage at the connection terminals S23, S22, and outputs it to the subsequent stage. The second ADC 14 of the sub-voltage detection unit 7 [24, 23] receives an input voltage corresponding to the voltage of the battery cell Cb24, specifically the output voltage of the second filter circuit 5 provided via the connection terminals S24, S23, or an input voltage corresponding to the voltage of the battery cell Cb23, specifically the output voltage of the second filter circuit 5 provided via the connection terminals S23, S22.

[0032] The cell selection circuit 13 of the sub-voltage detection unit 7[2,1] selects either the voltage at the connection terminals S2 and S1 or the voltage at the connection terminals S1 and S0 and outputs it to the subsequent stage. The second ADC 14 of the sub-voltage detection unit 7[2,1] receives an input voltage corresponding to the voltage of the battery cell Cb2, specifically the output voltage of the second filter circuit 5 provided via the connection terminals S2 and S1, or an input voltage corresponding to the voltage of the battery cell Cb1, specifically the output voltage of the second filter circuit 5 provided via the connection terminals S1 and S0.

[0033] The output signals of the first digital filter 12 and the second digital filter 15 are input to the detection control unit 9 and the comparator 8. That is, the output signal of the first digital filter 12 of the main voltage detection unit 6

[24] is input to the detection control unit 9 and also to one input terminal of the comparator 8

[24] . The output signal of the second digital filter 15 of the sub-voltage detection unit 7 [24, 23] is input to the detection control unit 9 and also to the other input terminal of the comparator 8

[24] . In addition, the output signal of the second digital filter 15 of the sub-voltage detection unit 7 [24, 23] is input to one input terminal of the comparator 8

[23] . The output signal of the first digital filter 12 of the main voltage detection unit 6

[23] is input to the other input terminal of the comparator 8

[23] .

[0034] The output signal of the first digital filter 12 of the main voltage detection unit 6[2] is input to the detection control unit 9 and also input to one input terminal of the comparator 8[2]. The output signal of the second digital filter 15 of the sub-voltage detection unit 7[2,1] is input to the detection control unit 9 and also input to the other input terminal of the comparator 8[2]. In addition, the output signal of the second digital filter 15 of the sub-voltage detection unit 7[2,1] is input to one input terminal of the comparator 8[1]. The output signal of the first digital filter 12 of the main voltage detection unit 6[1] is input to the other input terminal of the comparator 8[1].

[0035] In the above configuration, the first digital filter 12, the second digital filter 15, the comparator 8, and the detection control unit 9 are configured as a digital circuit 16. In addition, in the above configuration, the first ADC 11 and the second ADC 14 are ΔΣ A / D converters of the same order. Note that "order" here refers to the number of integrators cascade-connected within the ΔΣ A / D converter. In the above configuration, the first digital filter 12 and the second digital filter 15 are digital filters having the same transfer function, for example, two-stage SINC filters.

[0036] When detecting the voltage of a detection target battery cell, which is battery cell Cb selected as a detection target by the sub-voltage detection unit 7, the detection control unit 9 controls the operation of the main voltage detection unit 6 and the sub-voltage detection unit 7 so that the difference in the start timing of A / D conversion and the difference in the conversion period of A / D conversion between the second ADC 14 of the sub-voltage detection unit 7 and the first ADC 11 of the main voltage detection unit 6 that detects the voltage of the detection target battery cell are within a predetermined tolerance. The tolerance can be, for example, the time equivalent to one clock of the operating clock of the first ADC 11 and the second ADC 14.

[0037] In the above configuration, the main voltage detection unit 6 detects the battery voltage of each of the multiple battery cells Cb. Furthermore, in the above configuration, the sub-voltage detection unit 7 uses the cell selection circuit 13 to select the battery cell Cb to be subjected to voltage detection, thereby sequentially detecting the voltages of battery cells Cb1 to Cb24. Furthermore, in the above configuration, the battery cell CbN of the first ADC 11 of the main voltage detection unit 6 and the battery cell CbN of the second ADC 14 of the sub-voltage detection unit 7 are operated simultaneously, and the output results are compared using the comparator 8, thereby diagnosing faults in various paths and components related to voltage detection.

[0038] <Voltage detection operations> Next, the operation of voltage detection using the above configuration will be described with reference to FIGS. Here, it is assumed that the detection target battery cells are a specific battery cell CbN and a battery cell CbN+1 that is located one cell higher in potential than the specific battery cell CbN. Note that the battery cell CbN is one of the battery cells Cb1 to Cb23. In other words, N is any number between 1 and 23.

[0039] First, the configuration related to such voltage detection will be described with reference to Fig. 2. The main voltage detection unit 6[N], comparator 8[N], and filter 21[N] are configured to correspond to battery cell CbN. The main voltage detection unit 6[N+1], comparator 8[N+1], and filter 21[N+1] are configured to correspond to battery cell CbN+1. The sub-voltage detection unit 7[N+1,N] is configured to correspond to two battery cells CbN and CbN+1.

[0040] The main voltage detection unit 6 includes a first ADC 11, which is a ΔΣ ADC, and a first digital filter 12, which is a two-stage SINC filter. In FIG. 2 and other figures, the two-stage SINC filter is referred to as SINC2. Filter 21 is an IIR filter and is included in the detection control unit 9. The sub-voltage detection unit 7 includes a cell selection circuit 13, a second ADC 14, which is a ΔΣ ADC, and a second digital filter 15, which is a two-stage SINC filter.

[0041] The operation of each part in the above configuration is as shown in the timing chart of Figure 3. In this case, because the first digital filter 12 and the second digital filter 15 are two-stage SINC filters, the second data is used for detection; that is, two pieces of data are required. Note that in Figure 3, battery cell CbN is abbreviated as cell N, and battery cell CbN+1 is abbreviated as cell N+1. Also, in Figure 3, of the periods t1 to t8, periods t1 and the like are conversion periods Ta for A / D conversion, and periods t3 and t6 are input switching periods Tb by the cell selection circuit 13. Therefore, during periods t3 and t6, no operations directly related to voltage detection are performed.

[0042] During periods t1 and t2, the first ADC 11 of the main voltage detection unit 6[N] and the second ADC 14 of the sub-voltage detection unit 7[N+1,N] simultaneously perform A / D conversion to detect the voltage of battery cell CbN. Then, during period t2, the comparator 8[N] compares the two output results obtained by the A / D conversions described above. In this case, if the difference between the two output results, i.e., the absolute value of the difference between the values ​​of the two digital signals, exceeds a predetermined threshold, the output comparison is determined to be "mismatch." However, if the absolute value of the difference between the values ​​of the two digital signals is equal to or less than the predetermined threshold, the output comparison is determined to be "match." During period t2, the difference between the two output results is equal to or less than the threshold, so the output comparison is determined to be "match."

[0043] During periods t4 and t5, the first ADC 11 of the main voltage detection unit 6[N+1] and the second ADC 14 of the sub-voltage detection unit 7[N+1,N] simultaneously perform A / D conversion to detect the voltage of battery cell CbN+1. Then, during period t5, the comparator 8[N+1] compares the output results obtained by each A / D conversion. During period t5, the difference between the two output results is equal to or less than the threshold, so the output comparison is determined to be "match."

[0044] During periods t7 and t8, the first ADC 11 of the main voltage detection unit 6[N] and the second ADC 14 of the sub-voltage detection unit 7[N+1,N] simultaneously perform A / D conversion to detect the voltage of battery cell CbN. Then, during period t8, the comparator 8[N] compares the output results obtained by each of the A / D conversions described above. During period t8, the difference between the two output results exceeds the judgment value, so the output comparison is determined to be "mismatch." This causes the signal representing the abnormality judgment result to go high. Note that in this case, the signal representing the abnormality judgment result is a high-active binary signal that indicates an abnormality when it is high.

[0045] The above-described operational flow can be represented as a flowchart as shown in Figure 4. First, in step S101, the normal path, i.e., voltage detection by the main voltage detection unit 6, is performed. In step S102, the diagnostic path, i.e., voltage detection by the sub-voltage detection unit 7, is performed. In steps S101 and S102, voltage detection for the same battery cell Cb is performed at the same timing.

[0046] In step S103, the result of voltage detection of battery cell Cb is read. In step S104, it is determined whether the difference between the two output results is equal to or less than a judgment value based on the following equation (1). In this case, the result of voltage detection via the normal path is represented as "normal," the result of voltage detection via the diagnostic path is represented as "diagnostic," and the judgment value is represented as A. The unit of judgment value A is, for example, mV. |Normal-Diagnosis|≦AmV …(1)

[0047] Here, if it is determined that the difference between the two output results is equal to or less than the judgment value, the result in step S104 is "YES" and the process proceeds to step S105. In step S105, various paths, configurations, etc. related to voltage detection are diagnosed as normal. On the other hand, if it is determined that the difference between the two output results exceeds the judgment value, the result in step S104 is "NO" and the process proceeds to step S106. In step S106, various paths, configurations, etc. related to voltage detection are diagnosed as abnormal. After step S105 or S106 is executed, this series of processes ends.

[0048] <Specific configuration of the cell selection circuit> As a specific configuration of the cell selection circuit 13, for example, a configuration example such as that shown in Fig. 5 can be adopted. In this case, a specific configuration example of the cell selection circuit 13 will be described using the cell selection circuit 13 of the sub-voltage detection unit 7[2,1] as an example, but a similar configuration example can also be adopted for other cell selection circuits 13, such as the cell selection circuit 13 of the sub-voltage detection unit 7[24,23].

[0049] 5, the first-stage integrator 31 of the second ADC 14, which is a ΔΣ ADC, has a double-sampling configuration. Note that a typical configuration can be used as the configuration of a ΔΣ ADC whose first-stage integrator 31 has a double-sampling configuration, and therefore a detailed description thereof will be omitted here. However, in this case, the second ADC 14 has the same number of sampling circuits 32 as the number of corresponding battery cells Cb, each of which is composed of a pair of sampling capacitors CS, a sampling switch SS consisting of four switches, and four selection switches, i.e., two sampling circuits 32.

[0050] In one sampling circuit 32, one input node is connected to connection terminal S2, and the other input node is connected to connection terminal S1. In the other sampling circuit 32, one input node is connected to connection terminal S1, and the other input node is connected to connection terminal S0. A high-voltage switch is used for the sampling switch SS so that it can withstand the relatively high voltage superimposed on the battery cell Cb.

[0051] Of the sampling switches SS, the switch connected between one input node and one sampling capacitor CS and the switch connected between the other input node and the other sampling capacitor CS are switched on and off by a clock CKA. Of the sampling switches SS, the switch connected between one input node and the other sampling capacitor CS and the switch connected between the other input node and one sampling capacitor CS are switched on and off by a clock CKB.

[0052] In one sampling circuit 32, the on / off states of two selection switches connected between the sampling capacitor CS and the output node of the sampling circuit 32 are switched by a selection signal SEL1. In one sampling circuit 32, the on / off states of two switches connected between the sampling capacitor CS and the node to which the common voltage VCMI is applied are switched by a selection signal SEL1B.

[0053] In the other sampling circuit 32, the two selection switches connected between the sampling capacitor CS and the output node of the sampling circuit 32 are switched on and off by a selection signal SEL1B. In the other sampling circuit 32, the two switches connected between the sampling capacitor CS and the node to which the common voltage VCMI is applied are switched on and off by a selection signal SEL1. The four selection switches are used to select one of the two sampling circuits 32. The four selection switches can be low-voltage switches with a lower withstand voltage than the sampling switch SS.

[0054] The second ADC 14 includes D / A converters 33a and 33b. Each of the D / A converters 33a and 33b includes three switches and a capacitor CD. In the D / A converter 33a, the on / off state of a switch connected between the node to which the reference voltage VREFH is applied and the capacitor CD is switched by a clock CKB+. In the D / A converter 33a, the on / off state of a switch connected between the node to which the reference voltage VREFL is applied and the capacitor CD is switched by a clock CKB-.

[0055] In the D / A converter 33b, the on / off state of a switch connected between the node to which the reference voltage VREFL is applied and the capacitance CD is switched by the clock CKB+. In the D / A converter 33b, the on / off state of a switch connected between the node to which the reference voltage VREFH is applied and the capacitance CD is switched by the clock CKB-. In the D / A converters 33a and 33b, the on / off state of a switch connected between the node to which the common voltage VCMO is applied and the capacitance CD is switched by the clock CKA.

[0056] The second ADC 14 includes a first-stage integrator 31 that integrates the charge on the sampling capacitor CS. The integrator 31 includes four switches, a fully differential operational amplifier 34, and a pair of integration capacitors CF. Two switches connected between the input node of the integrator 31 and a node to which a common voltage VCMI is applied are switched on and off by a clock CKA. Two switches connected between the input node of the integrator 31 and the input terminal of the operational amplifier 34 are switched on and off by a clock CKB.

[0057] The second ADC 14 includes a second-stage integrator 35, a quantizer 36, a clock generator 37, and an FB clock generator 38. The output of the quantizer 36 is output as a digital signal representing the result of A / D conversion. The clock generator 37 generates and outputs clocks CKA and CKB. The FB clock generator 38 generates and outputs clocks CKB+ and CKB-.

[0058] The clocks and selection signals SEL1 and SEL1B used in the above configuration are as shown in the timing chart of Fig. 6. In this case, the reference voltages VREFH and VREFL are selected according to the output of the quantizer 36. Specifically, when the output of the quantizer 36 is at an L level, the clock CKB+ operates to select the reference voltage VREFH, and when the output of the quantizer 36 is at an H level, the clock CKB- operates to select the reference voltage VREFL.

[0059] According to the above configuration, the double sampling configuration makes it possible to ensure double the gain, thereby reducing the sampling capacitance CS by half. In the above configuration example, the cell selection circuit 13 selects the battery cell Cb to be detected by sampling the input voltage using one of the two sampling circuits 32 included in the second ADC 14.

[0060] According to the present embodiment described above, the following effects can be obtained. With the above configuration, the number of sub-voltage detection units 7 is reduced to half compared to a configuration in which a sub-voltage detection unit 7 is provided corresponding to each of all battery cells Cb, thereby reducing the circuit area. Furthermore, with the above configuration, when the main voltage detection unit 6 and the sub-voltage detection unit 7 detect the voltage of the same battery cell Cb, the difference in the start timing of A / D conversion and the difference in the conversion period of A / D conversion between the second A / D converter 14 of the sub-voltage detection unit 7 and the first A / D converter 11 of the main voltage detection unit 6 are kept within a predetermined allowable error, thereby improving the synchronization of voltage detection.

[0061] Therefore, according to this embodiment, it is possible to reduce the circuit area and improve the synchronization of voltage detection by the main voltage detection unit 6 and the sub-voltage detection unit 7. According to this embodiment, the above-mentioned synchronization is improved, which makes it possible to improve the accuracy of fault diagnosis, and as a result, the energy available in the battery cell Cb increases, thereby extending the distance the vehicle can travel.

[0062] In this embodiment, the first A / D converter 11 of the main voltage detection unit 6 and the second A / D converter 14 of the sub-voltage detection unit 7 are ΔΣ A / D converters of the same order, and the first digital filter 12 of the main voltage detection unit 6 and the second digital filter 15 of the sub-voltage detection unit 7 are digital filters having the same transfer function. Furthermore, in this embodiment, the first filter circuit 4 corresponding to the main voltage detection unit 6 and the second filter circuit 5 corresponding to the sub-voltage detection unit 7 have the same circuit format. With this configuration, the synchronization of voltage detection by the main voltage detection unit 6 and the sub-voltage detection unit 7 can be further improved.

[0063] In this embodiment, the second A / D converter 14 has two sampling circuits 32, each configured with a sampling capacitor CS and a sampling switch SS, the same number as the number of corresponding battery cells Cb, and also has a first-stage integrator 31 that integrates the charge of the sampling capacitor CS. Based on this configuration, the cell selection circuit 13 of this embodiment selects the battery cell Cb to be detected by sampling the input voltage using one of the two sampling circuits 32 provided in the second A / D converter 14.

[0064] With this configuration, the circuit area can be kept small compared to a configuration in which a separate multiplexer, etc. Also, in the configuration of this embodiment, the selection switches for the above selection are provided on the low-voltage side of the sampling capacitor CS, which makes it possible to use low-voltage switches, and therefore the switches can be made smaller, and the circuit area can be reduced, compared to a configuration in which these switches are provided on the high-voltage side.

[0065] (Second embodiment) A second embodiment in which the specific configuration of the cell selection circuit is modified from that of the first embodiment will be described below with reference to FIGS. The cell selection circuit 41 of this embodiment has a configuration as shown in Fig. 7. In this embodiment, the first-stage integrator 31 of the second ADC 14, which is a ΔΣ ADC, has a single-sampling configuration. Note that a general configuration can be adopted as the configuration of a ΔΣ ADC in which the first-stage integrator 31 has a single-sampling configuration, so a detailed description thereof will be omitted here. In this case, the second ADC 14 has two sampling circuits 42.

[0066] The sampling circuit 42 differs from the sampling circuit 32 in the connection configuration of the sampling switches SS. Of the sampling switches SS, two switches connected between each input node of the sampling circuit 42 and the sampling capacitor CS are switched on and off by a clock CKA. Of the sampling switches SS, two switches connected between the sampling capacitor CS and a node to which a common voltage VCMI is applied are switched on and off by a clock CKB.

[0067] The clocks and selection signals SEL1 and SEL1B used in the above configuration are as shown in the timing chart of FIG. 8. In a configuration in which a sampling capacitor CS is provided for every two battery cells Cb, as in the configuration of this embodiment or the configuration of the first embodiment, leakage cancellation can be performed by operating two systems of sampling circuits 32 and 42. The cell selection circuit 41 of this embodiment can also perform the same operation as the cell selection circuit 13 of the first embodiment. Therefore, the present embodiment can also achieve the same effects as the first embodiment.

[0068] (Third embodiment) Hereinafter, a third embodiment in which the specific configuration of the cell selection circuit is modified from that of the second embodiment will be described with reference to FIGS. The cell selection circuit 51 of this embodiment has a configuration as shown in Fig. 9. In this embodiment, the first-stage integrator 31 of the second ADC 14, which is a ΔΣ ADC, has a single sampling configuration. Note that a general configuration can be adopted as the configuration of a ΔΣ ADC in which the first-stage integrator 31 has a single sampling configuration, so detailed description thereof will be omitted here.

[0069] In this case, the second ADC 14 includes one sampling circuit 52. The sampling circuit 52 differs from the sampling circuit 42 of the second embodiment in that two of the sampling switches SS that are switched on and off by the clock CKA are omitted, and four selection switches are omitted.

[0070] The cell selection circuit 51 has a plurality of switches configured by MOS transistors, and selects the battery cell Cb to be detected by switching these switches on and off. One terminal of each of the switches in the cell selection circuit 51 is connected to connection terminals S24 to S0, and the other terminal of each is connected to a sampling capacitor CS. The switches in the cell selection circuit 51 are switched on and off by a clock CKA.

[0071] The clocks and selection signals SEL1 and SEL1B used in the above configuration are as shown in the timing chart of Fig. 10. The cell selection circuit 51 of this embodiment can also perform the same operations as the cell selection circuits 13 and 41 of the above embodiments. Therefore, this embodiment can also achieve the same effects as the above embodiments.

[0072] (Other embodiments) The present invention is not limited to the embodiments described above and illustrated in the drawings, but can be modified, combined, or expanded as desired without departing from the spirit of the invention. The numerical values ​​and the like shown in the above embodiments are examples and are not limited to these. The specific configuration of the cell selection circuit is not limited to those described in the above embodiments, and can be changed as appropriate as long as the configuration can achieve the same function.

[0073] In each of the above embodiments, a 2-in-1 configuration was used in which the sub-voltage detection units 7 were provided corresponding to two battery cells Cb, but this is not limiting and an N-in-1 configuration in which the sub-voltage detection units are provided corresponding to three or more battery cells Cb may also be used, where N is a positive integer greater than or equal to 3. In other words, it is sufficient that the sub-voltage detection units are provided corresponding to two or more battery cells Cb out of the multiple battery cells Cb and are configured to detect the voltages of those two or more battery cells Cb in a time-division manner.

[0074] Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and equivalent modifications. In addition, various combinations and forms, including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0075] In addition to the inventions set forth in the claims, the present disclosure includes the following inventions. [1] A battery monitoring device that monitors a battery pack (2) in which a plurality of battery cells (Cb) are connected in series, a main voltage detection unit (6) provided corresponding to each of the plurality of battery cells and detecting the voltages of the plurality of battery cells; a sub-voltage detection unit (7) provided corresponding to two or more of the plurality of battery cells, and configured to detect the voltages of the two or more battery cells in a time-division manner; a detection control unit (9) that controls the operation of the main voltage detection unit and the sub-voltage detection unit; Equipped with The main voltage detection unit a first A / D converter (11) that receives an input voltage corresponding to the voltage of the corresponding battery cell; a first digital filter (12) that receives the digital signal output from the first A / D converter and functions as a low-pass filter; Equipped with The sub-voltage detection unit a cell selection circuit (13, 41, 51) that selects one of the corresponding battery cells as a detection target; a second A / D converter (14) that receives an input voltage corresponding to the voltage of the battery cell selected by the cell selection circuit; a second digital filter (15) that receives the digital signal output from the second A / D converter and functions as a low-pass filter; Equipped with The detection control unit A battery monitoring device that, when detecting the voltage of a detection target battery cell, which is the battery cell selected as the detection target by the sub-voltage detection unit, controls the operation of the main voltage detection unit and the sub-voltage detection unit so that the difference in the start timing of A / D conversion and the difference in the conversion period of A / D conversion between the second A / D converter of the sub-voltage detection unit and the first A / D converter of the main voltage detection unit that detects the voltage of the detection target battery cell are within a predetermined allowable error. [2] moreover, a first filter circuit (4) provided corresponding to each of the plurality of battery cells, receiving the voltage of the corresponding battery cell and functioning as a low-pass filter; a second filter circuit (5) provided corresponding to each of the plurality of battery cells, receiving the voltage of the corresponding battery cell and functioning as a low-pass filter; Equipped with the output voltage of the first filter circuit is input to the first A / D converter of the main voltage detection unit as the input voltage; the second A / D converter of the sub-voltage detection unit receives an output voltage of the second filter circuit as the input voltage, the first A / D converter and the second A / D converter are ΔΣ A / D converters of the same order, the first digital filter and the second digital filter are digital filters having the same transfer function; The battery monitoring device according to [1], wherein the first filter circuit and the second filter circuit have the same circuit format. [3] The second A / D converter Sampling circuits (32, 42) each consisting of a sampling capacitor (CS) and a sampling switch (SS) are provided in the same number as the corresponding battery cells, a first-stage integrator that integrates the charge of the sampling capacitor; The battery monitoring device according to [1] or [2], wherein the cell selection circuit (13, 41) selects the battery cell to be detected by sampling the input voltage using any one of the plurality of sampling circuits provided in the second A / D converter. [4] The battery monitoring device according to [1] or [2], wherein the cell selection circuit (51) includes a plurality of switches configured by MOS transistors, and selects the battery cell to be detected by switching the plurality of switches on and off. [5] The battery monitoring device according to any one of [1] to [4], wherein the allowable error is a time equivalent to one clock of the operation clock of the first A / D converter and the second A / D converter. [Explanation of symbols]

[0076] 1...battery monitoring device, 2...battery pack, 4...first filter circuit, 5...second filter circuit, 6...main voltage detection unit, 7...sub-voltage detection unit, 9...detection control unit, 11...first A / D converter, 12...first digital filter, 13, 41, 51...cell selection circuit, 14...second A / D converter, 15...second digital filter, 32, 42...sampling circuit, CS...sampling capacitor, SS...sampling switch.

Claims

1. A battery monitoring device that monitors a battery pack (2) in which multiple battery cells (Cb) are connected in series, A main voltage detection unit (6) is provided corresponding to each of the plurality of battery cells and detects the voltage of the plurality of battery cells, A sub-voltage detection unit (7) is provided corresponding to two or more of the aforementioned plurality of battery cells, and detects the voltage of those two or more battery cells in a time-division manner. A detection control unit (9) that controls the operation of the main voltage detection unit and the sub-voltage detection unit, Equipped with, The main voltage detection unit is A first A / D converter (11) inputs an input voltage corresponding to the voltage of the battery cell, A first digital filter (12) that receives the digital signal output from the first A / D converter and functions as a low-pass filter, Equipped with, The aforementioned sub-voltage detection unit is A cell selection circuit (13, 41, 51) selects one of the corresponding battery cells as the target for detection, A second A / D converter (14) inputs an input voltage corresponding to the voltage of the battery cell selected by the cell selection circuit, A second digital filter (15) receives the digital signal output from the second A / D converter and functions as a low-pass filter, Equipped with, The detection control unit, When detecting the voltage of the battery cell to be detected, which is the battery cell selected as the target of detection by the sub-voltage detection unit, the operation of the main voltage detection unit and the sub-voltage detection unit is controlled such that the difference in the start timing of the A / D conversion and the difference in the conversion period of the A / D conversion between the second A / D converter of the sub-voltage detection unit and the first A / D converter of the main voltage detection unit that detects the voltage of the battery cell to be detected are within a predetermined tolerance. The tolerance is the time of one clock cycle of the operating clocks of the first A / D converter and the second A / D converter in the battery monitoring device.

2. moreover, A first filter circuit (4) is provided corresponding to each of the plurality of battery cells, and receives the voltage of the corresponding battery cell and functions as a low-pass filter, A second filter circuit (5) is provided corresponding to each of the plurality of battery cells, and receives the voltage of the corresponding battery cell and functions as a low-pass filter, Equipped with, The output voltage of the first filter circuit is input to the first A / D converter of the main voltage detection unit, The output voltage of the second filter circuit is input to the second A / D converter of the sub-voltage detection unit, The first A / D converter and the second A / D converter are ΔΣ A / D converters of the same order. The first digital filter and the second digital filter are digital filters having the same transfer function as each other. The battery monitoring device according to claim 1, wherein the first filter circuit and the second filter circuit have the same circuit configuration.

3. The second A / D converter is The system is provided with a sampling circuit (32, 42) consisting of a sampling capacitor (CS) and a sampling switch (SS) in the same number as the corresponding battery cells, The system includes a first-stage integrator for integrating the charge of the sampling capacitor, The battery monitoring device according to claim 1 or 2, wherein the cell selection circuit (13, 41) selects the battery cell to be detected by sampling the input voltage using one of the plurality of sampling circuits provided in the second A / D converter.

4. The battery monitoring device according to claim 1 or 2, wherein the cell selection circuit (51) comprises a plurality of switches made of MOS transistors, and the battery cell to be detected is selected by switching the on and off states of the plurality of switches.

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