Display device and method for controlling display device

Abstract

To provide a display device capable of preventing occurrence of blur of an image caused by low temperature while maintaining image quality, and to provide a control method of the display device.SOLUTION: The display device 100 includes a control circuit 4 and a temperature sensor 6. The control circuit 4 causes the gate drive circuit 2 to transmit the gate signal to the plurality of gate lines 11 in a non-lighting period that is a period other than the lighting period in one cycle of the vertical synchronization signal. When the detected temperature Ad is lower than the first temperature Ath1, the control circuit 4 sets the set number, which is the number of gate lines 11 to which the gate signal is supplied from the gate driving circuit 2 in one cycle of the horizontal synchronization signal, to a first number larger than one.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a display device and a method for controlling the display device. [Background technology]

[0002] The liquid crystal display device described in Patent Document 1 writes an image signal to a liquid crystal display panel within one cycle of a vertical synchronization signal and turns on the backlight intermittently. The liquid crystal display device also includes a temperature detection means for detecting the temperature inside the device. The liquid crystal display device is configured to double the frame frequency of the image signal supplied to the liquid crystal display panel when the detected temperature is 20 degrees or lower. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-163828 Summary of the Invention [Problem to be solved by the invention]

[0004] In a liquid crystal display device, an image signal is written to a liquid crystal display panel within one cycle of a vertical synchronization signal, and then the backlight is turned on within one cycle of the vertical synchronization signal. After the image signal is written to the liquid crystal display panel, it takes time for the liquid crystal layer of the liquid crystal display panel to respond to the image signal and become activated. The lower the temperature of the liquid crystal layer, the longer this time becomes (the longer this time takes). Therefore, if the temperature of the liquid crystal display panel (liquid crystal layer) is low, the backlight starts to turn on before the activation of the liquid crystal layer of the liquid crystal display panel is completed, resulting in a blurred image on the screen.

[0005] The liquid crystal display device described in Patent Document 1 attempts to suppress the above-mentioned image blur by doubling the frame frequency of the image signal supplied to the liquid crystal display panel when the detected temperature is below 20 degrees C. However, increasing (doubling) the frame frequency means shortening (halving) the cycle of the horizontal synchronization signal, which poses a problem of reduced image quality due to the shorter time it takes to write the image signal to each row of pixels.

[0006] Therefore, the present disclosure has been made to solve the above-mentioned problems, and aims to provide a display device and a control method for a display device that can prevent image blurring caused by low temperatures while maintaining image quality. [Means for solving the problem]

[0007] In order to solve the above problem, a display device according to a first aspect includes a display panel including a plurality of pixel electrodes arranged in a matrix and a liquid crystal layer that is driven in response to a voltage applied to the plurality of pixel electrodes; a backlight that irradiates light onto the display panel during a lighting period, which is a portion of one cycle of a vertical synchronization signal; a plurality of transistors connected to the plurality of pixel electrodes; a plurality of gate lines connected to the plurality of transistors; a gate drive circuit that supplies gate signals to the plurality of gate lines; a control circuit that controls the gate drive circuit and causes the gate drive circuit to transmit the gate signals to the plurality of gate lines during a lighting period, which is a period other than the lighting period within one cycle of the vertical synchronization signal; and a temperature sensor, wherein when the temperature detected by the temperature sensor is less than a first threshold temperature, the control circuit sets a set number, which is the number of gate lines to which gate signals are supplied from the gate drive circuit within one cycle of the horizontal synchronization signal, to a first number greater than 1.

[0008] A second aspect of the present invention provides a control method for a display device comprising: a display panel including a plurality of pixel electrodes arranged in a matrix and a liquid crystal layer that is driven in response to a voltage applied to the plurality of pixel electrodes; a backlight that irradiates light onto the display panel during a lighting period, which is a portion of one cycle of a vertical synchronization signal; a plurality of transistors connected to the plurality of pixel electrodes; a plurality of gate lines connected to the plurality of transistors; a gate drive circuit that supplies gate signals to the plurality of gate lines; a control circuit that controls the gate drive circuit and causes the gate drive circuit to transmit the gate signals to the plurality of gate lines during a lighting period, which is a period other than the lighting period within one cycle of the vertical synchronization signal; and a temperature sensor. The control method acquires a temperature detected by the temperature sensor, and if the detected temperature is less than a first threshold temperature, sets a set number, which is the number of gate lines to which gate signals are supplied from the gate drive circuit within one cycle of the horizontal synchronization signal, to a first number greater than 1. [Effects of the Invention]

[0009] According to the above configuration, it is possible to prevent blurring of the image caused by low temperature while maintaining the image quality. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram showing the configuration of a display device 100 according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view schematically showing the display panel 10. As shown in FIG. [Figure 3] FIG. 3 is a block diagram showing the internal configuration of the display panel 10. As shown in FIG. [Figure 4] FIG. 4 is a diagram showing a part of the configuration of the source driver circuit 3. As shown in FIG. [Figure 5] FIG. 5 is a timing chart for explaining normal display (vertical single-size display). [Figure 6] FIG. 6 is a diagram for explaining an example of normal display (single-size vertical display). [Figure 7]FIG. 7 is a diagram for explaining the relationship between the periods in normal display. [Figure 8] FIG. 8 is a timing chart for explaining the operation of the source drive circuit 3 according to the first embodiment for double-height display. [Figure 9] FIG. 9 is a diagram for explaining an example of double-height display of the source driving circuit 3. In FIG. [Figure 10] FIG. 10 is a diagram for explaining the relationship between the periods in double-height display. [Figure 11] FIG. 11 is a block diagram showing the configuration of a display device 200 according to the second embodiment. [Figure 12] FIG. 12 is a diagram showing an example of a table stored in the setting register 244 according to the second embodiment. [Figure 13] FIG. 13 is a diagram for explaining the operation of the display device 200 according to the second embodiment (when the detected temperature Ad is equal to or higher than the first threshold temperature Ath1). [Figure 14] FIG. 14 is a diagram for explaining the operation of the display device 200 according to the second embodiment (when the detected temperature Ad is equal to or higher than the second threshold temperature Ath2 and lower than the first threshold temperature Ath1). [Figure 15] FIG. 15 is a diagram for explaining the operation of the display device 200 according to the second embodiment (when the detected temperature Ad is equal to or higher than the third threshold temperature Ath3 and lower than the second threshold temperature Ath2). [Figure 16] FIG. 16 is a diagram for explaining the operation of the display device 200 according to the second embodiment (when the detected temperature Ad is lower than the third threshold temperature Ath3). [Figure 17] FIG. 17 is a block diagram showing the configuration of a display device 300 according to the third embodiment. [Figure 18] FIG. 18 is a diagram showing an example of a table stored in the setting register 344 according to the third embodiment. [Figure 19] FIG. 19 is a timing chart for explaining 1.5x vertical size display according to the third embodiment. [Figure 20] FIG. 20 is a diagram showing an example of a screen display in 1.5x vertical size display according to the third embodiment. [Figure 21] FIG. 21 is a block diagram showing the configuration of a display device 400 according to the fourth embodiment. [Figure 22] FIG. 22 is a diagram showing an example of a table stored in the setting register 444 according to the fourth embodiment. [Figure 23] FIG. 23 is a block diagram showing the configuration of a display device 500 according to the fifth embodiment. [Figure 24] FIG. 24 is a diagram for explaining control of the display device 500 according to the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The present disclosure is not limited to the following embodiments, and appropriate design modifications can be made within the scope of the configuration of the present disclosure. In the following description, the same reference numerals are used in common between different drawings for identical parts or parts having similar functions, and repeated description thereof will be omitted. The configurations described in the embodiments and modifications may be combined or modified as appropriate within the scope of the gist of the present disclosure. To facilitate understanding of the description, the drawings referred to below show simplified or schematic configurations, and some components may be omitted.

[0012] [First embodiment] (Overall configuration of the display device) FIG. 1 is a block diagram showing the configuration of a display device 100 according to the first embodiment. The display device 100 according to the first embodiment is configured as a head-mounted display worn on a person's head. As shown in FIG. 1, the display device 100 includes a display panel 10, a control circuit 4, a backlight 5, and a temperature sensor 6. The backlight 5 irradiates the display panel 10 with light, and a user visually recognizes the light transmitted through the display panel 10. The backlight 5 irradiates the display panel 10 with light during a lighting period Tb (see FIG. 7), which is a portion of one cycle Tf (see FIG. 7) of a vertical synchronization signal. The display panel 10 also includes a display section 1, which is an area where an image is displayed, a gate drive circuit 2, and a source drive circuit 3. While FIG. 1 shows an example in which the control circuit 4 is disposed outside the display panel 10 (on a substrate separate from the display panel 10), the control circuit 4 may also be disposed on the display panel 10. The control circuit 4 includes a timing controller 41, an image compression calculation unit 42, and a backlight control unit 43. The timing controller 41, the image compression calculation unit 42, and the backlight control unit 43 may be configured as a common integrated circuit, or may be configured as separate circuits for each function.

[0013] The timing controller 41 receives timing signals (horizontal synchronization signal, vertical synchronization signal, data enable signal, etc.) and video signals, and generates part of the source control signals (digital video signal, source start pulse signal, and source clock signal) and gate control signals (gate start pulse signal, gate clock signal, etc.) based on the received signals. The image compression calculation unit 42 generates part of the source control signals (switch control signals SWA and SWB) and controls the timing of the switch control signals SWA and SWB to switch between normal display (see FIG. 5) and double-height display (see FIG. 8). The timing controller 41 and the image compression calculation unit 42 supply the source control signals to the source drive circuit 3. The timing controller 41 also supplies a gate control signal to the gate drive circuit 2. The backlight control unit 43 turns on the backlight 5 by supplying a signal instructing the backlight 5 to turn on (or power for turning on the backlight 5) to the backlight 5 during a lighting period Tb (see FIG. 7), which is a part of one cycle Tf (see FIG. 7) of the vertical synchronization signal. The lighting period Tb is set, for example, at the end of one cycle Tf of the vertical synchronization signal.

[0014] 1 is disposed within the display device 100 and detects the temperature of the display panel 10 within the display device 100. The temperature sensor 6 may be in contact with the display panel 10, or may be disposed near the display panel 10 within the display device 100 (at a position where the temperature of the display panel 10 can be estimated). The temperature sensor 6 transmits the detected temperature to the control circuit 4.

[0015] Fig. 2 is a cross-sectional view that schematically shows the display panel 10. As shown in Fig. 2, the display panel 10 includes an active matrix substrate 10a, a counter substrate 10b that is disposed opposite the active matrix substrate 10a, and a liquid crystal layer 10c that is disposed between the active matrix substrate 10a and the counter substrate 10b.

[0016] Fig. 2 is a block diagram showing the internal configuration of the active matrix substrate 10a. Fig. 3 is a block diagram showing the internal configuration of the display panel 10. A plurality of gate lines 11 connected to a gate drive circuit 2 and a plurality of source lines 12 connected to a source drive circuit 3 are arranged on the active matrix substrate 10a. The plurality of gate lines 11 and the plurality of source lines 12 are arranged to intersect with each other, and pixels are arranged in each region defined by the plurality of gate lines 11 and the plurality of source lines 12. The plurality of pixels are arranged in a matrix on the active matrix substrate 10a.

[0017] Each pixel is provided with a transistor 13 and a pixel electrode 14. The gate electrode of the transistor 13 is connected to a gate line 11. The source electrode of the transistor 13 is connected to a source line 12. The drain electrode of the transistor 13 is connected to the pixel electrode 14.

[0018] When the transistor 13 is turned on by a drive signal (gate signal) supplied via the gate line 11, the source signal supplied via the source line 12 is written to (charged into) the pixel electrode 14. As a result, an electric field is formed between the pixel electrode 14 and a common electrode 15 disposed opposite the pixel electrode 14. After the electric field is formed (after time Ta1 in FIG. 7 has elapsed), the liquid crystal layer 10c is driven by the electric field generated between the pixel electrode 14 and the common electrode 15, and transmits light from the backlight 5, causing an image to be displayed on the display unit 1.

[0019] (Configuration of source driver circuit 3) FIG. 4 is a diagram showing a portion of the configuration of the source driving circuit 3. As shown in FIG. 4, the source driving circuit 3 includes an output unit 31 that outputs a source signal and a signal distribution unit 32. The source lines 12 include a source line 12a and a source line 12b. For example, as shown in FIG. 4, in the display device 100, two source lines 12a and two source lines 12b are alternately arranged. The multiple source lines 12a constitute a first source line group. The multiple source lines 12b constitute a second source line group. The output unit 31 outputs source signals having different voltage values ​​(gradations) for each cycle T1 (see FIG. 5) of the horizontal synchronization signal based on a digital video signal, a source start pulse signal, and a source clock signal. The output unit 31 includes multiple output terminals 31a (half the number of source lines 12). The multiple output terminals 31a output source signals having different gradations.

[0020] The signal distribution unit 32 is a demultiplexer that distributes the source signals output from the output unit 31 to a first group of source lines and a second group of source lines. Specifically, the signal distribution unit 32 includes a switch 32a arranged between the source line 12a and the output terminal 31a, and a switch 32b arranged between the source line 12b and the output terminal 31a. When a switch control signal SWA is input, the switch 32a is turned on and supplies the source signal from the output terminal 31a to the source line 12a. When a switch control signal SWB is input, the switch 32b is turned on and supplies the source signal from the output terminal 31a to the source line 12b. One output terminal 31a is connected to one source line 12a via the switch 32a and one source line 12b via the switch 32b.

[0021] 4, a pixel (sub-pixel) having a red color filter disposed therein is designated as "R," a pixel (sub-pixel) having a green color filter disposed therein is designated as "G," and a pixel (sub-pixel) having a blue color filter disposed therein is designated as "B." For example, the source line 12a at the left end of the paper in FIG. 3 is connected to the source electrodes of the transistors 13 in the multiple "R" pixels (referred to as "R1") arranged in the column at the left end of the paper. The red, green, and blue color filters are arranged on the counter substrate 10b.

[0022] (Operation of the display device 100 according to the first embodiment) Here, in the first embodiment, the timing controller 41 and the image compression calculation unit 42 transmit a gate control signal to the gate drive circuit 2 and a source control signal to the source drive circuit 3 to charge the pixel electrode 14 during a writing period (period Tw1 in the case of normal display in FIG. 7, period Tw2 in the case of double-width vertical display in FIG. 10) within the off period Tc, which is a period other than the on period Tb within one cycle of the vertical synchronization signal.

[0023] In the first embodiment, the timing controller 41 is configured to switch between normal display (see FIGS. 5 to 7) and double-height display (see FIGS. 8 to 10) based on the temperature of the display panel 10 detected by the temperature sensor 6 (hereinafter referred to as the "detected temperature Ad"). Specifically, the timing controller 41 sets a set number, which is the number of gate signals supplied from the gate drive circuit 2 and source signals written to the pixel electrodes 14 within one cycle (T1) of the horizontal synchronization signal, based on the detected temperature Ad. In other words, the "set number" is the number of gate lines 11 to which gate signals are supplied within the period T1. "Normal display" refers to the display operation of the display unit 1 when the set number is one line. "Double-height display" refers to the display operation of the display unit 1 when the set number is two rows.

[0024] When the detected temperature Ad is equal to or higher than the first threshold temperature Ath1, the timing controller 41 sets the set number to one line during the writing period Tw1, which is at least a part of the off period Tc (the display unit 1 displays an image in normal display). When the detected temperature Ad is lower than the first threshold temperature Ath1, the timing controller 41 sets the set number to two lines during the writing period Tw2, which is at least a part of the off period Tc (the display unit 1 displays an image in double-height display). The first threshold temperature Ath1 can be set to, for example, 10°C. Note that the first threshold temperature Ath1 may be set to a value within a range of 0°C to 30°C depending on the characteristics of the display device 100 or the liquid crystal layer 10c, but is not limited to these numerical examples.

[0025] <Normal display> FIG. 5 is a timing diagram illustrating normal display (vertical single-size display). FIG. 6 is a diagram illustrating an example of normal display (vertical single-size display). FIG. 7 is a diagram illustrating the relationship between each period in normal display. As shown in FIG. 5, the voltages of the switch control signals SWA and SWB each become high level once within one cycle (period T1) of the horizontal synchronization signal. As a result, the switches 32a and 32b of the source drive circuit 3 are turned on once within one cycle (period T1) of the horizontal synchronization signal. Note that "A" in the diagram indicates a period during which the switch 32a is on, and "B" in the diagram indicates a period during which the switch 32b is on.

[0026] As a result of the switches 32a and 32b operating as described above, in normal display, the source signal V output within one cycle of the horizontal synchronization signal charges a plurality of pixel electrodes 14 (each pixel electrode) via a plurality of transistors 13 (each pixel electrode) connected to one gate line 11. For example, as shown in FIG. 5, in the case of a source signal V having a gradation in which light and dark alternate every period T1, as shown in FIG. 6, the pixels connected to odd-numbered gate lines 11 ("GL1", "GL3", ...) become "bright" (transmitting light from the backlight 5), and the pixels connected to even-numbered gate lines 11 ("GL2", "GL4", ...) become "dark" (blocking light from the backlight 5).

[0027] As shown in FIG. 7, one cycle (one frame period) Tf of the vertical synchronization signal is the period from time t0 to time t4. One frame period Tf is composed of an on period Tb during which the backlight 5 is on and an off period Tc during which the backlight 5 is off. The on period Tb is the period from time t3, which is after time t0, to time t4, which is the final time of one frame period Tf. The off period Tc is the period from time t0 to time t3. Here, "GL1" refers to the first gate line 11, and "GLn" refers to the gate line 11 in the last row. During a write period Tw1 from time t0 to time t2, the gate lines 11 from GL1 to GLn are scanned sequentially, and a source signal is written (charged) to the pixel electrodes 14.

[0028] Here, after writing to the pixel electrodes 14, the liquid crystal layer 10c is driven after the lapse of the period Ta1 due to the properties of the liquid crystal layer 10c. Therefore, the driving of the liquid crystal layer 10c is performed from time t1, which is the period Ta1 after time t0, to a time slightly before time t3. As a result, the driving of the liquid crystal layer 10c is completed by time t3 when the backlight 5 starts to light up, and in this case, no blurring occurs in the image.

[0029] <Double vertical display> Fig. 8 is a timing chart illustrating the operation of the source drive circuit 3 according to the first embodiment for double-height display. Fig. 9 is a diagram illustrating an example of double-height display by the source drive circuit 3. Fig. 10 is a diagram illustrating the relationship between each period in double-height display.

[0030] 8, the switch control signals SWA and SWB each go to a high level voltage once within one cycle (period T1) of the horizontal synchronization signal, as in normal display, which causes the switches 32a and 32b of the source drive circuit 3 to turn on once within one cycle (period T1) of the horizontal synchronization signal.

[0031] As a result of the switches 32a and 32b operating as described above, in double-height display, the source signal output within one cycle of the horizontal synchronization signal charges a plurality of pixel electrodes 14 (for two rows) via a plurality of transistors 13 (for two rows) connected to two gate lines 11. For example, in the case of a source signal V having a gradation that alternates between light and dark every period T1 as shown in FIG. 8, the pixels connected to gate lines 11 "GL1," "GL2," "GL5," "GL6," ... become "light," and the pixels connected to gate lines 11 "GL3," "GL4," "GL7," "GL8," ... become "dark," as shown in FIG.

[0032] As shown in FIG. 10, in double-height display, during a writing period Tw2 from time t0 to time t12, the gate lines 11 of GL1 to GLn are scanned sequentially, and a source signal is written (charged) to the pixel electrodes 14.

[0033] After the pixel electrodes 14 are written, the liquid crystal layer 10c is driven after a period Ta2 has elapsed. The lower the temperature, the longer the period (response period) from when the pixel electrodes 14 are written until the liquid crystal layer 10c is driven. Therefore, the period Ta2 when the detected temperature Ad is less than the first threshold temperature Ath1 is longer than the period Ta1 when the detected temperature Ad is equal to or greater than the first threshold temperature Ath1. The liquid crystal layer 10c is driven from time t11, which is the period Ta2 after time t0, until a time slightly before time t3. As a result, the driving of the liquid crystal layer 10c is completed by time t3 when the backlight 5 starts to light up, and no blurring occurs in the image even when the detected temperature Ad is less than the first threshold temperature Ath1 (even when the temperature of the display panel 10 is low).

[0034] [Second embodiment] Next, the configuration of a display device 200 according to a second embodiment will be described with reference to Figures 11 to 16. In the second embodiment, the display device 200 is configured to refer to a setting register 244 based on a detected temperature Ad, and set the number output from the setting register 244 to a set number. Note that the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and description thereof will be omitted.

[0035] FIG. 11 is a block diagram showing the configuration of the display device 200 according to the second embodiment. FIG. 12 is a diagram showing an example of a table stored in the setting register 244 according to the second embodiment. FIG. 13 is a diagram for explaining the operation of the display device 200 according to the second embodiment (when the detected temperature Ad is equal to or greater than the first threshold temperature Ath1). FIG. 14 is a diagram for explaining the operation of the display device 200 according to the second embodiment (when the detected temperature Ad is equal to or greater than the second threshold temperature Ath2 and less than the first threshold temperature Ath1). FIG. 15 is a diagram for explaining the operation of the display device 200 according to the second embodiment (when the detected temperature Ad is equal to or greater than the third threshold temperature Ath3 and less than the second threshold temperature Ath2). FIG. 16 is a diagram for explaining the operation of the display device 200 according to the second embodiment (when the detected temperature Ad is less than the third threshold temperature Ath3). The first threshold temperature Ath1, the second threshold temperature Ath2, and the third threshold temperature Ath3 can be set to, for example, 30°C, 15°C, and 0°C. Depending on the characteristics of the display device 200 or the liquid crystal layer 10c, the first threshold temperature Ath1, the second threshold temperature Ath2, and the third threshold temperature Ath3 may be set to values ​​different from those mentioned above, within the range of 0°C to 30°C, but are not limited to these numerical examples.

[0036] As shown in FIG. 11, the display device 200 according to the second embodiment includes a control circuit 204. The control circuit 204 includes a timing controller 241, an image compression calculation unit 242, and a setting register 244 (a storage circuit). As shown in FIG. 12, the setting register 244 stores information (double-height display area) indicating whether each of the multiple gate lines belongs to the first gate line group, the second gate line group, or the third gate line group, in association with the detected temperature Ad. The "first gate line group" and the "second gate line group" are groups of gate lines 11 whose set number is changed to 2 when the detected temperature Ad is lower than a first threshold temperature Ath1. The "first gate line group" is a group of gate lines 11 from the first row ("GL1") to any other row. The "second gate line group" is a group of gate lines 11 from the last row ("GLn") to any other row. In the second embodiment, the "third gate line group" is a group of gate lines 11 whose set number is 1 even when the detected temperature Ad is lower than the first threshold temperature Ath1. The "third gate line group" is disposed between the "first gate line group" and the "second gate line group" and is disposed in the center of the screen. The setting register 244 is configured so that the table stored therein can be rewritten by a setting signal supplied from a host controller (not shown) or an external device that supplies a video signal to the display device 200. That is, the table (correspondence between the "detected temperature Ad" and the "double-height display area") stored in the setting register 244 shown in FIG. 12 is configured to be changeable.

[0037] 12, the second threshold temperature Ath2 is a temperature lower than the first threshold temperature Ath1, and the third threshold temperature Ath3 is a temperature lower than the second threshold temperature Ath2. As shown in Fig. 12, the setting register 244 stores a table in which the number of first gate line groups and the number of second gate line groups corresponding to the detection temperature Ad increases as the detection temperature Ad decreases.

[0038] <When Ath1≦Ad> When the detected temperature Ad is equal to or higher than the first threshold temperature Ath1, the timing controller 241 refers to the setting register 244 and sets the gate line 11 of the first gate line group to be off and the second gate line group to be off. As a result, as shown in FIG. 13, the timing controller 241 performs normal display in which a gate signal is transmitted to each gate line 11 one by one per cycle of the horizontal synchronization signal.

[0039] 〈When Ath2 ≤ Ad < Ath1〉 When the detected temperature Ad is greater than or equal to the second threshold temperature Ath2 and less than the first threshold temperature Ath1, the timing controller 241 refers to the setting register 244 and sets the gate line 11 of the first gate line group as 200 gate lines 11 from "GL1" to "GL200", and sets the second gate line group as 200 gate lines 11 from "GLn-199" to "GLn". As a result, as shown in FIG. 14, during the period Tw3a (the period from time point t20 to time point t21) when the timing controller 241 supplies a gate signal to the 200 gate lines 11 from "GL1" to "GL200", the timing controller 241 transmits a gate signal to two gate lines 11 per cycle of the horizontal synchronization signal (performs control according to the setting number 2) and performs vertical double angle display. Also, during the period Tw3b (the period from time point t21 to time point t22) when the timing controller 241 supplies a gate signal to the gate lines 11 from "GL201" to "GLn-199", the timing controller 241 transmits a gate signal to one gate line 11 per cycle of the horizontal synchronization signal (performs control according to the setting number 1) and performs normal display. Further, during the period Tw3c (the period from time point t22 to time point t23) when the timing controller 241 supplies a gate signal to the 200 gate lines 11 from "GLn-199" to "GLn", the timing controller 241 transmits a gate signal to two gate lines 11 per cycle of the horizontal synchronization signal (performs control according to the setting number 2) and performs vertical double angle display. As a result, the liquid crystal layer 10c is driven during the period Tr3 from time point t24 to a time point slightly before time point t3. As a result, even when the detected temperature Ad is less than the first threshold temperature Ath1 (even when the temperature of the display panel 10 is low), no blurring occurs in the image while normal display is performed for the central portion of the screen (the region where the third gate line group is arranged).

[0040] <When Ath3 ≤ Ad < Ath2> When the detected temperature Ad is greater than or equal to the third threshold temperature Ath3 and less than the second threshold temperature Ath2, the timing controller 241 refers to the setting register 244 and sets the gate line 11 of the first gate line group as 500 gate lines 11 from "GL1" to "GL500", and sets the second gate line group as 500 gate lines 11 from "GLn - 499" to "GLn". As a result, as shown in FIG. 15, during the period Tw4a (the period from time point t30 to time point t31) when the timing controller 241 supplies the gate signal to the 500 gate lines 11 from "GL1" to "GL500", the timing controller 241 transmits the gate signal to two gate lines 11 per cycle of the horizontal synchronization signal (performs control according to the setting number 2) and performs vertical double angle display. Also, during the period Tw4b (the period from time point t31 to time point t32) when the timing controller 241 supplies the gate signal to the gate lines 11 from "GL501" to "GLn - 499", the timing controller 241 transmits the gate signal to one gate line 11 per cycle of the horizontal synchronization signal (performs control according to the setting number 1) and performs normal display. Further, during the period Tw4c (the period from time point t32 to time point t33) when the timing controller 241 supplies the gate signal to the 500 gate lines 11 from "GLn - 499" to "GLn", the timing controller 241 transmits the gate signal to two gate lines 11 per cycle of the horizontal synchronization signal (performs control according to the setting number 2) and performs vertical double angle display. As a result, the liquid crystal layer 10c is driven during the period Tr4 from time point t34 to a time point slightly before time point t3. As a result, for the central portion of the screen (the region where the third gate line group is arranged), even when the detected temperature Ad is less than the second threshold temperature Ath2 (even when the temperature of the display panel 10 is low), no blurring occurs in the image while performing normal display. / / 这里的翻译严格按照要求,尽量保持了原文的结构和专业术语,但可能在一些表述上会显得比较生硬,不过符合专利文本翻译的准确性要求。对于专利文本翻译,准确性是首要的,在符合语法和专业领域习惯的前提下,尽量不改变原文的句式结构,以确保准确传达原文的技术信息。

[0041] 〈When Ad < Ath3〉 When the detected temperature Ad is lower than the third threshold temperature Ath3, the timing controller 241 refers to the setting register 244 and sets the gate lines 11 of the third gate line group to none. As a result, as shown in FIG. 15, the timing controller 241 performs double-height display (see FIG. 7) in which gate signals are sent to two gate lines 11 per cycle of the horizontal synchronization signal to all gate lines 11. As a result, no blurring occurs in the image even when the detected temperature Ad is lower than the third threshold temperature Ath3.

[0042] [Third embodiment] Next, the configuration of a display device 300 according to a third embodiment will be described with reference to Fig. 17 to Fig. 20. In the third embodiment, the display device 300 is configured so that the set number can be set to a rational number other than an integer. Note that the same components as those in the first or second embodiment are denoted by the same reference numerals as those in the first or second embodiment, and description thereof will be omitted.

[0043] Fig. 17 is a block diagram showing the configuration of a display device 300 according to the third embodiment. Fig. 18 is a diagram showing an example of a table stored in a setting register 344 according to the third embodiment. Fig. 19 is a timing chart for explaining 1.5x vertical size display according to the third embodiment. Fig. 20 is a diagram showing an example of a screen display for 1.5x vertical size display according to the third embodiment.

[0044] As shown in FIG. 17, the display device 300 according to the third embodiment includes a control circuit 304. The control circuit 304 includes a timing controller 341, an image compression calculation unit 342, and a setting register 344 (storage circuit). As shown in FIG. 18, the setting register 344 stores a number k (k is a positive rational number) associated with the detected temperature Ad. When the detected temperature Ad is equal to or greater than a first threshold temperature Ath1, the timing controller 341 references the setting register 344 and sets the output number 1 as the set number. That is, when the detected temperature Ad is equal to or greater than the first threshold temperature Ath1, the timing controller 341 performs normal display. When the detected temperature Ad is equal to or greater than a second threshold temperature Ath2 and less than the first threshold temperature Ath1, the timing controller 341 performs 1.5x vertical size display (see FIGS. 19 and 20). The timing controller 341 performs double-height display when the detected temperature Ad is equal to or greater than the third threshold temperature Ath3 and less than the second threshold temperature Ath2. The timing controller 341 performs triple-height display when the detected temperature Ad is less than the third threshold temperature Ath3. "Triple-height display" is a display method in which gate signals are supplied to three gate lines 11 per cycle of the horizontal synchronization signal. This prevents blurring of the image even when the detected temperature Ad is less than the third threshold temperature Ath3.

[0045] <1.5x vertical display> Here, "1.5x vertical size display" refers to a method of supplying gate signals to three gate lines 11 and source signals to multiple source lines 12 within two cycles of the horizontal synchronization signal (two periods T1 in FIG. 19) to display an image on the display unit 1. In other words, 1.5x vertical size display is a method in which 1.5 gate lines 11 (1.5 times the number of normal display lines) are scanned at a time.

[0046] 19, the switch control signals SWA and SWB each go to a high level voltage once within one cycle (period T1) of the horizontal synchronization signal, as in normal display, which causes the switches 32a and 32b of the source drive circuit 3 to turn on once within one cycle (period T1) of the horizontal synchronization signal.

[0047] As a result of the switches 32a and 32b operating as described above, in a 1.5x vertical size display, the source signal output within two cycles of the horizontal synchronization signal charges a plurality of pixel electrodes 14 (for three rows) via a plurality of transistors 13 (for three rows) connected to three gate lines 11. For example, as shown in FIG. 19, in the case of a source signal V having a gradation that alternates between light and dark every period T1, half of the pixels connected to gate lines 11 "GL1" to "GL3" become "light" and the remaining half become "dark," as shown in FIG. 20. Also, half of the pixels connected to gate lines 11 "GL4" to "GL6" become "light" and the remaining half become "dark."

[0048] As shown in FIG. 19 , the period during which a gate signal is supplied to the gate line 11 of “GL1” is referred to as a first period P1, the period during which a gate signal is supplied to the gate line 11 of “GL2” is referred to as a second period P2, the period during which a gate signal is supplied to the gate line 11 of “GL3” is referred to as a third period P3, and the period during which a gate signal is supplied to the gate line 11 of “GL4” is referred to as a fourth period P4. In a 1.5x vertical display, the second period P2 starts at time t42, which is later than the start time t41 of the first period P1. The third period P3 starts at time t43, which is later than the start time t42 of the second period P2. The fourth period P4 starts at time t44, which is later than the start time t43 of the third period P3.

[0049] Furthermore, part of the first period P1 overlaps with part of the second period P2. Part of the second period P2 overlaps with part of the third period P3. However, the third period P3 does not overlap with the fourth period P4. In other words, the gate drive circuit 2 supplies gate signals to the gate lines 11 "GL1" to "GL3" so that part of the first period P1 overlaps with part of the second period P2, and part of the second period P2 overlaps with part of the third period P3, during two cycles of the horizontal synchronization signal.

[0050] 19, during a period R1 when the first period P1 and the second period P2 overlap, a switch control signal SWB is supplied to the switch 32b, and the switch 32b is turned on during the period R1. As a result, the source signal of the first period P1 is supplied to the transistors 13 connected to the gate line 11 of "GL2" and connected to the second source line group (the source line group to which the source signal is supplied when the switch 32b is on). Also, during a period R2 when the second period P2 and the third period P3 overlap, a switch control signal SWA is supplied to the switch 32a, and the switch 32a is turned on during the period R2. As a result, the source signal of the second period P2 is supplied to the transistors 13 connected to the gate line 11 of "GL2" and connected to the first source line group (the source line group to which the source signal is supplied when the switch 32a is on). As a result, as shown in FIG. 20, half of the pixels connected to the gate line 11 of "GL2" become "bright" and the other half become "dark."

[0051] As described above, while periods R1 and R2 are each shorter than one cycle of the horizontal synchronization signal, one of the switches 32a and 32b is turned on during periods R1 and R2. This allows the source signal V to be supplied to either the first or second source line group during periods R1 and R2, enabling the display device 300 to display an image. As a result, gate signals can be supplied to 1.5 gate lines 11 (not an integer) per cycle of the horizontal synchronization signal (enabling 1.5x vertical display). In this way, when the detected temperature Ad is below the first threshold temperature Ath1 but is relatively high (e.g., equal to or greater than the second threshold temperature Ath2), it is possible to prevent the setting number from being increased more than necessary. As a result, image quality can be improved even when the detected temperature Ad is below the first threshold temperature Ath1.

[0052] [Fourth embodiment] Next, the configuration of a display device 400 according to a fourth embodiment will be described with reference to Figures 21 and 22. In the fourth embodiment, the control method according to the second embodiment and the control method according to the third embodiment are combined. Note that the same components as those in any of the first to third embodiments are denoted by the same reference numerals as those in any of the first to third embodiments, and description thereof will be omitted.

[0053] Fig. 21 is a block diagram showing the configuration of a display device 400 according to the fourth embodiment. Fig. 22 is a diagram showing an example of a table stored in a setting register 444 according to the fourth embodiment. As shown in Fig. 21, the display device 400 according to the fourth embodiment includes a control circuit 404. The control circuit 404 includes a timing controller 441, an image compression calculation unit 442, and a setting register 444.

[0054] 22, the setting register 444 stores a table in which the number k and the double-height display area are associated with the detected temperature Ad. The threshold temperature Ath11 is a temperature lower than the first threshold temperature Ath1. Of the threshold temperatures Ath11 to Ath19, the threshold temperature Ath11 is the highest temperature, and of these, the threshold temperature Ath19 is the lowest temperature. The threshold temperatures Ath11 to Ath19 are in this order of decreasing temperatures.

[0055] As shown in FIG. 22, in the table stored in the setting register 444, when the detected temperature Ad is equal to or greater than the threshold temperature Ath13 and less than the first threshold temperature Ath1, the set numbers of the first gate line group and the second gate line group are set to 1.5 (=3 / 2), and the set number of the third gate line group is set to 1. The detected temperature Ad is associated with the double-height display area such that the lower the detected temperature Ad, the greater the number of gate lines 11 in the first gate line group and the second gate line group. Furthermore, in this table, when the detected temperature Ad is equal to or greater than the threshold temperature Ath16 and less than the threshold temperature Ath15, the set numbers of the first gate line group and the second gate line group are set to 2, and the set number of the third gate line group is set to 1.5. The detected temperature Ad is associated with the double-height display area such that the lower the detected temperature Ad, the greater the number of gate lines 11 in the first gate line group and the second gate line group. Furthermore, in this table, when the detected temperature Ad is lower than the threshold temperature Ath16, the set number of the first gate line group and the second gate line group is set to 3, and the set number of the third gate line group is set to 2. The detected temperature Ad and the double-height display area are associated so that the lower the detected temperature Ad, the greater the number of gate lines 11 in the first gate line group and the second gate line group. As a result, the lower the detected temperature Ad, the shorter the write period, so that even when the detected temperature Ad is low, the image does not become blurred.

[0056] [Fifth embodiment] Next, the configuration of a display device 500 according to a fifth embodiment will be described with reference to Fig. 23 and Fig. 24. In the fifth embodiment, the display device 500 determines a third gate line group in accordance with a detection result from the line-of-sight sensor 507. Note that the same components as those in any of the first to fourth embodiments are denoted by the same reference numerals as those in any of the first to fourth embodiments, and description thereof will be omitted.

[0057] FIG. 23 is a block diagram showing the configuration of a display device 500 according to a fifth embodiment. FIG. 24 is a diagram for explaining control of the display device 500 according to the fifth embodiment. As shown in FIG. 23, the display device 500 according to the fifth embodiment includes a control circuit 504 and an eye-gaze sensor 507. The control circuit 204 includes a timing controller 541 and an image compression calculation unit 542. The eye-gaze sensor 507 includes a camera that captures visible light and detects a reference point (e.g., the inner corner of the eye) and a moving point (e.g., the iris) of the user's eye using the camera. The eye-gaze sensor 507 transmits information indicating which position on the display panel 10 of the display device 500 the user is viewing, based on the positional relationship between the reference point and the moving point, to the control circuit 504.

[0058] The control circuit 504 sets the center GLm (m is a natural number) of the third gate line group based on the detection result from the line-of-sight sensor 507. Then, the timing controller 541 performs normal display when the detected temperature Ad is equal to or higher than the first threshold temperature Ath1. Furthermore, when the detected temperature Ad is equal to or higher than the second threshold temperature Ath2 and lower than the first threshold temperature Ath1, the timing controller 541 sets the gate line group from the gate line 11 at "GLm-500" to the gate line 11 at "GLm+499" as the third gate line group, including the gate line 11 at the center GLm of the third gate line group. That is, the timing controller 541 controls the gate line group from the gate line 11 at "GLm-500" to the gate line 11 at "GLm+499" using normal display (setting number 1), and controls the gate lines 11 other than the above using double-height display (setting number 2). Furthermore, when the detected temperature Ad is equal to or higher than the third threshold temperature Ath3 and lower than the second threshold temperature Ath2, the timing controller 541 sets the gate line group from the gate line 11 at "GLm-200" to the gate line 11 at "GLm+199," including the gate line 11 at the center GLm of the third gate line group, to the third gate line group. That is, the timing controller 541 controls the gate line group from the gate line 11 at "GLm-200" to the gate line 11 at "GLm+199" to use normal display (setting number 1), and controls the gate lines 11 other than the above to use double-height display (setting number 2). As a result, it is possible to suppress image blurring while performing normal display in the area visible to the user (the area where the third gate line group is arranged).

[0059] [Variations] Although the embodiments of the present invention have been described above, the above-described embodiments are merely examples for carrying out the invention. Therefore, the present invention is not limited to the above-described embodiments, and can be modified as appropriate within the scope of the spirit of the invention. Modifications of the above-described embodiments will be described below.

[0060] (1) In the first to fifth embodiments, examples have been shown in which the display device performs normal display, 1.5x vertical size display, 2x vertical size display, and 3x vertical size display, but the present disclosure is not limited to this. For example, the display device may be configured to perform 1.33x vertical size display (a rational number size display other than 1.5) and 4x vertical size display (a size display that is 4 or more times larger).

[0061] (2) In the first to fifth embodiments, the switch control signal SWA and the switch control signal SWB are set to high level in this order within one cycle of the horizontal synchronization signal, but the present disclosure is not limited to this. For example, the distribution unit (demultiplexer) may be configured so that three or more switch control signals are set to high level in this order within one cycle of the horizontal synchronization signal, or the distribution unit (demultiplexer) may not be provided in the source drive circuit.

[0062] (3) In the first to fifth embodiments, the lighting period is a period that includes the end of one frame period, but the present disclosure is not limited to this. For example, a lighting period may be provided at the beginning of one frame period, and a writing period may be provided after the lighting period.

[0063] The above-described configuration can also be explained as follows.

[0064] A display device according to a first configuration includes a display panel including a plurality of pixel electrodes arranged in a matrix and a liquid crystal layer that is driven in response to a voltage applied to the plurality of pixel electrodes; a backlight that irradiates the display panel with light during a lighting period, which is a portion of one cycle of a vertical synchronization signal; a plurality of transistors connected to the plurality of pixel electrodes; a plurality of gate lines connected to the plurality of transistors; a gate drive circuit that supplies gate signals to the plurality of gate lines; a control circuit that controls the gate drive circuit and causes the gate drive circuit to transmit the gate signals to the plurality of gate lines during a lighting period, which is a period other than the lighting period within one cycle of the vertical synchronization signal; and a temperature sensor, wherein when the temperature detected by the temperature sensor is less than a first threshold temperature, the control circuit sets a set number, which is the number of gate lines to which gate signals are supplied from the gate drive circuit within one cycle of the horizontal synchronization signal, to a first number greater than 1 (first configuration).

[0065] In a display device having a display panel including a liquid crystal layer, gate signals are supplied to multiple gate lines within one cycle of a vertical synchronization signal. Voltages are supplied to pixel electrodes via transistors that are turned on by the gate signals (image signals are written). The backlight then lights up within one cycle of the vertical synchronization signal. After the image signals are written to the display panel, it takes time for the liquid crystal layer of the display panel to respond to the image signals and become activated. The lower the temperature of the liquid crystal layer, the longer this time becomes. Therefore, when the temperature of the display panel (liquid crystal layer) is low, the backlight starts to light up before the liquid crystal layer of the display panel is fully activated, resulting in a blurred image on the screen. In contrast, with the first configuration, when the temperature of the display panel is below a first threshold temperature, the number of gate lines to which a voltage is supplied within one cycle of a horizontal synchronization signal can be increased to more than one. That is, voltages can be applied simultaneously to more than one row of pixel electrodes within one cycle of a horizontal synchronization signal. This allows the time required to apply voltage to all pixel electrodes (the time required to write image signals to the pixel electrodes) to be shortened without changing the length of one cycle of the horizontal synchronization signal (while maintaining image quality). This ensures a period during which the liquid crystal layer of the display panel is driven in response to the voltage (image signal), preventing the backlight from starting to light up before the liquid crystal layer of the display panel is fully driven. As a result, blurring of the image on the screen can be prevented while maintaining image quality.

[0066] In the first configuration, the plurality of gate lines may include a first gate line group, a second gate line group, and a third gate line group disposed between the first gate line group and the second gate line group. The control circuit may be configured to, when the detected temperature is lower than the first threshold temperature, set the set numbers for the first gate line group and the second gate line group to the first number, and set the set number for the third gate line group to a second number greater than or equal to 1 and less than the first number (second configuration).

[0067] Here, a user generally views the central portion of the screen. In contrast, according to the second configuration, the number of gate lines to which gate signals are supplied per cycle of the horizontal synchronization signal in the central portion of the screen (the region where the third gate line group is arranged) can be made smaller than that in other regions (the regions at the top and bottom of the screen). This makes it possible to prevent the image from becoming blurred on the screen while improving the image quality in the central portion viewed by the user.

[0068] In a second configuration, the display device may further include a first memory circuit in which information indicating whether at least some of the gate lines belong to the first gate line group, the second gate line group, or the third gate line group is stored in association with the detected temperature. The control circuit may be configured to refer to the information based on the detected temperature and to set whether the at least some of the gate lines belong to the first gate line group, the second gate line group, or the third gate line group (third configuration).

[0069] According to the third configuration, it is possible to change the size of the area in the central part of the screen in accordance with the temperature of the display panel while preventing the image from becoming blurred on the screen.

[0070] In the second configuration, the display device may further include a gaze sensor that detects a user's gaze, and the control circuit may be configured to set the third gate line group based on a detection result from the gaze sensor so that the third gate line group includes a gate line corresponding to a position viewed by the user.

[0071] According to the fourth configuration, it is possible to improve the quality of the image on the screen in front of the user's line of sight, while speeding up the scanning of areas other than the line of sight.

[0072] In any one of the first to fourth configurations, the control circuit may be configured to set the set number to a third number greater than the first number when the temperature of the display panel detected by the temperature sensor is less than a second threshold temperature lower than the first threshold temperature (fifth configuration).

[0073] According to the fifth configuration, even when the temperature of the display panel is lower than a second threshold temperature that is lower than the first threshold temperature, it is possible to prevent the image from becoming blurred on the screen while maintaining image quality.

[0074] In any one of the first to fourth configurations, the display device may further include a second storage circuit in which a number is stored in association with the detected temperature. The control circuit may be configured to refer to the second storage circuit based on the detected temperature and set the number read from the second storage circuit to the set number (sixth configuration).

[0075] According to the sixth configuration, it is possible to prevent the image from becoming blurred on the screen while maintaining the image quality in accordance with the temperature of the display panel.

[0076] A seventh configuration of a control method for a display device includes: a display panel including a plurality of pixel electrodes arranged in a matrix and a liquid crystal layer that is driven in response to a voltage applied to the plurality of pixel electrodes; a backlight that irradiates light onto the display panel during a lighting period that is a portion of one cycle of a vertical synchronization signal; a plurality of transistors connected to the plurality of pixel electrodes; a plurality of gate lines connected to the plurality of transistors; a gate drive circuit that supplies gate signals to the plurality of gate lines; a control circuit that controls the gate drive circuit and causes the gate drive circuit to transmit the gate signals to the plurality of gate lines during a lighting period that is a period other than the lighting period within one cycle of the vertical synchronization signal; and a temperature sensor, wherein the control circuit acquires a temperature detected by the temperature sensor, and, if the detected temperature is less than a first threshold temperature, sets a set number, which is the number of gate lines to which gate signals are supplied from the gate drive circuit within one cycle of the horizontal synchronization signal, to a first number greater than 1 (seventh configuration).

[0077] According to the seventh configuration, it is possible to provide a method for controlling a display device that can prevent blurring of an image caused by low temperature while maintaining image quality. [Explanation of symbols]

[0078] 1: display unit, 2: gate drive circuit, 3: source drive circuit, 4: control circuit, 5: backlight, 6: temperature sensor, 10: display panel, 10a: active matrix substrate, 10b: opposing substrate, 10c: liquid crystal layer, 11: gate line, 12: source line, 12a: source line, 12b: source line, 13: transistor, 14: pixel electrode, 15: common electrode, 31: output unit, 31a: output terminal, 32: signal distribution unit, 32a: switch, 32b: switch, 41: timing controller, 42: image compression calculation unit, 43: backlight control unit, 100: display device, 200: display device, 204: control circuit, 241: timing controller, 242: image compression calculation unit, 244: setting register, 300: display device, 304: control circuit, 341: timing controller, 342: image compression calculation unit, 344: setting register, 400: display device, 404: control circuit, 441: timing controller, 442: image compression calculation unit, 444: setting register, 500: display device, 504: control circuit, 507: line of sight sensor, 541: timing controller, 542: image compression calculation unit

Claims

1. a display panel including a plurality of pixel electrodes arranged in a matrix and a liquid crystal layer that is driven in response to voltages applied to the plurality of pixel electrodes; a backlight that irradiates the display panel with light during a lighting period that is a portion of one cycle of a vertical synchronization signal; a plurality of transistors connected to the plurality of pixel electrodes; a plurality of gate lines connected to the plurality of transistors; a gate drive circuit for supplying gate signals to the plurality of gate lines; a control circuit for controlling the gate drive circuit, the control circuit causing the gate drive circuit to transmit the gate signals to the plurality of gate lines during a light-off period, which is a period other than the light-on period within one cycle of the vertical synchronization signal; a temperature sensor; The display device, wherein the control circuit sets a set number, which is the number of gate lines to which gate signals are supplied from the gate drive circuit within one period of a horizontal synchronization signal, to a first number greater than 1 when the temperature detected by the temperature sensor is less than a first threshold temperature.

2. the plurality of gate lines include a first gate line group, a second gate line group, and a third gate line group disposed between the first gate line group and the second gate line group; 2. The display device of claim 1, wherein when the detected temperature is less than the first threshold temperature, the control circuit sets the set number for the first gate line group and the second gate line group to the first number, and sets the set number for the third gate line group to a second number that is greater than or equal to 1 and less than the first number.

3. a first storage circuit storing information indicating whether at least some of the gate lines belong to the first gate line group, the second gate line group, or the third gate line group, in association with the detected temperature; 3. The display device according to claim 2, wherein the control circuit refers to the information based on the detected temperature and determines whether the at least some of the gate lines belong to the first gate line group, the second gate line group, or the third gate line group.

4. Further provided with a gaze sensor for detecting the gaze of a user, 3. The display device according to claim 2, wherein the control circuit sets the third gate line group based on the detection result from the line-of-sight sensor so that the third gate line group includes a gate line corresponding to a position viewed by a user.

5. A display device described in any one of claims 1 to 4, wherein the control circuit sets the set number to a third number greater than the first number when the detected temperature is less than a second threshold temperature lower than the first threshold temperature.

6. a second memory circuit in which a number is stored in association with the detected temperature; The display device according to any one of claims 1 to 4, wherein the control circuit refers to the second memory circuit based on the detected temperature and sets the number read from the second memory circuit to the set number.

7. a display panel including a plurality of pixel electrodes arranged in a matrix and a liquid crystal layer that is driven in response to voltages applied to the plurality of pixel electrodes; a backlight that irradiates the display panel with light during a lighting period that is a portion of one cycle of a vertical synchronization signal; a plurality of transistors connected to the plurality of pixel electrodes; a plurality of gate lines connected to the plurality of transistors; a gate drive circuit for supplying gate signals to the plurality of gate lines; a control circuit for controlling the gate drive circuit, the control circuit causing the gate drive circuit to transmit the gate signals to the plurality of gate lines during a light-off period, which is a period other than the light-on period within one cycle of the vertical synchronization signal; A method for controlling a display device including a temperature sensor, the method comprising: acquiring a temperature detected by the temperature sensor; A method for controlling a display device, wherein when the pre-detected temperature is lower than a first threshold temperature, a set number, which is the number of gate lines to which gate signals are supplied from the gate drive circuit within one period of a horizontal synchronization signal, is set to a first number greater than 1.

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