Display driver and display device

Abstract

PURPOSE: To provide a display driver capable of driving various display panels at high speed while suppressing a manufacturing cost, and a display device including the display driver.CONSTITUTION: According to the present disclosure, each of a plurality of circuit blocks that generates, as a drive signal, a signal representing, by time-division multiplexing, each of voltage values corresponding to luminance levels indicated by each of K pixel data pieces generates first to Qth pixel data signals representing the K pixel data pieces with Q signals, where Q is smaller than K, by time-division multiplexing at least one set of pixel data pieces including two data pieces among the K pixel data pieces. Then, each of the first to Qth pixel data signals is converted into first to Qth gradation voltages having an analog voltage value, a gradation voltage signal representing the voltage value corresponding to each of the K pixel data pieces represented by the first to Qth gradation voltages by time division multiplexing is generated for each horizontal scanning period, and a signal obtained by amplifying the gradation voltage signal is output as the drive signal described above.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a display driver that drives a display panel in response to a video signal, and a display device. [Background technology]

[0002] A commonly known liquid crystal or organic EL display device has a display panel in which display cells are formed at each intersection of a plurality of scanning lines and a plurality of signal lines (hereinafter referred to as data lines), and a display driver that drives the plurality of data lines of the display panel.

[0003] The display driver includes a latch unit that captures multiple pieces of pixel data, each representing a digital value representing the brightness level of each pixel based on a video signal, multiple level shifters that increase the signal level of each of the captured pixel data pieces, and multiple DA (Digital to Analog) converters that convert each of the increased-voltage pixel data pieces into grayscale voltages having analog voltage values. Furthermore, the display driver includes multiple output amplifiers that respectively amplify multiple grayscale voltages corresponding to each of the pixel data pieces and supply them to multiple data lines of the display panel (see, for example, Patent Document 1). That is, the display driver includes level shifters, DA converters, and output amplifiers, each equal in number to the number of data lines formed on the display panel.

[0004] Recently, the resolution of images has been increasing in liquid crystal or organic electroluminescence (EL) display devices installed in portable information terminals such as smartphones, and the number of data lines in the display panel has been increasing accordingly. Therefore, the number of output amplifiers required corresponds to the number of data lines, which has led to a problem of the display driver becoming larger. To address this, a display driver has been proposed in which a single output amplifier drives multiple data lines of a display panel one by one in a time-division manner (referred to as time-division driving) (see, for example, Patent Document 2). This allows the number of output amplifiers to be reduced to 1 / n (n: number of time divisions), thereby enabling the circuit scale of the display driver to be correspondingly reduced. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-301946 [Patent Document 2] Patent 7367006

[0006] [overview] However, even if the above-mentioned time division driving is adopted, the number of level shifters and DA converters included in the display driver increases in proportion to the increase in the number of data lines of the display panel, so it is not possible to significantly reduce the circuit scale.

[0007] Furthermore, as display panels become more highly detailed, the number of level shifters and DA converters increases, which increases current consumption. In particular, if the instantaneous current flowing through all level shifters and DA converters becomes large under heavy loads, the power supply voltage may drop, resulting in operational malfunctions.

[0008] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a display driver and a display device that are capable of high-speed driving, reducing the circuit scale, and reducing current consumption without causing operational malfunctions.

[0009] A display driver according to the present invention is a display driver for driving a display panel including a plurality of data lines and a demultiplexer that receives one drive signal corresponding to each of K (K is an integer of 2 or more) of the plurality of data lines and sequentially supplies the one drive signal to the K data lines one by one for each of the K data lines, the display driver having a plurality of circuit blocks that receive a plurality of pixel data pieces corresponding to each pixel based on a video signal and each generate, as the one drive signal, a signal that represents, for each of the K pixel data pieces, by time-division multiplexing each of voltage values ​​corresponding to brightness levels indicated by the K pixel data pieces, and each of the plurality of circuit blocks time-division multiplexes at least one set of pixel data pieces consisting of two data pieces out of the K pixel data pieces, thereby generating a signal representing the voltage values ​​corresponding to brightness levels indicated by the K pixel data pieces. a first multiplexer unit that outputs first to Qth pixel data signals representing the K pixel data pieces via each of Q (Q is an integer of 2 or more) signal lines, the Q signal lines being less than K; a level shift unit that generates first to Qth high-voltage pixel data signals by level-shifting the amplitudes of the first to Qth pixel data signals to higher voltages; a digital-to-analog conversion unit that converts the first to Qth high-voltage pixel data signals into first to Qth gradation voltages having voltage values ​​corresponding to the luminance levels represented by the first to Qth high-voltage pixel data signals; a second multiplexer unit that outputs, for each horizontal scanning period of the video signal, gradation voltage signals that time-division multiplex the voltage values ​​corresponding to each of the K pixel data pieces represented by the first to Qth gradation voltages; and an output amplifier unit that outputs a signal obtained by amplifying the gradation voltage signal as the single drive signal.

[0010] Further, a display device according to the present invention is a display device having a display panel including a plurality of data lines, a demultiplexer that receives one drive signal corresponding to each of K (K is an integer of 2 or more) of the plurality of data lines and sequentially supplies the one drive signal to the K data lines one by one for each of the K data lines, and a display driver that drives the display panel, wherein the display driver has a plurality of circuit blocks that receive a plurality of pixel data pieces corresponding to each pixel based on a video signal, and each circuit block generates, for each of the K pixel data pieces, a signal that represents, by time division multiplexing, each of voltage values ​​corresponding to brightness levels indicated by the K pixel data pieces, and each of the plurality of circuit blocks generates at least one set of pixel data consisting of two data pieces out of the K pixel data pieces. a level shift unit that generates first to Qth high-voltage pixel data signals by level-shifting the amplitudes of the first to Qth pixel data signals to the high-voltage side; a digital-to-analog conversion unit that converts the first to Qth high-voltage pixel data signals into first to Qth gradation voltages having voltage values ​​corresponding to the luminance levels represented by the first to Qth gradation voltages; a second multiplexer unit that outputs, for each horizontal scanning period of the video signal, gradation voltage signals that time-division multiplex the voltage values ​​corresponding to each of the K pixel data pieces represented by the first to Q gradation voltages; and an output amplifier unit that amplifies the gradation voltage signals and outputs the amplified signals as the single drive signal. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a block diagram showing a schematic configuration of a display device 100 including a display driver according to the present invention. [Figure 2] FIG. 2 is a block diagram showing the internal configuration of a data driver 12. [Figure 3] FIG. 10 is a block diagram showing the internal configuration of a circuit block BL1 when the number of divisions K in time-division driving is 3. [Figure 4]4 is a time chart showing an example of the internal operation of the circuit block BL1 having the configuration (K=3) shown in FIG. [Figure 5] FIG. 10 is a block diagram showing the internal configuration of a circuit block BL1 when the number of divisions K in time-division driving is 4. [Figure 6] 6 is a time chart showing an example of the internal operation of the circuit block BL1 having the configuration (K=4) shown in FIG. 5. [Figure 7] FIG. 10 is a block diagram showing the internal configuration of a circuit block BL1 when the number of divisions K in time-division driving is 6. [Figure 8] 8 is a time chart showing an example of the internal operation of the circuit block BL1 having the configuration (K=6) shown in Fig. 7. [Detailed Description] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. Example 1

[0012] FIG. 1 is a block diagram showing a schematic configuration of a display device 100 including a display driver according to the present invention.

[0013] As shown in FIG. 1, the display device 100 includes a display control unit 10, a scan driver 11, a data driver 12, and a display panel 20.

[0014] The display panel 20 is, for example, a time-division driven liquid crystal or organic EL display panel provided with r (r is an integer of 2 or more) horizontal scanning lines S1 to Sr extending in the horizontal direction of the two-dimensional screen, m (m is an integer of 2 or more) data lines D1 to Dm extending in the vertical direction of the two-dimensional screen, and a demultiplexer unit DMX. In the area (encircled area) of the intersection of the horizontal scanning lines and data lines included in the display panel 20, display cells for each color component required for color display, such as a red display cell for displaying red, a green display cell for displaying green, or a blue display cell for displaying blue, are formed.

[0015] The demultiplexer unit DMX receives the input switching signal CHS and the drive signals G1 to Gy output from the data driver 12. Note that "y" represents y=m / K m: total number of data lines K: Number of divisions for time-division drive (an integer of 3 or more) is a positive integer expressed as

[0016] The demultiplexer section DMX includes first to y-th demultiplexers (not shown), each connected to one of the drive signals G1 to Gy and connected to K data lines of the data lines D1 to Dm. Each of the first to y-th demultiplexers outputs one drive signal received by itself to the K data lines connected to it one by one in one horizontal scanning period (hereinafter also referred to as 1H) in response to the input switching signal CHS.

[0017] The display control unit 10 receives a video signal VS that includes a horizontal synchronization signal and indicates the brightness level of each pixel. Based on the video signal VS, the display control unit 10 generates a video digital signal DVS that includes various control signals such as a start pulse STA, a clock signal CLK, vertical and horizontal synchronization signals, and a series of pixel data pieces that indicate the brightness level of each pixel in, for example, 8 bits, and supplies this to the data driver 12.

[0018] Furthermore, the display control unit 10 generates a scan timing signal indicating the timing for selecting a scan line in accordance with the horizontal synchronization signal included in the video signal VS, and supplies this to the scan driver 11.

[0019] The scan driver 11 generates scan pulses in response to scan timing signals supplied from the display control unit 10, and applies these pulses to the horizontal scan lines S1 to Sr formed on the display panel 20 one by one in sequence.

[0020] Based on the digital video signal DVS, the data driver 12 converts each pixel data piece included in the digital video signal DVS into an analog voltage value, amplifies the converted voltage value, and generates the resulting drive signals. The data driver 12 outputs the generated drive signals to the display panel 20 as drive signals G1 to Gy, y being an integer of 2 or greater.

[0021] Furthermore, the data driver 12 outputs to the display panel 20 an input switching signal CHS that switches the data line to which the drive signal is to be input on the display panel 20 side.

[0022] FIG. 2 is a block diagram showing the internal configuration of the data driver 12. As shown in FIG.

[0023] As shown in FIG. 2, the data driver 12 includes a control circuit 120, a shift register 121, a data latch unit 122, a first multiplexer unit (hereinafter referred to as the first MUX unit) 123, a level shift unit 124, a DA conversion unit 125, a second multiplexer unit (hereinafter referred to as the second MUX unit) 126, and an output amplifier unit 127.

[0024] The control circuit 120 receives the digital video signal DVS, extracts a start pulse STA and a clock signal CLK from the digital video signal DVS, and supplies them to a shift register 121. The control circuit 120 also supplies a load signal LOAD that prompts data loading to a data latch unit 122 in response to a horizontal synchronization signal included in the digital video signal DVS. The control circuit 120 also generates an input switching signal CHS that controls a demultiplexer unit DMX included in the display panel 20 in response to the horizontal synchronization signal, and outputs this to the data driver 12.

[0025] Furthermore, the control circuit 120 generates at least one selection control signal Sd and supplies it to the first MUX unit 123 in response to the horizontal synchronization signal, and also generates at least one selection control signal Sv and supplies it to the second MUX unit 126.

[0026] The shift register 121 generates latch timing signals t1 to tm in synchronization with the clock signal CLK in response to a start pulse STA included in the video digital signal DVS, and supplies the latch timing signals t1 to tm to the data latch unit 122, indicating the timing at which each of the m data pieces is latched in order at different timings.

[0027] The data latch unit 122 latches each pixel data piece in the series of pixel data pieces contained in the video digital signal DVS in sequence at the timing of latch timing signals t1 to tm, holds m pixel data pieces, and outputs each of them to the first MUX unit 123 as pixel data P1 to Pm in response to a load signal LOAD.

[0028] The first MUX unit 123 takes in the pixel data P1 to Pm in units of K, which is the division number of time-division driving, and time-division multiplexes at least one pair of pixel data pieces among the K pixel data pieces within 1H in response to the selection control signal Sd to output one gradation voltage signal. As a result, the first MUX unit 123 outputs the pixel data P1 to Pm as Q (Q is an integer equal to or greater than 2) pixel data signals, which is less than K, for each K pixel data piece.

[0029] For example, when K is 3, the first MUX unit 123 takes in pixel data P1 to Pm in groups of three pixel data pieces, and outputs them as two pixel data signals consisting of a first pixel data signal that represents two of the three pixel data pieces by time division multiplexing, and a second pixel data signal that represents the remaining one.

[0030] Also, when K is 4, the first MUX unit 123 takes in pixel data P1 to Pm in groups of four pixel data pieces, and outputs them as two pixel data signals consisting of a first pixel data signal that represents two of the four pixel data pieces by time division multiplexing, and a second pixel data signal that represents the remaining two by time division multiplexing.

[0031] Also, when K is 6, the first MUX unit 123 takes in pixel data P1 to Pm in groups of six pixel data pieces, and outputs them as three pixel data signals consisting of a first pixel data signal representing two of the six pixel data pieces by time division multiplexing, a second pixel data signal representing the other two by time division multiplexing, and a third pixel data signal representing the remaining two by time division multiplexing.

[0032] Through the above-described operation, the first MUX unit 123 converts the m pieces of pixel data P1 to Pm supplied from the data latch unit 122 into j pieces of pixel data signals U1 to Uj (j is a positive integer expressed as m·Q / K) and outputs them to the level shift unit 124.

[0033] The level shifter 124 outputs to the DA converter 125 high-voltage pixel data signals F1 to Fj obtained by level-shifting the signal amplitude of each of the pixel data signals U1 to Uj to the high-voltage side.

[0034] The DA conversion unit 125 converts each of the high-voltage pixel data signals F1 to Fj into grayscale voltages V1 to Vj having voltage values ​​corresponding to the luminance levels represented by the signals, and outputs the voltages to the second MUX unit 126.

[0035] The second MUX unit 126 takes in the gradation voltages V1 to Vj in groups of Q, and time-division multiplexes the Q gradation voltages within 1H in accordance with the selection control signal Sv to output them as one gradation voltage signal. As a result, the second MUX unit 126 outputs the j gradation voltages V1 to Vj supplied from the DA conversion unit 125 to the output amplifier unit 127 as y gradation voltage signals E1 to Ey.

[0036] As described above, the total number m of pixel data P1 to Pm, the total number j of pixel data signals U1 to Uj, and the total number y of grayscale voltage signals E1 to Ey have the following magnitude relationship.

[0037] m>j>y The output amplifier section 127 generates the above-mentioned drive signals G1 to Gy by amplifying the grayscale voltage signals E1 to Ey individually, and outputs them to the display panel 20. The internal configurations of the data latch section 122, first MUX section 123, level shift section 124, DA conversion section 125, second MUX section 126 and output amplifier section 127 will be described below.

[0038] Each of the drive signals G1 to Gy is generated individually for each of the circuit blocks BL1 to BLy divided by the broken line areas shown in Fig. 2 across the data latch unit 122, first MUX unit 123, level shift unit 124, DA conversion unit 125, second MUX unit 126, and output amplifier unit 127. In this case, each of the circuit blocks BL1 to BLy has the same basic configuration, although the pixel data fragments (P1 to Pm) held and output by the data latch unit 122 from the series of pixel data fragments included in the video digital signal DVS are different.

[0039] Therefore, the internal configuration and operation of the circuit block BL1 that generates the drive signal G1 will be explained in detail below, with the number of divisions K in time-division driving being 3, 4, and 6. [When the number of divisions K=3] FIG. 3 is a block diagram showing the internal configuration of the circuit block BL1 when the division number K is 3.

[0040] As shown in FIG. 3, the circuit block BL1 is composed of hold latches L1 to L3 included in the data latch unit 122, a hold latch Lc1 and a data selector SL included in the first MUX unit, level shifters Ls1 and Ls2 included in the level shift unit 124, DA converters Da1 and Da2 included in the DA conversion unit 125, a voltage selector SeL included in the second MUX unit 126, and an amplifier Ap1 included in the output amplifier unit 127.

[0041] The hold latches L1 to L3 of the data latch unit 122 hold pixel data P1 to P3, each consisting of, for example, 8 bits, from a series of pixel data pieces included in the video digital signal DVS, and output each to the first MUX unit 123 in response to the load signal LOAD.

[0042] The hold latch Lc1 of the first MUX unit 123 receives a binary (logical levels 0 and 1) selection control signal Sd, and captures and holds pixel data P3 at the timing of the falling edge of the selection control signal Sd, while supplying it to the data selector SL. The data selector SL receives the pixel data P1 output from the hold latch L1 and the pixel data P3 supplied from the hold latch Lc1, as well as the selection control signal Sd. While the selection control signal Sd indicates logical level 0, the data selector SL selects the pixel data P1 output from the hold latch Lc1 and outputs a pixel data signal U1 representing this pixel data P1 to the level shift unit 124. Meanwhile, while the selection control signal Sd indicates logical level 1, the data selector SL selects the pixel data P3 supplied from the hold latch Lc1 and outputs a pixel data signal U1 representing this pixel data P3 to the level shift unit 124.

[0043] Furthermore, the first MUX unit 123 receives the pixel data P2 output from the hold latch L2, and outputs a pixel data signal U2 representing the pixel data P2 to the level shift unit .

[0044] The level shifter Ls1 of the level shift unit 124 level-shifts the signal amplitude of the pixel data signal U1 to the high-voltage side and outputs the result as a high-voltage pixel data signal F1 to the DA conversion unit 125. The level shifter Ls2 level-shifts the signal amplitude of the pixel data signal U2 to the high-voltage side and outputs the result as a high-voltage pixel data signal F2 to the DA conversion unit 125.

[0045] The DA converter Da1 of the DA conversion unit 125 converts the high-voltage pixel data signal F1 into a gradation voltage V1 having a voltage value corresponding to the luminance level indicated by the high-voltage pixel data signal F1 and outputs it to the second MUX unit 126. The DA converter Da2 converts the high-voltage pixel data signal F2 into a gradation voltage V2 having a voltage value corresponding to the luminance level indicated by the high-voltage pixel data signal F2 and outputs it to the second MUX unit 126.

[0046] The voltage selector SeL of the second MUX unit 126 receives the above-mentioned gradation voltages V1 and V2, as well as the selection control signal Sv. While the selection control signal Sv indicates a logical level of 0, the voltage selector SeL selects the gradation voltage V1 and outputs it as a gradation voltage signal E1 to the output amplifier unit 127. On the other hand, while the selection control signal Sv indicates a logical level of 1, the voltage selector SeL selects the gradation voltage V2 and outputs it as a gradation voltage signal E1 to the output amplifier unit 127.

[0047] The amplifier Ap1 of the output amplifier section 127 is, for example, an operational amplifier having a voltage follower configuration, and outputs a signal obtained by amplifying the grayscale voltage signal E1 as the drive signal G1.

[0048] FIG. 4 is a time chart showing an example of the internal operation of the circuit block BL1 having the configuration (K=3) shown in FIG.

[0049] First, in response to the load signal LOAD, which appears as a single pulse every 1H, the hold latches L1 to L3 output pixel data P1 indicating a luminance level a1, pixel data P2 indicating a luminance level a2, and pixel data P3 indicating a luminance level a3, as shown in FIG.

[0050] Here, in response to the load signal LOAD, the control circuit 120 transitions from logic level 1 to logic level 0 at a predetermined beginning point within 1H, as shown in FIG. 4, and after maintaining this logic level 0 state for a predetermined period (for example, 1H / 2), supplies a binary selection control signal Sd that transitions to logic level 1 to the first MUX section 123.

[0051] The hold latch Lc1 captures and holds pixel data P3 indicating the luminance level a3 at the timing of the falling edge of the selection control signal Sd, and supplies this to the data selector SL.

[0052] While the selection control signal Sd is at logic level 0, the data selector SL selects pixel data P1 from among P1 and P3, and supplies a pixel data signal U1 indicating the luminance level a1 indicated by the pixel data P1 to the level shifter Ls1. On the other hand, while the selection control signal Sd is at logic level 1, the data selector SL selects pixel data P3, and supplies a pixel data signal U1 indicating the luminance level a3 indicated by the pixel data P3 to the level shifter Ls1. The level shifter Ls2 receives a pixel data signal U2 indicating the luminance level a2 indicated by the pixel data P2.

[0053] Here, while the pixel data signal U1 represents the luminance level a1, the level shifter Ls1 and DA converter Da1 output a gradation voltage V1 having a voltage value Va1 corresponding to the luminance level a1. On the other hand, while the pixel data signal U1 represents the luminance level a3, the level shifter Ls1 and DA converter Da1 output a gradation voltage V1 having a voltage value Va3 corresponding to the luminance level a3. Note that the level shifter Ls2 and DA converter Da2 output a gradation voltage V2 having a voltage value Va2 corresponding to the luminance level a2 indicated by the pixel data signal U2.

[0054] Here, the control circuit 120 transitions from logic level 1 to logic level 0 as shown in FIG. 4 in response to the load signal LOAD, and subsequently supplies the voltage selector SeL with a binary selection control signal Sv whose logic level is inverted for each of the three intervals into which the remaining period within 1H is divided.

[0055] Therefore, in the first interval within 1H, the voltage selector SeL and amplifier Ap1 output a drive signal G1 having a voltage value Va1 indicated by the gradation voltage V1 in response to the selection control signal Sv representing logic level 0. In the following second interval, the voltage selector SeL and amplifier Ap1 output a drive signal G1 having a voltage value Va2 indicated by the gradation voltage V2 in response to the selection control signal Sv having logic level 1. Then, in the following third interval, the voltage selector SeL and amplifier Ap1 output a drive signal G1 having a voltage value Va3 indicated by the gradation voltage V1 in response to the selection control signal Sv having logic level 0.

[0056] In this way, the circuit block BL1 generates a drive signal G1 that transmits the voltage values ​​Va1 to Va3 corresponding to the three pixel data P1 to P3 contained in the video digital signal DVS by time-division multiplexing within 1H, and outputs this to the display panel 20.

[0057] In this case, according to the configuration shown in FIG. 3, the output delay time of each of the voltage values ​​Va1 to Va3 represented by the drive signal G1 is, as shown in FIG. 4, the delay time DEs from the rising or falling edge of the selection control signal Sv through the time spent for the operation of the voltage selector SeL and the amplifier Ap1, thereby enabling high-speed drive.

[0058] Furthermore, in the configuration shown in Figure 3, when three pixel data P1 to P3 are time-division multiplexed, a hold latch Lc1 and a data selector SL are added, but the number of level shifters and DA converters that are originally required is reduced from three to two (Ls1, Ls2, Da1, Da2), respectively.

[0059] Therefore, the overall circuit scale of the data driver 12 is significantly reduced compared to the display driver described in Patent Document 2, and accordingly, current consumption is also significantly reduced. Furthermore, with the configuration shown in Figure 3, the total number of level shifters and the total number of DA converters are both two-thirds of the numbers conventionally required. Therefore, the instantaneous current flowing due to the simultaneous operation of these level shifters and DA converters is also significantly reduced, making it possible to eliminate problems associated with drops in power supply voltage. [When the number of divisions K=4] FIG. 5 is a block diagram showing the internal configuration of the circuit block BL1 when the division number K is four.

[0060] In the configuration shown in Fig. 5, the data latch section 122 includes hold latches L1 to L4, and the first MUX section 123 includes hold latches Lc1 and Lc2 and data selectors SL1 and SL2. Note that the internal configurations of the level shift section 124, DA conversion section 125, second MUX section 126, and output amplifier section 127 in Fig. 5 are the same as those shown in Fig. 3, so a description thereof will be omitted.

[0061] The hold latches L1 to L4 of the data latch unit 122 hold, for example, 8-bit pixel data P1 to P4 from a series of pixel data pieces included in the video digital signal DVS, and output each to the first MUX unit 123 in response to the load signal LOAD.

[0062] The hold latch Lc1 of the first MUX unit 123 receives a binary (logical levels 0 and 1) selection control signal Sd1, and captures and holds pixel data P3 at the timing of the falling edge of the selection control signal Sd1 while supplying it to the data selector SL1. The data selector SL1 receives the pixel data P1 output from the hold latch L1 and the pixel data P3 supplied from the hold latch Lc1, as well as the selection control signal Sd1. While the selection control signal Sd1 indicates logical level 0, the data selector SL1 selects the pixel data P1 output from the hold latch L1 and outputs a pixel data signal U1 representing this pixel data P1 to the level shift unit 124. Meanwhile, while the selection control signal Sd1 indicates logical level 1, the data selector SL1 selects the pixel data P3 supplied from the hold latch Lc1 and outputs a pixel data signal U1 representing this pixel data P3 to the level shift unit 124.

[0063] The hold latch Lc2 of the first MUX unit 123 receives a binary (logical levels 0 and 1) selection control signal Sd2, and captures and holds pixel data P4 at the falling edge of the selection control signal Sd2 while supplying it to the data selector SL2. The data selector SL2 receives the pixel data P2 output from the hold latch L2 and the pixel data P4 supplied from the hold latch Lc2, as well as the selection control signal Sd2. While the selection control signal Sd2 indicates a logical level 0, the data selector SL2 selects the pixel data P2 output from the hold latch L2 and outputs a pixel data signal U2 representing this pixel data P2 to the level shift unit 124. Meanwhile, while the selection control signal Sd2 indicates a logical level 1, the data selector SL2 selects the pixel data P4 supplied from the hold latch Lc2 and outputs a pixel data signal U2 representing this pixel data P4 to the level shift unit 124.

[0064] FIG. 6 is a time chart showing an example of the internal operation of the circuit block BL1 having the configuration (K=4) shown in FIG.

[0065] First, in response to a load signal LOAD in which a single pulse appears every 1H, hold latches L1 to L4 output pixel data P1 to P4 indicating luminance levels a1 to a4, respectively, as shown in FIG.

[0066] 6, the control circuit 120 generates a binary selection control signal Sd1 that transitions from logic level 1 to logic level 0 at a predetermined beginning point within 1H, maintains this logic level 0 state for a predetermined period (e.g., 1H / 2), and then transitions to logic level 1, in response to the load signal LOAD. Furthermore, the control circuit 120 generates a binary selection control signal Sd2 that transitions from logic level 1 to logic level 0 at a time later than the beginning point, for example, 1H / 4, maintains this logic level 0 state for a predetermined period (e.g., 1H / 2), and then transitions to logic level 1. The control circuit 120 then supplies the generated selection control signals Sd1 and Sd2 to the first MUX unit 123.

[0067] The hold latch Lc1 captures and holds pixel data P3 indicating the luminance level a3 at the timing of the falling edge of the selection control signal Sd1, and supplies this to the data selector SL1.

[0068] While the selection control signal Sd1 is at logic level 0, the data selector SL1 selects pixel data P1 from among P1 and P3, and supplies a pixel data signal U1 indicating the luminance level a1 indicated by the pixel data P1 to the level shifter Ls1. On the other hand, while the selection control signal Sd1 is at logic level 1, the data selector SL1 selects pixel data P3, and supplies a pixel data signal U1 indicating the luminance level a3 indicated by the pixel data P3 to the level shifter Ls1.

[0069] The hold latch Lc2 captures and holds pixel data P4 indicating luminance level a4 at the timing of the falling edge of the selection control signal Sd2, and supplies this to the data selector SL2.

[0070] While the selection control signal Sd2 is at logic level 0, the data selector SL2 selects pixel data P2 from among pixel data P2 and P4, and supplies a pixel data signal U2 indicating the luminance level a2 indicated by the pixel data P2 to the level shifter Ls2. On the other hand, while the selection control signal Sd2 is at logic level 1, the data selector SL2 selects pixel data P4, and supplies a pixel data signal U2 indicating the luminance level a4 indicated by the pixel data P4 to the level shifter Ls2.

[0071] Here, while the pixel data signal U1 represents the luminance level a1, the level shifter Ls1 and the DA converter Da1 output the gradation voltage V1 having the voltage value Va1 corresponding to the luminance level a1. On the other hand, while the pixel data signal U1 represents the luminance level a3, the level shifter Ls1 and the DA converter Da1 output the gradation voltage V1 having the voltage value Va3 corresponding to the luminance level a3.

[0072] While the pixel data signal U2 represents the luminance level a2, the level shifter Ls2 and the DA converter Da2 output the gradation voltage V2 having the voltage value Va2 corresponding to the luminance level a2. On the other hand, while the pixel data signal U2 represents the luminance level a4, the level shifter Ls2 and the DA converter Da2 output the gradation voltage V2 having the voltage value Va4 corresponding to the luminance level a4.

[0073] Here, the control circuit 120 transitions from logic level 1 to logic level 0 as shown in FIG. 6 in response to the load signal LOAD, and subsequently supplies the voltage selector SeL with a binary selection control signal Sv whose logic level is inverted for each of the four intervals into which the remaining period within 1H is divided.

[0074] Therefore, in the first interval within 1H, the voltage selector SeL and amplifier Ap1 output a drive signal G1 having a voltage value Va1 indicated by the gradation voltage V1 in response to the selection control signal Sv representing a logical level of 0. In the following second interval, the voltage selector SeL and amplifier Ap1 output a drive signal G1 having a voltage value Va2 indicated by the gradation voltage V2 in response to the selection control signal Sv representing a logical level of 1. Subsequently, in the third interval, the voltage selector SeL and amplifier Ap1 output a drive signal G1 having a voltage value Va3 indicated by the gradation voltage V1 in response to the selection control signal Sv representing a logical level of 0. And in the fourth interval, the voltage selector SeL and amplifier Ap1 output a drive signal G1 having a voltage value Va4 indicated by the gradation voltage V2 in response to the selection control signal Sv representing a logical level of 1.

[0075] In this way, the circuit block BL1 having the configuration shown in Figure 5 (K=4) generates a drive signal G1 that transmits voltage values ​​Va1 to Va4 corresponding to the four pixel data P1 to P4 contained in the video digital signal DVS by time-division multiplexing them within 1H, and outputs this to the display panel 20.

[0076] In this case, according to the configuration shown in FIG. 5, the output delay time of each of the voltage values ​​Va1 to Va4 represented by the drive signal G1 is the delay time DEs from the rising or falling edge of the selection control signal Sv through the time spent for the operation of the voltage selector SeL and the amplifier Ap1, as shown in FIG. 6, thereby enabling high-speed drive.

[0077] Furthermore, in the configuration shown in FIG. 5, when time-division multiplexing four pixel data P1 to P4, hold latches Lc1 and Lc2 and data selectors SL1 and SL2 are added, but the number of level shifters and DA converters that would otherwise be required is reduced from four to two (Ls1, Ls2, Da1, Da2), respectively.

[0078] Therefore, the overall circuit scale of the data driver 12 is significantly reduced compared to the display driver described in Patent Document 2, and accordingly, current consumption is also significantly reduced. Furthermore, with the configuration shown in Figure 5, the total number of level shifters and the total number of DA converters are both half of the numbers previously required. Therefore, the instantaneous current flowing due to the simultaneous operation of these level shifters and DA converters is also significantly reduced, making it possible to eliminate problems associated with drops in power supply voltage. [When the number of divisions K=6] FIG. 7 is a block diagram showing the internal configuration of the circuit block BL1 when the division number K is six.

[0079] 7, the data latch unit 122 includes hold latches L1 to L6, and the first MUX unit 123 includes hold latches Lc1 to Lc3 and data selectors SL1 to SL3. The level shift unit 124 includes level shifters Ls1 to Ls3, the DA conversion unit 125 includes DA converters Da1 to Da3, the second MUX unit 126 includes a voltage selector SeLL, and the output amplifier unit 127 includes an amplifier Ap1.

[0080] The hold latches L1 to L6 of the data latch unit 122 hold pixel data P1 to P6, each consisting of, for example, 8 bits, from a series of pixel data pieces included in the video digital signal DVS, and output each to the first MUX unit 123 in response to the load signal LOAD.

[0081] The hold latch Lc1 of the first MUX unit 123 receives a binary (logical levels 0 and 1) selection control signal Sd1, and captures and holds pixel data P4 at the timing of the falling edge of the selection control signal Sd1 while supplying it to the data selector SL1. The data selector SL1 receives the pixel data P1 output from the hold latch L1 and the pixel data P4 supplied from the hold latch Lc1, as well as the selection control signal Sd1. While the selection control signal Sd1 indicates logical level 0, the data selector SL1 selects the pixel data P1 output from the hold latch L1 and outputs a pixel data signal U1 representing this pixel data P1 to the level shift unit 124. Meanwhile, while the selection control signal Sd1 indicates logical level 1, the data selector SL1 selects the pixel data P4 supplied from the hold latch Lc1 and outputs a pixel data signal U1 representing this pixel data P4 to the level shift unit 124.

[0082] The hold latch Lc2 of the first MUX unit 123 receives a binary (logical levels 0 and 1) selection control signal Sd2, and captures and holds pixel data P5 at the falling edge of the selection control signal Sd2 while supplying it to the data selector SL2. The data selector SL2 receives the pixel data P2 output from the hold latch L2 and the pixel data P5 supplied from the hold latch Lc2, as well as the selection control signal Sd2. While the selection control signal Sd2 indicates a logical level 0, the data selector SL2 selects the pixel data P2 output from the hold latch L2 and outputs a pixel data signal U2 representing this pixel data P2 to the level shift unit 124. Meanwhile, while the selection control signal Sd2 indicates a logical level 1, the data selector SL2 selects the pixel data P5 supplied from the hold latch Lc2 and outputs a pixel data signal U2 representing this pixel data P5 to the level shift unit 124.

[0083] The hold latch Lc3 of the first MUX unit 123 receives a binary (logical levels 0 and 1) selection control signal Sd3, and captures and holds pixel data P6 at the falling edge of the selection control signal Sd3 while supplying it to the data selector SL3. The data selector SL3 receives the pixel data P3 output from the hold latch L3 and the pixel data P6 supplied from the hold latch Lc3, as well as the selection control signal Sd3. While the selection control signal Sd3 indicates a logical level 0, the data selector SL3 selects the pixel data P3 output from the hold latch L3 and outputs a pixel data signal U3 representing this pixel data P3 to the level shift unit 124. Meanwhile, while the selection control signal Sd3 indicates a logical level 1, the data selector SL3 selects the pixel data P6 supplied from the hold latch Lc3 and outputs a pixel data signal U3 representing this pixel data P6 to the level shift unit 124.

[0084] The level shifters Ls1 to Ls3 of the level shift unit 124 level-shift the signal amplitude of each of the pixel data signals U1 to U3 to the high voltage side and output the resulting signals to the DA conversion unit 125 as high voltage pixel data signals F1 to F3.

[0085] The DA converters Da1 to Da3 of the DA conversion unit 125 convert the high-voltage pixel data signals F1 to F3 into grayscale voltages V1 to V3 having voltage values ​​corresponding to the luminance levels indicated by the signals, and output them to the second MUX unit 126.

[0086] The voltage selector SeLL of the second MUX section 126 receives the above-mentioned three systems of grayscale voltages V1 to V3, and also receives a selection control signal Sv that represents one of three values: "0", "1" or "2".

[0087] While the selection control signal Sv indicates "0", the voltage selector SeLL selects the gradation voltage V1 and outputs it as the gradation voltage signal E1 to the output amplifier unit 127. Meanwhile, while the selection control signal Sv indicates "1", the voltage selector SeLL selects the gradation voltage V2 and outputs it as the gradation voltage signal E1 to the output amplifier unit 127. Meanwhile, while the selection control signal Sv indicates "2", the voltage selector SeLL selects the gradation voltage V3 and outputs it as the gradation voltage signal E1 to the output amplifier unit 127.

[0088] The amplifier Ap1 of the output amplifier section 127 is, for example, an operational amplifier having a voltage follower configuration, and outputs a signal obtained by amplifying the grayscale voltage signal E1 as the drive signal G1.

[0089] FIG. 8 is a time chart showing an example of the internal operation of the circuit block BL1 having the configuration (K=6) shown in FIG.

[0090] First, in response to the load signal LOAD, the hold latches L1 to L6 output pixel data P1 to P6 indicating the luminance levels a1 to a6, respectively, as shown in FIG.

[0091] 8, the control circuit 120 generates a binary selection control signal Sd1 that transitions from logic level 1 to logic level 0 at a predetermined leading time point (first time point) within 1H in response to the load signal LOAD, maintains this logic level 0 state for a predetermined period (e.g., 1H / 2), and then transitions to logic level 1. The control circuit 120 also generates a binary selection control signal Sd2 that transitions from logic level 1 to logic level 0 at a second time point later than the first time point, e.g., 1H / 6, maintains this logic level 0 state for a predetermined period (e.g., 1H / 2), and then transitions to logic level 1. The control circuit 120 also generates a binary selection control signal Sd3 that transitions from logic level 1 to logic level 0 at a third time point later than the second time point, e.g., 1H / 6, maintains this logic level 0 state for a predetermined period (e.g., 1H / 2), and then transitions to logic level 1. Then, the control circuit 120 supplies the generated selection control signals Sd1 to Sd3 to the first MUX unit 123.

[0092] The hold latch Lc1 captures and holds pixel data P4 indicating luminance level a4 at the timing of the falling edge of the selection control signal Sd1, and supplies this to the data selector SL1.

[0093] While the selection control signal Sd1 is at logic level 0, the data selector SL1 selects pixel data P1 from among P1 and P4, and supplies a pixel data signal U1 indicating the luminance level a1 indicated by the pixel data P1 to the level shifter Ls1. On the other hand, while the selection control signal Sd1 is at logic level 1, the data selector SL1 selects pixel data P4, and supplies a pixel data signal U1 indicating the luminance level a4 indicated by the pixel data P4 to the level shifter Ls1.

[0094] The hold latch Lc2 captures and holds pixel data P5 indicating the luminance level a5 at the timing of the falling edge of the selection control signal Sd2, and supplies this to the data selector SL2.

[0095] While the selection control signal Sd2 is at logic level 0, the data selector SL2 selects pixel data P2 from among pixel data P2 and P5, and supplies a pixel data signal U2 indicating the luminance level a2 indicated by the pixel data P2 to the level shifter Ls2. On the other hand, while the selection control signal Sd2 is at logic level 1, the data selector SL2 selects pixel data P5, and supplies a pixel data signal U2 indicating the luminance level a5 indicated by the pixel data P5 to the level shifter Ls2.

[0096] The hold latch Lc3 captures and holds pixel data P6 indicating the luminance level a6 at the timing of the falling edge of the selection control signal Sd3, and supplies this to the data selector SL3.

[0097] While the selection control signal Sd3 is at logic level 0, the data selector SL3 selects pixel data P3 from among pixel data P3 and P6, and supplies a pixel data signal U3 indicating the luminance level a3 indicated by the pixel data P3 to the level shifter Ls3. On the other hand, while the selection control signal Sd3 is at logic level 1, the data selector SL3 selects pixel data P6, and supplies a pixel data signal U3 indicating the luminance level a6 indicated by the pixel data P6 to the level shifter Ls3.

[0098] Here, while the pixel data signal U1 represents the luminance level a1, the level shifter Ls1 and the DA converter Da1 output the gradation voltage V1 having the voltage value Va1 corresponding to the luminance level a1. On the other hand, while the pixel data signal U1 represents the luminance level a4, the level shifter Ls1 and the DA converter Da1 output the gradation voltage V1 having the voltage value Va4 corresponding to the luminance level a4.

[0099] While the pixel data signal U2 represents the luminance level a2, the level shifter Ls2 and the DA converter Da2 output the gradation voltage V2 having the voltage value Va2 corresponding to the luminance level a2. On the other hand, while the pixel data signal U2 represents the luminance level a5, the level shifter Ls2 and the DA converter Da2 output the gradation voltage V2 having the voltage value Va5 corresponding to the luminance level a5.

[0100] While the pixel data signal U3 represents the luminance level a3, the level shifter Ls3 and the DA converter Da3 output the gradation voltage V3 having the voltage value Va3 corresponding to the luminance level a3. On the other hand, while the pixel data signal U3 represents the luminance level a6, the level shifter Ls3 and the DA converter Da3 output the gradation voltage V3 having the voltage value Va6 corresponding to the luminance level a6.

[0101] Here, as shown in FIG. 8, the control circuit 120 supplies the voltage selector SeLL with a selection control signal Sv that sequentially represents "0" in the first section, "1" in the second section, "2" in the third section, "0" in the fourth section, "1" in the fifth section, and "2" in the sixth section, with 1H divided into six sections.

[0102] 8, in the first interval, the voltage selector SeLL and amplifier Ap1 output a drive signal G1 having a voltage value Va1 indicated by the gradation voltage V1 in response to the selection control signal Sv representing "0." In the second interval, the voltage selector SeLL and amplifier Ap1 output a drive signal G1 having a voltage value Va2 indicated by the gradation voltage V2 in response to the selection control signal Sv representing "1." In the third interval, the voltage selector SeLL and amplifier Ap1 output a drive signal G1 having a voltage value Va3 indicated by the gradation voltage V3 in response to the selection control signal Sv representing "2." In the fourth interval, the voltage selector SeLL and amplifier Ap1 output a drive signal G1 having a voltage value Va4 indicated by the gradation voltage V1 in response to the selection control signal Sv representing "0." In the fifth interval, the voltage selector SeLL and amplifier Ap1 output a drive signal G1 having a voltage value Va5 indicated by the gradation voltage V2 in response to the selection control signal Sv representing "1." Then, in the next sixth interval, the voltage selector SeLL and the amplifier Ap1 output the drive signal G1 having the voltage value Va6 indicated by the gradation voltage V3 in response to the selection control signal Sv indicating "2".

[0103] In this way, the circuit block BL1 having the configuration shown in Figure 7 (K=6) generates a drive signal G1 that transmits voltage values ​​Va1 to Va6 corresponding to six pixel data P1 to P6 contained in the video digital signal DVS by time-division multiplexing them within 1H, and outputs this to the display panel 20.

[0104] In this case, according to the configuration shown in FIG. 7, the output delay time of each of the voltage values ​​Va1 to Va6 represented by the drive signal G1 associated with time-division driving is the delay time DEs from the time point at which the value of the selection control signal Sv is switched through the time spent on the operation of the voltage selector SeL and amplifier Ap1, as shown in FIG. 8, thereby enabling high-speed driving.

[0105] Furthermore, in the configuration shown in FIG. 7, when six pixel data P1 to P6 are time-division multiplexed, hold latches Lc1 to Lc3 and data selectors SL1 to SL3 are added, but the number of level shifters and DA converters that are originally required is reduced from six to three (Ls1 to Ls3, Da1 to Da3), respectively.

[0106] Therefore, the overall circuit scale of the data driver 12 is significantly reduced compared to the display driver described in Patent Document 2, and accordingly, current consumption is also significantly reduced. Furthermore, with the configuration shown in Figure 7, the total number of level shifters and the total number of DA converters are both half of the numbers previously required. Therefore, the instantaneous current flowing due to the simultaneous operation of these level shifters and DA converters is also significantly reduced, making it possible to eliminate problems associated with drops in power supply voltage.

[0107] In short, the data driver 12, which is a display driver according to the present invention, may have the following circuit block (e.g., BL1) for driving a display panel (20) including a plurality of data lines (D1 to Dm) and a demultiplexer (DMX) that receives one drive signal (e.g., one of G1 to Gy) corresponding to each of K data lines (e.g., 3, 4, or 6) and sequentially supplies each drive signal to the K data lines one by one. The circuit block receives a plurality of pixel data pieces (P1 to Pm) corresponding to each pixel based on a video signal (DVS), and generates, for each of the K pixel data pieces, a signal that represents, by time-division multiplexing, a voltage value corresponding to the brightness level indicated by each of the K pixel data pieces.

[0108] In this case, the circuit block includes the following first and second multiplexer units, a level shift unit, a digital-to-analog conversion unit, a second multiplexer unit, and an output amplifier unit.

[0109] The first multiplexer unit (123) time-division multiplexes at least one set of pixel data pieces, each consisting of two data pieces, out of the K pixel data pieces, to output first to Qth pixel data signals (e.g., U1 to U3) representing the K pixel data pieces using Q (e.g., an integer equal to or greater than K) signals. The level shift unit (124) level-shifts the amplitude of each of the first to Qth pixel data signals to a higher voltage, thereby generating first to Qth high-voltage pixel data signals (e.g., F1 to F3). The digital-to-analog conversion unit (125) converts the first to Qth high-voltage pixel data signals into first to Qth grayscale voltages (e.g., V1 to V3) having voltage values ​​corresponding to the brightness levels represented by the first to Qth high-voltage pixel data signals. The second multiplexer unit (126) outputs a grayscale voltage signal (E1) that time-division multiplexes and represents voltage values ​​corresponding to each of the K pixel data pieces represented by the first to Qth grayscale voltages for each horizontal scanning period of the video signal. The output amplifier section (127) amplifies the grayscale voltage signal and outputs the amplified signal as the single drive signal.

[0110] According to the display driver of this embodiment, when driving a display panel by time-division driving, it is possible to reduce not only the number of output amplifiers but also the number of level shifters and DA converters relative to the number of data lines of the display panel. As a result, the instantaneous current flowing through the level shifters and DA converters can be reduced, thereby avoiding problems caused by a drop in power supply voltage due to the instantaneous current. Therefore, according to this display driver, it is possible to reduce the circuit scale and current consumption without causing problems. [Explanation of symbols]

[0111] 12 Data Driver 20 Display panel 120 control circuit 122 Data latch section 123 1st MUX section 124 Level shift section 125 DA conversion section 126 2nd MUX section Lc1~Lc3 Hold latch SL, SL1~SL3 data selector SeL, SeLL voltage selector

Claims

1. A display driver for driving a display panel including a plurality of data lines, and a demultiplexer that receives one drive signal corresponding to each of K data lines (K is an integer of 2 or more) of the plurality of data lines, and sequentially supplies the one drive signal to the K data lines one by one for each of the K data lines, a plurality of circuit blocks that receive a plurality of pixel data pieces corresponding to each pixel based on a video signal, and each generate, for each of the K pixel data pieces, a signal that represents, by time division multiplexing, each of voltage values ​​corresponding to a luminance level indicated by each of the K pixel data pieces, as the single drive signal; Each of the plurality of circuit blocks a first multiplexer unit that outputs first to Qth pixel data signals representing the K pixel data pieces via Q (Q is an integer equal to or greater than 2) signal lines, each of which is less than the K pixel data pieces, by time-division multiplexing at least one set of pixel data pieces consisting of two data pieces out of the K pixel data pieces; a level shift unit that generates first to Qth high-voltage pixel data signals by level-shifting the amplitudes of the first to Qth pixel data signals to a high voltage side; a digital-to-analog converter for converting the first to Qth high-voltage pixel data signals into first to Qth grayscale voltages having voltage values ​​corresponding to the luminance levels represented by the first to Qth high-voltage pixel data signals; a second multiplexer unit that outputs a grayscale voltage signal that represents, by time division multiplexing, the voltage values ​​corresponding to each of the K pixel data pieces represented by the first to Qth grayscale voltages for each horizontal scanning period of the video signal; an output amplifier section that amplifies the grayscale voltage signal and outputs the amplified signal as the one drive signal.

2. said K is 3, said Q is 2; the first multiplexer unit generates a second pixel data signal representing a second pixel data piece among the first to third pixel data pieces as the three pixel data pieces; The first multiplexer unit a first hold latch for latching and holding the third piece of pixel data; a data selector that receives the first pixel data piece and the third pixel data piece held in the first hold latch, and outputs a signal representing the first pixel data piece as the first pixel data signal for a predetermined period from a predetermined start point in one horizontal scanning period, and outputs a signal representing the third pixel data piece held in the first hold latch as the first pixel data signal for a subsequent period following the predetermined period, The level shift unit a first level shifter and a second level shifter for generating first and second high-voltage pixel data signals by level-shifting the amplitudes of the first pixel data signal and the second pixel data signal to a high voltage side, respectively; The digital-to-analog conversion unit a first digital-to-analog converter and a second digital-to-analog converter for converting the first high-voltage pixel data signal and the second high-voltage pixel data signal into first and second grayscale voltages, each having a voltage value corresponding to a brightness level represented by the first high-voltage pixel data signal and the second high-voltage pixel data signal; 2. The display driver according to claim 1, wherein the second multiplexer section includes a voltage selector that receives the first and second grayscale voltages, outputs a signal having the first grayscale voltage as the grayscale voltage signal in each of the first and third sections among first to third sections obtained by dividing one horizontal scanning period into three sections, and outputs a signal having the second grayscale voltage as the grayscale voltage signal in the second section.

3. said K is 4, said Q is 2; The first multiplexer unit a first hold latch that latches and holds the third pixel data piece among the first to fourth pixel data pieces as the four pixel data pieces; a second hold latch for latching and holding the fourth piece of pixel data; a first data selector that receives the first pixel data piece and the third pixel data piece held in the first hold latch, and outputs a signal representing the first pixel data piece as the first pixel data signal over a first predetermined period from a predetermined start point in one horizontal scanning period, and outputs a signal representing the third pixel data piece held in the first hold latch as the first pixel data signal during a subsequent period following the first predetermined period; a second data selector that receives the second pixel data piece and the fourth pixel data piece held in the second hold latch, and outputs a signal representing the second pixel data piece as the second pixel data signal over a second predetermined period from a point in time later than the start point in the one horizontal scanning period, and outputs a signal representing the fourth pixel data piece held in the second hold latch as the second pixel data signal during a subsequent period following the second predetermined period, The level shift unit a first level shifter and a second level shifter for generating first and second high-voltage pixel data signals by level-shifting the amplitudes of the first pixel data signal and the second pixel data signal to a high voltage side, respectively; The digital-to-analog conversion unit a first digital-to-analog converter and a second digital-to-analog converter for converting the first high-voltage pixel data signal and the second high-voltage pixel data signal into first and second grayscale voltages having voltage values ​​corresponding to brightness levels represented by the first and second high-voltage pixel data signals, respectively; 2. The display driver according to claim 1, wherein the second multiplexer section includes a voltage selector that receives the first grayscale voltage and the second grayscale voltage, and outputs a signal having the first grayscale voltage as the grayscale voltage signal in each of the first and third sections among first to fourth sections obtained by dividing one horizontal scanning period into four sections, and outputs a signal having the second grayscale voltage as the grayscale voltage signal in each of the second and fourth sections.

4. said K is 6, said Q is 3; The first multiplexer unit a first hold latch that latches and holds the fourth pixel data piece among the first to sixth pixel data pieces as the six pixel data pieces; a second hold latch for latching and holding the fifth piece of pixel data; a third hold latch for latching and holding the sixth piece of pixel data; a first data selector that receives the first pixel data piece and the fourth pixel data piece held in the first hold latch, and outputs a signal representing the first pixel data piece as the first pixel data signal over a first predetermined period from a first predetermined time point within one horizontal scanning period, and outputs a signal representing the fourth pixel data piece held in the first hold latch as the first pixel data signal during a subsequent period following the first predetermined period; a second data selector that receives the second pixel data piece and the fifth pixel data piece held in the second hold latch, and outputs a signal representing the second pixel data piece as the second pixel data signal over a second predetermined period from a second time point that is later than the first time point within the one horizontal scanning period, and outputs a signal representing the fifth pixel data piece held in the second hold latch as the second pixel data signal during a subsequent period following the second predetermined period; a third data selector that receives the third pixel data piece and the sixth pixel data piece held in the third hold latch, and outputs a signal representing the third pixel data piece as the third pixel data signal over a third predetermined period from a third time point that is after the second time point within the one horizontal scanning period, and outputs a signal representing the sixth pixel data piece held in the third hold latch as the third pixel data signal during a subsequent period following the third predetermined period; The level shift unit first to third level shifters for generating first to third high-voltage pixel data signals by level-shifting the amplitudes of the first pixel data signal, the second pixel data signal, and the third pixel data signal to a high voltage side, respectively; The digital-to-analog conversion unit first to third digital-to-analog converters for converting the first to third high-voltage pixel data signals into first to third grayscale voltages having voltage values ​​corresponding to brightness levels represented by the first to third high-voltage pixel data signals, respectively; 2. The display driver according to claim 1, wherein the second multiplexer unit includes a voltage selector that receives the first to third grayscale voltages, outputs a signal having the first grayscale voltage as the grayscale voltage signal in each of the first and fourth intervals among first to sixth intervals obtained by dividing one horizontal scanning period into six intervals, outputs a signal having the second grayscale voltage as the grayscale voltage signal in each of the second and fifth intervals, and outputs a signal having the third grayscale voltage as the grayscale voltage signal in each of the third and sixth intervals.

5. a display panel including a plurality of data lines; and a demultiplexer that receives one drive signal corresponding to each of K (K is an integer of 2 or more) of the plurality of data lines, and sequentially supplies the one drive signal to the K data lines one by one for each of the K data lines; a display driver that drives the display panel, The display driver a plurality of circuit blocks that receive a plurality of pixel data pieces corresponding to each pixel based on a video signal, and each generate, for each of the K pixel data pieces, a signal that represents, by time division multiplexing, each of voltage values ​​corresponding to a luminance level indicated by each of the K pixel data pieces, as the single drive signal; Each of the plurality of circuit blocks a first multiplexer unit that outputs first to Qth pixel data signals representing the K pixel data pieces via Q (Q is an integer equal to or greater than 2) signal lines, each of which is less than the K pixel data pieces, by time-division multiplexing at least one set of pixel data pieces consisting of two data pieces out of the K pixel data pieces; a level shift unit that generates first to Qth high-voltage pixel data signals by level-shifting the amplitudes of the first to Qth pixel data signals to a high voltage side; a digital-to-analog converter for converting the first to Qth high-voltage pixel data signals into first to Qth grayscale voltages having voltage values ​​corresponding to the luminance levels represented by the first to Qth high-voltage pixel data signals; a second multiplexer unit that outputs a grayscale voltage signal that represents, by time division multiplexing, the voltage values ​​corresponding to each of the K pixel data pieces represented by the first to Qth grayscale voltages for each horizontal scanning period of the video signal; an output amplifier section that amplifies the grayscale voltage signal and outputs the amplified signal as the one drive signal.

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