Display driver and display device

Abstract

PURPOSE: To provide a display driver and a display device capable of drastically reducing power consumption.CONSTITUTION: The present invention includes a plurality of circuit blocks each of which receives K pixel data pieces among a plurality of pixel data pieces corresponding to each pixel based on a video signal, generates first to Kth gradation voltages having magnitudes corresponding to luminance indicated by the respective pixel data pieces, and outputs a signal sequentially representing each of the gradation voltages to a display panel as one drive signal. When the first to K-th pixel data pieces represent different luminances, each of the circuit blocks sequentially selects the first to K-th gradation voltages one by one in the horizontal scanning period and outputs one drive signal sequentially having the selected voltage, and when the first to K-th pixel data pieces represent the same luminance, each of the circuit blocks: Only one gradation voltage among the first to Kth gradation voltages is selected over the horizontal scanning period, one drive signal having the one gradation voltage is output, and the generation operation of the other gradation voltages excluding the one gradation voltage among the first to Kth gradation voltages is stopped.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a display driver that drives a display panel in response to a video signal, and a display device. [Background technology]

[0002] A commonly known liquid crystal or organic EL (Electroluminescence) display device has a display panel in which display cells are formed at each intersection of a plurality of scanning lines and a plurality of signal lines (hereinafter referred to as data lines), and a display driver that drives the plurality of data lines of the display panel.

[0003] The display driver includes a latch unit that captures a plurality of pixel data pieces that represent the brightness of each pixel based on a video signal as a digital value, a plurality of level shifters that increase the signal level of each of the captured pixel data pieces, and a plurality of DA (Digital to Analog) converters that convert each of the increased voltage pixel data pieces into gray scale voltages having analog voltage values.Furthermore, the display driver includes a plurality of output amplifiers that respectively amplify the gray scale voltages corresponding to each of the pixel data pieces and supply them to a plurality of data lines of the display panel.

[0004] That is, the display driver is provided with a level shifter, a DA converter, and an output amplifier for driving each data line formed on the display panel.

[0005] In recent years, the resolution of images has been increased in liquid crystal or organic EL display devices mounted on portable information terminals such as smartphones, and this has resulted in an increase in the number of data lines in the display panel.

[0006] Therefore, there has been a problem in that the circuit scale increases by the amount of the increase in the number of data lines (number of channels) that accompanies the trend toward higher definition display panels, resulting in an increase in power consumption.

[0007] To address this issue, a display driver has been proposed in which one output amplifier drives multiple data lines of a display panel one by one in a time-division manner (referred to as time-division driving) (see, for example, Patent Document 1). This allows the number of output amplifiers to be reduced to 1 / n of the total number of channels (n: number of time divisions), thereby reducing the power consumption of the display driver. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-149125

[0009] [overview] However, as mentioned above, according to the display device described in Patent Document 1, although the number of output amplifiers can be reduced, level shifters and DA converters, which consume relatively large amounts of current, are provided for the total number of channels, so it is not possible to significantly reduce power consumption.

[0010] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a display driver and a display device that can significantly reduce power consumption.

[0011] A display driver according to the present invention is a display driver for driving a display panel including a plurality of data lines and a demultiplexer that receives one drive signal corresponding to each of K (K is an integer of 2 or more) of the plurality of data lines and sequentially supplies the one drive signal to the K data lines one by one, and includes a plurality of circuit blocks that each receive K pixel data pieces out of a plurality of pixel data pieces corresponding to each pixel based on a video signal as first to K-th pixel data pieces, generate first to K-th gradation voltages having magnitudes corresponding to the luminance indicated by the respective pixel data pieces, and output a signal having each of the first to K-th gradation voltages in order to the display panel as the one drive signal. Each of the plurality of circuit blocks includes a selector that selects the first to Kth gradation voltages one by one in sequence during a horizontal scanning period of the video signal when the first to Kth pixel data pieces represent different luminances and outputs the one drive signal having the selected gradation voltages in sequence, while selecting only one of the first to Kth gradation voltages over the horizontal scanning period when the first to Kth pixel data pieces represent the same luminance and outputs the one drive signal having this gradation voltage, and a switch circuit that stops the generation of gradation voltages other than the one gradation voltage among the first to Kth gradation voltages when the first to Kth pixel data pieces represent the same luminance.

[0012] A display device according to the present invention comprises a display panel including a plurality of data lines, a demultiplexer that receives one drive signal corresponding to each of K data lines (K is an integer of 2 or more) of the plurality of data lines, and sequentially supplies the one drive signal to the K data lines one by one, and a display driver that drives the display panel based on a video signal, wherein the display drivers each receive K pixel data pieces out of a plurality of pixel data pieces corresponding to each pixel based on the video signal as first to K-th pixel data pieces, generate first to K-th grayscale voltages having magnitudes corresponding to the respective luminances, and drive the display panel using a signal having each of the first to K-th grayscale voltages in order. each of the plurality of circuit blocks includes a selector that selects the first to Kth gradation voltages one by one in sequence during a horizontal scanning period of the video signal when the first to Kth pixel data pieces represent different luminances and outputs the one drive signal having the selected gradation voltages in sequence, and that selects only one of the first to Kth gradation voltages over the horizontal scanning period when the first to Kth pixel data pieces represent the same luminance and outputs the one drive signal having this selected gradation voltage; and a switch circuit that stops the generation of gradation voltages other than the one gradation voltage among the first to Kth gradation voltages when the first to Kth pixel data pieces represent the same luminance. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a block diagram showing a schematic configuration of a display device 100 including a display driver according to the present invention. [Figure 2] 2 is a block diagram showing an internal configuration of a data driver 12_1 as a first embodiment of the data driver 12. FIG. [Figure 3] FIG. 2 is a block diagram showing the internal configuration of a circuit block BLK_1. [Figure 4] FIG. 10 is a circuit diagram showing the internal configuration of a comparison circuit 1230. [Figure 5] 10 is a time chart showing the operation of the circuit block BLK_1 when P(N)≠P(N+3). [Figure 6A] FIG. 10 is a circuit diagram illustrating a signal path in a circuit block BLK_1 in a first divided period when P(N)≠P(N+3). [Figure 6B] FIG. 10 is a circuit diagram illustrating a signal path in the circuit block BLK_1 in a second divided period when P(N)≠P(N+3). [Figure 7] 10 is a time chart showing the operation of the circuit block BLK_1 when P(N)=P(N+3). [Figure 8A] FIG. 10 is a circuit diagram illustrating a signal path in the circuit block BLK_1 in the first divided period when P(N)=P(N+3). [Figure 8B] FIG. 10 is a circuit diagram illustrating a signal path in the circuit block BLK_1 in a second divided period when P(N)=P(N+3). [Figure 9] FIG. 10 is a block diagram showing an internal configuration of a data driver 12_2 as a second embodiment of the data driver 12. [Figure 10] FIG. 2 is a block diagram showing the internal configuration of a circuit block BLK_2. [Figure 11] FIG. 10 is a circuit diagram showing the internal configuration of a comparison circuit 1230a. [Figure 12] 10 is a time chart showing the operation of the circuit block BLK_2 when P(N)≠P(N+3) or P(N+3)≠P(N+6). [Figure 13A] FIG. 10 is a circuit diagram showing a signal path in the circuit block BLK_2 in the first divided period when P(N)≠P(N+3) or P(N+3)≠P(N+6). [Figure 13B] FIG. 10 is a circuit diagram showing a signal path in the circuit block BLK_2 in the second divided period when P(N)≠P(N+3) or P(N+3)≠P(N+6). [Figure 13C] FIG. 10 is a circuit diagram showing a signal path in the circuit block BLK_2 in the third divided period when P(N)≠P(N+3) or P(N+3)≠P(N+6). [Figure 14] 10 is a time chart showing the operation of the circuit block BLK_2 when P(N)=P(N+3)=P(N+6). [Figure 15A]FIG. 10 is a circuit diagram showing a signal path in the circuit block BLK_2 in the first divided period when P(N)=P(N+3)=P(N+6). [Figure 15B] FIG. 10 is a circuit diagram showing a signal path in the circuit block BLK_2 in the second divided period when P(N)=P(N+3)=P(N+6). [Figure 15C] FIG. 10 is a circuit diagram showing a signal path in the circuit block BLK_2 in the third divided period when P(N)=P(N+3)=P(N+6). [Figure 16] FIG. 10 is a block diagram showing an internal configuration of a data driver 12_3 as a third embodiment of the data driver 12. [Figure 17] 10 is a time chart showing an example of pixel data series PDa and PDb, in which first to twelfth pixel data PD1 to PD12 are extracted from a series of pixel data PD1 to PDm. [Figure 18] 10 is a block diagram showing the internal configuration of a circuit block BLK_3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Example 1

[0014] FIG. 1 is a block diagram showing a schematic configuration of a display device 100 including a display driver according to the present invention.

[0015] As shown in FIG. 1, the display device 100 includes a display control unit 10, a gate driver 11, a data driver 12, and a display panel 20.

[0016] The display panel 20 is, for example, a time-division driven liquid crystal or organic EL display panel, which is provided with gate lines GL1 to GLr (r is an integer of 2 or more) extending in the horizontal direction of the two-dimensional screen, data lines DL1 to DLm (m is an integer of 2 or more) extending in the vertical direction of the two-dimensional screen, and a demultiplexer 200. In the area (encircled area) where the gate lines and data lines included in the display panel 20 intersect, display cells for each color component required for color display are formed, such as a red display cell Pr for displaying red, a green display cell Pg for displaying green, and a blue display cell Pb for displaying blue.

[0017] 1, one color pixel is formed by a cell group PX consisting of three adjacent display cells (Pr, Pg, Pb) on each of the gate lines GL1 to GLr. Therefore, as shown in Fig. 1, a red display cell Pr is arranged on each of the (3n-2)th (n is an integer of 1 or more) data lines DL1, 4, 7, ..., a green display cell Pg is arranged on each of the (3n-1)th data lines DL2, 5, 8, ..., and a blue display cell Pb is arranged on each of the (3n)th data lines DL3, 6, 9, ....

[0018] The demultiplexer 200 receives the drive signals G1 to Gy together with a plurality of channel selection signals CH for time-division drive control output from the data driver 12. Note that "y" represents y=m / K m: total number of data lines K: Number of divisions for time-division drive (an integer of 2 or more) is a positive integer expressed as

[0019] The demultiplexer 200 includes y channel selectors CSEL, each of which receives the above-mentioned drive signals G1 to Gy individually and is connected to K data lines among the data lines DL1 to DLm.

[0020] Each of the channel selectors CSEL selects one data line from among the K data lines connected to itself for each divided period obtained by dividing each horizontal scanning period into K periods in response to a channel selection signal CH, and supplies the drive signal received by itself to that one data line.

[0021] The display control unit 10 receives a video signal VS that includes a horizontal synchronization signal and represents the brightness of each pixel. Based on the video signal VS, the display control unit 10 generates a digital video signal DVS that includes a start pulse STA consisting of a single pulse, a clock signal CLK, various control signals such as vertical and horizontal synchronization signals, and a series of pixel data pieces that represent the brightness of each pixel in, for example, 8 bits, and supplies this to the data driver 12.

[0022] Furthermore, the display control unit 10 generates timing signals indicating the timing for selecting each gate line in accordance with the horizontal synchronization signal included in the video signal VS, and supplies these to the gate driver 11.

[0023] The gate driver 11 generates gate pulses in response to timing signals supplied from the display control unit 10, and applies these to the gate lines GL1 to GLr of the display panel 20 one by one in sequence.

[0024] Based on the digital video signal DVS, the data driver 12 converts each of the pixel data pieces included in the digital video signal DVS into an analog voltage value, and generates the resultant signals as a group of drive signals by amplifying each of the analog voltage values ​​individually.

[0025] Furthermore, the data driver 12 generates a plurality of channel selection signals CH, each representing a binary value (0 or 1), as signals for selecting a group of data lines to which y drive signals are supplied for each of K divided periods obtained by dividing each horizontal scanning period.

[0026] The data driver 12 then outputs the y drive signals generated as described above to the display panel 20 as drive signals G1 to Gy, together with the generated channel selection signal CH.

[0027] In this way, the data driver 12 is a time-division driving type driver that drives all the data lines DL1 to DLm of the display panel 20 in a time-division manner using the drive signals G1 to Gy(m / K).

[0028] FIG. 2 is a block diagram showing an example of the internal configuration of a data driver 12_1 as the data driver 12, in which the division number K of the time-division driving is "2".

[0029] As shown in FIG. 2, the data driver 12_1 includes a control circuit 120, a shift register 121, a data latch unit 122, a data switch unit 123, a level shift unit 124, a DA conversion unit 125, a selector unit 126, and an output amplifier unit 127.

[0030] The control circuit 120 receives the digital video signal DVS, extracts the horizontal synchronization signal, start pulse STA, and clock signal CLK contained in the digital video signal DVS, and supplies the start pulse STA and the clock signal CLK to a shift register 121 in synchronization with the horizontal synchronization signal.

[0031] Furthermore, the control circuit 120 converts each of the pixel data pieces included in the video digital signal DVS into pixel data PD, and supplies a series of this pixel data PD to the data latch unit 122 together with the clock signal CLK.

[0032] In addition, the control circuit 120 generates binary (0 or 1) channel selection signals CHa and CHb for each divided period into two (K=2) periods obtained by dividing each horizontal scanning period, and outputs these to the demultiplexer 200 of the display panel 20. The channel selection signals CHa and CHb each have a value of 0 or 1 and select a group of data lines to which y (y=m / 2) groups of drive signals are output.

[0033] Furthermore, in response to this horizontal synchronization signal, the control circuit 120 generates a binary (0 or 1) data selection control signal SC for selecting y (y=m / 2) grayscale voltages from among m grayscale voltages (described later) for each of the above-mentioned divided periods, and supplies the signal to the selector unit 126. For example, the control circuit 120 supplies the selector unit 126 with a data selection control signal SC having a logical value of 0 in a first divided period obtained by dividing the horizontal scanning period into two, and a logical value of 1 in a second divided period following the first divided period.

[0034] When the shift register 121 receives a start pulse STA, it shifts it in sequence in accordance with the timing of the clock signal CLK to generate load signals L1 to Lm that cause each of the m pixel data pieces to be loaded in sequence at different timings. The shift register 121 supplies the load signals L1 to Lm to the data latch unit 122.

[0035] The data latch unit 122 holds m pieces of pixel data PD in the sequence of pixel data PD supplied from the control circuit 120 by sequentially latching the m pieces of pixel data PD at the timing of each of the load signals L1 to Lm. Then, the data latch unit 122 supplies pixel data signals P1 to Pm representing the held m pieces of pixel data PD to the data switch unit 123.

[0036] The data switch unit 123 determines, for each pair of pixel data signals P1 to Pm corresponding to display cells of the same color that are adjacent in the horizontal direction of the screen, whether the pair of pixel data signals represent the same luminance. For example, the data switch unit 123 determines whether the pixel data signal P1 corresponding to a red display cell Pr and the pixel data signal P4 corresponding to the adjacent red display cell Pr represent the same luminance. Furthermore, for example, the data switch unit 123 determines whether the pixel data signal P2 corresponding to a green display cell Pg and the pixel data signal P5 corresponding to the adjacent green display cell Pg represent the same luminance, and whether the pixel data signal P3 corresponding to a blue display cell Pb and the pixel data signal P6 corresponding to the blue display cell Pb represent the same luminance.

[0037] Here, if the result of the determination made on the pixel data signals P1 to Pm between a pair of pixel data signals indicates that they are not all the same luminance, that is, that they have different luminances, the data switch unit 123 supplies the pixel data signals P1 to Pm as is to the level shift unit 124. However, if there is a pair of pixel data signals among the pixel data signals P1 to Pm that have the same luminance, the data switch unit 123 blocks the supply of one of the pair of pixel data signals to the level shift unit 124. For example, if pixel data signals P1 and P4 represent different luminances and pixel data signals P2 and P5 represent different luminances, but pixel data signals P3 and P6 represent the same luminance, the data switch unit 123 supplies the pixel data signals P1 to P5 to the level shift unit 124, but does not supply the pixel data signal P6 to the level shift unit 124.

[0038] Furthermore, for each pair of pixel data signals corresponding to the same adjacent display color, the data switch unit 123 generates a comparison result signal that indicates, with a binary value (0 or 1), whether or not the pixel data signals represent the same luminance. The data switch unit 123 supplies this comparison result signal to the level shift unit 124.

[0039] The level shift unit 124 level-shifts the signal amplitude of each of the pixel data signals P1 to Pm supplied from the data switch unit 123 to the high-voltage side, and outputs the resultant signals as high-voltage pixel data signals F1 to Fm to the DA conversion unit 125. Furthermore, the level shift unit 124 level-shifts the signal amplitude of the comparison result signal supplied from the data switch unit 123 to the high-voltage side, and supplies the resultant signals to the selector unit 126.

[0040] The DA conversion unit 125 converts each of the high-voltage pixel data signals F1 to Fm into grayscale voltages V1 to Vm having voltage values ​​corresponding to the luminance represented by each of the signals, and outputs the voltages to the selector unit 126.

[0041] The selector unit 126 includes y voltage selectors (described later), each of which receives a data selection control signal SC. Each of the y voltage selectors receives at its first input terminal one of a first group of gradation voltages consisting of y (y=m / 2) gradation voltages obtained by dividing the gradation voltages V1 to Vm into two, and receives at its second input terminal one of a second group of gradation voltages consisting of the remaining y gradation voltages. The selector unit 126 performs a selection process using the y voltage selectors to select one of the first and second groups of gradation voltages in accordance with the data selection control signal SC in each of the first and second divided periods obtained by dividing the horizontal scanning period into two, as follows: When the comparison result signal indicates a logical value of 1, the y voltage selectors select the first group of gradation voltages in the initial first divided period, and supply the y gradation voltages included in the first group of gradation voltages to the output amplifier unit 127 as gradation voltage signals E1 to Ey. Then, in a second division period following the first division period, the y voltage selectors are switched to a state in which they select the second gradation voltage group described above, and the y gradation voltages included in the second gradation voltage group are supplied to the output amplifier section 127 as gradation voltage signals E1 to Ey.

[0042] However, when a comparison result signal representing a logical value 0 is received, the voltage selector corresponding to the comparison result signal representing the logical value 0, i.e., the voltage selector that has received a pair of pixel data signals representing the same luminance, maintains the state of selecting the first gradation voltage group over the first and second division periods.

[0043] The output amplifier section 127 receives the grayscale voltage signals E1 to Ey supplied from the selector section 126, and amplifies each of them individually to generate the above-mentioned drive signals G1 to Gy, which are output to the display panel 20.

[0044] Here, the data driver 12_1 has y output channels corresponding to the drive signals G1 to Gy, respectively. The data driver 12_1 has a data latch unit 122, a data switch unit 123, a level shift unit 124, a DA conversion unit 125, a selector unit 126, and an output amplifier unit 127, each of which has the same internal configuration for each of the three output channels.

[0045] Therefore, by extracting the circuit block BL1_1 that is responsible for three output channels and is divided into areas surrounded by dashed lines as shown in FIG. 2, the internal configurations of the above-mentioned data latch unit 122, data switch unit 123, level shift unit 124, DA conversion unit 125, selector unit 126, and output amplifier unit 127 will be described in detail.

[0046] FIG. 3 is a block diagram showing the internal configuration of the circuit block BLK_1.

[0047] 3, the circuit block BLK_1 has latches 1221 and 1222 included in the data latch unit 122, and a comparison circuit 1230 and a switch 1232 included in the data switch unit 123. The circuit block BLK_1 also has level shifters (LSF) 1240 to 1242 included in the level shift unit 124, and DA converters (DAC) 1251 and 1252 included in the DA conversion unit 125. The circuit block BLK_1 also has a gate circuit 1260 and a voltage selector 1261 included in the selector unit 126, and an amplifier 1270 included in the output amplifier unit 127.

[0048] The data latch unit 122 includes m latches that individually capture the pixel data signals P1 to Pm. The latch 1221 is the Nth (N is an integer greater than or equal to 2) latch in the circuit block BLK_1, and captures and holds the Nth pixel data signal P(N) of the pixel data signals P1 to Pm at the timing of the clock signal CLK in response to the load signal L(N), and supplies this to the data switch unit 123 and the level shift unit 124. The latch 1222 is the (N+3)th latch in the circuit block BLK_1, and captures and holds the (N+3)th pixel data signal P(N+3) of the pixel data signals P1 to Pm at the timing of the clock signal CLK in response to the load signal L(N+3), and supplies this to the data switch unit 123.

[0049] The comparison circuit 1230 of the data switch unit 123 receives and compares the pixel data signals P(N) and P(N+3) to determine whether the pixel data signals P(N) and P(N+3) represent the same luminance or different luminances. In this case, the comparison circuit 1230 supplies a binary comparison result signal DM to the switch 1232 and the level shift unit 124. The binary comparison result signal DM indicates a logical value of 0 if the pixel data signals P(N) and P(N+3) represent the same luminance, and a logical value of 1 if the pixel data signals P(N) and P(N+3) represent different luminances.

[0050] FIG. 4 is a circuit diagram showing an example of the internal configuration of the comparison circuit 1230 when each of the pixel data signals P1 to Pm is digital data that represents luminance in 8 bits.

[0051] As shown in Figure 4, the comparison circuit 1230 receives 8-bit pixel data signals P(N)_[0] to P(N)_[7], each consisting of bits [0] to [7], and pixel data signals P(N+3)_[0] to P(N+3)_[7].

[0052] The comparison circuit 1230 includes non-exclusive OR circuits EX0 to EX7 that receive the pixel data signals P(N)_[0] to P(N)_[7] and the pixel data signals P(N+3)_[0] to P(N+3)_[7] at the same bit digits, and a NAND circuit AN1. The NAND circuit AN1 outputs a comparison result signal DM with a logical value of 0 when the output results of the non-exclusive OR circuits EX0 to EX7 are all logical 1, and with a logical value of 1 when at least one of the output results of the non-exclusive OR circuits EX0 to EX7 is logical 0.

[0053] When the comparison result signal DM is a logical value 1, that is, when the pixel data signals P(N) and P(N+3) represent different luminances, the switch 1232 is turned on and supplies the pixel data signal P(N+3) supplied from the latch 1222 to the level shift unit 124. On the other hand, when the comparison result signal DM is a logical value 0, that is, when the pixel data signals P(N) and P(N+3) represent the same luminance, the switch 1232 is turned off. In other words, at this time, the switch 1232 stops supplying the pixel data signal P(N+3) to the level shift unit 124.

[0054] The level shifter 1240 of the level shift unit 124 generates a high-voltage comparison result signal DMs by level-shifting the signal amplitude of the comparison result signal DM to the high-voltage side, and supplies this to the selector unit 126 .

[0055] The level shifter 1241 of the level shift unit 124 level-shifts the signal amplitude of the pixel data signal P(N) to a higher voltage and supplies the resultant signal to the DA conversion unit 125 as a high-voltage pixel data signal F(N). When the switch 1232 supplies a pixel data signal P(N+3), the level shifter 1242 of the level shift unit 124 level-shifts the signal amplitude of the pixel data signal P(N+3) to a higher voltage and supplies the resultant signal to the DA conversion unit 125 as a high-voltage pixel data signal F(N+3). However, the level shifter 1242 does not operate unless it receives the pixel data signal P(N+3) from the switch 1232. Therefore, at this time, the level shifter 1242 does not generate the high-voltage pixel data signal F(N+3) based on the pixel data signal P(N+3), and therefore the high-voltage pixel data signal F(N+3) is not supplied to the DA conversion unit 125.

[0056] The DA converter 1251 of the DA conversion unit 125 receives the high-voltage pixel data signal F(N) and converts it into a voltage having a voltage value corresponding to the luminance indicated by the high-voltage pixel data signal F(N). The DA converter 1251 then supplies this voltage to the selector unit 126 as a gradation voltage V(N). When the DA converter 1252 of the DA conversion unit 125 receives the high-voltage pixel data signal F(N+3) from the level shifter 1242, it converts this signal into a voltage having a voltage value corresponding to the luminance indicated by the high-voltage pixel data signal F(N+3). The DA converter 1252 then supplies this voltage to the selector unit 126 as a gradation voltage V(N+3).

[0057] The gate circuit 1260 of the selector unit 126 receives the high-voltage comparison result signal DMs supplied from the level shift unit 124 and the data selection control signal SC supplied from the control circuit 120. When the high-voltage comparison result signal DMs has a logical value of 0, indicating that the pixel data signals P(N) and P(N+3) both represent the same luminance, the gate circuit 1260 supplies a selection signal CSW of logical value 0 to the voltage selector 1261, which causes the selection signal to select the gradation voltage V(N). When the high-voltage comparison result signal DMs has a logical value of 1, that is, when the pixel data signals P(N) and P(N+3) represent different luminances, the gate circuit 1260 supplies a selection signal CSW having the logical value of the data selection control signal SC to the voltage selector 1261. As described above, the data selection control signal SC is a binary signal that has a logical value of 0 in the first divided period obtained by dividing the horizontal scanning period into two and a logical value of 1 in the second divided period.

[0058] The voltage selector 1261 receives the grayscale voltage V(N) supplied from the DA converter 1251 at a first input terminal thereof, and receives the grayscale voltage V(N+3) supplied from the DA converter 1252 at a second input terminal thereof. The voltage selector 1261 selects one of the grayscale voltages V(N) and V(N+3) based on the selection signal CSW. For example, the voltage selector 1261 selects the grayscale voltage V(N) when the selection signal CSW indicates a logical value of 0, and selects the grayscale voltage V(N+3) when the selection signal CSW indicates a logical value of 1. The voltage selector 1261 then supplies a signal having the selected grayscale voltage V(N) or V(N+3) to the output amplifier unit 127 as a grayscale voltage signal E(N).

[0059] The amplifier 1270 of the output amplifier unit 127 is, for example, a voltage follower operational amplifier that receives at its non-inverting input terminal the grayscale voltage signal E(N) supplied from the voltage selector 1261. The amplifier 1270 amplifies the grayscale voltage signal E(N) to generate a drive signal G(N), which is output from the external terminal TM of the data driver 12_1 to the display panel 20.

[0060] At this time, in the display panel 20, the channel selector CSEL that receives the drive signal G(N) supplies the drive signal G(N) to the data line DL(N) selected by the channel selection signal CHa in the first division period, and to the data line DL(N+3) selected by the channel selection signal CHb in the second division period.

[0061] Below, we will explain the operations of the switch 1232, voltage selector 1261, and channel selector CSEL shown in Figure 3, and the signal flow within the circuit block BLK_1, dividing into cases where the pixel data signals P(N) and P(N+3) represent the same luminance and where they represent different luminances. [When P(N)≠P(N+3)] FIG. 5 is a time chart showing the operation of the switch 1232, the voltage selector 1261, and the channel selector CSEL within a horizontal scanning period (also referred to as 1H) when the pixel data signals P(N) and P(N+3) represent different luminances.

[0062] Also, Figure 6A is a circuit diagram showing, with thick solid lines, the flow of signals within circuit block BLK_1 during the first division period of the first and second division periods obtained by dividing 1H into two, and Figure 6B is a circuit diagram showing, with thick solid lines, the flow of signals within circuit block BLK_1 during the second division period.

[0063] In this way, when the pixel data signals P(N) and P(N+3) represent different luminance values, the switch 1232 is in the on state for 1H, as shown in Fig. 5. Therefore, the gradation voltage V(N) based on the pixel data signal P(N) output from the latch 1221 is supplied to a first input terminal of the voltage selector 1261 via a path A indicated by a thick solid line in Fig. 6A. Furthermore, the gradation voltage V(N+3) based on the pixel data signal P(N+3) output from the latch 1222 is supplied to a second input terminal of the voltage selector 1261 via a path B indicated by a thick solid line in Fig. 6A.

[0064] 5, during a first divisional period within 1H, the voltage selector 1261 selects path A from paths A and B. Therefore, during this first divisional period, a drive signal G(N) having a gradation voltage V(N) is output from the external terminal TM to the display panel 20 via path A shown by a thick solid line in FIG. 6A and the voltage selector 1261. At this time, the channel selector CSEL that has received the drive signal G(N) within the display panel 20 supplies the drive signal G(N) having the gradation voltage V(N) to the data line DL(N), as shown by a thick solid line in FIG. 6A, while receiving a channel selection signal CHa with a logical value of 1 during the first divisional period.

[0065] Then, in a second divisional period following the first divisional period, as shown in Fig. 5, the voltage selector 1261 selects path B from paths A and B. Therefore, in the second divisional period, a drive signal G(N) having a gradation voltage V(N+3) is output from the external terminal TM to the display panel 20 via path B shown by a thick solid line in Fig. 6B and the voltage selector 1261. At this time, the channel selector CSEL that has received the drive signal G(N) in the display panel 20 supplies the drive signal G(N) having the gradation voltage V(N+3) to the data line DL(N+3), as shown by a thick solid line in Fig. 6B, while receiving a channel selection signal CHb with a logic value of 1 in the second divisional period, as shown in Fig. 5. [When P(N)=P(N+3)] FIG. 7 is a time chart showing the operations of the switch 1232, the voltage selector 1261, and the channel selector CSEL within 1H when the pixel data signals P(N) and P(N+3) represent the same luminance.

[0066] Also, Figure 8A is a circuit diagram showing, with thick solid lines, the flow of signals within circuit block BLK_1 during the first division period of the first and second division periods obtained by dividing 1H into two, and Figure 8B is a circuit diagram showing, with thick solid lines, the flow of signals within circuit block BLK_1 during the second division period.

[0067] When the pixel data signals P(N) and P(N+3) represent the same luminance, the switch 1232 is turned off for 1H, and the voltage selector 1261 is fixed to a state in which it selects path A, as shown in FIG. 7. Therefore, the gradation voltage V(N) based on the pixel data signal P(N) output from the latch 1221 is supplied to the first input terminal of the voltage selector 1261 via path A indicated by a thick solid line in FIG. 8A during the first divisional period. Here, as shown in FIG. 7, the voltage selector 1261 selects path A for 1H, and therefore, during the first divisional period, the drive signal G(N) having the gradation voltage V(N) is output from the external terminal TM to the display panel 20 via path A indicated by a thick solid line in FIG. 8A and the voltage selector 1261. At this time, the channel selector CSEL that receives the drive signal G(N) in the display panel 20 supplies the drive signal G(N) having the gradation voltage V(N) to the data line DL(N) as shown by the thick solid line in FIG. 8A while receiving the channel selection signal CHa with a logical value of 1 in the first division period, as shown in FIG. 7.

[0068] 7, the voltage selector 1261 also selects path A. Therefore, as shown by the thick solid line in Fig. 8B, a drive signal G(N) having a gradation voltage V(N) is output from the external terminal TM to the display panel 20 via path A and the voltage selector 1261. At this time, the channel selector CSEL that has received the drive signal G(N) in the display panel 20 supplies the drive signal G(N) having the gradation voltage V(N) to the data line DL(N+3) as shown by the thick solid line in Fig. 8B while it is receiving a channel selection signal CHb with a logical value of 1 in the second divisional period.

[0069] Here, as described above, when the pixel data signals P(N) and P(N+3) represent the same luminance, the switch 1232 is in the OFF state for 1H, as shown in FIGS. 7, 8A, and 8B.

[0070] As a result, the pixel data signal P(N+3) output from the latch 1222 is stopped at the switch 1232 for 1H and is not supplied to the level shifter 1242 and the DA converter 1252, causing the level shifter 1242 and the DA converter 1252 to stop operating.

[0071] In other words, when the pixel data signals P(N) and P(N+3) represent the same luminance, the voltage selector 1261 selects the gradation voltage V(N) from the gradation voltages V(N) and V(N+3) and outputs the drive signal G(N) having this gradation voltage V(N). Furthermore, at this time, the switch 1232 is turned off to cut off the supply of the pixel data signal P(N+3), which is responsible for generating the gradation voltage V(N+3), to the level shifter 1242, thereby stopping the generation of the gradation voltage V(N+3) by the level shifter 1242 and the DA converter 1252.

[0072] Generally, in a display device that displays an image based on a video signal, adjacent pixels in the horizontal direction of a two-dimensional screen often have the same brightness, so the operation of the voltage selector 1261 and switch 1232 described above can significantly reduce power consumption.

[0073] In the above embodiment, the configuration and operation of the data driver 12 are explained using the data driver 12_1, which has a time-division driving division number K=2, as an example. However, the power consumption can be similarly reduced even when the division number K=3. Example 2

[0074] FIG. 9 is a block diagram showing an example of the internal configuration of a data driver 12_2, which is the data driver 12 and has the division number K=3 for time-division driving.

[0075] The data driver 12_2 has the same configuration as that shown in FIG. 2 except that it employs a control circuit 120a instead of the control circuit 120 shown in FIG. 2 and employs a data switch unit 123a instead of the data switch unit 123.

[0076] The control circuit 120a receives the digital video signal DVS, extracts the horizontal synchronization signal, start pulse STA, and clock signal CLK contained in the digital video signal DVS, and supplies the start pulse STA and the clock signal CLK to the shift register 121 in synchronization with the horizontal synchronization signal.

[0077] Furthermore, the control circuit 120a converts each of the pixel data pieces included in the video digital signal DVS into pixel data PD, and supplies a series of this pixel data PD to the data latch unit 122 together with the clock signal CLK.

[0078] In addition, in response to the horizontal synchronization signal, the control circuit 120a generates channel selection signals CHa, CHb, and CHc, each of which is binary (0 or 1) for selecting a group of data lines to which y (y=m / 3) groups of drive signals are output, for each of the three (K=3) divided periods into which the horizontal scanning period is divided, and outputs these to the demultiplexer 200 of the display panel 20.

[0079] Furthermore, the control circuit 120a generates a binary (0 or 1) data selection control signal SCa for selecting y (y=m / 3) grayscale voltages from among m grayscale voltages (described later) for each of the above-mentioned divided periods in response to the horizontal synchronization signal, and supplies the signal to the selector unit 126. For example, the control circuit 120 supplies the selector unit 126 with a data selection control signal SCa that represents a logical value of 0 in a first divided period obtained by dividing a horizontal scanning period into three, a logical value of 1 in a second divided period following the first divided period, and a logical value of 0 in a third divided period following the second divided period.

[0080] Incidentally, in the data driver 12_2, in the y output channels that output the drive signals G1 to Gy, the data latch unit 122, the data switch unit 123a, the level shift unit 124, the DA conversion unit 125, the selector unit 126, and the output amplifier unit 127 have the same internal configuration for every three output channels.

[0081] Therefore, by extracting the circuit block BLK_2 that is responsible for three output channels and is divided into areas surrounded by dashed lines as shown in FIG. 9, the internal configurations of the data latch unit 122, data switch unit 123a, level shift unit 124, DA conversion unit 125, selector unit 126, and output amplifier unit 127 will be described in detail.

[0082] FIG. 10 is a block diagram showing the internal configuration of the circuit block BLK_2.

[0083] 10, the circuit block BLK_2 has three latches 1221, 1222, and 1223 included in the data latch unit 122, and a comparison circuit 1230a and a switch circuit 1235 included in the data switch unit 123a. The circuit block BLK_2 also has level shifters (LSF) 1240 to 1242 included in the level shift unit 124, and DA converters (DAC) 1251 and 1252 included in the DA conversion unit 125. The circuit block BLK_1 also has a gate circuit 1260 and a voltage selector 1261 included in the selector unit 126, and an amplifier 1270 included in the output amplifier unit 127.

[0084] Latch 1221 of data latch unit 122 is the Nth latch in circuit block BLK_2, and in response to load signal L(N), acquires and holds the Nth pixel data signal P(N) of pixel data signals P1 to Pm at the timing of clock signal CLK, and supplies this to data switch unit 123a. Latch 1222 is the (N+3)th latch in circuit block BLK_2, and in response to load signal L(N+3), acquires and holds the (N+3)th pixel data signal P(N+3) of pixel data signals P1 to Pm at the timing of clock signal CLK, and supplies this to data switch unit 123a. Latch 1223 is the (N+6)th latch in circuit block BLK_2, and in response to load signal L(N+6), acquires and holds the (N+6)th pixel data signal P(N+6) of pixel data signals P1 to Pm at the timing of clock signal CLK, and supplies this to data switch unit 123a.

[0085] The comparison circuit 1230a of the data switch unit 123a receives and compares the pixel data signals P(N), P(N+3), and P(N+6) to determine whether the pixel data signals P(N), P(N+3), and P(N+6) all represent the same luminance or different luminances.

[0086] The comparison circuit 1230a generates a binary comparison result signal DMa that indicates a logical value of 0 when the pixel data signals P(N), P(N+3), and P(N+6) all represent the same luminance, and a logical value of 1 when P(N) and P(N+3) represent different luminances or when P(N+3) and P(N+6) represent different luminances. The comparison circuit 1230a supplies the comparison result signal DMa to the switch circuit 1235 and the level shift unit 124.

[0087] FIG. 11 is a circuit diagram showing an example of the internal configuration of the comparison circuit 1230a.

[0088] As shown in Figure 11, the comparison circuit 1230a receives pixel data signals P(N)_[0] to P(N)_[7], pixel data signals P(N+3)_[0] to P(N+3)_[7], and pixel data signals P(N+6)_[0] to P(N+6)_[7], each consisting of 8 bits from bit [0] to bit [7].

[0089] The comparison circuit 1230a includes 2-to-1 selectors S0 to S7, non-exclusive OR circuits EX0 to EX7, and a NAND circuit AN1.

[0090] As shown in Fig. 11, each of the 2-to-1 selectors S0 to S7 receives pixel data signals P(N)_[0] to P(N)_[7] and pixel data signals P(N+6)_[0] to P(N+6)_[7] with the same bit digits. The 2-to-1 selectors S0 to S7 selectively supply one of the pixel data signals P(N)_[0] to P(N)_[7] and the pixel data signals P(N+6)_[0] to P(N+6)_[7] to a first input terminal of each of the non-exclusive OR circuits EX0 to EX7. Note that, as shown in Fig. 11, the non-exclusive OR circuits EX0 to EX7 individually receive the pixel data signals P(N+6)_[0] to P(N+6)_[7] at their second input terminals. The NAND circuit AN1 supplies a comparison result signal DMa to the switch circuit 1235 with a logical value of 0 when the output results of each of the non-exclusive OR circuits EX0 to EX7 are all logical value 1, and with a logical value of 1 when at least one of the output results of each of the non-exclusive OR circuits EX0 to EX7 is logical value 0.

[0091] The switch circuit 1235 includes a switch 1232 and a data selector 1237 .

[0092] When the comparison result signal DMa is a logical value 1, that is, when at least one of the pixel data signals P(N), P(N+3), and P(N+6) represents a luminance different from that of the other two, the switch 1232 is turned on and supplies the pixel data signal P(N+3) supplied from the latch 1222 to the level shift unit 124. On the other hand, when the comparison result signal DMa is a logical value 0, that is, when the pixel data signals P(N), P(N+3), and P(N+6) all represent the same luminance, the switch 1232 is turned off. In other words, at this time, the switch 1232 stops supplying the pixel data signal P(N+3) to the level shift unit 124.

[0093] The data selector 1237 receives the comparison result signal DMa, pixel data signals P(N), and P(N+6), as well as a data selection control signal SCa supplied from the control circuit 120a. While the comparison result signal DMa indicates a logical value of 1, the data selector 1237 selects one of the pixel data signals P(N) and P(N+6) in accordance with the data selection control signal SCa. For example, the data selector 1237 selects the pixel data signal P(N) when the data selection control signal SCa indicates a logical value of 0, and selects the pixel data signal P(N+6) when the data selection control signal SCa indicates a logical value of 1. The data selector 1237 then supplies the selected pixel data signal P(N) or (N+6) to the level shift unit 124. However, when the comparison result signal DMa represents a logical value of 0, that is, when the pixel data signals P(N), P(N+3), and P(N+6) all represent the same luminance, the data selector 1237 selects the pixel data signal P(N) and supplies it to the level shift unit 124 regardless of the data selection control signal SCa.

[0094] The level shifter 1240 of the level shift unit 124 level-shifts the signal amplitude of the comparison result signal DMa supplied from the comparison circuit 1230a to the high-voltage side, and supplies this to the selector unit 126 as a high-voltage comparison result signal DMs. The level shifter 1241 of the level shift unit 124 receives the pixel data signal P(N) or P(N+6) supplied from the data selector 1237. Here, when the level shifter 1241 receives the pixel data signal P(N), the level shifter 1241 level-shifts the signal amplitude of the pixel data signal P(N) to the high-voltage side, and supplies this to the DA conversion unit 125 as a high-voltage pixel data signal F(N). On the other hand, when the level shifter 1241 receives the pixel data signal P(N+6), the level shifter 1241 level-shifts the signal amplitude of the pixel data signal P(N+6) to the high-voltage side, and supplies this to the DA conversion unit 125 as a high-voltage pixel data signal F(N+6).

[0095] When the level shifter 1242 of the level shift unit 124 receives the pixel data signal P(N+3) from the switch 1232, the level shifter 1242 shifts the signal amplitude of the pixel data signal P(N+3) to the high-voltage side and supplies the resultant signal as a high-voltage pixel data signal F(N+3) to the DA conversion unit 125. However, the level shifter 1242 does not operate if it does not receive the pixel data signal P(N+3) from the switch 1232. Therefore, at this time, the level shifter 1242 does not generate the high-voltage pixel data signal F(N+3) based on the pixel data signal P(N+3), and therefore the high-voltage pixel data signal F(N+3) is not supplied to the DA conversion unit 125.

[0096] The DA converter 1251 of the DA conversion unit 125 receives the high-voltage pixel data signal F(N) or F(N+6). When the DA converter 1251 receives the high-voltage pixel data signal F(N), it converts it into a voltage having a voltage value corresponding to the luminance indicated by the high-voltage pixel data signal F(N), and supplies the converted voltage to the selector unit 126 as the gradation voltage V(N). On the other hand, when the DA converter 1251 receives the high-voltage pixel data signal F(N+6), it converts it into a voltage having a voltage value corresponding to the luminance indicated by the high-voltage pixel data signal F(N+6), and supplies the converted voltage to the selector unit 126 as the gradation voltage V(N+6).

[0097] When the DA converter 1252 of the DA conversion unit 125 receives the high-voltage pixel data signal F(N+3) from the level shifter 1242, it converts the signal into a voltage having a voltage value corresponding to the luminance indicated by the high-voltage pixel data signal F(N+3).The DA converter 1252 then supplies this voltage to the selector unit 126 as the gradation voltage V(N+3).

[0098] The gate circuit 1260 of the selector unit 126 receives the high-voltage comparison result signal DMs supplied from the level shift unit 124 and the data selection control signal SCa supplied from the control circuit 120a. When the high-voltage comparison result signal DMs has a logical value of 0, indicating that the pixel data signals P(N) and P(N+3) both represent the same luminance, the gate circuit 1260 supplies a selection signal CSW of a logical value of 0, which selects the gradation voltage V(N) or V(N+6), to the voltage selector 1261. When the high-voltage comparison result signal DMs has a logical value of 1, that is, when the pixel data signals P(N), P(N+3), and P(N+6) represent different luminances, the gate circuit 1260 supplies a selection signal CSW having the logical value of the data selection control signal SCa to the voltage selector 1261. As mentioned above, the data selection control signal SCa is a binary signal that represents a logical value of 0 in the first divided period, a logical value of 1 in the second divided period, and a logical value of 0 in the third divided period, when the horizontal scanning period is divided into three parts.

[0099] The voltage selector 1261 receives the gradation voltage V(N) or V(N+6) supplied from the DA converter 1251 at a first input terminal, and receives the gradation voltage V(N+3) supplied from the DA converter 1252 at a second input terminal.

[0100] The voltage selector 1261 selects one of the grayscale voltages V(N) or V(N+6) and the grayscale voltage V(N+3) based on the selection signal CSW. For example, the voltage selector 1261 selects the grayscale voltage V(N) or V(N+6) when the selection signal CSW indicates a logical value of 0, and selects the grayscale voltage V(N+3) when the selection signal CSW indicates a logical value of 1. The voltage selector 1261 then supplies a signal representing the selected grayscale voltage V(N), V(N+3), or V(N+6) to the output amplifier unit 127 as a grayscale voltage signal E(N).

[0101] The amplifier 1270 of the output amplifier unit 127 is, for example, a voltage follower operational amplifier that receives at its non-inverting input terminal the grayscale voltage signal E(N) supplied from the voltage selector 1261. The amplifier 1270 amplifies the grayscale voltage signal E(N) to generate a drive signal G(N), which is output from the external terminal TM of the data driver 12_1 to the display panel 20.

[0102] In this case, the demultiplexer 200 of the display panel 20 includes, instead of the aforementioned channel selector CSEL, y channel selectors CSELa, each of which individually receives the drive signals G1 to Gy (y=m / 3) and is connected to three of the data lines DL1 to DLm.

[0103] Each of the channel selectors CSELa selects one data line from the three data lines connected to it for each divided period into three that each horizontal scanning period is divided into, in response to the channel selection signals CHa to CHc supplied from the control circuit 120a, and supplies the drive signal that it has received to that one data line.

[0104] Below, we will explain the operation of the switch circuit 1235, voltage selector 1261 and channel selector CSEL, as well as the flow of signals within circuit block BLK_1, for cases where pixel data signals P(N), P(N+3) and P(N+6) represent the same luminance, and cases where pixel data signals P(N) and P(N+3) represent different luminances or where P(N+3) and P(N+6) represent different luminances. [When P(N)≠P(N+3) or P(N+3)≠P(N+6)] FIG. 12 is a time chart showing the operation of the switch 1232, the data selector 1237, the voltage selector 1261, and the channel selector CSEL within 1H when the pixel data signals P(N) and P(N+3) represent different luminances, or when the pixel data signals P(N+3) and P(N+6) represent different luminances.

[0105] Fig. 13A is a circuit diagram showing, with thick solid lines, the signal flow in circuit block BLK_2 in a first divided period of first to third divided periods obtained by dividing 1H into three, Fig. 13B is a circuit diagram showing, with thick solid lines, the signal flow in circuit block BLK_2 in a second divided period, and Fig. 13C is a circuit diagram showing, with thick solid lines, the signal flow in circuit block BLK_2 in a third divided period.

[0106] Here, when pixel data signals P(N) and P(N+3) represent different luminances, or when P(N+3) and P(N+6) represent different luminances, switch 1232 is in the on state for 1H, as shown in Fig. 12. Data selector 1237 selects pixel data signal P(N) output from latch 1221 over the first and second division periods, as shown in Fig. 12, and supplies this to level shifter 1241. Note that, in the third division period, as shown in Fig. 12, data selector 1237 selects pixel data signal P(N+6) output from latch 1223 and supplies this to level shifter 1241.

[0107] Therefore, in the first division period, the gradation voltage V(N) based on the pixel data signal P(N) is supplied to the first input terminal of the voltage selector 1261 via path A shown by the thick solid line in Fig. 13A. Furthermore, the gradation voltage V(N+3) based on the pixel data signal P(N+3) output from the latch 1222 is supplied to the second input terminal of the voltage selector 1261 via path B shown by the thick solid line in Fig. 13A.

[0108] Furthermore, in the first divisional period, as shown in Fig. 12, the voltage selector 1261 selects path A from paths A and B. Therefore, in the first divisional period, a drive signal G(N) having a gradation voltage V(N) is output from the external terminal TM to the display panel 20 via path A shown by a thick solid line in Fig. 13A and the voltage selector 1261. At this time, the channel selector CSELa that receives the drive signal G(N) in the display panel 20 supplies the drive signal G(N) having the gradation voltage V(N) to the data line DL(N), as shown by a thick solid line in Fig. 13A, while it is receiving a channel selection signal CHa with a logical value of 1 in the first divisional period, as shown in Fig. 12.

[0109] In a second divisional period following the first divisional period, as shown in Fig. 12, the voltage selector 1261 selects path B from paths A and B. Therefore, in the second divisional period, a drive signal G(N) having a gradation voltage V(N+3) is output from the external terminal TM to the display panel 20 via path B shown by a thick solid line in Fig. 13B and the voltage selector 1261. At this time, the channel selector CSELa that receives the drive signal G(N) in the display panel 20 supplies the drive signal G(N) having the gradation voltage V(N+3) to the data line DL(N+3), as shown by a thick solid line in Fig. 13B, while receiving a channel selection signal CHb with a logic value of 1 in the second divisional period, as shown in Fig. 12.

[0110] Then, in the third divisional period following the second divisional period, as shown in Fig. 12, the voltage selector 1261 selects path A from paths A and B. Therefore, in the third divisional period, a drive signal G(N) having a gradation voltage V(N+6) is output from the external terminal TM to the display panel 20 via path A shown by a thick solid line in Fig. 13C and the voltage selector 1261. At this time, the channel selector CSELa that receives the drive signal G(N) in the display panel 20 supplies the drive signal G(N) having the gradation voltage V(N+6) to the data line DL(N+6), as shown by a thick solid line in Fig. 13C, while receiving the channel selection signal CHc with a logical value of 1 during the third divisional period, as shown in Fig. 12. [When P(N)=P(N+3)=P(N+6)] Figure 14 is a time chart showing the operation of the switch 1232, data selector 1237, voltage selector 1261, and channel selector CSEL within 1H when pixel data signals P(N), P(N+3), and P(N+6) represent the same luminance.

[0111] Fig. 15A is a circuit diagram showing, with thick solid lines, the signal flow in circuit block BLK_2 in a first divided period of first to third divided periods obtained by dividing 1H into three, Fig. 15B is a circuit diagram showing, with thick solid lines, the signal flow in circuit block BLK_2 in a second divided period, and Fig. 15C is a circuit diagram showing, with thick solid lines, the signal flow in circuit block BLK_2 in a third divided period.

[0112] In this way, when the pixel data signals P(N), P(N+3), and P(N+6) represent the same luminance, the switch 1232 is in the OFF state for 1H, as shown in Fig. 14. The data selector 1237 maintains the state of selecting the pixel data signal P(N) output from the latch 1221 and supplying it to the level shifter 1241 for 1H, as shown in Fig. 14.

[0113] 15A to 15C, over 1H, a gradation voltage V(N) based on the pixel data signal P(N) is supplied to the first input terminal of the voltage selector 1261 via path A indicated by a thick solid line. Then, via the voltage selector 1261, a drive signal G(N) having the gradation voltage V(N) is output from the external terminal TM to the display panel 20.

[0114] In this case, during a first divisional period of 1H, the channel selector CSELa supplies a drive signal G(N) having a gradation voltage V(N) to the data line DL(N) of the display panel 20 as shown by the thick solid line in Fig. 15A while the channel selector CSELa receives a channel selection signal CHa having a logic value of 1 as shown in Fig. 14. During a second divisional period, the channel selector CSELa supplies a drive signal G(N) having a gradation voltage V(N) to the data line DL(N+3) of the display panel 20 as shown by the thick solid line in Fig. 15B while the channel selector CSELa receives a channel selection signal CHb having a logic value of 1 as shown in Fig. 14. During a third divisional period, the channel selector CSELa supplies a drive signal G(N) having a gradation voltage V(N) to the data line DL(N+6) of the display panel 20 as shown by the thick solid line in Fig. 15C while the channel selector CSELa receives a channel selection signal CHc having a logic value of 1 as shown in Fig. 14.

[0115] 15A to 15C, the pixel data signal P(N+3) output from the latch 1222 is stopped at the switch 1232 for 1H and is not supplied to the level shifter 1242 and the DA converter 1252. Therefore, the level shifter 1242 and the DA converter 1252 stop operating.

[0116] In other words, in the data driver 12_2, when the pixel data signals P(N), P(N+3), and P(N+6) represent the same luminance, the voltage selector 1261 selects the gradation voltage V(N) from among the gradation voltages V(N) and V(N+6), and outputs the drive signal G(N) having this gradation voltage V(N). Furthermore, at this time, the switch 1232 cuts off the supply of the pixel data signal P(N+3), which is responsible for generating the gradation voltage V(N+3), to the level shifter 1242, and the data selector 1237 cuts off the supply of the pixel data signal P(N+6), which is responsible for generating the gradation voltage V(N+6), to the level shifter 1241. As a result, the generation of the gradation voltages V(N+3) and V(N+6) is stopped.

[0117] Therefore, in the data driver 12_2 in which the division number K=3 of the time-division driving is used, it is possible to significantly reduce the power consumption, similar to the data driver 12_1 in which the division number K=2 is used.

[0118] 3 or 10, the data driver 12_1 or 12_2 requires one comparison circuit 1230 for each of two pixel data signals P(N) and P(N+3) or three pixel data signals P(N), P(N+3) and P(N+6). However, it is also possible to provide one comparison circuit for the entire data driver 12. Example 3

[0119] FIG. 16 is a block diagram showing an example of the internal configuration of a data driver 12_3, which is a data driver 12 designed in consideration of the above points and has a division number K=2 for time-division driving.

[0120] The data driver 12_3 has the same configuration as that shown in FIG. 2 except that it employs a control circuit 120b, a shift register 121a, a data latch unit 122a, and a data switch unit 123b instead of the control circuit 120, the shift register 121, the data latch unit 122, and the data switch unit 123 shown in FIG. 2, and that it is newly provided with a comparison circuit 130.

[0121] The control circuit 120b receives the digital video signal DVS in the same manner as the control circuit 120, and extracts the horizontal synchronization signal, start pulse STA, and clock signal CLK contained in the digital video signal DVS. Then, the control circuit 120b supplies the clock signal CLK together with the start pulse STA to the shift register 121a at a timing synchronized with the horizontal synchronization signal.

[0122] In addition, like the control circuit 120, the control circuit 120b generates channel selection signals CHa and CHb, each of which is binary (0 or 1) for selecting a group of data lines to which y (y=m / 2) groups of drive signals are output, for each divided period obtained by dividing the horizontal scanning period into two (K=2) periods, and outputs these to the demultiplexer 200 of the display panel 20.

[0123] Furthermore, the control circuit 120b generates a binary (0 or 1) data selection control signal SC for selecting y (y=m / 2) grayscale voltages from among m grayscale voltages (described later) for each of the above-mentioned divided periods in response to the horizontal synchronization signal, and supplies the signal to the selector unit 126. For example, the control circuit 120b supplies the selector unit 126 with a data selection control signal SC having a logical value of 0 in a first divided period obtained by dividing the horizontal scanning period into two, and a logical value of 1 in a second divided period following the first divided period.

[0124] Furthermore, the control circuit 120b separates the series of pixel data PD included in the video digital signal DVS into a series of pixel data PD corresponding to each display cell (Pr, Pg, Pb) belonging to odd-numbered cell groups PX in the horizontal direction of the display panel 20, and a series of pixel data PD corresponding to each display cell belonging to even-numbered cell groups PX.

[0125] That is, the control circuit 120b defines the series of pixel data PD arranged at the 1st to 3rd, 7th to 9th, 13th to 15th, etc. positions in the series of the 1st to mth pixel data PD1 to PDm as a pixel data series PDa, and further defines the series of pixel data PD arranged at the 4th to 6th, 10th to 12th, 16th to 18th, etc. positions in the series of the 1st to mth pixel data PD as a pixel data series PDb.

[0126] FIG. 17 is a time chart showing an example of pixel data series PDa and PDb, in which the first to twelfth pixel data PD1 to PD12 are extracted from the series of pixel data PD1 to PDm.

[0127] 17, the control circuit 120b supplies a pixel data series PDa consisting of a series of pixel data PD1, PD2, PD3, PD7, PD8, and PD9 to the comparison circuit 130 in synchronization with the clock signal CLK. The control circuit 120b also supplies a pixel data series PDb consisting of a series of pixel data PD4, PD5, PD6, PD10, PD11, and PD12 to the comparison circuit 130 in synchronization with the clock signal CLK. The control circuit 120b also supplies the pixel data series PDa and PDb as shown in FIG. 17 and the clock signal CLK to the data latch unit 122a.

[0128] The comparison circuit 130 compares each pixel data PD(N) in the pixel data series PDa with each pixel data PD(N+3) in the pixel data series PDb, pair by pair, and sequentially determines whether or not the two match, as shown in Fig. 17. At this time, the comparison circuit 130 generates a comparison result series signal DMC that sequentially indicates a binary determination result that indicates a logical value of 1 if the pair of pixel data match and a logical value of 0 if they do not match, as shown in Fig. 17, and supplies this to the data latch unit 122a.

[0129] Incidentally, in the data driver 12_3, in the y output channels that output the drive signals G1 to Gy, the data latch unit 122a, the data switch unit 123b, the level shift unit 124, the DA conversion unit 125, the selector unit 126, and the output amplifier unit 127 have the same internal configuration for every three output channels.

[0130] Therefore, by extracting the circuit block BL1_3 which is responsible for three output channels and is divided into areas surrounded by dashed lines as shown in FIG. 16, the internal configurations of the above-mentioned data latch unit 122a, data switch unit 123b, level shift unit 124, DA conversion unit 125, selector unit 126, and output amplifier unit 127 will be described in detail.

[0131] FIG. 18 is a block diagram showing the internal configuration of the circuit block BLK_3.

[0132] 18, the circuit block BLK_3 has three latches 1220 to 1222 included in the data latch unit 122a, a switch 1232 included in the data switch unit 123a, and level shifters (LSF) 1240 to 1242 included in the level shift unit 124. Furthermore, the circuit block BLK_3 has DA converters (DAC) 1251 and 1252 included in the DA conversion unit 125, a gate circuit 1260 and a voltage selector 1261 included in the selector unit 126, and an amplifier 1270 included in the output amplifier unit 127.

[0133] Here, the latch 1220 of the data latch unit 122a captures and holds the comparison result series signal DMC supplied from the comparison circuit 130 at the timing of the clock signal CLK in response to the load signal L(N), and supplies this as a comparison result signal DM to the data switch unit 123b and the level shift unit 124.

[0134] The latch 1221 of the data latch unit 122a is the Nth latch in the circuit block BLK_3, and in response to the load signal L(N), captures and holds the pixel data PD in the pixel data series PDa at the timing of the clock signal CLK, and supplies this to the level shift unit 124.

[0135] The latch 1222 is the (N+3)th latch in the circuit block BLK_3, and in response to the load signal L(N), captures and holds the pixel data PD in the pixel data series PDb at the timing of the clock signal CLK, and supplies this to the data switch unit 123b.

[0136] For example, when N=1, the first latch 1221, in response to the load signal L1 of logical 1, captures and holds the first pixel data PD1 in the pixel data series PDa at the rising edge of the clock signal CLK, as shown in FIG. 17. Meanwhile, the fourth latch 1222, in response to the load signal L1 of logical 1, captures and holds the fourth pixel data PD4 in the pixel data series PDb at the rising edge of the clock signal CLK, as shown in FIG. 17. At this time, the comparator circuit 130 determines whether the pixel data PD1 and PD4 match, and if it determines that they do not match, it outputs a comparison result series signal DMC of logical 0, as shown in FIG. 17. Therefore, the latch 1220, in response to the load signal L1 of logical 1, captures the comparison result series signal DMC of logical 0 at the rising edge of the clock signal CLK, and outputs this as the comparison result signal DM, as shown in FIG. 17.

[0137] Next, for example, as shown in Figure 17, the second latch 1221 retrieves and holds the second pixel data PD2 in the pixel data series PDa at the rising edge of the clock signal CLK in response to the load signal L2 of logical 1. Meanwhile, as shown in Figure 17, the fifth latch 1222 retrieves and holds the fifth pixel data PD5 in the pixel data series PDb at the rising edge of the clock signal CLK in response to the load signal L2 of logical 1. At this time, the comparator circuit 130 determines whether the pixel data PD2 and PD5 match, and if it determines that they match, it outputs a comparison result series signal DMC of logical 1, as shown in Figure 17. Therefore, as shown in Figure 17, the latch 1220 retrieves the comparison result series signal DMC of logical 1 at the rising edge of the clock signal CLK in response to the load signal L2 of logical 1, and outputs it as the comparison result signal DM.

[0138] At this time, the switch 1232 of the data switch unit 123a receives the comparison result signal DM that the latch 1220 has captured and held, the comparison result series signal DMC output from the comparison circuit 130. When the comparison result signal DM is a logical value 1, that is, when the pixel data signals P(N) and P(N+3) both represent different luminance values, the switch 1232 of the data switch unit 123a is turned on like the switch 1232 of the data driver 12_1, and supplies the pixel data signal P(N+3) supplied from the latch 1222 to the level shift unit 124. On the other hand, when the comparison result signal DM is a logical value 0, that is, when the pixel data signals P(N) and P(N+3) both represent the same luminance value, the switch 1232 is turned off like the switch 1232 of the data driver 12_1, and cuts off the supply of the pixel data signal P(N+3) to the level shift unit 124. This causes the level shifter 1242 and the DA converter 1252 to stop operating.

[0139] In the data driver 12_3, the level shifters 1240 to 1242 of the level shift section 124, the DA converters 1251 and 1252 of the DA conversion section 125, the gate circuit 1260 and voltage selector 1261 of the selector section 126, and the amplifier 1270 of the output amplifier section 127 are the same as those included in the data driver 12_1 shown in Figure 3.

[0140] Therefore, in the data driver 12_3, similar to the data driver 12_1, the operations shown in FIGS. 5, 6A, 6B, 7, 8A and 8B are performed, and as a result, it is possible to significantly reduce power consumption.

[0141] Furthermore, according to the data driver 12_3, although it is necessary to provide a latch 1220 for each of the two pixel data signals P(N) and P(N+3), the comparison between the pixel data signals P(N) and P(N+3) can be realized with only a single comparison circuit 130, and therefore the overall circuit scale of the data driver 12 can be reduced.

[0142] In the above embodiment, the number of divisions K in the time-division driving is set to "2" or "3", but the number of divisions K may be set to 4 or more.

[0143] In short, a display driver (12, 12_1 to 12_3) that drives a display panel (20) including a plurality of data lines (DL1 to DLm) and a demultiplexer (200) that receives one drive signal (G) for each of K (K is an integer equal to or greater than 2) data lines and supplies the one drive signal to the K data lines one by one in sequence may be any display driver that includes the following plurality of circuit blocks:

[0144] Each circuit block (BLK_1 to BLK_3) receives K pixel data pieces out of a plurality of pixel data pieces (PD) corresponding to each pixel based on a video signal (DVS) as the first to Kth pixel data pieces, generates first to Kth gradation voltages (V) having magnitudes corresponding to the brightness indicated by each of the pixel data pieces, and outputs a signal having each of the first to Kth gradation voltages in order as one drive signal to the display panel.

[0145] Each of the plurality of circuit blocks includes the following selector and switch circuits.

[0146] When the first to Kth pixel data pieces [e.g., P(N), P(N+3), P(N+6)] represent different luminances, the selectors (1260, 1261) sequentially select the first to Kth gradation voltages [e.g., V(N), V(N+3), V(N+6)] one by one within the horizontal scanning period and output the selected gradation voltage as one drive signal [G(N)]. On the other hand, when the first to Kth pixel data pieces represent the same luminance, the selectors (1260, 1261) select only one gradation voltage [e.g., V(N)] from the first to Kth gradation voltages throughout the horizontal scanning period and output this as one drive signal.

[0147] When the first to Kth pixel data pieces represent the same brightness, the switch circuits (1232, 1237) stop the generation operation of the other gradation voltages [e.g., V(N+3), V(N+6)] among the first to Kth gradation voltages [e.g., V(N), V(N+3), V(N+6)] except for the one gradation voltage [e.g., V(N)].

[0148] In this way, the display driver according to this embodiment generates first to K-th grayscale voltages based on the first to K-th pixel data pieces, selects these first to K-th grayscale voltages one by one during a horizontal scanning period, and outputs the selected grayscale voltage to the display panel as one drive signal. At this time, if the first to K-th pixel data pieces indicate the same luminance, the display driver selects only one of the first to K-th grayscale voltages and outputs this as one drive signal over the horizontal scanning period, while halting the generation of the other grayscale voltages except for the one grayscale voltage among the first to K-th grayscale voltages. Therefore, with this display driver, the level shifters and DA converters required to generate grayscale voltages based on the pixel data pieces stop operating, making it possible to significantly reduce power consumption. [Explanation of symbols]

[0149] 12 Data Driver 20 Display panel 120 control circuit 122 Data latch section 123 Data switch section 124 Level shift section 125 DA conversion section 126 Selector section 1220~1222 Latch 1230, 1230a comparison circuit 1232 Switch 1235 Switch Circuit 1237 Data Selector 1240~1242 Level Shifter 1251, 1252 DA converters 1261 Voltage Selector

Claims

1. A display driver for driving a display panel including a plurality of data lines, and a demultiplexer for receiving one drive signal corresponding to each of K data lines (K is an integer of 2 or more) of the plurality of data lines, and supplying the one drive signal to the K data lines one by one in sequence, each of the plurality of circuit blocks receives K pixel data pieces from a plurality of pixel data pieces corresponding to each pixel based on a video signal as first to K-th pixel data pieces, generates first to K-th gradation voltages having magnitudes corresponding to the luminance indicated by the respective pixel data pieces, and outputs a signal having each of the first to K-th gradation voltages in order as the one drive signal to the display panel; Each of the plurality of circuit blocks a selector which, when the first to Kth pixel data pieces represent different luminances, selects the first to Kth gray scale voltages one by one in a horizontal scanning period of the video signal and outputs the one driving signal having the selected gray scale voltages in order, and, when the first to Kth pixel data pieces represent the same luminance, selects only one gray scale voltage from the first to Kth gray scale voltages over the horizontal scanning period and outputs the one driving signal having the selected gray scale voltage; a switch circuit that stops the generation of all the gradation voltages other than the one gradation voltage among the first to Kth gradation voltages when the first to Kth pixel data pieces represent the same luminance.

2. Each of the plurality of circuit blocks first to K-th latches that receive the K pixel data pieces, individually capture and hold each of the K pixel data pieces, and individually output first to K-th pixel data signals that indicate each of the K pixel data pieces that have been held; first to K-th level shifters that individually receive the first to K-th pixel data signals and level-shift the signal amplitudes of the first to K-th pixel data signals to high voltages to individually generate first to K-th high-voltage pixel data signals; first to Kth DA converters that individually receive the first to Kth high-voltage pixel data signals, convert them into the first to Kth gradation voltages having analog voltage values, and individually output the first to Kth gradation voltages; The display driver according to claim 1, characterized in that, when the first to Kth pixel data signals represent the same luminance, the switch circuit cuts off the supply of other pixel data signals, except for the pixel data signal that is responsible for generating the one gradation voltage, among the first to Kth pixel data signals, to the first to Kth level shifters.

3. Each of the plurality of circuit blocks a comparison circuit that compares the first to Kth pixel data signals with each other and generates a comparison result signal that indicates whether the first to Kth pixel data signals represent different luminances or the same luminance; a level shifter that generates a high-voltage comparison result signal by level-shifting the signal amplitude of the comparison result signal to a high voltage, The display driver according to claim 2, characterized in that the selector receives the comparison result signal and the switch circuit receives the high-voltage comparison result signal, and the selector and the switch circuit determine whether the first to Kth pixel data signals represent different luminances or the same luminance.

4. said K is 2; The comparison circuit first to j-th non-exclusive OR circuits each receiving the same bit digits of the first pixel data signal and the second pixel data signal, each of which is j (j is an integer of 2 or more) bits; 4. The display driver according to claim 3, further comprising: an AND circuit that receives outputs from the first to jth non-exclusive OR circuits and outputs its own output result as the comparison result signal.

5. said K is 3; The comparison circuit receiving the first to third pixel data signals each consisting of j bits (j is an integer of 2 or more); first to jth non-exclusive OR circuits each receiving the first to jth bits of the first pixel data signal at a first input terminal thereof; first to j-th selectors each receiving the first to j-th bits of the second pixel data signal and the first to j-th bits of the third pixel data signal at the same bit digit, and each selecting the first to j-th bit of one of the second pixel data signal and the third pixel data signal, and supplying the selected bit to second input terminals of first to j-th non-exclusive OR circuits; 4. The display driver according to claim 3, further comprising: an AND circuit that receives outputs from the first to jth non-exclusive OR circuits and outputs its own output result as the comparison result signal.

6. a control circuit that receives the video signal and outputs, based on the video signal, a first pixel data sequence and a second pixel data sequence, each of which is composed of a sequence of pixel data pieces corresponding to each pixel; a comparison circuit that receives the first pixel data series and the second pixel data series, compares pixel data pieces in the first pixel data series with pixel data pieces in the second pixel data series pair by pair, and outputs comparison result series signals that indicate, for each pair, whether the two pieces represent different luminances or the same luminance; Each of the plurality of circuit blocks a latch that acquires and holds the comparison result of 1 in the comparison result series signal and outputs a comparison result signal that indicates the held comparison result; a level shifter that generates a high-voltage comparison result signal by level-shifting the signal amplitude of the comparison result signal to a high voltage, The display driver according to claim 2, characterized in that the selector receives the comparison result signal and the switch circuit receives the high-voltage comparison result signal, and the selector and the switch circuit determine whether the first to Kth pixel data signals represent different luminances or the same luminance.

7. A display device comprising: a display panel including a plurality of data lines; and a demultiplexer that receives one drive signal corresponding to each of K data lines (K is an integer of 2 or more) of the plurality of data lines and sequentially supplies the one drive signal to the K data lines one by one; and a display driver that drives the display panel based on a video signal, The display driver each of the plurality of circuit blocks receives K pixel data pieces from a plurality of pixel data pieces corresponding to each pixel based on a video signal as first to K-th pixel data pieces, generates first to K-th gradation voltages having magnitudes corresponding to the luminance indicated by the respective pixel data pieces, and outputs a signal having each of the first to K-th gradation voltages in order as the one drive signal to the display panel; Each of the plurality of circuit blocks a selector which, when the first to Kth pixel data pieces represent different luminances, selects the first to Kth gray scale voltages one by one in a horizontal scanning period of the video signal and outputs the one driving signal having the selected gray scale voltages in order, and, when the first to Kth pixel data pieces represent the same luminance, selects only one gray scale voltage from the first to Kth gray scale voltages over the horizontal scanning period and outputs the one driving signal having the selected gray scale voltage; a switch circuit that stops the generation of all the gradation voltages other than the one gradation voltage among the first to Kth gradation voltages when the first to Kth pixel data pieces represent the same luminance.

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