Semiconductor Devices

Abstract

A semiconductor device is provided in which the force exerted on the wires due to vibration of the sealing body is suppressed. [Solution] The semiconductor device includes a substrate (40), a semiconductor element (30), a wire (80), a snubber circuit, and an encapsulant (90). The semiconductor element (30) has a pad (33) electrically connected to a signal terminal. The wire (80) forms at least a part of a communication line connecting the signal terminal and the pad (33). The snubber circuit includes a capacitor (131) and electrically bridges a first wiring and a second wiring of the substrate (40). The encapsulant (90) encapsulates at least a part of the capacitor (131) together with the semiconductor element (30) and the wire (80). An upper end (1315) of the capacitor (131) is located higher than the pad (33).

Description

[Technical Field]

[0001] TECHNICAL FIELD The disclosure herein relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device with a built-in snubber circuit. This snubber circuit is configured with a capacitor and a resistor connected in series. The capacitor and resistor electrically bridge a P line connected to a power supply terminal of a DC power supply and an N line connected to a ground terminal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-182575 Summary of the Invention [Problem to be solved by the invention]

[0004] It is desirable to seal these types of electronic components, such as capacitors and resistors, with a sealant such as gel. However, because the sealant has fluidity, it may vibrate and sway. As a result, the waves of the vibrating sealant may push against the wires bonded to the semiconductor element, applying force to the wires, which may cause damage to the wires.

[0005] One disclosed object is to provide a semiconductor device that suppresses the force exerted on the wires by vibration of the sealing body. [Means for solving the problem]

[0006] One aspect of the disclosure is A semiconductor device constituting a power conversion circuit (6), A first main terminal (611), A second main terminal (612); A signal terminal (62); a substrate (40) having an insulating base material (41), a first wiring (421) disposed on one surface of the insulating base material and electrically connected to a first main terminal, and a second wiring (422) disposed on one surface of the insulating base material and electrically connected to a second main terminal; a semiconductor element (30, 30H) having main electrodes (31, 32) electrically connected to the first wiring and a pad (33) electrically connected to a signal terminal (62); Wires (80, 801, 802, 80a) forming at least a portion of a communication line connecting the signal terminals and pads; a snubber circuit (13) including a capacitor (131) and electrically bridging the first wiring and the second wiring; a flowable encapsulant (90) that encapsulates at least a portion of the capacitor together with the semiconductor element and the wire; This is a semiconductor device in which the upper end (1315) of the capacitor is located higher than the pad.

[0007] According to the semiconductor device disclosed above, the capacitor functions as a breakwater that protects the wire from vibrations of the sealing body, thereby reducing the force that the sealing body exerts on the wire and the risk of damage to the wire.

[0008] The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The reference numerals in parentheses in the claims and in this section are intended to exemplify correspondences with the following embodiments and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become more apparent by reference to the following detailed description and the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram showing a circuit configuration of a power conversion device to which a semiconductor device according to a first embodiment is applied; [Figure 2] 1 is a perspective view of a semiconductor module including a semiconductor device according to a first embodiment. [Figure 3]FIG. 3 is a plan view of the semiconductor module shown in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. [Figure 5] FIG. 4 is a cross-sectional view of the semiconductor module shown in FIG. [Figure 6] 4 is a plan view of the semiconductor module shown in FIG. 3 with the housing removed. [Figure 7] FIG. 2 is a detailed diagram of the snubber circuit shown in FIG. [Figure 8] 8 is a plan view showing the arrangement of capacitors and resistors in the snubber circuit shown in FIG. 7. [Figure 9] FIG. 10 is a plan view showing the arrangement of capacitors and resistors of a snubber circuit in a modified example of the first embodiment. [Figure 10] FIG. 10 is a plan view showing the arrangement of capacitors and resistors of a snubber circuit in a modified example of the first embodiment. [Figure 11] FIG. 10 is a plan view showing the arrangement of capacitors and resistors of a snubber circuit in a modified example of the first embodiment. [Figure 12] FIG. 10 is a plan view showing the arrangement of capacitors and resistors of a snubber circuit in a modified example of the first embodiment. [Figure 13] FIG. 10 is a plan view showing the arrangement of capacitors and resistors of a snubber circuit in a modified example of the first embodiment. [Figure 14] FIG. 10 is a plan view of a semiconductor module including a semiconductor device according to a second embodiment. [Figure 15] FIG. 10 is a plan view of a semiconductor module according to a modified example of the second embodiment. [Figure 16] FIG. 10 is a front view of a capacitor included in the semiconductor device according to the third embodiment. [Figure 17] 17 is a side view of the capacitor shown in FIG. 16 as viewed from the direction of arrow XVII. [Figure 18] 10 is a plan view showing the arrangement of capacitors and resistors in a snubber circuit included in a semiconductor device according to a fourth embodiment. FIG. [Figure 19] FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 18. [Figure 20] 19 is a cross-sectional view taken in the Y direction. [Figure 21] 19 is a plan view showing the relationship between the electronic component of the snubber circuit shown in FIG. 18 and the first projection range, the second projection range, the first range, and the second range. FIG. [Figure 22] FIG. 11 is a plan view showing the arrangement of electronic components in a snubber circuit in a modified example of the fourth embodiment. [Figure 23] FIG. 11 is a plan view showing the arrangement of electronic components in a snubber circuit in a modified example of the fourth embodiment. [Figure 24] FIG. 11 is a plan view showing the arrangement of electronic components in a snubber circuit in a modified example of the fourth embodiment. [Figure 25] FIG. 11 is a plan view showing the arrangement of electronic components in a snubber circuit in a modified example of the fourth embodiment. [Figure 26] FIG. 11 is a plan view showing the arrangement of electronic components in a snubber circuit in a modified example of the fourth embodiment. [Figure 27] FIG. 11 is a plan view showing the arrangement of electronic components in a snubber circuit in a modified example of the fourth embodiment. [Figure 28] FIG. 11 is a plan view showing the arrangement of electronic components in a snubber circuit in a modified example of the fourth embodiment. [Figure 29] FIG. 11 is a plan view showing the arrangement of electronic components in a snubber circuit in a modified example of the fourth embodiment. [Figure 30] FIG. 10 is a plan view showing the arrangement of capacitors and resistors in a snubber circuit included in a semiconductor device according to a fifth embodiment. [Figure 31] FIG. 10 is a cross-sectional view of a snubber circuit according to a fifth embodiment. [Figure 32] FIG. 13 is a cross-sectional view of a snubber circuit according to a first comparative example of the fifth embodiment. [Figure 33] FIG. 13 is a cross-sectional view of a snubber circuit according to a second comparative example of the fifth embodiment. [Figure 34] FIG. 10 is a cross-sectional view showing a semiconductor device according to a sixth embodiment. [Figure 35] FIG. 10 is a plan view showing a semiconductor device according to a sixth embodiment. [Figure 36]FIG. 13 is a cross-sectional view of a semiconductor device according to a modification of the sixth embodiment. [Figure 37] FIG. 13 is a plan view showing the arrangement of capacitors and resistors in a snubber circuit according to a seventh embodiment. [Figure 38] FIG. 38 is a cross-sectional view taken along line XXXVIII-XXXVIII in FIG. 37. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, several embodiments will be described with reference to the drawings. Note that in each embodiment, corresponding components are designated by the same reference numerals, and redundant description may be omitted. When only a portion of the configuration is described in each embodiment, the configuration of another embodiment previously described may be applied to the remaining portion of the configuration. Furthermore, in addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations of several embodiments may be partially combined together even if not explicitly stated, provided that there is no particular problem with the combination.

[0011] The semiconductor device of this embodiment is applied to, for example, a power conversion device of a mobile object using a rotating electric machine as a drive source. The mobile object may be, for example, an electric vehicle such as a battery electric vehicle (BEV), a hybrid electric vehicle (HEV), or a plug-in hybrid electric vehicle (PHEV), an aircraft such as an electric vertical take-off and landing aircraft or a drone, a ship, a construction machine, or an agricultural machine. An example of application to a vehicle will be described below.

[0012] (First embodiment) First, the schematic configuration of a vehicle drive system will be described with reference to FIG.

[0013] <Vehicle drive system> As shown in FIG. 1, a vehicle drive system 1 includes a DC power supply 2, a motor generator 3, and a power conversion device 4.

[0014] The DC power supply 2 is a DC voltage source made up of a rechargeable secondary battery. The secondary battery is, for example, a lithium-ion battery or a nickel-metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a drive source for the vehicle, i.e., an electric motor. The motor generator 3 functions as a generator during regeneration. The power conversion device 4 converts power between the DC power supply 2 and the motor generator 3.

[0015] <Power conversion device> Next, the circuit configuration of the power conversion device 4 will be described with reference to Fig. 1. The power conversion device 4 includes a power conversion circuit. The power conversion device 4 of this embodiment includes a smoothing capacitor 5 and an inverter 6 which is a power conversion circuit.

[0016] The smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to a P line 7, which is a power supply line on the high potential side, and an N line 8, which is a power supply line on the low potential side. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. The negative electrode of the smoothing capacitor 5 is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

[0017] The inverter 6 is a DC-AC conversion circuit. The inverter 6 converts a DC voltage into a three-phase AC voltage in accordance with switching control by a control circuit (not shown) and outputs the voltage to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to rotational force from the wheels into a DC voltage in accordance with switching control by the control circuit and outputs the DC voltage to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power supply 2 and the motor generator 3.

[0018] The inverter 6 is configured to include upper and lower arm circuits 9 for three phases. The upper and lower arm circuits 9 are sometimes referred to as legs. Each upper and lower arm circuit 9 has an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side.

[0019] The connection point between the upper arm 9H and the lower arm 9L is connected to the corresponding phase winding 3a of the motor generator 3 via an output line 10. Of the upper and lower arm circuits 9, the U-phase upper and lower arm circuit 9U is connected to the U-phase winding 3a via a corresponding output line 10. The V-phase upper and lower arm circuit 9V is connected to the V-phase winding 3a via a corresponding output line 10. The W-phase upper and lower arm circuit 9W is connected to the W-phase winding 3a via a corresponding output line 10. At least a portion of each of the P line 7, the N line 8, and the output line 10 is formed of a conductive member such as a bus bar.

[0020] The inverter 6 has six arms. Each arm is configured with a switching element. The number of switching elements constituting each arm is not particularly limited. There may be one or more. When there are more than one switching elements, the multiple switching elements connected in parallel are turned on and off at the same timing by a common gate drive signal (drive voltage).

[0021] In this embodiment, an n-channel MOSFET 11 is used as a switching element constituting each arm. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. In the upper arm 9H, the drain of the MOSFET 11 is connected to the P line 7. In the lower arm 9L, the source of the MOSFET 11 is connected to the N line 8. The source of the MOSFET 11 in the upper arm 9H and the drain of the MOSFET 11 in the lower arm 9L are connected to each other.

[0022] A freewheeling diode 12 is connected in antiparallel to each MOSFET 11. The diode 12 may be a parasitic diode (body diode) of the MOSFET 11, or may be provided separately from the parasitic diode. The anode of the diode 12 is connected to the source of the corresponding MOSFET 11, and the cathode is connected to the drain.

[0023] The switching element is not limited to the MOSFET 11. For example, an IGBT may be used. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. In the case of an IGBT, a freewheeling diode is also connected in anti-parallel.

[0024] The inverter 6 includes a snubber circuit 13 in addition to the upper and lower arm circuits 9 described above. The snubber circuit 13 absorbs a transient high voltage that occurs during switching, a so-called switching surge. This enables high-speed switching. The snubber circuits 13 may be provided individually for the upper and lower arm circuits 9 and connected in parallel to the corresponding upper and lower arm circuits 9. The snubber circuits 13 may be provided individually for each arm 9H, 9L and connected in parallel to the corresponding arms 9H, 9L. As an example, the snubber circuits 13 in this embodiment are connected in parallel to the upper and lower arm circuits 9.

[0025] The snubber circuit 13 includes at least a capacitor 131. The snubber circuit 13 may be, for example, a C snubber circuit including the capacitor 131, or an RC snubber circuit including the capacitor 131 and a resistor 132 as shown in Fig. 1. Alternatively, the snubber circuit 13 may be an RCD snubber circuit including the capacitor 131, the resistor 132, and a diode.

[0026] The power conversion device 4 may further include a converter as a power conversion circuit. The converter is a DC-DC conversion circuit that converts a DC voltage, for example, into a DC voltage of a different value. The converter is provided between the DC power supply 2 and the smoothing capacitor 5. The converter is configured with, for example, a reactor and the above-mentioned upper and lower arm circuits 9. This configuration allows for voltage step-up and step-down. The power conversion device 4 may also include a filter capacitor that removes power supply noise from the DC power supply 2. The filter capacitor is provided between the DC power supply 2 and the converter.

[0027] The power conversion device 4 may include a drive circuit for a switching element constituting the inverter 6 or the like. The drive circuit supplies a drive voltage to the gate of the MOSFET 11 of the corresponding arm based on a drive command from the control circuit. The drive circuit drives the corresponding MOSFET 11, i.e., turns it on and off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0028] The power conversion device 4 may include a control circuit for the switching element. The control circuit generates a drive command for operating the MOSFET 11 and outputs it to the drive circuit. The control circuit generates the drive command based on, for example, a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. ECU is an abbreviation for Electronic Control Unit.

[0029] The various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as a drive command. The control circuit is configured with, for example, a processor and a memory. PWM is an abbreviation for Pulse Width Modulation.

[0030] <Semiconductor module> Fig. 2 is a perspective view showing an example of a semiconductor module. Fig. 3 is a top plan view of the semiconductor module shown in Fig. 2. Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 3. Fig. 4 shows a simplified structure of the semiconductor module. The housing is omitted from Fig. 4.

[0031] In the following, the thickness direction of the substrate is referred to as the Z direction, and the direction perpendicular to the Z direction is referred to as the Y direction. The direction perpendicular to both the Z direction and the Y direction is referred to as the X direction. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is referred to as the planar shape. Furthermore, the planar view from the Z direction may sometimes be simply referred to as the planar view.

[0032] 2, 3, and 4, the semiconductor module 20 may include a semiconductor device 21, a housing 22, and a cooler 23. The semiconductor module 20, together with a capacitor device that provides a smoothing capacitor 5, an input terminal block, an output terminal block, and the like, constitutes the power conversion device 4. The semiconductor module 20 may be housed in a case of the power conversion device 4 together with other elements such as the capacitor device.

[0033] The semiconductor device 21 is arranged on one surface of the cooler 23 in the Z direction. The semiconductor device 21 provides at least one arm of the inverter 6, which is a power conversion circuit. Each of the semiconductor devices 21 illustrated in FIG. 2 provides the upper and lower arm circuits 9 for one phase. The semiconductor module 20 includes three semiconductor devices 21 to provide the inverter 6. The three semiconductor devices 21 are arranged on the same surface of the cooler 23 and are aligned in the X direction. Each of the semiconductor devices 21 is fixed to the cooler 23.

[0034] One of the semiconductor devices 21, semiconductor device 21U, provides a U-phase upper and lower arm circuit 9U. Another of the semiconductor devices 21, semiconductor device 21V, provides a V-phase upper and lower arm circuit 9V. Another of the semiconductor devices 21, semiconductor device 21W, provides a W-phase upper and lower arm circuit 9W. In other words, the semiconductor module 20 provides the inverter 6. Details of the semiconductor device 21 will be described later.

[0035] The housing 22 is formed using an electrically insulating material such as resin. The housing 22 may be, for example, a resin molded body. The housing 22 may hold some of the components of the semiconductor device 21. Some of the components of the semiconductor device 21 may be integrally molded with the housing 22 as an insert part. The housing 22 may be fixed to the cooler 23. The housing 22 may be fixed to the case of the power conversion device 4 together with the cooler 23.

[0036] The housing 22 may be arranged on one side of the cooler 23, and together with the cooler 23, may provide an accommodation space 22v (see FIG. 5) for the semiconductor device 21. A seal 90 may be arranged in the accommodation space 22v formed by the housing 22 and the cooler 23. The seal 90 is filled up to a predetermined position lower than the top end of the housing 22.

[0037] The encapsulant 90 encapsulates the elements of the semiconductor device 21. The encapsulant 90 integrally encapsulates a portion of each of the semiconductor element 30, the substrate 40, the clip 50, and the external connection terminal 60. The encapsulant 90 also encapsulates the wire 80 that electrically connects the pad 33 of the semiconductor element 30 to the signal terminal 62. In the example shown in FIG. 5, the encapsulant 90 is made of a fluid material such as gel. A potting resin may be used instead of the gel. The encapsulant 90 may be provided in the semiconductor device 21 or in the semiconductor module 20.

[0038] 2 and 3, the housing 22 may include a frame body 221 and a partition wall 222. The frame body 221 has a predetermined height in the Z direction and is annular so as to surround the semiconductor device 21 in a plan view in the Z direction. The frame body 221 may be referred to as an annular wall portion. The frame body 221 may be an approximately rectangular annular portion. The rectangular annular frame body 221 has four walls 221a, 221b, 221c, and 221d.

[0039] The walls 221a and 221b extend in the X direction. The walls 221a and 221b are arranged opposite each other with a predetermined gap in the Y direction. The wall 221a is arranged on one end side of the semiconductor device 21 in the Y direction, and the wall 221b is arranged on the other end side of the semiconductor device 21. The walls 221a and 221b include walls that define an area and extensions that extend outward from the walls in the Y direction. The walls 221c and 221d extend in the Y direction. The wall 221c is continuous with the walls 221a and 221b at one end side in the X direction. The wall 221d is continuous with the walls 221a and 221b at the other end side in the X direction.

[0040] The partition wall 222 has a predetermined height in the Z direction and is continuous with the frame body 221. The partition wall 222 divides the area defined by the frame body 221 into a plurality of areas. The partition wall 222 may divide the area into areas corresponding to the number of semiconductor devices 21, for example. The partition wall 222 divides the accommodation space 22v into the same number of areas as the number of substrates 40 in the X direction, which is the direction in which the substrates 40 are arranged. The partition wall 222 extends in the Y direction perpendicular to the direction in which the substrates 40 are arranged, and both ends of the partition wall 222 are continuous with the wall portions 221a, 221b of the frame body 221.

[0041] The housing 22 may have two partition walls 222a and 222b as the partition wall 222. The partition walls 222a and 222b and the wall portions 221c and 221d are aligned in the X direction at a predetermined interval. The partition walls 222 divide the opposing area of ​​the frame body 221 into three regions. A semiconductor device 21 is housed in each of the three divided regions. The partition walls 222 are provided between adjacent substrates 40 in the arranging direction of the substrates 40. The partition wall 222a is provided between the substrate 40 constituting the U-phase semiconductor device 21 and the substrate 40 constituting the V-phase semiconductor device 21. The partition wall 222b is provided between the substrate 40 constituting the V-phase semiconductor device 21 and the substrate 40 constituting the W-phase semiconductor device 21. The substrates 40, i.e., the semiconductor devices 21 for each phase, are arranged in the three divided storage spaces 22v.

[0042] The cooler 23 cools the semiconductor devices 21. As illustrated in Fig. 4, the cooler 23 may have a flow path 231 therein. The flow path 231 is provided so as to overlap at least a portion of the semiconductor device 21 in a plan view so as to effectively cool the semiconductor device 21. The flow path 231 may be provided so as to encompass most of each semiconductor device 21 in a plan view.

[0043] The cooler 23 has a base member 233 and a cooling plate 234. The base member 233 and the cooling plate 234 are made of a metal with excellent thermal conductivity, such as aluminum or copper. The cooling plate 234 is attached to the base member 233 and covers an opening 233a of the base member 233. In the example shown in FIG. 3, the cooling plate 234 is fastened to the base member 233 with bolts BT. As shown in FIG. 2, the cooling plate 234 is formed with a plurality of bolt insertion holes 234a into which the bolts BT are inserted.

[0044] The flow path 231 is formed in a space surrounded by a base member 233 and a cooling plate 234. An inlet pipe and an outlet pipe (not shown) are connected to the main body. A refrigerant 232 is supplied to the flow path 231 via the inlet pipe. The refrigerant 232 that has flowed through the flow path 231 is discharged to the outside of the cooler 23 via the outlet pipe. As the refrigerant 232, a phase-change refrigerant such as water or ammonia, or a phase-non-change refrigerant such as an ethylene glycol-based refrigerant can be used. The cooler 23 is not limited to the configuration having the flow path 231 described above. A heat dissipation member such as a heat sink may also be used as the cooler 23. The heat dissipation member may include heat dissipation fins.

[0045] 4, a bonding material 24 is interposed between the semiconductor device 21 and the cooler 23. Specifically, the bonding material 24 is interposed between the conductor 43 and the cooling plate 234. As the bonding material 24, solder, a sintered member, or the like can be used.

[0046] The semiconductor module 20 includes a bonding material 24 disposed between the semiconductor device 21 and the cooler 23. The semiconductor device 21 is fixed to the cooler 23 by bonding. If insulation is required, an electrically insulating member may be disposed between the semiconductor device 21 and the cooler 23. For example, a ceramic plate or a resin sheet may be used as the insulating member. A TIM such as silicon gel may be used to improve thermal conductivity. TIM is an abbreviation for Thermal Interface Material.

[0047] The semiconductor module 20 may include a circuit board (not shown). The drive circuit described above is formed on the circuit board. The circuit board is arranged above the semiconductor device 21 in the Z direction. The semiconductor module 20 may include a cover that provides a case together with the housing 22 and the cooler 23. The cover is arranged on the opposite side of the semiconductor device 21 from the cooler 23. The cover may be arranged to cover the three semiconductor devices 21 as a whole.

[0048] <Semiconductor device> As described above, the semiconductor device 21 may provide one phase of upper and lower arm circuits 9. As illustrated in Figures 4, 5, and 6, the semiconductor device 21 may include a semiconductor element 30, a substrate 40, a clip 50, and an external connection terminal 60.

[0049] The semiconductor element 30 is a vertical element formed on a semiconductor substrate made of silicon (Si) or a wide bandgap semiconductor with a wider bandgap than silicon. Wide bandgap semiconductors include, for example, silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. The semiconductor element 30 may also be called a power element or a semiconductor chip.

[0050] The vertical element is configured to pass a main current in the thickness direction of the semiconductor element 30 (semiconductor substrate). The semiconductor element 30 is disposed so that its thickness direction is approximately parallel to the Z direction. The semiconductor element 30 has main electrodes on both sides in the thickness direction. The semiconductor element 30 of this embodiment is formed by forming an n-channel MOSFET 11 as a vertical element on a semiconductor substrate made of SiC. As shown in FIG. 4, the semiconductor element 30 has a drain electrode 31 on its lower surface facing the substrate 40 and a source electrode 32 on its upper surface opposite the lower surface, as main electrodes.

[0051] When the MOSFET 11 is turned on, a current (main current) flows between the main electrodes, that is, between the drain electrode 31 and the source electrode 32. If the diode 12 is a parasitic diode, the source electrode 32 also serves as the anode electrode, and the drain electrode 31 also serves as the cathode electrode. The diode 12 may be formed on a chip separate from the MOSFET 11. The drain electrode 31 is a main electrode on the high potential side, and the source electrode 32 is a main electrode on the low potential side. The drain electrode 31 is formed on almost the entire bottom surface. The source electrode 32 is formed on a part of the top surface.

[0052] The semiconductor element 30 has a generally rectangular shape in plan view. The semiconductor element 30 has, on its upper surface, pads 33 (see FIG. 5) which are electrodes for signals. The pads 33 are formed at positions on the upper surface different from the source electrodes 32. The pads 33 include at least a gate pad.

[0053] As shown in FIG. 3, the multiple semiconductor elements 30 include a semiconductor element 30H that constitutes an upper arm 9H and a semiconductor element 30L that constitutes a lower arm 9L. The semiconductor element 30H may be referred to as an upper arm element. The semiconductor element 30L may be referred to as a lower arm element. For example, the semiconductor elements 30H and 30L may have a common configuration. The semiconductor elements 30H and 30L are aligned in the Y direction.

[0054] The number of each of the semiconductor elements 30H, 30L is not particularly limited. There may be one of each, or multiple of each. In the example shown in FIGS. 2 and 3, the semiconductor element 30 includes four of each of the semiconductor elements 30H, 30L. The four semiconductor elements 30H are connected in parallel to provide the MOSFET 11 of the upper arm 9H of one phase. The four semiconductor elements 30L are connected in parallel to provide the MOSFET 11 of the lower arm 9L of one phase. The four semiconductor elements 30H are lined up in the X direction. The four semiconductor elements 30L are lined up in the X direction.

[0055] The substrate 40 contains all of the semiconductor elements 30 (30H, 30L) in a plan view. The substrate 40 is disposed on the drain electrode 31 side of the semiconductor elements 30. As will be described later, the substrate 40 is electrically connected to the drain electrode 31 and provides a wiring function. The substrate 40 may also be called a wiring board, a printed circuit board, or the like.

[0056] The substrate 40 has an insulating base material 41 and a conductor disposed on the insulating base material 41. The insulating base material 41 is formed using an electrically insulating material such as ceramic or resin. As shown in FIG. 4, the insulating base material 41 has one surface 41a that faces the semiconductor element 30 and a back surface 41b that is the surface opposite to the one surface 41a in the Z direction. The substrate 40 may be divided into units of semiconductor devices 21, or may be integrated into units of semiconductor modules 20.

[0057] The conductor is made of a metal such as Cu or Al that has good electrical and thermal conductivity. The conductor may have a plating film of Ni, Au, or the like on its surface. The conductor may be disposed on only one surface 41a of the insulating substrate 41, or on both the one surface 41a and the back surface 41b. The conductor may be disposed inside the insulating substrate 41. In other words, the substrate 40 may be a single-sided substrate, a double-sided substrate, or a multilayer substrate having three or more layers of conductors. The conductor may include a via conductor. The via conductor is formed by disposing a conductor such as plating in a through hole (via) formed in an insulating layer that constitutes the insulating substrate 41. The via conductor electrically connects conductors disposed on different layers.

[0058] The substrate 40 has conductors 42 arranged on one surface 41a. The conductors 42 are patterned. The patterned conductors 42 provide wiring, i.e., circuits. The conductors 42 include P wiring 421, N wiring 422, and O wiring 423. Each wiring is electrically separated by a predetermined interval (gap). The substrate 40 has conductors 43 arranged on the back surface 41b.

[0059] The P wiring 421 is connected to the drain electrode 31 of the semiconductor element 30H. The P wiring 421 is connected to a P terminal 611, which will be described later. The P wiring 421 electrically connects the drain electrode 31 of the semiconductor element 30H and the P terminal 611. The P wiring 421 may be referred to as a positive wiring, a high potential power supply wiring, or the like.

[0060] The N wiring 422 is connected to the N terminal 612. The source electrode 32 of the semiconductor element 30L is electrically connected to the N wiring 422 via the clip 50L. The N wiring 422 electrically connects the source electrode 32 of the semiconductor element 30L and the N terminal 612. The N wiring 422 may be referred to as a negative wiring, a low potential power supply wiring, or the like.

[0061] The O wiring 423 is connected to the drain electrode 31 of the semiconductor element 30L. The O wiring 423 is connected to an O terminal 613, which will be described later. The source electrode 32 of the semiconductor element 30H is electrically connected to the O wiring 423 via a clip 50H. The O wiring 423 electrically connects the source electrode 32 of the semiconductor element 30H, the drain electrode 31 of the semiconductor element 30L, and the O terminal 613. The O wiring 423 may be referred to as an output wiring, etc.

[0062] The clip 50 may also be referred to as a bridging member, a relay member, a metal bridge, etc. The clip 50 is a metal plate material whose base material is a metal with good conductivity, such as Cu or a Cu alloy. The clip 50 may be formed by punching out a metal plate of a predetermined thickness and then pressing it.

[0063] The clips 50 include a clip 50H connected to the semiconductor element 30H and a clip 50L connected to the semiconductor element 30L. The clip 50H electrically connects the source electrode 32 of the semiconductor element 30H to the O wiring 423. The clips 50H extend in the Y direction. The clips 50H may be provided individually for each semiconductor element 30H, or may be provided collectively for multiple semiconductor elements 30H. As shown in FIG. 3 and other figures, one clip 50H may be provided for two semiconductor elements 30H. The semiconductor device 21 includes two clips 50H. Each of the clips 50H has a substantially Y-shape in plan view.

[0064] The clip 50L electrically connects the source electrode 32 of the semiconductor element 30L and the N wiring 422. The clip 50L extends in the Y direction. The clip 50L may be provided individually for each semiconductor element 30L, or may be provided collectively for multiple semiconductor elements 30L. In the example shown in FIG. 3 etc., the clip 50L is provided individually for each semiconductor element 30L. The semiconductor device 21 includes four clips 50L.

[0065] The solder 81 joins the source electrode 32 to the clip 50H. The solder 81 joins the O wiring 423 to the clip 50H. The sintered member 82 joins the drain electrode 31 to the O wiring 423. The sintered member 82 further joins the drain electrode 31 to the P wiring 421. The sintered member 82 is made of Ag or Cu, and can be bonded at a lower temperature than solder.

[0066] The external connection terminals 60 are terminals for electrically connecting the semiconductor device 21 to external devices. The external connection terminals 60 are formed using a metal material with good conductivity, such as copper. The external connection terminals 60 are, for example, a plate material. The external connection terminals 60 include a main terminal 61 and a signal terminal 62. The main terminal 61 is a terminal electrically connected to a main electrode of the semiconductor element 30. The signal terminal 62 is a terminal electrically connected to a pad 33 (see FIG. 5 ) of the semiconductor element 30. The main terminals 61 include a P terminal 611 and an N terminal 612, which are power supply terminals, and an O terminal 613. The P terminal 611 corresponds to a first main terminal, and the N terminal 612 corresponds to a second main terminal.

[0067] The P terminal 611 is an external connection terminal 60 electrically connected to the P line 7. The P terminal 611 is electrically connected to the positive terminal of the smoothing capacitor 5. The P terminal 611 may also be referred to as a positive terminal, a high-potential power supply terminal, or the like. The P terminal 611 is connected to the terminal connection portion 421c of the P wiring 421. The P terminal 611 is electrically connected via the P wiring 421 to the drain electrode 31 of the semiconductor element 30H that constitutes the upper arm 9H.

[0068] As shown in FIGS. 2 and 3, P terminal 611 has a connection portion 611a for connecting to an external device and a connection portion 611b for connecting to board 40. P terminal 611 extends generally in the Y direction. One of the Y-direction ends of P terminal 611 forms connection portion 611a, and the other Y-direction end forms connection portion 611b. In the example shown in FIG. 2 and other figures, a portion of P terminal 611 is held by frame 221 of housing 22. Connection portion 611a of P terminal 611 protrudes outward from wall portion 221a of frame 221, and connection portion 611b protrudes inward from wall portion 221a, i.e., toward the partitioned area. Connection portion 611b is connected to P wiring 421. Smoothing capacitor 5 is connected to connection portion 611a, for example, via a bus bar.

[0069] The N terminal 612 is an external connection terminal 60 electrically connected to the above-described N line 8. The N terminal 612 is electrically connected to the negative terminal of the smoothing capacitor 5. The N terminal 612 may also be referred to as a negative terminal, a low-potential power supply terminal, or the like. The N terminal 612 is connected to the terminal connection portion 422c of the N wiring 422. The N terminal 612 is electrically connected to the source electrode 32 of the semiconductor element 30L constituting the lower arm 9L via the N wiring 422 and the clip 50L.

[0070] The N terminal 612 has a connection portion 612a with an external device and a connection portion 612b with the substrate 40. The N terminal 612 extends generally in the Y direction. One of the Y-direction ends of the N terminal 612 forms the connection portion 612a, and the other end forms the connection portion 612b. In this embodiment, as an example, a portion of the N terminal 612 is held by the frame 221 of the housing 22. The connection portion 612a of the N terminal 612 protrudes outward from the wall portion 221a of the frame 221, and the connection portion 612b protrudes inward from the wall portion 221a. The connection portion 612b is connected to the N wiring 422. The smoothing capacitor 5 is connected to the connection portion 612a, for example, via a bus bar or the like.

[0071] The O terminal 613 is an external connection terminal 60 electrically connected to the output line 10. The O terminal 613 is electrically connected to the winding 3a of the opposing phase of the motor generator 3. The O terminal 613 may also be referred to as an output terminal, an AC terminal, or the like. The semiconductor module 20 includes, as the O terminals 613, a U-phase O terminal 613U, a V-phase O terminal 613V, and a W-phase O terminal 613W.

[0072] The O terminal 613 is connected to the O wiring 423. The O terminal 613 is electrically connected to the drain electrode 31 of the semiconductor element 30L that constitutes the lower arm 9L via the O wiring 423. The O terminal 613 is electrically connected to the source electrode 32 of the semiconductor element 30H that constitutes the upper arm 9H via the O wiring 423 and the clip 50H.

[0073] The O terminal 613 has a connection portion 613a for connecting to an external device and a connection portion 613b for connecting to the board 40. The O terminal 613 extends generally in the Y direction. One of the Y-direction ends of the O terminal 613 forms the connection portion 613a, and the other of the Y-direction ends forms the connection portion 613b. In this embodiment, as an example, a portion of the O terminal 613 is held by the frame 221 of the housing 22. The connection portion 613a of the O terminal 613 protrudes outward from the wall portion 221b of the frame 221, and the connection portion 613b protrudes inward from the wall portion 221b. The connection portion 613b is connected to the O wiring 423. The motor generator 3 is connected to the connection portion 613a via, for example, a bus bar.

[0074] The signal terminals 62 electrically connect the semiconductor element 30 to a circuit board (not shown). The signal terminals 62 are electrically connected to the pads 33 of the semiconductor element 30 via connecting members such as wires 80 (see FIG. 5). The number of signal terminals 62 is not particularly limited. The signal terminals 62 only need to include at least a terminal for applying a drive voltage to the gate electrode of the semiconductor element 30. The signal terminals 62 may include a terminal for detecting the source potential of the semiconductor element 30. The signal terminals 62 may include a terminal for detecting the drain potential of the semiconductor element 30. The signal terminals 62 may include a terminal for detecting the temperature of the semiconductor element 30.

[0075] 2 and other examples, a portion of the signal terminal 62 is held by the walls 221b, 221c and the partition walls 222a, 222b of the frame body 221. The signal terminal 62 on the upper arm 9H side is held by the frame body 221 and the partition wall 222. For example, the U-phase signal terminal 62 is held by the wall 221c of the frame body 221. The V-phase signal terminal 62 is held by the partition wall 222a, and the W-phase signal terminal 62 is held by the partition wall 222b. The signal terminal 62 of the lower arm 9L is held by the wall 221b of the frame body 221.

[0076] <Snubber circuit> As shown in FIGS. 1 and 7, snubber circuit 13 electrically bridges P wiring 421 and N wiring 422. P wiring 421 corresponds to the first wiring, and N wiring 422 corresponds to the second wiring. Snubber circuit 13 has capacitor 131 and resistor 132 connected in series. As shown in FIG. 7, which is an equivalent circuit of FIG. 1, capacitor 131 may be multiple capacitors C1 and C2 connected in parallel. Capacitor C1 corresponds to the first capacitor, and capacitor C2 corresponds to the second capacitor.

[0077] Capacitor 131 is a chip capacitor and is surface-mounted on substrate 40. Capacitor 131 has a main body and terminals. The main body is configured by sealing electrodes and dielectrics inside a resin. These electrodes and dielectrics correspond to functional elements. Ceramic is used for the dielectric, and multiple dielectrics are stacked. The terminals are electrically connected to the electrodes of the main body. The portion of the terminal exposed from the main body is connected to conductor 42 (wiring) on ​​substrate 40 by solder. Chip-type capacitor 131 is cubic. Capacitor 131 may also be a through-mount type in which the terminals are lead wires.

[0078] The resistor 132 may be a plurality of resistors R11, R21, R12, and R22 connected to each other. The resistors R11 and R21 are connected in series, and the resistors R12 and R22 are connected in series. The resistors R11 and R12 are connected in parallel, and the resistors R21 and R22 are connected in parallel. The resistors R11 and R12 correspond to a first resistor, and the resistors R21 and R22 correspond to a second resistor. In short, the first resistor and the second resistor are connected in series.

[0079] The resistor 132 is a chip resistor and is surface-mounted on the substrate 40. The resistor 132 has a main body and a pair of terminals. The main body is configured by sealing a resistive element (functional element) inside a resin. The pair of terminals are electrically connected to the resistive element in the main body. The portion of the pair of terminals exposed from the main body is connected to the conductor 42 of the substrate 40 by soldering. The chip-type resistor 132 has a cubic shape. The resistor 132 may also be a through-mount type in which the terminals are lead wires.

[0080] 6 and 8, relay wiring 424 is provided in a portion of insulating substrate 41 sandwiched between P wiring 421 and N wiring 422. A capacitor 131 and resistors R11 and R12 are connected to one relay wiring 424. Resistors R11 and R12 and resistors R21 and R22 are connected to one relay wiring 424. Relay wiring 424 corresponds to a third wiring separate from P wiring 421 (first wiring) and N wiring 422 (second wiring).

[0081] <Summary of the First Embodiment> In the semiconductor device 21 according to this embodiment, the resistor 132 of the snubber circuit 13 includes a first resistor (resistors R11 and R12) and a second resistor (resistors R21 and R22) connected in series with each other. The effects of this configuration will be described below.

[0082] There is a concern that capacitor 131 of snubber circuit 13 may short-circuit due to various causes, such as repeated application of an overvoltage when an internal defect exists. If capacitor 131 short-circuits, snubber circuit 13 may short-circuit P wiring 421 and N wiring 422, causing other related components to fail. In other words, there is a concern that the failure of capacitor 131 may escalate to failures of related components.

[0083] To address this concern, in this embodiment, the resistor 132 of the snubber circuit 13 is divided into multiple resistors R11 to R22. The divided first resistors R11 and R12 and the divided second resistors R21 and R22 are connected in series. This allows the resistance of each of the multiple resistors to be small. As a result, when the capacitor 131 short-circuits and a high voltage is applied to the resistor 132, the possibility of one resistor melting and causing an open circuit failure is increased. Furthermore, the time from the short-circuit failure of the capacitor 131 to the open circuit failure of the resistor 132 can be shortened. In other words, even if the capacitor 131 short-circuits, one of the multiple resistors R11 to R22 instantly fails open. This reduces the risk that the short-circuit failure of the capacitor 131 will escalate to failures in related components.

[0084] Furthermore, in this embodiment, since the resistor 132 is divided into a plurality of resistors R11 to R22, the amount of heat generated in the resistor 132 due to current flow during normal operation when the capacitor 131 is not broken is distributed among the plurality of resistors R11 to R22. This reduces the risk of thermal damage to the resistors R11 to R22 during normal operation.

[0085] Furthermore, in this embodiment, the first resistor includes multiple resistors R11 and R12 connected in parallel. The second resistor includes multiple resistors R21 and R22 connected in parallel. This allows for more efficient dispersion of heat generation during normal operation than when there is only one first resistor and one second resistor. This further reduces the risk of thermal damage to the resistors R11 to R22 during normal operation. Furthermore, in this embodiment, the number of first resistors is the same as the number of second resistors. This facilitates component sharing for the multiple resistors R11 to R22. Note that in this embodiment, the snubber circuit 13 will not experience an open circuit fault until all of the multiple resistors R11 and R12 included in the first resistor experience an open circuit fault. Similarly, the snubber circuit 13 will not experience an open circuit fault until all of the multiple resistors R21 and R22 included in the second resistor experience an open circuit fault.

[0086] Furthermore, in this embodiment, the capacitor 131 includes a first capacitor C1 and a second capacitor C2 connected in parallel to each other. The resistor 132 includes a first resistor and a second resistor connected in series to the first capacitor C1, and a first resistor and a second resistor connected in series to the second capacitor C2. With this, even if one of the first capacitor C1 and the second capacitor C2 fails due to a short circuit, the other continues to function as the snubber circuit 13, thereby achieving redundancy for the snubber circuit 13. Furthermore, an increase in the number of resistors can promote the dispersion of heat generated during normal operation, as described above, and further reduce the risk of thermal damage to the resistors R11 to R22 during normal operation.

[0087] <Modification of the first embodiment> As shown in FIG. 9, the first resistor may be three resistors R11, R12, and R13, and the second resistor may be one resistor R21. That is, one of the first resistor and the second resistor may include multiple resistors R11, R12, and R13 connected in parallel. The other of the first resistor and the second resistor may not include any resistors connected in parallel. In this case, the smaller of the first resistor and the second resistor can be quickly detected as an open circuit when a short circuit occurs in the capacitor 131. In FIG. 9, the resistor R21 surrounded by the dotted line can be quickly detected as an open circuit. Note that all of the resistors R11, R12, R13, and R21 shown in FIG. 9 are the same size.

[0088] As shown in FIG. 10, the first resistors may be two resistors R11 and R12, and the second resistors R21 and R22 may be arranged in separate current paths. That is, even if the number of first resistors and second resistors is the same, one of the first resistors and the second resistor is connected in parallel, while the other is not. In this case, the resistor with the fewer parallel connections can be quickly faulted open in the event of a short circuit in the capacitor 131. In the case of FIG. 10, the resistors R21 and R22 enclosed by the dotted line can be quickly faulted open. Note that all resistors R11, R12, R21, and R22 shown in FIG. 10 are the same size.

[0089] As shown in Fig. 11, two first capacitors C1 may be provided. In this case, even if one of the first capacitors C1 experiences a short-circuit failure and the resistors R11 and R21 experience an open-circuit failure, the other first capacitor C1 and resistors R12 and R22 function normally. This improves the redundancy of the snubber circuit 13, reducing the loss of symmetry of the current paths on the substrate 40. Note that all of the resistors R11, R12, R21, and R22 shown in Fig. 11 have the same capacitance.

[0090] As shown in FIG. 12, the snubber circuit 13 may include a wire W in addition to the first resistors R11, R12 and the second resistors R21, R22. The wire W is connected in series to the first resistors R11, R12 and the second resistors R21, R22. A plurality of wires W are provided, and the plurality of wires W are connected in parallel. The first resistors R11, R12 and the second resistors R21, R22 are chip resistors. The electrical resistance of one wire W is greater than the electrical resistance of one chip resistor included in the first resistors R11, R12 and the second resistors R21, R22. This can be expected to cause the wire W to melt and become open when a short-circuit fault occurs in the capacitor 131.

[0091] In the example shown in FIG. 13, a wire R2W is used for the second resistor. In other words, the resistors R21 and R22 shown in FIG. 8 are replaced with the wire R2W. A plurality of wires R2W are provided, and the plurality of wires R2W are connected in parallel. The electrical resistance of one wire R2W is greater than the electrical resistance of one chip resistor included in the first resistors R11 and R12. This can be expected to cause the wire R2W to melt and become open when a short-circuit fault occurs in the capacitor 131.

[0092] When the first resistor and the second resistor each include multiple resistors connected in parallel, the number of resistors included in the first resistor and the number of resistors included in the second resistor may be the same or different.

[0093] (Second embodiment) The semiconductor device according to this embodiment is based on the semiconductor device 21 according to the first embodiment, and has the following additional configuration.

[0094] As shown in FIG. 14 , the semiconductor device may include a monitor terminal 63. The monitor terminal 63 is connected to a relay wiring 424. The relay wiring 424 corresponds to a third wiring. The monitor terminal 63 detects the potential between the capacitor 131 and the resistor 132. The monitor terminal 63 is connected to an external device and outputs a signal of the detected potential. The monitor terminal 63 is arranged in a row together with a P terminal 611 and an N terminal 612. The external device is, for example, a computer. Based on the signal output from the monitor terminal 63, the computer determines whether or not an open circuit fault has occurred in the resistor 132 due to a short circuit fault in the capacitor 131.

[0095] 15, monitor terminal 63 may have a shape that extends perpendicularly to one surface 41a of insulating substrate 41 from the connection point with relay wiring 424. The computer described above that acquires signals from monitor terminal 63 is mounted on a control board (not shown). This control board is disposed in a position facing board 40. Monitor terminal 63 has a shape that extends perpendicularly to board 40 and control board. One end of monitor terminal 63 is connected to board 40, and the other end of monitor terminal 63 is connected to the control board.

[0096] As described above, according to this embodiment provided with the monitor terminal 63, it is possible to determine whether or not the resistor 132 is in an open fault state.

[0097] (Third embodiment) The semiconductor device according to this embodiment is based on the semiconductor device 21 according to the first embodiment, and has the following additional configuration.

[0098] As shown in FIGS. 16 and 17 , the capacitor 131 has a main body 1314 and lead terminals 1313. The main body 1314 is configured by sealing a dielectric 1311 (functional element) and an electrode 1312 (functional element) inside a sealing resin. The dielectric 1311 is disposed between a pair of electrodes 1312. A lead terminal 1313 is connected to each of the pair of electrodes 1312. The dielectric 1311 and the electrode 1312 are sealed with a sealing resin. A portion of the lead terminal 1313 is exposed from the sealing resin. One of the pair of lead terminals 1313 is connected to a P wiring 421 or an N wiring 422. The other of the pair of lead terminals 1313 is connected to a relay wiring 424. The electrode 1312 and the dielectric 1311 correspond to the functional element.

[0099] The lead terminal 1313 is provided with a small section 1313a. The small section 1313a has a shape in which the cross-sectional area is reduced in part so that the electrical resistance of the current flowing through the lead terminal 1313 is locally increased. The electrical resistance (i.e., cross-sectional area) of the small section 1313a is set so that the small section 1313a will melt down due to the current flowing in response to a short-circuit fault in the capacitor 131. The electrical resistance of the small section 1313a is set to be greater than the electrical resistance of one of the chip resistors included in the first resistors R11 and R12 and the second resistors R21 and R22.

[0100] As described above, capacitor 131 according to this embodiment is provided with fusing portion 1313a in lead terminal 1313. This makes it possible to expect that portion 1313a will fuse and become open in the event of a short-circuit fault in capacitor 131. Note that as long as capacitor 131 is provided with portion 1313a according to this embodiment, either the first resistor or the second resistor may be eliminated.

[0101] In this embodiment, a configuration in which the lead terminal 1313 is provided with the detailed portion 1313a is combined with a configuration in which the resistor 132 of the snubber circuit 13 includes the first resistor and the second resistor. On the other hand, if the configuration in which the lead terminal 1313 is provided with the detailed portion 1313a is employed, the configuration in which the resistor 132 of the snubber circuit 13 includes the first resistor and the second resistor does not need to be employed.

[0102] (Fourth embodiment) In the semiconductor device 21 according to this embodiment, the configuration of the semiconductor device 21 according to the first embodiment is assumed, but the arrangement of the resistors 132 shown in Fig. 8 is changed to the arrangement shown in Fig. 18. The following describes the changes of this embodiment compared to the first embodiment, and configurations that are not particularly described are the same as those of the first embodiment.

[0103] The four resistors R11, R21, R12, and R22 included in the resistor 132 are arranged in order in the Y direction. The resistor R11 corresponds to the first electronic component, the resistor R21 corresponds to the second electronic component, the resistor R12 corresponds to the third electronic component, and the resistor R22 corresponds to the fourth electronic component.

[0104] The resistors R11 and R12 are located at the same position in the X direction, and the resistors R21 and R22 are located at the same position in the X direction. The resistors R11 and R21 are located at positions offset from each other in the X direction. The resistors R12 and R22 are also located at positions offset from each other in the X direction. In short, the four resistors 132 are arranged in the Y direction with their X direction positions alternately offset.

[0105] As shown in FIGS. 19 and 20, tunnel portions T1, T2, T3, and T4, which are tunnel-shaped spaces, exist between the resistor 132 and the substrate 40. These tunnel portions are shaped to penetrate in one direction. In the example shown in FIG. 18, the tunnel portions penetrate in the Y direction. Portions of the encapsulant 90 are filled into these tunnel portions. The arrows shown in FIGS. 18 and 19 indicate examples of the direction in which the encapsulant 90 flows into the tunnel portions during the filling process.

[0106] As described above in the first embodiment, the resistor 132 is a chip resistor and is surface-mounted on the substrate 40. The resistor 132 has a main body 1321 and a pair of terminals 1323. The main body is configured by sealing a resistive element 1322 (functional element) inside a resin. The pair of terminals 1323 are electrically connected to the resistive element 1322 of the main body 1321. Portions of the pair of terminals 1323 exposed from the main body 1321 are connected to the conductor 42 of the substrate 40 by soldering.

[0107] Tunnel portions T1, T2, T3, and T4 are spaces surrounded by a pair of terminals 1323, main body portion 1321, and substrate 40. The portions of substrate 40 that form the tunnel portions are conductor 42 to which terminal 1323 is connected, and insulating base material 41. Resistors R21 and R22 are connected across N wiring 422 (second wiring) and relay wiring 424 (third wiring). Resistors R11 and R12 are connected across two relay wirings 424 (third wiring). The portions of N wiring 422 and relay wiring 424 to which resistor 132 is connected have shapes that extend linearly in the Y direction.

[0108] For example, the Z-direction dimension obtained by adding the thickness of terminal 1323 to the thickness of relay wiring 424 is the Z-direction length (height) of the tunnel portion. In other words, the Z-direction distance between the bottom surface of main body 1321 and surface 41a of insulating substrate 41 corresponds to the height of the tunnel portion. The Y-direction length of resistor 132, i.e., the Y-direction length of main body 1321, corresponds to the Y-direction length of the tunnel portion.

[0109] The tunnel portion T1 formed by the resistor R11 corresponds to the first tunnel portion, the tunnel portion T2 formed by the resistor R21 corresponds to the first tunnel portion, the tunnel portion T3 formed by the resistor R12 corresponds to the third tunnel portion, and the tunnel portion T4 formed by the resistor R22 corresponds to the fourth tunnel portion.

[0110] Of the multiple resistors 132, the resistor R21 is located closest to the through-hole exit Tout of the tunnel portion T1. The resistor R12 is located closest to the through-hole exit Tout of the tunnel portion T2. ​​The resistor R22 is located closest to the through-hole exit Tout of the tunnel portion T3. When the flow of the sealing body 90 is in the opposite direction to the arrow shown in FIG. 18, it can be said that the resistor R21 is located closest to the through-hole entrance Tin of the tunnel portion T1. It can be said that the resistor R12 is located closest to the through-hole entrance Tin of the tunnel portion T2. ​​It can be said that the resistor R22 is located closest to the through-hole entrance Tin of the tunnel portion T3.

[0111] 21, the range of the tunnel portion T1 projected in the penetration direction of the tunnel portion T1 corresponds to a first projection range A1. The range of the tunnel portion T2 projected in the penetration direction of the tunnel portion T2 corresponds to a second projection range A2. The range of the resistor R11 projected in the penetration direction corresponds to a first range B1, and the range of the resistor R21 projected in the penetration direction corresponds to a second range B2.

[0112] The entire resistor R21 and the entire resistor R22 are located outside the first projection range A1. The entire resistor R11 and the entire resistor R12 are located outside the second projection range A2. The tunnel portion T3 extends parallel to the tunnel portion T1. At least a portion of the tunnel portion T3 is located in the first projection range A1. For example, in the example of FIG. 21, the entire tunnel portion T3 is located in the first projection range A1. The tunnel portion T4 extends parallel to the tunnel portion T2. ​​At least a portion of the tunnel portion T4 is located in the second projection range A2. For example, in the example of FIG. 21, the entire tunnel portion T4 is located in the second projection range A2. A portion of the resistor R21 and a portion of the resistor R22 are located in the first range B1. A portion of the resistor R11 and a portion of the resistor R12 are located in the second range B2.

[0113] A DESAT terminal may be connected to the P wiring 421 or the N wiring 422. The DESAT terminal is a terminal for overcurrent protection. If the voltage or current value at the DESAT terminal becomes excessive, overcurrent protection is achieved by, for example, limiting the output from the semiconductor device 21. The DESAT terminal differs from the signal terminal 62 in that a high voltage is applied to the DESAT terminal. One end of a wire is connected to the DESAT terminal, and the other end of the wire is connected to the conductor 42. The portion of the conductor 42 to which the other end of the wire is connected is called the DESAT wire outlet area. The DESAT outlet area is located between the resistor 132 and the semiconductor element 30 in the Y direction.

[0114] <Summary of the Fourth Embodiment> In the semiconductor device 21 according to this embodiment, the resistor R21 (second electronic component) closest to the resistor R11 (first electronic component) is located outside the first projection range A1. If, contrary to this embodiment, the resistor R21 were located within the first projection range A1 and the tunnel portion T2 were also located within the first projection range A1, the entrance of the tunnel portion T2 would be located immediately adjacent to the exit of the tunnel portion T1. In this case, the flow resistance when the sealing body 90 is filled into the tunnel portions T1 and T2 would be equivalent to two tunnel lengths. This raises the concern that voids not filled with the sealing body 90 may be formed in the tunnel portions T1 and T2. In this case, there is a concern that the unsealed portion of the resistor R11 may be oxidized by air and deteriorate.

[0115] To address this concern, in this embodiment, the resistor R21 is positioned outside the first projection range A1. This prevents the resistor R21 from being positioned immediately adjacent to the exit of the tunnel portion T1. This prevents the resistor R21 from interfering with the smooth flow of the sealing body 90 into the tunnel portion T1. This reduces the concern that the void will be formed in the tunnel portion T1.

[0116] Here, if the four resistors 132 shown in FIG. 18 are replaced with one resistor, the resulting resistor will be larger than the resistor 132. In this case, heat generated by current flow through a resistor is concentrated in the single resistor, which is disadvantageous in terms of heat dissipation. In contrast, according to this embodiment, in which the resistance of the snubber circuit 13 is configured with multiple resistors 132, heat is dispersed, which is advantageous in terms of heat dissipation. However, when multiple resistors 132 are configured, if the resistors 132 are arranged so that the tunnel portions are continuously connected, as opposed to this embodiment, there is a concern that the flow resistance of the sealing body 90 will increase. Therefore, in this embodiment, the multiple resistors 132 are arranged so that the multiple tunnel portions are not continuously connected, thereby suppressing the above-mentioned concern of increased flow resistance. Furthermore, as a result of arranging the multiple tunnel portions so that they are not continuously connected, the distance between the first electronic component and the second electronic component increases, which also promotes heat dissipation.

[0117] Furthermore, in this embodiment, a portion of the resistor R21 (second electronic component) is located in a first range B1 when the resistor R11 (first electronic component) is projected in the penetration direction. In other words, a portion of the mounting space for the resistor R21 overlaps with the mounting space for the resistor R11 in the X direction. This allows the mounting space for the two resistors R11 and R21 to be reduced in the X direction. In other words, the reliability of filling with the sealing body 90 can be improved while miniaturizing the semiconductor device 21 in the X direction.

[0118] Furthermore, in this embodiment, the tunnel portion T3 of the resistor R12 (third electronic component) is located within the first projection range A1. Here, the resistor R21 is located between the resistors R11 and R12. Therefore, even if the tunnel portion T3 is located within the first projection range A1, the distance L1 (see FIG. 18) between the exit of the tunnel portion T1 and the entrance of the tunnel portion T3 is sufficiently long. Therefore, the flow resistance when the sealing body 90 is filled into the tunnel portion T1 is not twice the tunnel length. In other words, the tunnel portion T3 of the resistor R12 does not hinder the smooth flow of the sealing body 90 into the tunnel portion T1. Nevertheless, the mounting space for the resistor R11 overlaps with the mounting space for the resistor R12 in the X direction. This allows the semiconductor device 21 to be miniaturized in the X direction while improving the reliability of filling with the sealing body 90.

[0119] Furthermore, in this embodiment, the tunnel portion T4 of the resistor R22 (fourth electronic component) is located within the second projection range A2. Here, the resistor R12 is located between the resistors R21 and R22. Therefore, even if the tunnel portion T4 is located within the second projection range A2, the distance L2 (see FIG. 18 ) between the exit of the tunnel portion T2 and the entrance of the tunnel portion T4 is sufficiently long. Therefore, the flow resistance when the sealing body 90 is filled into the tunnel portion T2 is not twice the tunnel length. In other words, the tunnel portion T4 of the resistor R22 does not hinder the smooth flow of the sealing body 90 into the tunnel portion T2. ​​Even so, the mounting space for the resistor R21 overlaps with the mounting space for the resistor R22 in the X direction. This allows the semiconductor device 21 to be miniaturized in the X direction while improving the reliability of filling with the sealing body 90.

[0120] <Modification of the Fourth Embodiment> In the fourth embodiment, the penetration direction of the tunnel portion T1 and the penetration direction of the tunnel portion T2 are parallel to each other. In contrast, as shown in Fig. 22, the penetration direction of the tunnel portion T1 and the penetration direction of the tunnel portion T2 may be non-parallel to each other. In the example of Fig. 22, two adjacent resistors R11 and R21 are arranged so that their penetration directions are perpendicular to each other.

[0121] In the fourth embodiment, two adjacent resistors R11 and R21 and two adjacent resistors R12 and R22 share the relay wiring 424. However, as shown in FIG. 23 , the relay wiring 424 connected to the resistors R11 and R21 and the relay wiring 424 connected to the resistors R12 and R22 may be different wirings.

[0122] In the fourth embodiment, the four resistors R11, R21, R12, and R22 arranged in one direction are arranged with their X-direction positions shifted alternately, as shown in FIG. 18 . That is, the X-direction positions of all adjacent resistors 132 are shifted from each other. In contrast, as shown in FIG. 24 , it is sufficient that the X-direction positions of at least two adjacent resistors 132 are shifted from each other. In the example of FIG. 24 , the X-direction positions of the tunnel portion T2 and the tunnel portion T3 are shifted from each other. In this case, the X-direction positions of the tunnel portion T1 and the tunnel portion T2 may be the same. Furthermore, the X-direction positions of the tunnel portion T3 and the tunnel portion T4 may be the same. Note that in the example shown in FIG. 24 , one of the tunnel portion T2 and the tunnel portion T3 corresponds to the first tunnel portion, and the other corresponds to the second tunnel portion. That is, one of the resistors R21 and R12 corresponds to the first electronic component, and the other corresponds to the second electronic component.

[0123] In the example shown in FIG. 25, the X-direction positions of tunnel portion T1 and tunnel portion T2 are shifted from each other. Furthermore, the X-direction positions of tunnel portion T3 and tunnel portion T4 are shifted from each other. In this case, the X-direction positions of tunnel portion T2 and tunnel portion T3 may be the same. Note that in the example shown in FIG. 25, one of the two adjacent tunnel portions T1 and T2 corresponds to the first tunnel portion, and the other corresponds to the second tunnel portion. Furthermore, one of the two adjacent tunnel portions T3 and T4 corresponds to the first tunnel portion, and the other corresponds to the second tunnel portion.

[0124] 26, for all resistors R11, R21, R12, and R22 arranged in one direction (Y direction), the positions of adjacent resistors in the X direction are shifted, but the direction in which the positions in the X direction are shifted is the same for all resistors.

[0125] In the fourth embodiment, one resistor is adjacent to one resistor on one side in the Y direction. In contrast, in the example shown in Fig. 27, two resistors are adjacent to one resistor on one side in the Y direction. Specifically, two resistors, R12 and R21, are arranged adjacent to resistor R11 on one side in the Y direction. Furthermore, two resistors, R12 and R21, are arranged adjacent to resistor R22 on the other side in the Y direction.

[0126] In the example shown in Figure 28, the X-direction position of one resistor R11 is different from the X-direction positions of three resistors R21, R12, and R22. The X-direction positions of these three resistors R21, R12, and R22 are the same. In the example shown in Figure 29, the X-direction position of one resistor R21 is different from the X-direction positions of three resistors R11, R12, and R22. The X-direction positions of these three resistors R11, R12, and R22 are the same.

[0127] In the fourth embodiment, the resistor 132 of the snubber circuit 13 is used as the first electronic component forming the tunnel portion. However, the capacitor 131 may be the first electronic component forming the tunnel portion. Alternatively, the capacitor 131 may be the second electronic component.

[0128] In the fourth embodiment, a part of the second electronic component is located in the first range B1, but the entire second electronic component may be located in the first range B1.

[0129] In the above fourth embodiment, the entire third tunnel section is located in the first projection range A1. Alternatively, a portion of the third tunnel section may be located in the first projection range A1. Also, in the above fourth embodiment, the entire fourth tunnel section is located in the second projection range A2. Alternatively, a portion of the fourth tunnel section may be located in the second projection range A2.

[0130] (Fifth embodiment) The conductor 42 of the substrate 40 according to this embodiment is subjected to laser roughening, as described below. For example, as shown in Fig. 30, a roughened portion 42L that has been subjected to laser roughening may be formed in a portion of the conductor 42 that corresponds to the relay wiring 424. The portion indicated by the dotted line in Fig. 28 is the roughened portion 42L. The roughened portion 42L is formed in a portion of the relay wiring 424 between the resistor R11 (first electronic component) and the resistor R21 (second electronic component).

[0131] As shown in FIG. 31 , the relay wiring 424 has a first connection portion 42L1 and a second connection portion 42L2. The first connection portion 42L1 is a portion of the relay wiring 424 to which a terminal 1323 of a first electronic component is connected via solder 83. The second connection portion 42L2 is a portion of the relay wiring 424 to which a terminal 1323 of a second electronic component is connected via solder 83. The roughened portion 42L is formed in a portion between the first connection portion 42L1 and the second connection portion 42L2. The surface roughness of the roughened portion 42L is greater than the surface roughness of the first connection portion 42L1 and the second connection portion 42L2. The roughened portion 42L may be roughened by irradiation with a laser beam, by oxidation with a chemical, or by using an abrasive.

[0132] Roughened portion 42L may be formed in a portion between a plurality of resistors 132. Roughened portion 42L may be formed in a portion between resistor 132 and capacitor 131. Roughened portion 42L may be formed in a portion between a plurality of capacitors 131.

[0133] The roughened portion 42L separates the solder 83 of the first connecting portion 42L1 from the solder 83 of the second connecting portion 42L2, and each of the separated solders 83 forms a fillet. Figures 32 and 33 show Comparative Examples 1 and 2, which, contrary to the present embodiment, do not have the roughened portion 42L. In these Comparative Examples 1 and 2, the solder 83 of the first connecting portion 42L1 and the solder 83 of the second connecting portion 42L2 are not separated but are bonded together. As a result, the solder 83 does not form a fillet in Comparative Examples 1 and 2.

[0134] In Comparative Example 1, a sufficient amount of solder 83 is provided on both the first connection portion 42L1 and the second connection portion 42L2. Therefore, the possibility of a disconnection due to damage to the solder 83 is sufficiently low. However, in Comparative Example 2, as shown by the dashed line in FIG. 33, the amount of solder 83 provided on the second connection portion 42L2 is small. Therefore, there is a concern that a disconnection due to damage to the solder 83 may occur, which can be considered a poor connection state. In both Comparative Examples 1 and 2, as described above, the solder 83 of both connection portions is bonded and integrated, so it is not possible to determine by visual inspection from the Z direction whether the state is normal as in Comparative Example 1 or poor connection as in Comparative Example 2.

[0135] In consideration of this point, in this embodiment, a roughened portion 42L is formed in the portion of the relay wiring 424 between the first connection portion 42L1 and the second connection portion 42L2. As a result, the solder 83 of the first connection portion 42L1 and the solder 83 of the second connection portion 42L2 are separated, and each separated solder 83 forms a fillet. If the amount of solder 83 is insufficient, a fillet will not be formed, so the presence or absence of a connection defect can be determined by visually inspecting the presence or absence of a fillet from the Z direction.

[0136] (Sixth embodiment) The semiconductor device 21 according to this embodiment is based on the configuration of the semiconductor device 21 according to the first embodiment and employs the configuration shown in Figures 34 and 35. Below, the configuration of this embodiment that is not specifically described is the same as that of the first embodiment.

[0137] As described above in the first embodiment, the semiconductor element 30 has a pad 33. The pad 33 is connected to the signal terminal 62 via the relay wiring 425 and the wire 80. The wire 80 includes the following wires 801, 802, 80a, and 80b. For example, the pad 33 and the relay wiring 425 are connected by the wires 801 and 802. The relay wirings 425 are connected to each other by the wire 80a. The relay wiring 425 and the signal terminal 62 are connected by the wire 80b. The signal terminal 62 is attached to the wall portion 221c of the frame body 221. The relay wiring 425 is included in the conductor 42. The relay wiring 425 is arranged between the capacitor 131 or the resistor 132 and the semiconductor element 30.

[0138] A plurality of semiconductor elements 30H, which are upper arm elements, are arranged side by side. In the example shown in Fig. 35, four semiconductor elements 30H are arranged in a row in the short side direction. Wire 802 is a wire connected to semiconductor elements 30H located at both ends in the short side direction. Wire 801 is a wire connected to semiconductor element 30H located in the center in the short side direction.

[0139] It should be noted that a relay substrate (not shown) may be used instead of relay wiring 425. The relay substrate is a substrate placed on one surface 41a of insulating substrate 41. The relay substrate has an insulating substrate and a conductor. When a relay substrate is used, it is advantageous over relay wiring 425 in that electronic components can be mounted on the relay substrate.

[0140] Here, the shape of the frame 221 in a top view is a rectangle surrounding the substrate 40. In the example shown in FIG. 35, the short side of the opposite sides of the rectangle extends in the X direction. The long side of the opposite sides of the rectangle extends in the Y direction. Hereinafter, the direction in which a pair of opposite sides face each other will be referred to as the opposite side direction. The direction in which a pair of short sides face each other corresponds to the Y direction and will also be referred to as the longitudinal direction. The direction in which a pair of long sides face each other corresponds to the X direction and will also be referred to as the lateral direction.

[0141] The seal 90 filled in the frame 221 vibrates within the frame 221 due to vehicle vibrations and the like. The main directions of the vibrations are the short-side direction and the long-side direction. The seal 90 is more likely to vibrate in the long-side direction than in the short-side direction. In other words, the vibration energy when the seal 90 vibrates in the long-side direction is greater than the vibration energy when the seal 90 vibrates in the short-side direction.

[0142] The capacitor 131 has a rectangular cubic shape. In the example shown in FIG. 34, the height dimension of the capacitor 131 is greater than the widthwise and lengthwise dimensions. However, the height dimension of the capacitor 131 may be smaller than the widthwise and lengthwise dimensions. Also, in the example shown in FIG. 34, the widthwise dimension of the capacitor 131 is greater than the lengthwise dimension, but the lengthwise dimension may be greater than the widthwise dimension. Note that the height dimension refers to the vertical length when the power conversion device 4 is mounted on a vehicle. In other words, it refers to the length in the direction perpendicular to the liquid surface of the sealing body 90.

[0143] As shown in FIG. 34 , the upper end 1315 of the capacitor 131 is located higher than the pad 33. In other words, the upper end 1315 is located higher than the connection portions of the wires 801 and 802 to the pad 33. The upper end 1315 is located higher than the upper end of the clip 50. The upper end 1315 is located higher than the apex 80p, which is the highest portion of the wire 80. The upper end 1315 is located at the highest position among the components mounted on the substrate 40 located in the accommodation space 22v. Furthermore, the upper end 1315 is located lower than the liquid level of the encapsulant 90. In other words, the entire capacitor 131 is encapsulated by the encapsulant 90.

[0144] Hereinafter, the ranges of the capacitor 131 projected in the opposite side direction are referred to as projection ranges C1 and C2. Projection range C1 is the projection range in the long side direction, and projection range C2 is the projection range in the short side direction. At least a portion of the wire 80 is located in the projection ranges C1 and C2. In the example shown in FIG. 35, the entire wire 801 is located in the projection range C1. A portion of the wire 80a is located in the projection range C1. The extension direction of the wire 80a is perpendicular to the projection direction (longitudinal direction) of the projection range C1. The extension direction of the wire 801 is a direction intersecting at an acute angle with the projection direction (longitudinal direction) of the projection range C1.

[0145] <Summary of the Sixth Embodiment> In the semiconductor device 21 according to this embodiment, the upper end 1315 of the capacitor 131 is located higher than the pad 33. Therefore, the capacitor 131 prevents the waves of the vibrating encapsulant 90 from colliding with the wire 80. In other words, the capacitor 131 functions as a breakwater that protects the wire 80 from the vibration waves of the encapsulant 90. This reduces the force that the wire 80 receives from the vibration waves of the encapsulant 90, thereby reducing the risk of damage to the wire 80. In particular, the capacitor 131 adequately protects the connection portions of the wires 801 and 802 connected to the pad 33. This prevents damage to the connections between the wires 801 and 802 and the pad 33. Moreover, because the wire 80 is protected as described above, the diameter of the wire 80 can be reduced. As a result, the pad 33 can be minimized, thereby enabling the semiconductor device 21 to be miniaturized.

[0146] Furthermore, in this embodiment, the upper end 1315 of the capacitor 131 is located higher than the apex 80p of the wire 80. Therefore, the degree to which the force caused by the vibration wave of the sealing body 90 is applied to the wire 80 can be further reduced.

[0147] Furthermore, in this embodiment, the frame 221 of the housing 22 has a rectangular shape that surrounds the substrate 40. At least a portion of the wire 80 is located within projection ranges C1 and C2 obtained by projecting the capacitor 131 in the direction of opposite sides of the rectangle. For example, the entire wire 801 is located within projection range C1, and a portion of the wire 80a is located within projection range C1. This enhances the function of the capacitor 131 as a breakwater, thereby enhancing the effect of reducing damage to the wire 80.

[0148] Furthermore, in this embodiment, in consideration of the fact that the vibration energy of sealing body 90 is greater in the longitudinal direction than in the lateral direction, wires 801 and 80a are arranged within a projection range C1 in the longitudinal direction of capacitor 131. Therefore, the breakwater function of capacitor 131 is effectively exhibited.

[0149] Furthermore, in this embodiment, the vertex 80p, which is the highest part of the wire 80, is located within the projection ranges C1 and C2. For example, the vertex 80p of the wire 801 is located within the projection range C1. Therefore, the breakwater function of the capacitor 131 provided to the wire 80 is more effectively exerted.

[0150] Furthermore, in this embodiment, the direction in which the wire 80 positioned in the projection range C1 extends is perpendicular to the direction of the projection. Here, the breakwater function of the capacitor 131 is weak in the direction perpendicular to the direction of the projection (Y direction). Therefore, in this embodiment, since the wire 80 extends in the Y direction, it is possible to suppress the wire 80 from receiving a force from the vibration wave in the Y direction.

[0151] Furthermore, in this embodiment, upper end 1315 of capacitor 131 is located lower than the liquid level of seal 90, and capacitor 131 is entirely sealed by seal 90. Therefore, capacitor 131 as a whole functions as a breakwater, which can further reduce damage to wire 80.

[0152] <Modification of the Sixth Embodiment> In the sixth embodiment, the upper end 1315 of the capacitor 131 is located lower than the liquid level in the seal 90. However, as shown in FIG. 36 , the upper end 1315 may be located higher than the liquid level in the seal 90. That is, a portion of the capacitor 131 (the upper end 1315) may be exposed from the seal 90. The upper end 1315 is not likely to deteriorate even if it is not sealed, so there is no problem if it is exposed. Alternatively, the entire lead terminal 1313 may be sealed, while a portion of the main body 1314 is exposed. Alternatively, the connection portion between the conductor 42 and the lead terminal 1313 may be sealed, while a portion of the lead terminal 1313 is exposed.

[0153] In the following description, the shortest distance between both ends of wires 801, 802 is referred to as wire length 80L. Furthermore, the creepage length of looped wires 801, 802 is referred to as creepage length. The creepage length relative to the wire diameter of wires 801, 802 is referred to as wire diameter ratio. In the manufacturing process for bonding wire 80, the nozzle that ejects the wire vibrates. The wire length 80L and wire diameter ratio are set so that the nozzle vibration does not resonate with the wire.

[0154] In the sixth embodiment, the upper end 1315 of the capacitor 131 is located higher than the apex 80p of the wire 80. However, as long as the upper end 1315 is located higher than the pad 33, the upper end 1315 may be located lower than the apex 80p.

[0155] In the sixth embodiment, at least a portion of the wire 80 is located within the projection ranges C1 and C2. In contrast, if the upper end 1315 is located higher than the pad 33, the wire 80 does not need to be located within the projection ranges C1 and C2.

[0156] In the sixth embodiment, the wires 80 are arranged in a projection range C1 in the longitudinal direction. Alternatively, the wires 80 may be arranged in a projection range C2 in the lateral direction.

[0157] In the sixth embodiment, the vertex 80p of the wire 80 is located within the projection ranges C1 and C2. However, if the upper end 1315 is located higher than the pad 33, the vertex 80p does not have to be located within the projection ranges C1 and C2.

[0158] (Seventh embodiment) The semiconductor device 21 according to this embodiment is based on the configuration of the semiconductor device 21 according to the first embodiment and employs the configuration shown in Figures 37 and 38. Below, the configuration of this embodiment that is not specifically described is the same as that of the first embodiment.

[0159] The resistors in the snubber circuit 13 include resistors R31 and R32. The resistors R31 and R32 are connected to the conductor 42 by soldering. The capacitor 131 is connected to the conductor 42 via the resistors R31 and R32. In other words, the capacitor 131 is not connected to the conductor 42 by soldering, but is connected to terminals 1323 of the resistors R31 and R32 by soldering. In other words, the resistors R31 and R32 are arranged between the conductor 42 and the capacitor 131, and the capacitor 131 is arranged in a layered manner on the resistors R31 and R32.

[0160] In the illustrated example, one capacitor 131 is connected to two resistors R31 and R32 so as to electrically bridge the resistor R31 connected to the relay wiring 424 and the resistor R32 connected to the P wiring 421. In other words, the capacitor 131, the resistors R31 and R32, the resistors R11 and R12, and the resistors R21 and R22 are connected in series with one another.

[0161] Between the capacitor 131 and the substrate 40, there is a tunnel portion T10, which is a tunnel-shaped space. This tunnel portion T10 has a shape that penetrates in one direction. In the example shown in Fig. 37, the tunnel portion penetrates in the Y direction. A portion of the sealing body 90 is filled in the tunnel portion T10.

[0162] Tunnel portion T10 is a space surrounded by a pair of resistors R31 and R32, capacitor 131, and substrate 40. The portions of substrate 40 that form tunnel portion T10 are conductor 42 to which terminal 1323 is connected, and insulating base material 41. Capacitor 131 is connected across P wiring 421 (first wiring) and relay wiring 424 (third wiring) via resistors R31 and R32.

[0163] As described in the first embodiment, the resistor 132 of the snubber circuit 13 includes a first resistor (resistors R11 and R12) and a second resistor (resistors R21 and R22) connected in series with each other. The first resistor may include the resistors R31 and R32 according to this embodiment, and the second resistor may include the resistors R31 and R32.

[0164] As described in the fourth embodiment, the resistor R21 (second electronic component) located closest to the through-hole exit or through-hole entrance of the tunnel portion T1 (first tunnel portion) of the resistor R11 (first electronic component) is located outside the first projection range A1. This first electronic component may be the capacitor 131 according to this embodiment. In this case, the tunnel portion T10 corresponds to the first tunnel portion, and the first projection range A1 corresponds to the projection range of the tunnel portion T10.

[0165] As described in the sixth embodiment, the upper end 1315 of the capacitor 131 is located higher than the pad 33. Similarly, in this embodiment, the upper end 1315 of the capacitor 131 when stacked on the resistors R31 and R32 is located higher than the pad 33. It is desirable that the lower end 1316 (see FIG. 38) of the capacitor 131 is located lower than the pad 33. However, the lower end 1316 may be located higher than the pad 33.

[0166] (Other embodiments) The disclosure in this specification and drawings, etc. is not limited to the exemplified embodiments. The disclosure encompasses the exemplified embodiments and modifications thereto by those skilled in the art. For example, the disclosure is not limited to the combinations of parts and / or elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure encompasses the omission of parts and / or elements from the embodiments. The disclosure encompasses the substitution or combination of parts and / or elements between one embodiment and another embodiment. The disclosed technical scope is not limited to the description of the embodiments.

[0167] In each of the above embodiments, the power conversion device 4 includes an inverter 6 as a power conversion unit, but is not limited to this. For example, the power conversion device 4 may include a plurality of inverters. The power conversion device 4 may include at least one inverter and a converter. The power conversion device 4 may include only a converter. Furthermore, the power conversion device 4 may be a semiconductor device that arbitrarily combines a plurality of technical concepts described below.

[0168] (Disclosure of technical ideas) This specification discloses multiple technical ideas described in the following multiple clauses. Some clauses may be written in a multiple dependent form, with the subsequent clause referring to the preceding clause as an alternative. Furthermore, some clauses may be written in a multiple dependent form, referring to another multiple dependent clause. These multiple dependent clauses define multiple technical ideas.

[0169] (Technical philosophy A1) A semiconductor device constituting a power conversion circuit (6), A first main terminal (611), A second main terminal (612); A signal terminal (62); a substrate (40) having an insulating base material (41), a first wiring (421) disposed on one surface of the insulating base material and electrically connected to the first main terminal, and a second wiring (422) disposed on the one surface and electrically connected to the second main terminal; a semiconductor element (30, 30H) electrically connected to the first wiring; a snubber circuit (13) including a capacitor (131) and a resistor (132) connected in series to each other, electrically bridging the first wiring and the second wiring; Equipped with The resistors include a first resistor (R11, R12, R13) and a second resistor (R21, R22, R2W) connected in series with each other.

[0170] (Technical philosophy A2) one of the first resistor and the second resistor includes a plurality of resistors connected in parallel with each other; The semiconductor device according to Technical Idea A1, wherein the other of the first resistor and the second resistor does not include resistors connected in parallel with each other.

[0171] (Technical philosophy A3) the first resistor includes a plurality of resistors connected in parallel with each other; the second resistor includes a plurality of resistors connected in parallel with each other, The semiconductor device according to Technical Idea A1, wherein the number of parallel connections of the first resistors is the same as the number of parallel connections of the second resistors.

[0172] (Technical philosophy A4) The capacitors include a first capacitor (C1) and a second capacitor (C2) connected in parallel with each other, A semiconductor device according to any one of technical ideas A1 to A3, wherein the resistors include the first resistor and the second resistor connected in series to the first capacitor, and the first resistor and the second resistor connected in series to the second capacitor.

[0173] (Technical philosophy A5) the resistor is a chip resistor, The semiconductor device according to any one of Technical Ideas A1 to A4, wherein the snubber circuit includes a wire (W) connected in series to the chip resistor.

[0174] (Technical philosophy A6) The semiconductor device according to any one of Technical Ideas A1 to A4, wherein at least one of the first resistor and the second resistor includes a resistor formed of a wire (R2W).

[0175] (Technical philosophy A7) The semiconductor device according to any one of Technical Ideas A1 to A6, further comprising a monitor terminal (63) that monitors the potential between the capacitor and the resistor.

[0176] (Technical philosophy A8) the substrate has a third wiring (424) separate from the first wiring and the second wiring, the capacitor and the resistor are connected in series with each other via the third wiring, The semiconductor device according to Technical Idea A7, wherein the monitor terminal is connected to the third wiring and extends perpendicularly to the one surface from a connection point with the third wiring.

[0177] (Technical philosophy A9) a flowable encapsulant (90) that encapsulates the resistor together with the semiconductor element; The resistor has a main body (1321) in which a resistive element (1322) is sealed, and a pair of terminals (1323) electrically connected to the resistive element and having portions extending from the main body, A portion of the sealing body is filled in a tunnel portion (T1, T2, T3, T4, T10) which is a tunnel-shaped space surrounded by the pair of terminals, the main body portion, and the substrate, The tunnel portion of the first resistor is defined as a first tunnel portion (T1), and a range obtained by projecting the first tunnel portion in a penetration direction of the first tunnel portion is defined as a first projection range (A1), The semiconductor device according to any one of Technical Ideas A1 to A8, wherein the second resistor is located outside the first projection range.

[0178] (Technical philosophy A10) A semiconductor device constituting a power conversion circuit (6), A first main terminal (611), A second main terminal (612); A signal terminal (62); a substrate (40) having an insulating base material (41), a first wiring (421) disposed on one surface of the insulating base material and electrically connected to the first main terminal, and a second wiring (422) disposed on the one surface and electrically connected to the second main terminal; a semiconductor element (30, 30H) electrically connected to the first wiring; a snubber circuit (13) including a capacitor (131) and electrically bridging the first wiring and the second wiring; Equipped with The capacitor has electrodes (1312) and lead terminals (1313) connected to the electrodes; The lead terminal is provided with a detail (1313a) that is configured to partially increase the electrical resistance of the current flowing through the lead terminal, The semiconductor device, wherein the detail is set to an electrical resistor that melts down due to a current that flows in association with a short-circuit fault in the capacitor.

[0179] (Technical philosophy B1) A semiconductor device constituting a power conversion circuit (6), A first main terminal (611), A second main terminal (612); A signal terminal (62); a substrate (40) having an insulating base material (41), a first wiring (421) disposed on one surface of the insulating base material and electrically connected to the first main terminal, and a second wiring (422) disposed on the one surface and electrically connected to the second main terminal; a semiconductor element (30, 30H) electrically connected to the first wiring; a snubber circuit (13) including a plurality of electronic components (131, 132) and electrically bridging the first wiring and the second wiring; a fluid sealant (90) that seals the semiconductor element and at least a part of the electronic component; Equipped with The electronic component includes a main body (1321, 1314) in which a functional element (1322, 1311, 1312) is sealed, and a pair of terminals (1323, 1313) electrically connected to the functional element and having portions extending from the main body, A portion of the sealing body is filled in a tunnel portion (T1, T2, T3, T4, T10) which is a tunnel-shaped space surrounded by the pair of terminals, the main body portion, and the substrate, one of the plurality of electronic components is a first electronic component (R11), the tunnel portion of the first electronic component is a first tunnel portion (T1), and a range obtained by projecting the first tunnel portion in a penetration direction of the first tunnel portion is a first projection range (A1); The plurality of electronic components include a second electronic component (R21) located closest to a through-hole exit (Tout) or a through-hole entrance (Tin) of the first tunnel portion, The semiconductor device, wherein the second electronic component is located outside the first projection range.

[0180] (Technical philosophy B2) a range in which the first electronic component is projected in the penetration direction is defined as a first range (B1); The semiconductor device according to Technical Concept B1, wherein at least a portion of the second electronic component is located in the first area.

[0181] (Technical philosophy B3) The plurality of electronic components include a third electronic component (R12) that is located closest to the second electronic component, in addition to the first electronic component; the tunnel portion of the third electronic component is a third tunnel portion (T3); the third tunnel portion extends parallel to the first tunnel portion; The semiconductor device according to Technical Concept B1 or B2, wherein at least a portion of the third tunnel portion is located in the first projection range.

[0182] (Technical philosophy B4) The plurality of electronic components include a fourth electronic component (R22) that is located closest to the second electronic component, in addition to the second electronic component; the tunnel portion of the second electronic component is a second tunnel portion (T2), a range obtained by projecting the second tunnel portion in a penetration direction of the second tunnel portion is a second projection range (A2), and the tunnel portion of the fourth electronic component is a fourth tunnel portion (T4), the fourth tunnel portion extends parallel to the second tunnel portion; The semiconductor device according to Technical Concept B3, wherein at least a portion of the fourth tunnel portion is located in the second projection range.

[0183] (Technical philosophy B5) The plurality of electronic components include a capacitor (131) and a resistor (132) connected in series with each other; The semiconductor device according to any one of Technical Concepts B1 to B4, wherein the first electronic component and the second electronic component are resistors.

[0184] (Technical philosophy B6) the substrate has relay wiring (424) connected to both the first electronic component and the second electronic component by soldering; the relay wiring has a first connection portion (42L1) connected to the first electronic component, a second connection portion (42L2) connected to the second electronic component, and a roughened portion (42L) that is a portion between the first connection portion and the second connection portion, The semiconductor device according to any one of Technical Concepts B1 to B5, wherein the surface roughness of the roughened portion is greater than the surface roughness of the first connecting portion and the second connecting portion.

[0185] (Technical philosophy C1) A semiconductor device constituting a power conversion circuit (6), A first main terminal (611), A second main terminal (612); A signal terminal (62); a substrate (40) having an insulating base material (41), a first wiring (421) disposed on one surface of the insulating base material and electrically connected to the first main terminal, and a second wiring (422) disposed on the one surface and electrically connected to the second main terminal; a semiconductor element (30, 30H) having main electrodes (31, 32) electrically connected to the first wiring and pads (33) electrically connected to signal terminals (62); Wires (80, 801, 802, 80a) forming at least a part of a communication line connecting the signal terminals and the pads; a snubber circuit (13) including a capacitor (131) and electrically bridging the first wiring and the second wiring; a flowable encapsulant (90) that encapsulates the semiconductor element, the wires, and at least a portion of the capacitor; Equipped with A semiconductor device, wherein the upper end (1315) of the capacitor is located higher than the pad.

[0186] (Technical thought C2) The semiconductor device according to technical idea C1, wherein the upper end is located higher than a vertex (80p) that is the highest part of the wire.

[0187] (Technical thought C3) The sealing body is filled inside a rectangular housing (22) that surrounds the substrate, The direction in which a pair of opposite sides of the rectangle face each other is defined as an opposite side direction, The semiconductor device according to technical idea C1 or C2, wherein at least a portion of the wire is located within a projection range (C1, C2) of the capacitor projected in the opposite side direction.

[0188] (Technical thought C4) Among the opposite side directions, the direction in which the short sides of the rectangle face each other is defined as a longitudinal direction, The semiconductor device according to technical idea C3, wherein the projection range is the range of the capacitor projected in the longitudinal direction.

[0189] (Technical thought C5) The semiconductor device according to technical idea C3 or C4, wherein the apex (80p), which is the highest part of the wire, is located within the projection range.

[0190] (Technical thought C6) The semiconductor device according to any one of Technical Concepts C3 to C5, wherein the direction in which the wires extend is perpendicular to the direction of projection.

[0191] (Technical philosophy C7) The semiconductor device according to any one of Technical Concepts C1 to C6, wherein the upper end is exposed from the sealing body.

[0192] (Technical philosophy C8) The semiconductor device according to any one of Technical Concepts C1 to C6, wherein the capacitor is entirely sealed with the sealing body. [Explanation of symbols]

[0193] 21 semiconductor device, 13 snubber circuit, 131 capacitor, 1315 upper end, 22 housing, 30, 30H semiconductor element, 31, 32 main electrode, 33 pad, 40 substrate, 41 insulating substrate, 421 first wiring, 422 second wiring, 6 power conversion circuit, 611 first main terminal, 612 second main terminal, 62 signal terminal, 80, 801, 802, 80a wire, 80p apex portion, 90 encapsulant, C1, C2 projection range.

Claims

1. A semiconductor device constituting a power conversion circuit (6), A first main terminal (611); A second main terminal (612); A signal terminal (62); a substrate (40) having an insulating base material (41), a first wiring (421) disposed on one surface of the insulating base material and electrically connected to the first main terminal, and a second wiring (422) disposed on the one surface and electrically connected to the second main terminal; a semiconductor element (30, 30H) having a main electrode (31, 32) electrically connected to the first wiring and a pad (33) electrically connected to a signal terminal (62); a wire (80, 801, 802, 80a) forming at least a part of a communication line connecting the signal terminal and the pad; a snubber circuit (13) including a capacitor (131) and electrically bridging the first wiring and the second wiring; a flowable encapsulant (90) that encapsulates the semiconductor element, the wires, and at least a portion of the capacitor; Equipped with A semiconductor device in which the upper end (1315) of the capacitor is located at a higher position than the pad.

2. 2. The semiconductor device according to claim 1, wherein said upper end is located at a position higher than a vertex (80p) which is the highest portion of said wire.

3. The encapsulant is filled inside a rectangular housing (22) surrounding the substrate, The direction in which a pair of opposite sides of the rectangle face each other is defined as an opposite side direction, 3. The semiconductor device according to claim 1, wherein at least a portion of said wire is located within a projection range (C1, C2) of said capacitor projected in the opposite side direction.

4. Among the opposite side directions, the direction in which the short sides of the rectangle face each other is defined as a longitudinal direction, The semiconductor device according to claim 3 , wherein the projection range is a range obtained by projecting the capacitor in the longitudinal direction.

5. 4. The semiconductor device according to claim 3, wherein a vertex (80p) which is the highest part of said wire is located within said projection range.

6. The semiconductor device according to claim 3 , wherein the direction in which the wire extends is perpendicular to the direction of the projection.

7. The semiconductor device according to claim 1 , wherein the upper end is exposed from the sealing body.

8. 3. The semiconductor device according to claim 1, wherein the capacitor is entirely sealed with the sealing body.

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