Electrode structure of semiconductor device

Abstract

To provide an electrode structure capable of preventing reduction in yield even when a semiconductor element is miniaturized.SOLUTION: The insulating material 23 covers the dielectric layer 12, the contact metal 22 is formed on the insulating material 23, and the base metal 21 penetrates the insulating material 23 and connects the contact metal 22 and the pad layer 14 exposed from the side A1 of the opening of the dielectric layer 12 to each other. The pad layer 14 is formed on the upper surface of the pad mesa 13. A1.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to the structure of an electrode included in a semiconductor element formed by stacking semiconductor layers on a substrate. [Background technology]

[0002] As the operating speed of semiconductor light-receiving elements increases, the light-receiving surface is becoming smaller to reduce element capacitance, and the light-absorbing layer is becoming thinner to shorten the transit time of generated carriers. On the other hand, to prevent sensitivity degradation, the mainstream structure is one in which light is incident from the backside of the chip, and the chip is flip-chip mounted on a carrier substrate with wiring (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-299680 Summary of the Invention [Problem to be solved by the invention]

[0004] Furthermore, optical components are becoming smaller overall, and as light-receiving element chips become smaller, the size of the mounting pads is also becoming smaller. This has resulted in reduced inspection and mounting margins, making these processes more difficult and contributing to lower yields.

[0005] 1 is a cross-sectional view illustrating a conventional electrode structure of a semiconductor element to be flip-chip mounted. In conventional flip-chip mounted semiconductor elements, it is necessary to prevent the metal wiring connecting the top of the element mesa and the electrode from contacting layers on the element substrate 10. For this reason, the electrode side is also formed by stacking the same semiconductor layers as the element mesa to form a pad mesa 13, and a metal electrode layer 14 is placed on the top of the pad mesa to serve as the electrode. This structure allows the electrode to be separated from the element substrate, and prevents the electrode layer 14, which also functions as wiring, from contacting layers on the element substrate 10.

[0006] The entire semiconductor element is covered with a dielectric layer 12, which serves as passivation, and only the top of this pad mesa 13 is open. In other words, the electrode layer 14 disposed on the top of the pad mesa 13 is exposed in the opening A1. The electrode layer 14 exposed in the opening A1 becomes the semiconductor bump connection region when the semiconductor element is flip-chip mounted. The area of ​​the opening A1 is smaller than the area of ​​the top of the pad mesa 13.

[0007] This semiconductor bump connection area is also the area where a contact probe for testing is pressed when testing a semiconductor element. If the contact probe hits the dielectric layer 12 during testing and the dielectric layer 12 is destroyed, the protective film will no longer be effective and the product will be rejected.

[0008] When performing an automated inspection, the contact position of the contact probe must be kept within the opening A1 from the start to the end of the inspection. As semiconductor elements become smaller, the opening A1 becomes smaller, leaving less margin for misalignment of the contact position, requiring advanced adjustment techniques for the inspection process.

[0009] Furthermore, during flip-chip mounting, if the position of the solder bumps formed on the substrate onto which the semiconductor element is mounted is misaligned with the position of the opening A1, the bonding area will be smaller and the strength will also decrease. As semiconductor elements become smaller, the opening A1 has become smaller and the margin for misalignment has become smaller, so advanced position adjustment technology is required during mounting.

[0010] As described above, miniaturization of semiconductor elements leads to a reduction in the area of ​​the opening A1, which requires advanced positioning adjustment (high alignment precision) during inspection and mounting, making it difficult to maintain yield. Therefore, in order to solve the above problem, an object of the present invention is to provide an electrode structure that can prevent a decrease in yield even when semiconductor elements are miniaturized. [Means for solving the problem]

[0011] To achieve the above object, the electrode structure according to the present invention covers the surface of the semiconductor element with a thick insulating material, and forms a contact metal thereon with an area larger than that of a conventional pad opening A1.

[0012] Specifically, the electrode structure according to the present invention comprises: a pad mesa in which a semiconductor layer is stacked in a mesa shape on an element substrate; an electrode layer formed on the top surface of the pad mesa; a dielectric layer having an opening exposing the electrode layer on the pad mesa; an insulating material covering the dielectric layer; a contact metal formed on the surface of the insulating material; a base metal that penetrates the insulating material and connects the electrode layer exposed from the opening of the dielectric layer to the contact metal; Equipped with.

[0013] By covering the surface of the semiconductor element with a new insulating material, it is possible to prevent the dielectric layer of the passivation from being damaged by the contact probe. Therefore, the present invention can provide an electrode structure that can prevent a decrease in yield even when the semiconductor element is miniaturized.

[0014] Furthermore, the electrode structure according to the present invention is characterized in that the area of ​​the contact metal is larger than the area of ​​the electrode layer exposed through the opening. This electrode structure allows the area of ​​the contact metal to be larger than the pad opening A1. This allows for a larger margin for positioning of the contact probe during automatic testing and for positioning during mounting (relaxing alignment accuracy). Therefore, the present invention can provide an electrode structure that can prevent a decrease in yield even when semiconductor elements are miniaturized.

[0015] Furthermore, a semiconductor element according to the present invention is a semiconductor element including the electrode structure, an element mesa in which the semiconductor layer is stacked in a mesa shape on the element substrate; The upper surface of the element mesa and the upper surface of the pad mesa are connected by the electrode layer.

[0016] The electrode manufacturing method according to the present invention further comprises: a pad mesa process in which semiconductor layers are stacked in a mesa shape on an element substrate to form a pad mesa; an organic material forming step of covering the pad mesa with an organic material; an electrode layer forming step of forming an electrode layer on an upper surface of the pad mesa; a dielectric layer forming step of covering the electrode layer with a dielectric layer; an insulating material forming step of covering the dielectric layer with an insulating material; a contact metal forming step of forming a contact metal on a surface of the insulating material; between the insulating material forming step and the contact metal forming step, The method is characterized in that a pedestal metal forming step is performed to form a pedestal metal that penetrates the insulating material and connects the electrode layer exposed from the opening in the dielectric layer to the contact metal.

[0017] The above inventions can be combined as much as possible. [Effects of the Invention]

[0018] The present invention can provide an electrode structure that can prevent a decrease in yield even when semiconductor elements are miniaturized. [Brief explanation of the drawings]

[0019] [Figure 1] 10A and 10B are cross-sectional views illustrating an electrode structure of a related semiconductor element. [Figure 2] 1 is a cross-sectional view illustrating an electrode structure of a semiconductor element according to the present invention. [Figure 3] 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0020] The following description of the preferred embodiments of the present invention will be given with reference to the accompanying drawings. The preferred embodiments described below are examples of the present invention, and the present invention is not limited to the preferred embodiments. In this specification and the drawings, components having the same reference numerals are intended to represent the same components.

[0021] [Comparative Example] FIG. 1 illustrates an electrode structure of a comparative example. The area of ​​the opening A1 in the dielectric layer 12, which serves as passivation, is smaller than the area of ​​the top of the pad mesa 13. As semiconductor devices are miniaturized, the pad mesa 13 also becomes smaller, and the opening A1 becomes even smaller. This makes it difficult to bring a contact probe into contact with the electrode layer 14 within the opening A1 during testing without damaging the dielectric layer 12. Furthermore, the reduction in opening A1 also reduces the solder bump connection area when flip-chip mounting on a wired substrate, requiring high alignment precision.

[0022] [Embodiment] FIG. 2 is a cross-sectional view illustrating the electrode structure of this embodiment. a pad mesa 13 formed by stacking semiconductor layers in a mesa shape on an element substrate 10; an electrode layer 14 formed on the top surface of the pad mesa 13; a dielectric layer 12 having an opening A1 exposing an electrode layer 14 on a pad mesa 13; an insulating material 23 covering the dielectric layer 12; a contact metal 22 formed on the surface of an insulating material 23; a base metal 21 that penetrates the insulating material 23 and connects the electrode layer 14 exposed from the opening A1 of the dielectric layer 12 to the contact metal 22; Equipped with.

[0023] In this embodiment, a case where the semiconductor element is a back-illuminated light-receiving element will be described as an example. The device substrate 10 is a semi-insulating InP substrate. The pad mesa 13 is formed by stacking multiple semiconductor layers in a mesa shape. For example, the pad mesa 13 is formed by stacking three InGaAs layers in the order of n-type, intrinsic, and p-type from the device substrate 10 side. These multiple semiconductor layers are the same as the semiconductor layers that make up the device mesa formed on the left side of FIG. 2, as will be described later. The periphery of the pad mesa 13 is filled with a passivation 11 made of an organic material such as BCB (Benzocyclobutene) or polyimide. The electrode layer 14 covers the upper surface of the pad mesa and serves as wiring that electrically connects to the element mesa formed on the left side of Fig. 2. The electrode layer 14 is made of, for example, copper (Cu). The dielectric layer 12 is, for example, SiN. The insulating material 23 is, for example, an organic material such as BCB or polyimide. The base metal 21 and the contact metal 22 are made of, for example, gold (Au). It is preferable that the size A2 of the contact metal 22 is larger than the size A1 of the opening, that is, the area of ​​the contact metal 22 is larger than the area of ​​the electrode layer 14 exposed from the opening A1.

[0024] FIG. 3 is a process diagram illustrating a method for manufacturing a light-receiving element having the electrode structure of FIG. Semiconductor lamination step S01: Three InGaAs layers are laminated on the element substrate 10 in the order of n-type, intrinsic, and p-type using an epitaxial layer growth technique such as MOCVD or MBE. Mesa formation step S02: Using wet etching and dry etching techniques, the InGaAs layer in the region other than the element mesa and pad mesa is removed down to the element substrate 10. Organic material formation step S03: An organic material 11 such as BCB or polyimide is applied to cover the element mesa and pad mesa. Then, using techniques such as photolithography or dry etching, the upper layer organic material is processed to expose the tops of the element mesa and pad mesa. Electrode layer formation step S04: As a method for forming the tops of the element mesa and pad mesa and the wiring portions connecting them, after photolithography patterning using a two-layer resist or a negative resist, metal for the electrode layer 14 is evaporated and a lift-off method is used. Dielectric layer forming step S05: A dielectric layer 12 is laminated on the entire surface using CVD technology. Opening formation step S06: Using lithography and etching techniques, a portion of the dielectric layer 12 that will become the opening A1 is removed, exposing the electrode layer 14. Pedestal Metal Forming Step S07: As a method for forming the pedestal metal inside the opening A1, after photolithography patterning using a two-layer resist or a negative resist, the pedestal metal 21 is vapor-deposited and a lift-off method is used. Insulating material lamination step S08: An insulating material 23 such as BCB or polyimide is applied to cover the dielectric layer 12 and the base metal 21. Contact hole forming step S09: The top surface of the pedestal metal 21 is exposed using lithography and etching techniques. Contact metal formation step S10: As a method for forming the contact metal, after photolithography patterning using a two-layer resist or a negative resist, metal for the contact metal 22 is evaporated and then lift-off is performed.

[0025] The "pad mesa process" described in the claims includes the semiconductor lamination process S01 to the organic material formation process S03. The "electrode layer forming step" recited in the claims is the electrode layer forming step S04. The "dielectric layer forming step" recited in the claims includes the dielectric layer forming step S05 and the opening forming step S06. The "base metal forming step" recited in the claims is the base metal forming step S07. The "insulating material forming step" described in the claims is the insulating material stacking step S08 and the contact hole forming step S09. The "contact metal forming step" recited in the claims is the contact metal forming step S10.

[0026] This manufacturing method allows the area of ​​the contact metal, as viewed from above, to be larger than the area of ​​the top of the pad mesa, thereby increasing the accuracy margin for probe contact during testing and positioning during flip-chip mounting.

[0027] (Other embodiments) Although the above embodiment has been described as an electrode structure of a photodetector, the present invention is not limited to the electrode structure of a photodetector. The electrode structure of the present invention can also be applied to a semiconductor element (such as a semiconductor laser) in which multiple semiconductor layers are stacked in a mesa shape. [Explanation of symbols]

[0028] 10: Element substrate 11: Passivation (organic materials) 12: Dielectric layer 13: Pad Mesa 14: Electrode layer 21: Metal base 22: Contact Metal 23: Insulating materials

Claims

1. a pad mesa in which a semiconductor layer is stacked in a mesa shape on an element substrate; an electrode layer formed on the top surface of the pad mesa; a dielectric layer having an opening exposing the electrode layer on the pad mesa; an insulating material covering the dielectric layer; a contact metal formed on the surface of the insulating material; a base metal that penetrates the insulating material and connects the electrode layer exposed from the opening of the dielectric layer to the contact metal; An electrode structure comprising:

2. 2. The electrode structure according to claim 1, wherein the area of ​​the contact metal is larger than the area of ​​the electrode layer exposed through the opening.

3. A semiconductor device comprising the electrode structure according to claim 1 or 2, an element mesa in which the semiconductor layer is stacked in a mesa shape on the element substrate; a semiconductor element, wherein the upper surface of the element mesa and the upper surface of the pad mesa are connected by the electrode layer;

4. a pad mesa process in which semiconductor layers are stacked in a mesa shape on an element substrate to form a pad mesa; an organic material forming step of covering the pad mesa with an organic material; an electrode layer forming step of forming an electrode layer on an upper surface of the pad mesa; a dielectric layer forming step of covering the electrode layer with a dielectric layer; an insulating material forming step of covering the dielectric layer with an insulating material; a contact metal forming step of forming a contact metal on a surface of the insulating material; between the insulating material forming step and the contact metal forming step, a base metal forming step of forming a base metal that penetrates the insulating material and connects the electrode layer exposed from the opening in the dielectric layer to the contact metal;

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