Semiconductor device and method for manufacturing semiconductor device

Abstract

To provide a semiconductor device which can be easily miniaturized.SOLUTION: The semiconductor device includes a first insulating layer, a second insulating layer, and a transistor. The transistor includes a first conductive layer, a second conductive layer, a first semiconductor layer, a third insulating layer, and a third conductive layer. The first insulating layer is located on the first conductive layer and has a slit reaching the first conductive layer, the second conductive layer is located on the first insulating layer, the first semiconductor layer has a first portion in contact with the second conductive layer, a second portion along a side surface of the slit, and a third portion in contact with an upper surface of the first conductive layer inside the slit, the third conductive layer includes a portion facing the second portion of the first semiconductor layer with the third insulating layer interposed therebetween, and the second insulating layer includes a portion facing the second portion of the first semiconductor layer with the third insulating layer and the third conductive layer interposed therebetween and a portion overlapping an upper surface of the first conductive layer with a third portion of the first semiconductor layer interposed therebetween.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a transistor, or a memory device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. [Background technology]

[0003] In recent years, semiconductor devices have been developed, and they mainly use CPUs (Central Processing Units), memories, or other LSIs. A CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) processed from semiconductor wafers and formed into chips, and on which electrodes serving as connection terminals are formed.

[0004] A CPU, a memory, or other semiconductor integrated circuit such as an LSI is mounted on a circuit board, such as a printed wiring board, and is used as one of the components of various electronic devices.

[0005] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors have also attracted attention as other materials.

[0006] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the low leakage current characteristic. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time.

[0007] In recent years, along with the trend toward smaller and lighter electronic devices, there has been an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 discloses a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in a superimposed manner. Patent Document 4 also discloses a vertical transistor in which a side surface of an oxide semiconductor is covered with a gate electrode via a gate insulator. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383 [Patent Document 3] International Publication No. 2021 / 053473 [Patent Document 4] Japanese Patent Application Laid-Open No. 2013-211537 [Non-patent literature]

[0009] [Non-Patent Document 1] Takashi Koida, "High Mobility Transparent Conductive Film", National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Presentation 2019, Internet<URL:https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf> Summary of the Invention [Problem to be solved by the invention]

[0010] An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a semiconductor device with high operating speed.An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with high on-state current.An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with low parasitic capacitance.An object of one embodiment of the present invention is to provide a novel semiconductor device.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device having the above characteristics.

[0011] An object of one embodiment of the present invention is to manufacture a semiconductor device with a high yield.An object of one embodiment of the present invention is to reduce the number of manufacturing steps of a semiconductor device.An object of one embodiment of the present invention is to reduce the manufacturing cost of a semiconductor device.

[0012] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0013] One embodiment of the present invention provides a semiconductor device including a first transistor, a first insulating layer, and a second insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a first semiconductor layer, a third insulating layer, and a third conductive layer. The first insulating layer is located on the first conductive layer and has a slit that reaches the first conductive layer. The second conductive layer is located on the first insulating layer. The first insulating layer has, within the slit, a first side surface and a second side surface facing the first side surface. The first semiconductor layer has a first portion in contact with the second conductive layer, a second portion along the first side surface, and a third portion in contact with the first top surface of the first conductive layer, the first top surface overlapping the slit in a planar view, the third conductive layer has a portion facing the second portion with a third insulating layer sandwiched therebetween, and the second insulating layer has a portion facing the second portion with the third insulating layer and third conductive layer sandwiched therebetween and a portion overlapping with the first top surface with the third portion sandwiched therebetween.

[0014] In the above-described embodiment, the semiconductor device further includes a second transistor and a fourth insulating layer, the second transistor including a fourth conductive layer, a fifth conductive layer, a second semiconductor layer, a fifth insulating layer, and a sixth conductive layer, the first insulating layer being located on the fourth conductive layer such that the second side surface overlaps with a first region of the second upper surface of the fourth conductive layer, the fifth conductive layer being located on the first insulating layer, and the second semiconductor layer including a fourth portion in contact with the fifth conductive layer, a second side surface overlapping with a first region of the second upper surface of the fourth conductive layer, and a sixth conductive layer. and a sixth portion in contact with the second region of the second upper surface of the fourth conductive layer, the second region of the second upper surface overlapping with the slit in a planar view, the sixth conductive layer having a portion facing the fifth portion with the fifth insulating layer sandwiched therebetween, and the fourth insulating layer preferably having a portion facing the fifth portion with the fifth insulating layer and the sixth conductive layer sandwiched therebetween and a portion overlapping with the second region of the second upper surface with the second semiconductor layer sandwiched therebetween.

[0015] In the above aspect, it is preferable that the third conductive layer and the second insulating layer each extend in the first direction in plan view.

[0016] In the above embodiment, the first semiconductor layer preferably contains indium oxide.

[0017] In the above aspect, it is also preferable that the capacitor element has a sixth insulating layer and a seventh conductive layer, the capacitor element has an eighth conductive layer, a ninth conductive layer and the seventh insulating layer, the sixth insulating layer is located on the seventh conductive layer and has an opening that reaches the seventh conductive layer, the eighth conductive layer contacts a side surface of the sixth insulating layer and an upper surface of the seventh conductive layer in the opening, the seventh insulating layer is located on the eighth conductive layer, the ninth conductive layer is located on the seventh insulating layer, and the first conductive layer contacts the upper surface of the ninth conductive layer.

[0018] In the above aspect, it is preferable that the slit extends in a first direction in a planar view, the first side surface and the second side surface are each aligned along the first direction, and the third conductive layer, the sixth conductive layer, the second insulating layer and the fourth insulating layer each extend in the first direction.

[0019] In the above embodiment, it is preferable that the semiconductor device has an eighth insulating layer and a ninth insulating layer, the third side of the first conductive layer and the fourth side of the fourth conductive layer face each other, the eighth insulating layer has a seventh portion covering the third side, an eighth portion covering the fourth side, a ninth portion covering the side of the second insulating layer, and a tenth portion covering the side of the fourth insulating layer, and the ninth insulating layer has a portion sandwiched between the seventh portion and the eighth portion and a portion sandwiched between the ninth portion and the tenth portion.

[0020] In the above aspect, it is preferable that the second insulating layer and the fourth insulating layer each contain one or more of silicon nitride and silicon nitride oxide, the eighth insulating layer contains one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate, and the ninth insulating layer contains one or more of silicon oxide, silicon oxynitride, silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen.

[0021] Alternatively, one embodiment of the present invention is a method for forming a first conductive layer, forming a first insulating layer on the first conductive layer, forming a second conductive layer on the first insulating layer, and removing parts of the second conductive layer and the first insulating layer using a first mask, thereby forming a slit in the first insulating layer that reaches the first conductive layer, and thereby forming a first side surface and a second side surface that face each other within the slit in a cross-sectional view in the first insulating layer, and forming a slit in a plan view in the second conductive layer. The first semiconductor layer is formed so as to cover the upper surface of the first conductive layer and the first and second side surfaces inside the slit of the first insulating layer, the first semiconductor layer being divided with the slit sandwiched therebetween, a second insulating layer being formed on the first semiconductor layer, a third conductive layer being formed on the second insulating layer, and a fourth conductive layer along the first side surface and a fifth conductive layer along the second side surface are formed by removing a portion of the third conductive layer using anisotropic etching, and the first conductive layer, the second insulating layer, and the fourth conductive layer are formed. a third insulating layer is formed to cover the first semiconductor layer and the fifth conductive layer, and a portion of the third insulating layer is removed by anisotropic etching to form a fourth insulating layer along the first side surface with the fourth conductive layer sandwiched therebetween and a fifth insulating layer along the second side surface with the fifth conductive layer sandwiched therebetween; the second insulating layer is divided inside the slit to form an eighth insulating layer and a ninth insulating layer; and the first semiconductor layer is divided inside the slit to form a second semiconductor layer and a third semiconductor layer. A method for manufacturing a semiconductor device, comprising forming a conductor layer and dividing a first conductive layer inside a slit to form a sixth conductive layer and a tenth conductive layer, wherein the slit extends in a first direction in a plan view, the first side surface and the second side surface each extend in the first direction, the second semiconductor layer has a portion covering the first side surface and a portion covering a top surface of the sixth conductive layer, and the third semiconductor layer has a portion covering the second side surface and a portion covering a top surface of the tenth conductive layer.

[0022] In the above aspect, it is preferable that the division of the second insulating layer, the division of the first semiconductor layer, and the division of the first conductive layer are performed using the fourth insulating layer and the fifth insulating layer as masks, respectively.

[0023] In the above embodiment, the first semiconductor layer preferably contains indium oxide.

[0024] In the above aspect, the third insulating layer preferably includes one or more of silicon nitride and silicon nitride oxide. [Effects of the Invention]

[0025] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with low parasitic capacitance can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a manufacturing method of a semiconductor device having the above characteristics can be provided.

[0026] According to one embodiment of the present invention, a semiconductor device can be manufactured with a high yield. According to one embodiment of the present invention, the number of manufacturing steps of a semiconductor device can be reduced. According to one embodiment of the present invention, the manufacturing cost of a semiconductor device can be reduced.

[0027] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0028] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 2] Fig. 2A is a diagram showing a configuration example of a semiconductor device, and Fig. 2B is a diagram showing a circuit configuration example of the semiconductor device. [Figure 3]3A to 3C are diagrams showing configuration examples of a semiconductor device. [Figure 4] 4A and 4B are diagrams showing an example of the configuration of a semiconductor device. [Figure 5] 5A and 5B are diagrams showing an example of the configuration of a semiconductor device. [Figure 6] 6A and 6B are diagrams showing configuration examples of a semiconductor device. [Figure 7] 7A to 7C are diagrams showing configuration examples of a semiconductor device. [Figure 8] 8A and 8B are diagrams showing configuration examples of a semiconductor device. [Figure 9] 9A and 9B are diagrams showing configuration examples of a semiconductor device. [Figure 10] 10A and 10B are diagrams showing an example of the configuration of a semiconductor device. [Figure 11] FIG. 11 is a diagram illustrating a configuration example of a semiconductor device. [Figure 12] 12A to 12C are diagrams showing configuration examples of a semiconductor device. [Figure 13] FIG. 13 is a diagram illustrating a configuration example of a semiconductor device. [Figure 14] 14A to 14C are diagrams showing configuration examples of a semiconductor device. [Figure 15] FIG. 15 is a diagram illustrating a configuration example of a semiconductor device. [Figure 16] 16A to 16D are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 17] 17A to 17D are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 18] 18A to 18D are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 19] 19A to 19D are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 20]20A to 20D are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 21] 21A to 21D are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 22] 22A to 22D are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 23] 23A to 23D are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 24] 24A to 24D are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 25] 25A to 25D are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 26] 26A to 26D are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 27] 27A to 27D are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 28] 28A to 28D are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 29] 29A to 29D are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 30] 30A to 30D are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 31] 31A to 31C are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 32] 32A and 32B are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 33] FIG. 33 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 34] FIG. 34 is a diagram illustrating an example of the circuit configuration of a memory cell array and memory cells. [Figure 35] FIG. 35(A) is a graph showing an example of a hysteresis characteristic, and FIG. 35(B) is a timing chart showing an example of a method for driving a memory cell. [Figure 36] 36A to 36H are diagrams illustrating examples of circuit configurations of memory cells. [Figure 37] 37A and 37B are perspective views illustrating a configuration example of a semiconductor device. [Figure 38] FIG. 38 is a block diagram illustrating the CPU. [Figure 39] 39(A) and 39(B) are perspective views of the semiconductor device. [Figure 40] 40(A) and 40(B) are perspective views of the semiconductor device. [Figure 41] 41(A) and 41(B) are diagrams showing configuration examples of electronic components. [Figure 42] 42(A) to 42(C) are diagrams showing examples of the configuration of a mainframe computer. [Figure 43] Fig. 43(A) is a diagram showing an example of the configuration of space equipment, and Fig. 43(B) is a diagram showing an example of the configuration of a storage system. [Figure 44] Figures 44(A) and 44(B) are diagrams illustrating the carrier concentration dependence of Hall mobility, and Figure 44(C) is a cross-sectional view illustrating an indium oxide film. DETAILED DESCRIPTION OF THE INVENTION

[0029] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0030] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0031] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0032] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0033] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. In this specification, the term "transistor" includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).

[0034] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0035] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A and B represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0036] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an electrical potential interaction occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an electrical potential interaction occurs between A and B, it can still be defined as "A and B are indirectly connected" if there is a time during the operation of the circuit when an electrical signal is exchanged or an electrical potential interaction occurs between A and B.

[0037] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film or the like is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0038] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another from a power supply, GND, etc.

[0039] In this specification, the phrase "top surface shapes generally match" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0040] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of the support (e.g., substrate) on which the component is formed.

[0041] In the following, expressions indicating directions such as "upper" and "lower" will basically be used in accordance with the directions in the drawings. However, for purposes such as facilitating explanation, the directions indicated by "upper" or "lower" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (such as a surface to be formed, a support surface, an adhesive surface, or a flat surface) is located above the laminate in the drawings, the surface to be formed may be expressed as "lower" and the laminate side as "upper."

[0042] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in an on-state. The channel width direction refers to the direction perpendicular to the channel length direction. Depending on the structure or shape of the transistor, the channel length direction and the channel width direction may not be defined as one.

[0043] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0044] Unless otherwise specified, in this specification, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate-source voltage Vgs is lower than the threshold voltage Vth for an n-channel transistor (higher than Vth for a p-channel transistor).

[0045] In this specification, "parallel or approximately parallel" refers to, for example, a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes a state in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "perpendicular or approximately perpendicular" refers to, for example, a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes a state in which the angle is 85 degrees or more and 95 degrees or less.

[0046] (Embodiment 1) In this embodiment, a structure example of a semiconductor device according to one embodiment of the present invention and an example of a manufacturing method thereof will be described. The semiconductor device exemplified below can be applied to a memory device.

[0047] A semiconductor device according to one embodiment of the present invention includes a plurality of memory cells, each of which includes one transistor and one memory element. The memory element can be any of various elements capable of storing stored data, such as a capacitor, a variable resistance element, a ferroelectric element, a charge trap element, and a floating gate element.

[0048] In a transistor included in a memory cell, a source electrode and a drain electrode are located at different heights, and a current flows in the height direction of a semiconductor layer. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, one embodiment of the present invention can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like. Note that the heights of the source electrode and the drain electrode can be based on, for example, a substrate surface. Alternatively, for example, the surface on which the electrodes are formed can be based on, for example.

[0049] The capacitor of the memory cell can be provided below the transistor. By stacking the transistor and the capacitor, memory cells can be arranged with high density. The capacitor can be a so-called MIM (Metal-Insulator-Metal) capacitor having a dielectric between a pair of electrodes. In this case, it is preferable that the lower electrode of the transistor also serves as the upper electrode of the capacitor. In this case, it is preferable that the upper electrode of the transistor functions as a bit line. Furthermore, by using a ferroelectric material for the dielectric of the capacitor, a ferroelectric capacitor can be formed. This makes it possible to realize a nonvolatile memory device.

[0050] In one embodiment of the present invention, a metal oxide (oxide semiconductor) exhibiting semiconductor properties is preferably used for the semiconductor layer. For example, silicon, a typical semiconductor material, needs to be doped with impurities that function as donors or acceptors to form source and drain regions. However, in a vertical transistor according to one embodiment of the present invention, it may be difficult to dope impurities into the semiconductor layer with high precision because the source and drain regions are different in height and the channel formation region is located vertically relative to the substrate surface. On the other hand, an oxide semiconductor can be well connected to source and drain electrodes without doping with such impurities. Therefore, a transistor having a three-dimensional structure according to one embodiment of the present invention can be manufactured with high yield.

[0051] A more specific example will be described below with reference to the drawings.

[0052] [Configuration example] FIG. 1 shows a top view of a semiconductor device 50. FIG. 2(A) shows a perspective view of the semiconductor device 50 shown in FIG. 1. FIGS. 3(A), 3(B), and 3(C) show cross-sectional views along the cutting lines AB, CD, and EF shown in FIG. 1. Note that some components (insulating layers, etc.) are omitted from FIGS. 1 and 2(A) and the top views and perspective views shown below. Also, arrows indicating the X, Y, and Z directions may be shown in the figures in this specification. The X, Y, and Z directions are perpendicular to each other.

[0053] The semiconductor device 50 has a configuration in which a plurality of memory cells 15 are arranged in the X and Y directions. In the semiconductor device 50, conductive layers 26 functioning as bit lines extend in the X direction, and conductive layers 23 functioning as word lines extend in the Y direction. As shown in FIG. 2A and other figures, the memory cell 15 has a transistor 10 and a capacitance element 30 thereunder.

[0054] FIG. 2B shows a circuit diagram corresponding to the semiconductor device 50. FIG. 2B shows a plurality of wirings BL functioning as bit lines, a plurality of wirings WL intersecting the bit lines and functioning as word lines, and wirings PL. FIG. 2B shows an example in which the wirings PL are parallel to the wirings WL. Note that memory cells 15 connected to different wirings WL may be connected to the same wiring PL in some cases. In such cases, the wirings PL may be formed as flat conductive layers, and the conductive layers functioning as the wirings PL may be shared among the memory cells 15 connected to the different wirings WL. The wirings PL may also be parallel to the wirings BL.

[0055] The memory cell 15 includes one transistor 10 and one capacitor 30. The transistor 10 has a gate connected to a wiring WL, one of a source and a drain connected to a wiring BL, and the other connected to one electrode of the capacitor 30. The other electrode of the capacitor 30 is connected to a wiring PL.

[0056] The wiring BL functions as a wiring for writing and reading data. The wiring WL functions as a wiring for controlling the on / off (conducting state or non-conducting state) of the transistor 10 functioning as a switch. The wiring PL functions as a constant potential line connected to the capacitor 30.

[0057] 3A and other drawings, the transistor 10 and the capacitor 30 are provided over an insulating layer 11 that is provided over a substrate (not shown). The insulating layer 11 functions as a base insulating layer.

[0058] The transistor 10 includes a semiconductor layer 21, an insulating layer 22 functioning as a gate insulating layer, a conductive layer 23 functioning as a gate electrode, a conductive layer 24 functioning as one of a source electrode and a drain electrode, and a conductive layer 25 functioning as the other of the source electrode and drain electrode.

[0059] The capacitance element 30 is provided on a conductive layer 55 that functions as the wiring PL. The capacitance element 30 has a conductive layer 51 that functions as a lower electrode, a conductive layer 53 that functions as an upper electrode, and an insulating layer 52 that is disposed therebetween and functions as a dielectric.

[0060] The conductive layer 24 is provided over the conductive layer 53. One of the source electrode and the drain electrode of the transistor 10 is connected to the upper electrode of the capacitor. Therefore, the conductive layer 24 is preferably provided in contact with the upper surface of the conductive layer 53.

[0061] The conductive layer 55 is provided so as to be embedded in the insulating layer 35 on the insulating layer 11 .

[0062] An insulating layer having a barrier property can be provided between the insulating layer 11 and the conductive layer 55. Alternatively, the insulating layer 11 may function as an insulating layer having a barrier property. The insulating layer has a function of preventing impurities such as hydrogen from diffusing into the semiconductor layer 21 from the insulating layer 11 or from below the insulating layer 11. For example, a film through which hydrogen is less likely to diffuse than a silicon oxide film (having a barrier property against hydrogen), such as a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, or a gallium oxide film, can be used. In particular, it is preferable to use a silicon nitride film or a silicon nitride oxide film.

[0063] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0064] An insulating layer 46 is provided on the conductive layer 55. The insulating layer 46 functions as an interlayer insulating layer. An opening is provided in the insulating layer 46, reaching the conductive layer 55. The side surfaces of the opening are preferably perpendicular or approximately perpendicular to the substrate surface.

[0065] The conductive layer 51 has a portion that is disposed inside the opening provided in the insulating layer 46. The conductive layer 51 has a region that contacts the upper surface of the conductive layer 55 in the opening, and a region that contacts the side surface of the insulating layer 46 in the opening. The insulating layer 52 is provided by being stacked on the conductive layer 51. The insulating layer 52 has a portion that faces the side surface of the insulating layer 46 inside the opening, with the conductive layer 51 sandwiched therebetween, and a portion that covers the upper surface of the insulating layer 46.

[0066] In the configuration shown in FIG. 3A and other figures, the height of the upper end of the conductive layer 51 and the height of the upper surface of the insulating layer 46 are approximately the same.

[0067] A conductive layer 51 and an insulating layer 52 are stacked along the side surface of the opening in the insulating layer 46 and the upper surface of the conductive layer 55. A conductive layer 53 is provided on the insulating layer 52 so as to fill the opening. The capacitive element 30 having such a configuration may be called a trench-type capacitor or a trench capacitor.

[0068] 3A, the insulating layer 52 covers the upper surface of the conductive layer 51 at the upper end of the conductive layer 51. This makes it possible to prevent a short circuit from occurring between the conductive layer 51 and the conductive layer 53, which function as a pair of electrodes of the capacitive element 30.

[0069] FIG. 3A and other figures show an example in which the bottom of the conductive layer 51 is rounded (has a concave curved surface). Furthermore, the bottoms of the insulating layer 52 provided along the conductive layer 51 and the conductive layer 53 provided along the insulating layer 52 are also rounded, and the bottom of the conductive layer 53 has a convex curved surface that protrudes toward the conductive layer 51. In this way, by configuring the conductive layer 51, which forms the surface on which the insulating layer 52 is formed, to have no corners, it is possible to prevent the insulating layer 52 from becoming locally thin. Furthermore, since the bottom of the conductive layer 51 has no corners, it is possible to prevent local concentration of the electric field. This makes it possible to suppress leakage current in the capacitance element and improve reliability.

[0070] Furthermore, a rounded recess is provided on the top surface of conductive layer 55, and the bottom of conductive layer 51 is provided to fit along this recess. With this configuration, the contact area between conductive layer 55 and conductive layer 51 is increased compared to when the contact surface between conductive layer 55 and conductive layer 51 is flat, thereby reducing the contact resistance therebetween. The recess in conductive layer 55 can be formed by etching a portion of the top of conductive layer 55 when forming an opening in insulating layer 46.

[0071] 3(A) and other drawings, an insulating layer 56 is provided on insulating layer 46 and insulating layer 52, and conductive layer 53 is provided so that its upper surface is roughly flush with that of insulating layer 56. Conductive layer 24 is provided at a position overlapping conductive layer 53. An insulating layer 41 is provided above conductive layer 53 and insulating layer 56. Insulating layer 41 has a strip-shaped slit 20 extending in the Y direction. The side surfaces inside slit 20 of insulating layer 41 are preferably perpendicular or roughly perpendicular to the substrate surface. The height of slit 20 in insulating layer 41 is preferably 0.5 times or more the width of slit 20 in the X direction.

[0072] In the configurations shown in FIGS. 2A, 3A, etc., two transistors (hereinafter, sometimes referred to as a transistor 10a and a transistor 10b) are provided in one slit 20.

[0073] The conductive layer 25 is provided on the insulating layer 41. The conductive layer 25 (conductive layer 25a) of the transistor 10a and the conductive layer 25 (conductive layer 25b) of the transistor 10b are provided separately with a slit 20 sandwiched between them in a plan view. The conductive layer 25a and the conductive layer 25b can be formed by dividing a conductive layer extending in the X direction. Specifically, the conductive layer extends in the X direction and has a portion overlapping the slit 20 and a portion located outside the slit 20, and the portion overlapping the slit 20 is removed. This divides the conductive layer into the conductive layer 25a and the conductive layer 25b. Alternatively, the conductive layer 25 can be expressed as not being disposed in a region overlapping the slit 20. That is, a pair of conductive layers 25 are provided on the insulating layer 41 so as to sandwich one slit 20 therebetween. 1, 2(A), 3(A), etc., island-shaped conductive layers 25 are arranged at equal intervals along the extension direction (Y direction) of the slits 20. An insulating layer 42 is provided on the insulating layer 41, and the conductive layers 25 are formed so as to be embedded in the insulating layer 42, as shown in FIG.

[0074] 3C shows an example in which the end portions of the conductive layer 25 and the semiconductor layer 21 are approximately aligned. Such a structure can be formed, for example, when the conductive layer 25 and the semiconductor layer 21 are processed in the same process using the same mask. Furthermore, when the conductive layer 25 and the semiconductor layer 21 are processed in different processes, the end portions do not necessarily have to be aligned. For example, the end portion of the conductive layer 25 may be located outside the end portion of the semiconductor layer 21.

[0075] In a method for manufacturing a semiconductor device according to one embodiment of the present invention, a conductive layer to be the conductive layer 23 (a conductive layer 23f described later) is processed by anisotropic etching, so that the conductive layer 23 can be formed along the side surface of the slit 20. By using such a method, the conductive layer 23 can be formed without using a mask. In other words, by using a self-alignment process, the conductive layer 23 can be formed without using a mask. Therefore, the conductive layer 23 can be formed without considering the accuracy of alignment between the slit 20 and the mask, which is suitable for manufacturing a semiconductor device having a high degree of integration and fine transistors.

[0076] Furthermore, in a semiconductor device in which the slit width in the X direction of the slit 20 is small, it may be difficult to process a conductive layer with a large thickness inside the slit 20 (for example, a conductive layer that fills the slit 20). In a method for manufacturing a semiconductor device according to one embodiment of the present invention, a conductive layer that becomes the conductive layer 23 (a conductive layer 23f described below) is formed so as to cover the side surface of the slit 20, the upper surface of the conductive layer 25 with the semiconductor layer 21 interposed therebetween, and the bottom of the slit 20 (for example, the upper surface of the conductive layer 24). After that, the conductive layer 23 can be formed by removing a portion of the conductive layer 23f that covers the upper surface of the conductive layer 25 with the semiconductor layer 21 interposed therebetween and a portion of the conductive layer 23f that covers the bottom of the slit 20. Therefore, inside the slit 20, it is only necessary to remove the conductive layer at the bottom of the slit 20, and processing a thick conductive layer is not necessary. This simplifies the manufacturing process.

[0077] At this time, the conductive layer (conductive layer 23f) that becomes the conductive layer 23 may remain in regions other than the side surfaces of the slits 20, for example, on the side surfaces of the steps in regions where the surface on which the conductive layer 23f is to be formed has steps. Such unintended remaining conductive layer 23f may cause leakage between the plurality of transistors 10.

[0078] By providing the insulating layer 42 between the conductive layers 25, it is possible to reduce the step on the surface on which the conductive layer 23f is formed, thereby preventing the conductive layer 23f from unintentionally remaining.

[0079] The conductive layer remaining in areas other than the side surfaces of the slits 20 can also be removed by etching using a mask.

[0080] The semiconductor layer 21, the insulating layer 22, and the conductive layer 23 have portions located inside the slit 20. The semiconductor layer 21 and the insulating layer 22 are provided along the side surface of the insulating layer 41 and the upper surface of the conductive layer 24 inside the slit 20. The conductive layer 23 is provided inside the slit 20 so as to face the side surface of the insulating layer 41 with the semiconductor layer 21 and the insulating layer 22 sandwiched therebetween. In the configurations shown in FIGS. 2(A), 3(A), etc., the semiconductor layer 21 and the insulating layer 22 are also provided on the conductive layer 25.

[0081] The semiconductor layer 21, the insulating layer 22, the conductive layer 23, and the conductive layer 24 are divided into two parts inside the slit 20 along the extension direction of the slit 20. One of the divided pair of semiconductor layers 21, the pair of insulating layers 22, the pair of conductive layers 23, and the pair of conductive layers 24 is a component of the transistor 10a, and the other is a component of the transistor 10b. In Figure 3(A) and other drawings, the conductive layer 23, the conductive layer 24, and the conductive layer 25 of the transistor 10a are shown as the conductive layer 23a, the conductive layer 24a, and the conductive layer 25 of the transistor 10b are shown as the conductive layer 23b, the conductive layer 24b, and the conductive layer 25b. The semiconductor layer 21, insulating layer 22, and conductive layer 25 of the transistor 10b are continuous with the semiconductor layer 21, insulating layer 22, and conductive layer 25 of the transistor 10 provided in the slit 20 adjacent to the slit 20 in which the transistor 10b is provided. The semiconductor layer 21 and insulating layer 22 of the transistor 10a are provided along one of a pair of side surfaces inside the slit 20 of the insulating layer 41, and the semiconductor layer 21 and insulating layer 22 of the transistor 10b are provided along the other side surface.

[0082] The conductive layer 53 of the capacitance element 30 is arranged so as to overlap each of the pair of separated conductive layers 24. It can be expressed that one slit 20 is shared by two memory cells 15.

[0083] The height of the upper end of the conductive layer 23 (height H1 shown in FIG. 3(A)) is preferably equal to or less than the height of the upper surface of the insulating layer 22 on the conductive layer 25 (height H5 shown in FIG. 3(A)), and may be equal to or less than the height of the upper surface of the conductive layer 25 (height H4 shown in FIG. 3(A)), for example. In the configuration shown in FIG. 3(A) and other figures, the conductive layer 25 has a side surface that is continuous with the side surface of the slit 20. Here, height H4 is the height of the upper surface of the conductive layer 25. Height H4 is, for example, the height of the upper surface of the conductive layer 25 near the side surface that is continuous with the slit 20. Heights H1 to H5, etc., are heights from a reference plane. For example, the substrate surface can be used as the reference plane. Alternatively, for example, the upper surface of the insulating layer 11, the upper surface of the conductive layer 24, etc. can be used as the reference plane.

[0084] Furthermore, the insulating layer on the conductive layer 25 may become thinner during the manufacturing process. FIG. 4A shows an example in which the thickness of the insulating layer 22 on the conductive layer 25 is thinner than the thickness of the portion of the insulating layer 41 covering the side surface of the slit 20. Furthermore, the insulating layer 22 on the conductive layer 25 may disappear during the manufacturing process. In such a case, for example, it is preferable that the height of the upper end of the conductive layer 23 is equal to or lower than the height of the upper surface of the semiconductor layer 21 on the conductive layer 25. It is also preferable that the height of the upper end of the conductive layer 23 (height H1 shown in FIG. 3A) is higher than the height of the lower surface of the conductive layer 25 on the insulating layer 41 (height H3 shown in FIG. 3A, i.e., the height of the upper surface of the insulating layer 41 in FIG. 3A, etc.).

[0085] An insulating layer 59 is provided along the side surface of the conductive layer 23. It is preferable that the insulating layer 59 covers at least a part of the side surface of the conductive layer 23. The insulating layer 59 can be formed so as to cover the side surface of the conductive layer 23 by processing an insulating layer that will become the insulating layer 59 (insulating layer 59f, described later) by anisotropic etching.

[0086] The conductive layers 24 of the two opposing transistors 10 (transistor 10a and transistor 10b) can be formed by dividing one conductive layer. In this case, the insulating layer 59 can function as a mask when etching is performed to divide the conductive layer. Similarly, the semiconductor layers 21 and insulating layers 22 of the two transistors 10 can be divided using the insulating layer 59 as a mask.

[0087] In this way, the conductive layer 24, the semiconductor layer 21, and the insulating layer 22 of the two opposing transistors 10 can be formed using the insulating layer 59 as a mask. This eliminates the need to consider the accuracy of mask alignment, and allows for a higher integration density of the semiconductor device.

[0088] As shown in FIG. 4B, the insulating layer 59 covers the conductive layer 23, thereby reducing damage to the conductive layer 23 during the manufacturing process of the semiconductor device.

[0089] The insulating layer 59 is provided inside the slit 20 of the insulating layer 41 so as to face the side surface of the insulating layer 41 with the semiconductor layer 21, insulating layer 22, and conductive layer 23 sandwiched therebetween. The insulating layer 59 may also be expressed as a sidewall, a sidewall insulating layer, a sidewall protective layer, etc.

[0090] Furthermore, when the lower end of conductive layer 23 formed on conductive layer 24 is used as a reference, the height H2 of the upper end of insulating layer 59 is preferably at least 0.3 times the height of the upper end of conductive layer 23, and more preferably at least half of that.

[0091] Insulating layer 59 can be formed, for example, by forming an insulating layer that will become insulating layer 59 so as to cover the inside of slit 20 and the portion outside slit 20 on conductive layer 25, and then processing using anisotropic etching so as to leave a portion that covers the side surface of conductive layer 23. At this time, a portion that covers the upper end of conductive layer 23 may also remain. Figure 4(B) shows a configuration in which insulating layer 59 covers the upper end of conductive layer 23.

[0092] As a material for the insulating layer 59, for example, it is preferable to use a material that has a high selectivity under the etching conditions for the conductive layer 24, the semiconductor layer 21, and the insulating layer 22, specifically, a material that makes the etching rate of the insulating layer 59 sufficiently low under each etching condition.

[0093] The insulating layer 59 may be made of, for example, silicon nitride or silicon nitride oxide.

[0094] The semiconductor layer 21 has a portion in contact with the upper surface and side surfaces of the conductive layer 25, a portion in contact with the side surfaces of the insulating layer 41 inside the slit 20, and a portion in contact with the upper surface of the conductive layer 24.

[0095] Because the semiconductor layer 21 and the insulating layer 22 are formed along the side surfaces of the slits 20 in the insulating layer 41, their thicknesses may be thin depending on the film formation method. For example, in film formation methods such as sputtering or plasma-enhanced chemical vapor deposition (PECVD), films formed on surfaces inclined or perpendicular to the substrate surface tend to be thinner than films formed on surfaces parallel to the substrate surface. On the other hand, film formation methods such as atomic layer deposition (ALD) or thermal CVD can form films of uniform thickness regardless of the angle of the surface on which they are formed. For example, when the angle of the side surfaces of the slits 20 in the insulating layer 41 relative to the substrate surface is 75 degrees or more, 80 degrees or more, or 85 degrees or more, it is preferable to form the semiconductor layer 21 and the insulating layer 22 using the ALD method.

[0096] In the transistor 10, the source electrode and the drain electrode are located at different heights, so that the current flows in the semiconductor in the vertical direction. Since the transistor 10 can have two or more of the source electrode, the semiconductor, and the drain electrode stacked, the occupied area can be significantly reduced compared to a so-called planar transistor (also called a lateral transistor, LFET (Lateral FET)) in which the semiconductor is arranged on a plane.

[0097] Furthermore, the channel length of the transistor 10 can be precisely controlled by adjusting the thickness of the insulating layer 41, which functions as a spacer. This allows for extremely small variations in channel length compared to planar transistors. Furthermore, by thinning the insulating layer 41, transistors with extremely short channel lengths can be fabricated. Therefore, transistors with extremely short channel lengths that could not be achieved using mass-production exposure equipment can be realized. Furthermore, transistors with channel lengths of less than 10 nm can be fabricated without using the extremely expensive exposure equipment used in cutting-edge LSI technology.

[0098] The channel length of the transistor 10 is, for example, 0.1 to 60 nm, 0.1 to 50 nm, 0.1 to 40 nm, 0.1 to 30 nm, 0.1 to 20 nm, or 0.1 to 10 nm. Alternatively, it may be, for example, 1 to 60 nm, 1 to 50 nm, 1 to 40 nm, 1 to 30 nm, 1 to 20 nm, or 1 to 10 nm. Alternatively, it may be, for example, 5 to 60 nm, 5 to 50 nm, 5 to 40 nm, 5 to 30 nm, 5 to 20 nm, or 5 to 10 nm.

[0099] The channel length of the transistor 10 corresponds to the thickness of the insulating layer 41 on the conductive layer 24 and does not affect the area occupied by the transistor 10, for example, the area of ​​the transistor 10 in a plan view. By setting the channel length of the transistor 10 to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved in forming the insulating layer 41, forming the slits 20 in the insulating layer 41, and the like.

[0100] Although various semiconductor materials can be used for the semiconductor layer 21, it is particularly preferable to use an oxide semiconductor containing a metal oxide. By using an oxide semiconductor formed under appropriate conditions, a transistor having both a large on-current and an extremely low off-current can be realized at low cost. Unless otherwise specified, the following describes a configuration example in which an oxide semiconductor is used for the semiconductor layer 21.

[0101] 3(A) shows an example in which the upper surface of the conductive layer 24 in the region overlapping the slit 20 has a rounded recess (concave surface). As a result, inside the slit 20, the bottoms of the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 are each provided along the concave surface of the conductive layer 24. This makes it possible to realize a configuration in which the electric field is less likely to concentrate. As a result, a transistor with low leakage current and high reliability can be realized.

[0102] An insulating layer 44, which functions as an interlayer insulating layer, is provided to cover the insulating layer 22, the conductive layer 23, and the insulating layer 59. A conductive layer 26, which functions as a bit line, is provided on the insulating layer 44. A plug 27, which connects the conductive layer 25 to the conductive layer 26, is provided inside an opening provided in the insulating layer 44, the insulating layer 22, and the semiconductor layer 21. This allows the conductive layer 26 to connect the multiple conductive layers 25 arranged in the X direction with the slit 20 therebetween. In FIG. 3(A) and other figures, the plug 27 is provided so that a portion of the plug 27 is embedded in the conductive layer 25.

[0103] An insulating layer that functions as a protective insulating layer can be used as each of the insulating layer 46, the insulating layer 41, and the insulating layer 44. Alternatively, when the insulating layer 46, the insulating layer 41, and the insulating layer 44 have a stacked structure, one or more layers may include an insulating layer that functions as a protective insulating layer.

[0104] Fig. 5(A) shows the conductive layer 24 and layers located above the conductive layer 24 in the top view shown in Fig. 1, and Fig. 6(A) shows the conductive layer 24 and layers located below the conductive layer 24 in the top view shown in Fig. 1. Note that the conductive layer 26 and the plug 27 are omitted in Fig. 5(A).

[0105] 5(B) shows a cross-sectional view taken along a plane Q parallel to the XY plane, as viewed from the Z direction, and FIG. 6(B) shows a cross-sectional view taken along a plane R parallel to the XY plane, as viewed from the Z direction. In FIGS. 3(A) to 3(C), dashed two-dot lines corresponding to plane Q and plane R are shown, respectively.

[0106] As shown in FIGS. 1, 5A, and 5B, the conductive layer 23 is provided along the side surfaces of the slit 20. The conductive layer 23 is divided at the Y-direction end of the slit 20. That is, a pair of divided conductive layers 23 is provided inside the slit 20. In FIGS. 5A and 5B, the conductive layer 23 that functions as the gate of the transistor 10a is indicated as conductive layer 23a, and the conductive layer 23 that functions as the gate of the transistor 10b is indicated as conductive layer 23b. Two conductive layers 23 (conductive layer 23a and conductive layer 23b) are provided inside the slit 20, and the conductive layer 23a is provided along one of the two side surfaces of the slit 20 that face each other, and the conductive layer 23b is provided along the other side surface.

[0107] The conductive layer 23a and the conductive layer 23b each extend in the Y direction inside the slit 20. A plurality of transistors 10a arranged in the Y direction and a plurality of transistors 10b arranged in the Y direction are provided in the slit 20. The conductive layer 23a is shared among the plurality of transistors 10a. The conductive layer 23b is also shared among the plurality of transistors 10b.

[0108] As shown in FIGS. 6A and 6B, the conductive layer 51 preferably has a circular shape in plan view. In a single capacitive element 30, the conductive layer 51, the insulating layer 52, and the conductive layer 53 are preferably arranged in this order in a roughly concentric pattern. While the conductive layer 51 has a circular shape in plan view, the shape of the conductive layer 51 is not limited to a circular shape and may be an ellipse, a rectangle with rounded corners, or other shapes. The conductive layer 51 may have a regular polygon, such as an equilateral triangle, square, or regular pentagon, or a polygon other than a regular polygon. A concave polygon, such as a star-shaped polygon, with at least one interior angle exceeding 180°, can increase the channel width. Alternatively, the conductive layer 51 may have a polygon with rounded corners or a closed curve combining straight lines and curves. The shapes of the insulating layer 52 and the conductive layer 53 in plan view reflect the shape of the conductive layer 51.

[0109] The structures shown in FIGS. 7A to 7C differ from those shown in FIGS. 3B and 3C mainly in that an insulating layer 42 is not provided on an insulating layer 41. Because the insulating layer 42 is not required, the number of manufacturing steps can be reduced. Furthermore, when using the manufacturing method shown in FIGS. 27A to 30D (described later), the conductive layer 25 and the semiconductor layer 21 can be processed using the same mask, thereby simplifying the manufacturing steps. Furthermore, in the structure shown in FIG. 7B, the end of the conductive layer 25 and the end of the semiconductor layer 21 can be aligned. This is advantageous for integrating the transistor 10.

[0110] 8(A) is a top view selectively showing the conductive layer 55, the conductive layer 53, the conductive layer 24, and the conductive layer 23. The conductive layer 23, which functions as the wiring WL, is provided to extend in the Y direction. The conductive layer 55, which functions as the wiring PL, is provided to extend in the Y direction, and the conductive layer 24, which functions as one of the source electrode and the drain electrode of the transistor 10, is disposed in a position overlapping with the conductive layer 55. FIG. 8(A) can be applied, for example, to a configuration in which the wiring PL is parallel to the wiring WL.

[0111] 8(B), the conductive layer 55 may have a two-dimensional flat plate shape. Fig. 8(B) can be applied to a configuration in which the wiring PL is shared by memory cells 15 connected to different wirings WL, for example.

[0112] The conductive layer 55 may also be a wiring that extends in the X direction, or in a direction different from both the X and Y directions, or may have a lattice shape that combines two or more portions that extend in different directions.

[0113] The configuration of the semiconductor device shown in FIGS. 9A to 11 differs from the configuration of the semiconductor device shown in FIGS. 1 to 6B in that the capacitive element 30 is disposed in a slit provided in the insulating layer 46.

[0114] 9A shows a top view of a semiconductor device 50. FIG. 9B shows a perspective view of the semiconductor device 50 shown in FIG. 9A. However, in FIG. 9A, the semiconductor layer 21, the conductive layer 23, and the insulating layer 59 are omitted for clarity. For the structure of the transistor 10 including the semiconductor layer 21, the conductive layer 23, and the insulating layer 59, refer to FIGS. 1 and 2A.

[0115] Figures 10(A) and 10(B) show cross-sectional views taken along the cutting lines AB and EF shown in Figure 9(A), respectively. Figure 11 shows a cross-sectional view of a cross section taken along a plane R2 parallel to the XY plane, viewed from the Z direction, and Figures 10(A) and 10(B) show a two-dot chain line corresponding to plane R2.

[0116] A plurality of slits 40 are provided in the insulating layer 46. The slits 40 extend in the Y direction. A plurality of capacitive elements 30 corresponding to a plurality of memory cells 15 arranged in the Y direction are provided in the slits 40. It is preferable that the side surfaces of the insulating layer 46 within the slits 40 are perpendicular or approximately perpendicular to the substrate surface. It is preferable that the height of the insulating layer 46 is greater than its width in the X direction.

[0117] Two slits 40 are provided for each slit 20. The slits 40 are provided at positions shifted in the X direction from the centers of the slits 20.

[0118] The slit 40 is provided so as to reach the conductive layer 55. The conductive layer 51 contacts the upper surface of the conductive layer 55 at the bottom of the slit 40.

[0119] The conductive layer 51 has a portion provided along the side surface of the insulating layer 46 at the slit 40 and a portion in contact with the upper surface of the conductive layer 55. The conductive layer 51 has a U-shaped cross section parallel to the XZ plane, and has a recess. The insulating layer 52 has a portion provided along the recess of the conductive layer 51, a portion in contact with the upper surface of the conductive layer 51, and a portion in contact with the upper surface of the insulating layer 46. The conductive layer 53 is provided so as to fill the recess of the conductive layer 51 via the insulating layer 52. The conductive layer 53 also has a portion provided on the insulating layer 46 via the insulating layer 52. The conductive layer 51 is provided so as to extend in the Y direction inside the slit 40. That is, the conductive layer 51 is provided in common to multiple capacitive elements 30 positioned in the Y direction. On the other hand, the conductive layer 53 is provided individually for each memory cell 15.

[0120] As shown in FIG. 11 and other figures, the conductive layer 51 is provided along the extension direction (Y direction) of the slit 40. Within the slit 40, the conductive layers 53 are provided at equal intervals in the Y direction. The conductive layer 51 may also be provided at the Y direction end of the slit 40, thereby providing a ring-shaped conductive layer along the side surface of the slit 40. In FIG. 11, the conductive layer 51 and the insulating layer 52 are provided along the side surface of the insulating layer 46 at the Y direction end of the slit 40, so that the conductive layer 51 and the insulating layer 52 each have a ring-shaped cross-sectional shape. Furthermore, the ring-shaped cross section can be expressed as a cross section parallel to the XY plane.

[0121] 10(A) and other figures, the bottom of the conductive layer 51 is rounded. The bottom of the insulating layer 52 provided along the conductive layer 51 and the bottom of the conductive layer 24 provided along the insulating layer 52 also have a rounded shape. This prevents the insulating layer 52 from becoming locally thin. Furthermore, it also prevents localized concentration of the electric field.

[0122] Furthermore, a rounded recess is provided on the top surface of conductive layer 55, and the bottom of conductive layer 51 is provided to fit into this recess. With this configuration, the contact area between conductive layer 55 and conductive layer 51 is increased, thereby reducing the contact resistance therebetween. The recess in conductive layer 55 can be formed by etching a portion of the top of conductive layer 55 when forming slits 40 in insulating layer 46.

[0123] When the conductive layer 51 extends in the Y direction, the conductive layer 55 does not necessarily have to be located on the entire bottom surface of the conductive layer 51. For example, the conductive layer 55 may be disposed only in a region overlapping the end of the conductive layer 51 extending in the Y direction and its vicinity. In this case, the conductive layer 51 functions as a wiring extending in the Y direction.

[0124] Here, in the above example, the slits 20 and 40 extend in the same direction (here, the Y direction), but the slits 20 and 40 may extend in different directions.

[0125] <Conductive layer> The conductive layer 24 and the conductive layer 25 are in contact with the semiconductor layer 21. When an oxide semiconductor is used as the semiconductor layer 21, if an easily oxidized metal such as aluminum is used in the portion of the conductive layer 24 or the conductive layer 25 in contact with the semiconductor layer 21, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 24 or the conductive layer 25 and the semiconductor layer 21, preventing electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material for at least the portion of the conductive layer 24 and the conductive layer 25 in contact with the semiconductor layer 21.

[0126] As the conductive layer in contact with the semiconductor layer 21, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. These are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxidized, and are therefore preferable.

[0127] Alternatively, conductive oxides such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide, and Ga-Zn oxide can be used. Conductive oxides containing indium are particularly preferred due to their high conductivity. Alternatively, oxide materials such as In-Ga-Zn oxide that can be used for the semiconductor layer 21 can also be used as a conductive layer by increasing the carrier concentration.

[0128] For example, the conductive layer 24 and the conductive layer 25 can each have a single-layer structure of the above-mentioned conductive oxide film, a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are stacked in this order, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on tungsten, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on the above-mentioned conductive oxide film, or a two-layer structure in which the above-mentioned conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film.

[0129] The conductive layer 23 functions as a gate electrode and can be made of various conductive materials. For example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing such a metal element, may be used. Alternatively, nitrides of the above metals or alloys, or oxides of the above metals or alloys, may be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel may be used. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may be used.

[0130] The conductive layer 23 may be made of the nitride or oxide that can be used for the conductive layers 24 and 25 described above.

[0131] Since the conductive layers 23, 24, and 25 also function as wiring, it is preferable to use a laminate of low-resistance conductive materials. For example, the conductive layers 24g and 25h can also be made of the low-resistance conductive materials that can be used for the conductive layer 23 described above.

[0132] <Insulating layer> The insulating layer 11, the insulating layer 35, the insulating layer 41, the insulating layer 42, the insulating layer 44, and the insulating layer 46 each function as an interlayer insulating film.

[0133] The insulating layer that functions as an interlayer insulating film is preferably formed by a film forming method such as a sputtering method or a plasma CVD method.

[0134] Furthermore, it is preferable to use a film formation method that allows for high film formation rate for the insulating layer that functions as an interlayer insulating film. For example, a silicon oxide film (also called a TEOS film) formed using TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC2H5)4) using a plasma CVD method may be used. This can improve productivity.

[0135] In particular, the layers in contact with or near the semiconductor layer 21 of the transistor 10, such as the insulating layer 41 and the insulating layer 44, preferably have an insulating layer that suppresses impurity diffusion and an insulating layer that functions as an impurity barrier film, thereby making it possible to suppress the diffusion of impurities into the semiconductor layer 21.

[0136] The insulating layer 41 is preferably an oxide insulating film because it is in contact with the channel formation region of the semiconductor layer 21. In particular, it is preferably an oxide insulating film that releases oxygen when heated. The insulating layer 41 can be an oxide insulating film that can be used for the gate insulating layer.

[0137] Furthermore, when the insulating layer 41 is formed by a sputtering method, hydrogen is not used as a deposition gas, and therefore the insulating layer 41 can have an extremely low hydrogen content. Therefore, supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 10 can be stabilized.

[0138] The insulating layer 59 is preferably made of a material that provides a sufficiently low etching rate under the etching conditions for the conductive layer 24, the semiconductor layer 21, and the insulating layer 22. For example, silicon nitride or silicon nitride oxide can be used for the insulating layer 59. Alternatively, for example, a material with a high relative dielectric constant, which will be described later, can be used for the insulating layer 59.

[0139] The insulating layer 52 functions as a dielectric for the capacitance element 30. The insulating layer 52 can be made of the same insulating material as the insulating layer 22. By using the ferroelectric material for the insulating layer 52, the capacitance element 30 can be made into a ferroelectric capacitor, thereby realizing a nonvolatile memory device. Note that the capacitance element 30 can also be a resistance change type memory element that utilizes the electric field induced giant resistance change (CER: Colossal Electro-Resistance) effect.

[0140] The conductive layer and the insulating layer may each have a stacked structure.

[0141] 12(A), 12(B), and 12(C) show an example in which the conductive layer 24 shown in FIGS. 3(A), 3(B), and 3(C) has a conductive layer 24g and a conductive layer 24h on the conductive layer 24g. Also, an example in which the conductive layer 25 has a conductive layer 25g and a conductive layer 25h on the conductive layer 25g is shown. Also, an example in which the insulating layer 41 has an insulating layer 41a, an insulating layer 41b on the insulating layer 41a, and an insulating layer 41c on the insulating layer 41b is shown. Also, an example in which the insulating layer 44 has an insulating layer 44a on the insulating layer 22 and the conductive layer 23, an insulating layer 44b covering the side surfaces of the insulating layer 44a, the side surfaces of the insulating layer 59, the side surfaces of the conductive layer 24, and the top surface of the insulating layer 56, and an insulating layer 44c covering the side surfaces of the insulating layer 44b and filling the inside of the slit 20 is shown.

[0142] It is preferable to use a conductive oxide (oxide conductor) for each of the conductive layers 24h and 25h.

[0143] Using a conductive oxide for the conductive layer 24h and the conductive layer 25h, which have a large contact area with the semiconductor layer 21 containing a metal oxide, is preferable because it reduces the contact resistance between the semiconductor layer and the conductive layer and reduces the load on the wiring. In particular, a configuration containing the same metal element as the metal element contained in the semiconductor layer 21 is preferable because it further reduces the contact resistance. Specifically, it is preferable that both the semiconductor layer 21 and the conductive layer contain the same one or more elements selected from In, Sn, Zn, Ga, and Ti. In particular, it is preferable that the semiconductor layer 21 and the conductive layer contain In.

[0144] Conductive layer 24g is preferably made of a conductive material having a lower resistance than conductive layer 24h. In particular, it is preferable that it contains a metal material. Conductive layer 25g is preferably made of a conductive material having a lower resistance than conductive layer 25h. In particular, it is preferable that it contains a metal material. By forming the conductive layer into a laminated structure of a layer using a low-resistance metal material and a layer that can reduce contact resistance, it is possible to reduce both contact resistance and wiring resistance, and therefore it is possible to further reduce the load on the wiring.

[0145] 12(A) shows an example in which plug 27 penetrates conductive layer 25h and is provided so as to be in contact with conductive layer 25g. This configuration in which low-resistance conductive layer 25g and plug 27 are in contact with each other is preferable because it reduces the contact resistance between them and reduces the wiring load. Alternatively, the bottom surface of plug 27 may be in contact with conductive layer 25h or with semiconductor layer 21.

[0146] The semiconductor layer 21 is provided in contact with the side surface of the insulating layer 41 inside the slit 20. It is preferable to use an oxide insulating film for the insulating layer 41b. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated. It is also preferable to have a structure in which the insulating layer 41b is sandwiched between insulating layers 41a and 41c that have a barrier property against oxygen. This makes it possible to confine oxygen contained in the insulating layer 41b in a region surrounded by the insulating layers 41a, 41c, and the semiconductor layer 21. Furthermore, it is possible to prevent oxygen in the insulating layer 41b from being desorbed and reduced during the process. This makes it possible to more efficiently supply oxygen to the semiconductor layer 21.

[0147] The portion of the semiconductor layer 21 that is in contact with the insulating layer 41b is a region with reduced oxygen vacancies and can be considered an i-type region. On the other hand, the portion that is not in contact with the insulating layer 41b is preferably an n-type region that contains many carriers. That is, the portion of the semiconductor layer 21 that is in contact with the insulating layer 41b can be called a channel formation region, and the region outside of that can be called a low-resistance region (also called a source region or a drain region).

[0148] The insulating layer 41b is preferably a film containing as little hydrogen as possible because it is in contact with the semiconductor layer 21. Carriers are generated when oxygen vacancies in the semiconductor layer 21 combine with hydrogen, which may affect the threshold voltage of the transistor 10, for example. Therefore, an insulating film other than an oxide insulating film through which hydrogen does not easily diffuse may be used as the insulating layer 41b. For example, a single layer of an insulating film having a barrier property against hydrogen and oxygen may be used as the insulating layer 41.

[0149] The insulating layer 41b can be used as an interlayer insulating film. For example, it is preferable to form the insulating layer 41b by a film formation method such as a sputtering method or a plasma CVD method. In particular, when a sputtering method is used, hydrogen is not used as a film formation gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 10 can be stabilized.

[0150] The insulating layer 41b is preferably an oxide insulating film because it is in contact with the channel formation region of the semiconductor layer 21. In particular, it is preferably an oxide insulating film that releases oxygen when heated. The oxide insulating film that can be used for the gate insulating layer can be used as the insulating layer 41b.

[0151] Furthermore, since the insulating layer 41b functions as an interlayer insulating layer, it is preferable to use a film formation method that allows for film formation at a higher film formation rate than other insulating layers. For example, an insulating film formed using TEOS by plasma CVD may be used as the insulating layer 41b. This can improve productivity.

[0152] Furthermore, since insulating layer 41b functions as an interlayer insulating layer, by using an insulating layer with a lower dielectric constant than other insulating layers, the parasitic capacitance between conductive layer 24 and conductive layer 25 can be reduced.

[0153] It is preferable that the insulating layers 41a and 41c are made of films that do not easily diffuse hydrogen. By sandwiching the insulating layer 41b between the insulating layers 41a and 41c, which do not easily diffuse hydrogen, it is possible to prevent external hydrogen from entering the insulating layer 41b that contacts the semiconductor layer 21.

[0154] For example, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used for the insulating layer 41a and the insulating layer 41c. Silicon nitride and silicon nitride oxide in particular have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate, and are therefore suitable for use as the insulating layer 41a and the insulating layer 41c.

[0155] The insulating layer 44b preferably functions as a barrier film against impurities, thereby preventing impurities such as hydrogen contained in layers located above the insulating layer 44b from diffusing into the semiconductor layer 21.

[0156] For example, the configurations and materials exemplified for the insulating layer 41a and the insulating layer 41c can be applied to the insulating layer 44b. Also, for example, the configurations and materials exemplified for the insulating layer 41b can be applied to the insulating layer 44a and the insulating layer 44c.

[0157] The insulating layer 44a can function as an interlayer insulating film between the conductive layer 25 and the conductive layer 26. By using an insulating layer with a low dielectric constant as the insulating layer 44a, the parasitic capacitance between the conductive layer 25 and the conductive layer 26 can be reduced. Furthermore, the insulating layer 44c is located between two opposing conductive layers 23. By using an insulating layer with a low dielectric constant as the insulating layer 44c, the parasitic capacitance between the two opposing conductive layers 23 can be reduced.

[0158] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide and silicon oxynitride, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low relative dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0159] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0160] As a barrier film for preventing the diffusion of hydrogen, etc., a film in which hydrogen is less likely to diffuse than in a silicon oxide film (having barrier properties against hydrogen), such as a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, or a gallium oxide film, can be used. In particular, it is preferable to use a silicon nitride film or a silicon nitride oxide film.

[0161] The insulating layers 46, 41, 44, and the like are preferably formed by stacking an insulating film functioning as a barrier film and an insulating film having a function of capturing or fixing hydrogen. The insulating film having a function of capturing or fixing hydrogen is preferably disposed closer to the semiconductor layer 21 of the transistor 10 or the capacitor 30 than the insulating film functioning as a barrier film. This allows hydrogen to be captured or fixed by the insulating film due to heat or the like applied during the manufacturing process of the transistor 10 or the capacitor 30, thereby reducing the concentration of hydrogen in the transistor 10 or the capacitor 30. Therefore, a highly reliable memory cell 15 with favorable electrical characteristics can be realized. A hafnium oxide film, a hafnium silicate film, an aluminum oxide film, a hafnium zirconium oxide film, or the like is preferably used as the insulating film that captures or fixes hydrogen.

[0162] 13 differs from FIG. 12(A) in that the conductive layer 26 has a configuration that serves both as a conductive layer on the insulating layer 44 and as a plug to be embedded in the opening of the insulating layer 44. The conductive layer 26 shown in FIG. 13 and the like can be formed using, for example, a dual damascene process.

[0163] 13 shows an example in which the conductive layer 26 has a conductive layer 26a and a conductive layer 26b on the conductive layer 26a. A conductive layer with high coverage is preferably used as the conductive layer 26a. Alternatively, a conductive layer having barrier properties against oxygen, hydrogen, and the like may be used as the conductive layer 26a. For example, a metal nitride can be used as the conductive layer 26a. Alternatively, a material with high conductivity is preferably used as the conductive layer 26b.

[0164] 14(A) to 14(C) are different from those of FIGS. 12(A) to 12(C) mainly in that the insulating layer 41a includes an insulating layer 41a_1 and an insulating layer 41a_2, and the upper surface of the insulating layer 41a_2 is planarized. The insulating layer 41a_1 can be formed, for example, by a film formation method with high coverage, preferably by an ALD method. The insulating layer 41a_2 can be formed, for example, by a method with high film formation rate, preferably by a sputtering method. The insulating layer 41a_2 is formed so as to fill the regions between the multiple conductive layers 24. The upper surface of the insulating layer 41a_2 is preferably planarized by a planarization treatment.

[0165] The top surfaces of the insulating layer 41a, the insulating layer 41b, and the insulating layer 41c can be flattened. For example, after the insulating layer 41a is formed, the insulating layer 41a is subjected to planarization treatment. Chemical mechanical polishing (CMP) is suitable as the planarization treatment. Note that etching (also referred to as etch-back treatment) may be performed as the planarization treatment. After the planarization treatment is performed on the insulating layer 41a, the insulating layer 41b and the insulating layer 41c are formed on the insulating layer 41a, thereby flattening the top surfaces of the insulating layer 41b and the insulating layer 41c. Here, by performing the planarization treatment on the insulating layer 41a, for example, the thickness of the insulating layer 41a in a region that does not overlap with the conductive layer 24 can be made thicker than the thickness of the insulating layer 41a in a region that overlaps with the conductive layer 24.

[0166] If the etching time is long in the etching step for processing the semiconductor layer 21 inside the slit 20, the insulating layer 41 will be exposed to the etching gas for a long time in the region of the insulating layer 41 inside the slit 20 that does not overlap with the conductive layer 24. In such a case, the etching may extend to the insulating layer 56 below the insulating layer 41 in that region, resulting in unintended processing of the insulating layer 56. By increasing the thickness of the insulating layer 41a in the region that does not overlap with the conductive layer 24, unintended processing of the insulating layer 56 can be suppressed.

[0167] Here, a material that functions as a ferroelectric and that can be used for the insulating layer 52 of the capacitor element 30 will be described.

[0168] Ferroelectric materials include oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. It is also preferable to use materials in which a Group 3 (IIIa) element is added to these oxides. For example, it is preferable to include one or more of scandium, yttrium, and lanthanoid elements. Yttrium, lanthanum, and scandium are particularly preferable because they are relatively easy to handle and have high compatibility with semiconductor manufacturing processes. Adding such elements not only ensures stable ferroelectricity, but also suppresses characteristic degradation during repeated rewriting, improving reliability. It also improves the breakdown voltage of the insulating layer 52. For example, these elements are preferably added at a ratio of 0.5 atomic % to 10 atomic %. Here, the content of these elements can be calculated so that the content of the metal elements in the metal oxides listed above is 100 atomic %. For example, when a first metal element and a second metal element are added to hafnium oxide, the sum of the contents of hafnium, the first metal element, and the second metal element can be calculated to be 100 atomic %. Other additive elements include silicon, aluminum, gadolinium, and scandium. Note that the insulating layer 52 can be made of not only a material exhibiting ferroelectricity, but also a material exhibiting antiferroelectricity.

[0169] Oxides containing either or both of hafnium and zirconium easily exhibit ferroelectricity even in extremely thin films prepared using thin film deposition methods such as sputtering and atomic layer deposition. This makes them highly compatible with semiconductor manufacturing processes and allows for reduced manufacturing costs.

[0170] Alternatively, the insulating layer 52 may be made of piezoelectric ceramics having a perovskite structure, such as barium titanate, lead titanate, strontium titanate, barium strontium titanate (BST), lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), or bismuth ferrite (BFO).

[0171] Alternatively, the insulating layer 52 may be made of an organic ferroelectric material such as polyvinylidene fluoride (PVDF) or a copolymer of vinylidene fluoride (VDF) and trifluoroethylene (TrFE).

[0172] The ferroelectric material may be, for example, a mixture or compound of multiple materials selected from the materials listed above. Alternatively, the insulating layer 52 may have a layered structure made of multiple materials selected from the materials listed above.

[0173] Among these, hafnium oxide, a material containing hafnium oxide and zirconium oxide (HZO), and a material containing yttrium in addition to HZO (HZYO) are preferred as ferroelectric materials because they exhibit ferroelectricity even in thin films of only a few nanometers. By using a film containing hafnium oxide, HZO, or HZYO, the thickness of insulating layer 52 can be set to 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 3 nm or more and 20 nm or less, and even more preferably 4 nm or more and 10 nm or less.

[0174] In addition, hafnium zirconium oxide (HfZrO X When using a plasma-enhanced ALD (where X is a real number greater than 0), it is preferable to form the film using an ALD method, particularly a thermal ALD method. It is also preferable to use an ALD method (including a thermal ALD method) that uses plasma to enhance reactivity (PEALD: Plasma Enhanced ALD).

[0175] Furthermore, when using the thermal ALD method, a material containing an organometallic compound can be used as a precursor. For example, when using hafnium zirconium oxide, an organometallic compound such as tetrakis(ethylmethylamido)hafnium (TEMAHf) can be used as a precursor containing hafnium, and tetrakis(ethylmethylamido)zirconium (TEMAZr) can be used as a precursor containing zirconium. Alternatively, a material that does not contain a hydrocarbon group can be used. For example, a chlorine-based material can be used as a precursor that does not contain a hydrocarbon group. Note that when using hafnium zirconium oxide, a chlorine-based precursor such as HfCl4 or ZrCl4 can be used as a precursor.

[0176] When an oxide such as hafnium oxide, zirconium oxide, or hafnium zirconium oxide is used for the insulating layer 52, the remanent polarization may be increased by including an appropriate amount of carbon.

[0177] Furthermore, when hafnium zirconium oxide is used for the insulating layer 52, it is preferable to alternately deposit layers containing hafnium and layers containing zirconium using a thermal ALD method or a PEALD method so that the hafnium and zirconium have a composition of 1:1 [atomic ratio] or a composition close to that.

[0178] The oxidizing agent used in the thermal ALD method or the PEALD method can be H2O or O3. However, the oxidizing agent is not limited to these, and O2, N2O, NO2, H2O2, etc. can also be used, or two or more of these can be used. In particular, to reduce the hydrogen concentration and nitrogen concentration in the film, it is preferable to use O2 or O3 as the oxidizing agent, and it is particularly preferable to use O3.

[0179] The film used for the insulating layer 52 preferably has a low hydrogen concentration in the film. This prevents hydrogen from diffusing from the insulating layer 52 to the semiconductor layer 21, which can prevent the carrier concentration in the semiconductor layer 21 from increasing. Specifically, the hydrogen concentration in the film is 5×10 20 atoms / cm 3Less than 1×10 is preferred 20 atoms / cm 3 The following is more preferred:

[0180] The crystalline structure of the film used for the insulating layer 52 is not particularly limited as long as it is a crystal structure that does not have centrosymmetrical structure and has polarity. For example, a crystal system other than a cubic system may be used. The film used for the insulating layer 52 may have a single crystal structure, a polycrystalline structure, or a composite structure having an amorphous structure and a crystalline structure.

[0181] The conductive layer 51 and the conductive layer 53, which are in contact with or near the insulating layer 52, are preferably made of a conductive material that has a function of absorbing oxygen. This allows oxygen to be absorbed from the insulating layer 52, thereby increasing the oxygen vacancy concentration in the insulating layer 52. This increases the remnant polarization of the insulating layer 52. As the conductive material that has a function of absorbing oxygen, it is preferable to use a metal or an alloy. In particular, it is preferable to use tungsten, molybdenum, titanium, tantalum, or the like. In particular, tungsten is preferable because it easily increases the remnant polarization of the insulating layer 52 from the viewpoint of stress.

[0182] It is also preferable to use a conductive material that does not easily diffuse oxygen for the conductive layers 51 and 53. This improves the withstand voltage of the insulating layer 52 and improves the rewrite durability of the ferroelectric capacitor. In particular, it is preferable to use a metal nitride such as titanium nitride or tantalum nitride.

[0183] The conductive layer 53 may have a stacked structure. In this case, a low-resistance conductive material is preferably used on the side not in contact with the insulating layer 52. For example, a metal or alloy containing one or more selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc. can be used. In particular, high-melting-point materials such as tungsten, molybdenum, tantalum, ruthenium, and hafnium are preferable because they allow for higher temperatures in subsequent heat treatments. In addition to the above low-resistance conductive materials, oxide materials such as indium tin oxide, indium tin oxide with added silicon, indium zinc oxide, and indium gallium zinc oxide may also be used.

[0184] Here, the semiconductor device 50 preferably has a layer in which the memory cells 15 are provided and a layer in which the functional circuits are provided stacked. The functional circuits may include, for example, a drive circuit for driving the memory cells 15, an arithmetic circuit, a power supply circuit, etc. The drive circuit may include, for example, one or more of a row decoder, a column decoder, a row driver, a column driver, an input circuit, an output circuit, a sense amplifier, etc. This not only reduces the footprint of the semiconductor chip including the semiconductor device 50, but also shortens the wiring length compared to when the functional circuits and the memory cells 15 are arranged side by side, thereby achieving high-speed operation and low power consumption.

[0185] 15 shows an example in which a layer 80 in which a memory cell 15 is provided and a transistor 90 constituting a functional circuit are arranged below the layer 80. Here, one of a source electrode and a drain electrode of the transistor 90 is connected to a conductive layer 26 functioning as a bit line. Although FIG. 15 shows an example in which two layers 80 (layer 80[1] and layer 80[2]) are stacked, the layer 80 may be a single layer or three or more layers.

[0186] The transistor 90 is a transistor in which a channel is formed in a part of a substrate 91, which is a single-crystal semiconductor substrate. The substrate 91 can typically be made of single-crystal silicon. Alternatively, the substrate 91 can be made of a semiconductor made of a single element such as germanium, or a compound semiconductor made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or gallium nitride. Alternatively, the substrate 91 can be a semiconductor substrate having an insulator region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate.

[0187] The transistor 90 is provided on a substrate 91 and includes a conductive layer 94 functioning as a gate, an insulating layer 93 functioning as a gate insulating layer, a semiconductor region 92 formed of part of the substrate 91, and a low-resistance region 95a and a low-resistance region 95b functioning as a source region and a drain region. The transistor 90 can be either a p-channel type or an n-channel type. An element isolation layer 98 is provided in the substrate 91 between two adjacent transistors 90.

[0188] In the transistor 90, a semiconductor region 92 in which a channel is formed has a convex shape (fin shape). Although not shown in Fig. 15, a conductive layer 94 is provided to cover the side and top surfaces of the semiconductor region 92 in the Y direction via an insulating layer 93. Such a transistor 90 is also called a FIN-type transistor.

[0189] An insulating layer 96 is provided covering the transistor 90, an insulating layer 86 is provided on the insulating layer 96, and an insulating layer 87 is provided on the insulating layer 86. A conductive layer 81 is provided so as to be embedded in the insulating layer 87. An insulating layer 88 is provided covering the conductive layer 81 and the insulating layer 87, an insulating layer 45 is provided on the insulating layer 88, and an insulating layer 11 is provided on the insulating layer 45. A plug 82 is provided inside an opening provided in the insulating layer 96 and the insulating layer 86, and the conductive layer 81 and the low-resistance region 95b are connected by the plug 82. A conductive layer 84 is provided on the insulating layer 45, and a plug 83 is provided inside an opening provided in the insulating layer 45 and the insulating layer 88, connecting the conductive layer 84 and the conductive layer 81. The conductive layer 84 and the conductive layer 26 are connected via a plug 85 provided inside an opening provided in each insulating layer between them. This connects one of the source and drain of the transistor 90 to the conductive layer 26.

[0190] Although an example in which a conductive layer 81 is provided as a wiring layer is shown here, a structure in which interlayer insulating layers and wiring layers are alternately stacked (also referred to as a multilayer wiring layer) can be used between the layer in which the transistor 90 is provided and the layer 80 in which the memory cell 15 is provided.

[0191] The plug 85 connects the conductive layer 84 and the conductive layer 26 of the layer 80[1]. The plug 89 also connects the conductive layers 26 of the two layers 80 together. As a result, the two conductive layers 26 of the layer 80[1] and the layer 80[2] are connected to one of the source and drain of the transistor 90.

[0192] Although the configuration shown here is one in which the layer 80 is stacked directly on the substrate 91 on which the transistor 90 is provided, this is not limiting. For example, the substrate 91 on which the transistor 90 is provided and the substrate on which the memory cell 15 is provided may be bonded together. For example, the two substrates may be bonded together by direct bonding (hybrid bonding) using a direct bonding technique, such as Cu-Cu bonding. Alternatively, a method may be used in which two or more layers are bonded together with their insulating films, and then through electrodes are formed to connect the electrodes provided on each layer. In particular, using a method using direct bonding or through electrodes allows the pitch of the connection electrodes to be extremely narrow, making it possible to arrange a large number of connection electrodes at high density, which is preferable because it increases the amount of data transmitted between layers.

[0193] When bonding two layers, any of the following methods can be used: CoC (Chip on Chip) bonding, CoW (Chip on Wafer) bonding, and WoW (Wafer on Wafer) bonding. WoW bonding is highly productive because it bonds wafers together, but it can reduce yields because all chips, including both good and bad, must be bonded together. On the other hand, CoW bonding, which bonds chips to wafers, and CoC bonding, which bonds chips together, are inferior to WoW bonding in terms of productivity, but their ability to bond good chips together significantly improves yields. CoC bonding is also less productive than the other two methods, but is highly versatile because it can bond two layers even when the sizes are significantly different.

[0194] A wiring layer such as an interposer may be provided between the two layers, which eliminates the need to align the positions of bonding electrodes between two adjacent layers, allowing for greater freedom in the design of each layer and enabling the realization of a higher performance semiconductor device.

[0195] [About the components] <substrate> Substrates on which transistors are formed can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Examples of semiconductor substrates having an insulating region within the semiconductor substrate, such as an SOI substrate, are also available. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Substrates containing metal nitrides and substrates containing metal oxides can also be used. Examples of substrates include an insulating substrate with a conductive layer or semiconductor layer provided thereon, a semiconductor substrate with a conductive layer or insulating layer provided thereon, and a conductive substrate with a semiconductor layer or insulating layer provided thereon. These substrates may also be used with elements provided thereon. The elements provided on the substrate include a capacitor element, a resistor element, a switch element (including a transistor), a light-emitting element, a memory element, and the like.

[0196] Semiconductor layer The semiconductor layer 21 preferably includes a metal oxide (oxide semiconductor).

[0197] As described above, the semiconductor layer 21 has a channel formation region. The semiconductor layer 21 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region. The semiconductor layer 21 may have a stacked structure of two or more layers.

[0198] The crystallinity of the semiconductor material used for the semiconductor layer 21 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0199] OS transistors have oxygen vacancies (V O ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. O H) and generate electrons that serve as carriers. Therefore, if the channel formation region in the metal oxide contains oxygen vacancies, the OS transistor is likely to be normally on. Therefore, it is preferable that the channel formation region in the metal oxide has as few oxygen vacancies and impurities as possible reduced. In other words, it is preferable that the channel formation region in the metal oxide has a reduced carrier concentration and is made i-type (intrinsic) or substantially i-type.

[0200] On the other hand, the source and drain regions of the OS transistor have more oxygen vacancies than the channel formation region. O The source and drain regions of an OS transistor are preferably n-type regions with a high carrier concentration and low resistance, which are obtained by increasing the concentration of H or impurities such as hydrogen, nitrogen, or metal elements. That is, the source and drain regions of an OS transistor are preferably n-type regions with a high carrier concentration and low resistance compared to the channel formation region.

[0201] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for an oxide semiconductor layer, the off-state current of a transistor can be reduced. Because the off-state current of an OS transistor is small, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, a semiconductor device can operate at high speed.

[0202] For example, indium oxide can be used as a metal oxide for the semiconductor layer of an OS transistor.

[0203] Examples of the metal oxide that can be used for the semiconductor layer of an OS transistor include oxides containing one or more elements selected from In, Sn, Zn, Ga, Al, and Ti. In these oxides, the content of each of the one or more elements selected from In, Sn, Zn, Ga, Al, and Ti is preferably 1 atomic % or more, for example.

[0204] Examples of the metal oxide include, in addition to the above-mentioned indium oxide, zinc oxide, tin oxide, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also written as "GZO"), aluminum zinc oxide (Al-Zn oxide, also written as "AZO"), indium Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also written as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as "IGZTO"), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as "IGAZO" or "IAGZO"). Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0205] Specifically, the composition of the In-Zn oxide can be In:Zn=1:1 (atomic ratio) or a composition close thereto, In:Zn=2:1 (atomic ratio) or a composition close thereto, or In:Zn=4:1 (atomic ratio) or a composition close thereto, where the term "close to" includes a range of ±30% of the desired atomic ratio.

[0206] Specifically, the composition of the In-M-Zn oxide may be a metal oxide having an In:M:Zn=1:1:1 (atomic ratio) or a composition close thereto, an In:M:Zn=1:1:1.2 (atomic ratio) or a composition close thereto, an In:M:Zn=1:1:0.5 (atomic ratio) or a composition close thereto, an In:M:Zn=1:1:2 (atomic ratio) or a composition close thereto, an In:M:Zn=4:2:3 (atomic ratio) or a composition close thereto, an In:M:Zn=1:3:2 (atomic ratio) or a composition close thereto, or an In:M:Zn=1:3:4 (atomic ratio) or a composition close thereto. Alternatively, examples of a composition containing a trace amount of element M include a composition in which the atomic ratio of In:M:Zn is 4:0.1:1 or thereabout, a composition in which the atomic ratio of In:M:Zn is 2:0.1:1 or thereabout, or a composition in which the atomic ratio of In:M:Zn is 1:0.1:1 or thereabout. Examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.

[0207] Crystal structures of metal oxides that function as semiconductors include amorphous (including completely amorphous), c-axis-aligned crystalline (CAAC), nanocrystalline (nc), cloud-aligned composite (CAC), single crystal, and polycrystal.

[0208] Furthermore, by increasing the ratio of the number of zinc atoms to the total number of atoms of the metal elements among the main component elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0209] Furthermore, by increasing the ratio of the number of atoms of element M to the total number of atoms of metal elements among the main component elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies is suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0210] By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased. Typically, by using single-crystal or polycrystalline indium oxide for the semiconductor layer, the field-effect mobility of the transistor can be significantly increased. Furthermore, a transistor using single-crystal or polycrystalline indium oxide for the semiconductor layer can achieve good frequency characteristics.

[0211] For example, the oxide semiconductor layer of one embodiment of the present invention includes a crystalline metal oxide. Examples of the structure of the crystalline metal oxide include a CAAC structure, a polycrystalline structure, and an nc structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0212] Note that the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material for a channel formation region, such as a semiconductor made of a single element or a compound semiconductor.

[0213] Examples of semiconductors made of simple elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0214] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned metal oxides are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0215] Hereinafter, an indium oxide film that can be used as the oxide semiconductor layer of one embodiment of the present invention will be described.

[0216] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0217] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0218] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 44(A) shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO X ), and FIG. 44(B) is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0219] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as indicated by the arrows in Figure 44(B). On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as indicated by the arrows in Figure 44(A) (see Non-Patent Document 1). This tendency is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is, and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties closer to silicon. Note that the characteristics of indium oxide shown in Figure 44(A) are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 44(A).

[0220] In Figure 44(A), the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration is 1 × 10 15 cm -3 The range includes, for example, 1×10 14 cm -3 That's it, 1 x 10 18 cm -3 By sufficiently reducing the carrier concentration, the Hall mobility can be reduced to 270 cm 2 It is expected that the efficiency can be increased to about / (V·s).

[0221] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0222] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. 20 cm -3 The range includes, for example, 1×10 19 cm -3 That's it, 1 x 10 22 cm -3 By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 -4 It is expected that the resistance can be reduced to Ω·cm or less.

[0223] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains the same element as the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0224] In this way, the low-carrier-concentration region of indium oxide is used as the channel region of a transistor, while the high-carrier-concentration region is used as the source and drain regions. In other words, indium oxide can be considered an oxide capable of valence electron control. Note that IGZO can sometimes develop strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. However, unlike IGZO, indium oxide can be valence-controlled, eliminating the need for strain within the film as in IGZO. Minimizing strain within the film is expected to improve reliability. For example, by creating regions within the indium oxide film with carrier concentrations in the range R1 and the range R2 shown in Figure 44(A), a so-called nin junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Valence electron control in silicon-based transistors is generally known. However, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0225] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) a high on-current (in other words, high mobility); (2) a low off-current; (3) a normally-off state; (4) high reliability; and (5) a high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, a low off-current, and is normally-off. The transistor has high mobility and is different from a normally-on transistor.

[0226] Note that a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in Figure 44(B), in IGZO, the lower the carrier concentration, the lower the hole mobility. Therefore, when Ef = Ei, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and the transistor may no longer function. On the other hand, in indium oxide, as shown in Figure 44(A), the lower the carrier concentration, the higher the hole mobility. When Ef = Ei, the hole mobility is maximized. That is, a transistor containing indium oxide can achieve high field-effect mobility by achieving Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0227] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated using the constant current method. More specifically, Vth is the value of the drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of a transistor when the value is 1 nA (1 × 10 -9 A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristics of a transistor is expressed logarithmically and the tangent with the maximum slope is Id=1 pA (1×10 -12 A) is the gate voltage (Vg) at the intersection with the line A), or the Vg at the intersection between the line extrapolated from the two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor and the line where Id = 1 pA. For example, if either or both of Vth and Vsh are zero or positive, the transistor can be considered to be normally off.

[0228] Furthermore, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef=Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef=Ei can be obtained.

[0229] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0230] The above film configuration can also be considered as a stacked configuration of a film capable of supplying oxygen to the indium oxide film from the indium oxide film side (e.g., a silicon oxide film), a film capable of gettering hydrogen (e.g., a hafnium oxide film), and a film suppressing the penetration of oxygen and hydrogen (e.g., a silicon nitride film). With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that minimizes the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to an i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0231] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also referred to as microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0232] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0233] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED), or a combination of these methods may be used.

[0234] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis changes continuously around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0235] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, source electrode, and drain electrode.

[0236] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can act as a scattering source for carriers, which can result in a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably has a concentration of each of these impurities of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that carbon, hydrogen, and the like are elements that can be contained in the film formation gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0237] The indium oxide film in the channel formation region may contain elements that can form the same trivalent cations as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such elements include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist primarily as trivalent cations in oxides, allowing the carrier concentration of indium oxide to be maintained low.

[0238] Furthermore, the indium oxide film in this specification etc. has a high film density. Table 1 shows the film density of an indium oxide film (here, In2O3) applicable to one embodiment of the present invention.

[0239] [Table 1]

[0240] As shown in Table 1, the film density of the indium oxide film was evaluated at six levels, Sample 1 to Sample 6. In Table 1, Condition 1 is the condition of the base of the indium oxide film, Samples 1 to 3 are glass, Sample 4 is an SiOx film formed by sputtering, and Samples 5 and 6 are yttria-stabilized zirconia (YSZ). Condition 2 is the film formation condition of the indium oxide film, Samples 1 to 3 are film formation by sputtering (SP), and Samples 4 to 6 are film formation by ALD. Condition 3 is the heat treatment condition after the indium oxide film is formed. Sample 1, Sample 4, and Sample 5 are not heat treated (as-depo), Sample 2 is baked at 350°C in a CDA atmosphere, Sample 3 is baked at 650°C in a CDA atmosphere, and Sample 6 is baked at 250°C in a vacuum atmosphere.

[0241] In Table 1, CDA stands for clean dry air. It is preferable that the atmosphere used for the heat treatment (condition 3) after the indium oxide film formation contains as little hydrogen and water as possible. It is preferable to use a high-purity gas with a dew point of −60°C or less, preferably −100°C or less, as the atmosphere.

[0242] As shown in Table 1, the indium oxide film tends to have a higher film density when subjected to heat treatment compared to when not subjected to heat treatment (Sample 1, Sample 4, or Sample 5). This is because the heat treatment removes impurity elements (e.g., carbon, nitrogen, hydrogen, argon, etc.) from the film, resulting in a higher purity of the indium oxide film. Furthermore, as shown in Samples 5 and 6, the indium oxide film on YSZ has a film density of 7.00 g / cm. 3 The theoretical film density of an indium oxide film is 7.18 g / cm 3 In this specification, the range of the film density of the indium oxide film is 6.70 g / cm 3 More than 7.18g / cm 3Preferably, it is 6.90 g / cm or less. 3 More than 7.18g / cm 3 More preferably, it is 7.00 g / cm or less. 3 More than 7.18g / cm 3 The following is the result.

[0243] The film density can be evaluated using, for example, Rutherford backscattering spectroscopy (RBS) or X-ray reflectometry (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscope (TEM) images. In TEM observation, if the film density is high, the transmission electron (TE) image will be dense (dark), and if the film density is low, the transmission electron (TE) image will be pale (bright).

[0244] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm 2 / (V·s) or more, preferably 100 cm 2 / (V·s) or more, preferably 150 cm 2 / (V·s) or more, more preferably 200 cm 2 / (V·s) or more, more preferably 250 cm 2 / (V·s) or more.

[0245] One of the features of the indium oxide film is that it has higher oxygen permeability (diffusibility) than the IGZO film. As shown in Figure 44(C), the indium oxide film (InO X Oxygen (O) that diffuses into the indium oxide film passes through the indium oxide film and is released as oxygen molecules (O2). It may also react with hydrogen contained in the film and be released as water molecules (H2O). In addition, oxygen vacancies (V O ) exists, the diffusing oxygen atoms compensate for the oxygen vacancies. Since oxygen diffuses easily in an indium oxide film, it can be said that oxygen vacancies are more easily compensated for in comparison with an IGZO film.

[0246] As described above, an indium oxide film is more likely to reduce oxygen vacancies in the film than an IGZO film, and therefore, by applying such an indium oxide film to a transistor, a transistor with extremely high reliability can be realized.

[0247] Furthermore, as shown in Figure 44(C), the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and is released as hydrogen molecules (H2). Alternatively, hydrogen reacts with oxygen contained in the film and is released as water molecules.

[0248] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0249] Table 2 shows the effective masses of single-crystal indium oxide (here, In2O3) and single-crystal silicon (Si). As shown in Table 2, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, it is possible to realize transistors with high field-effect mobility and high frequency characteristics (also called f characteristics). Furthermore, because the effective mass of holes is large, it is possible to realize transistors with extremely small off-current. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1 × 10 -15 A) or less, or 1aA (1 × 10 -18 A) or less, and under room temperature (25°C) -18 A) or less, or 1zA (1 x 10 -21Furthermore, as shown in Table 2, indium oxide has a smaller effective mass for electrons and a larger effective mass for holes than silicon, which may enable the realization of a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0250] [Table 2]

[0251] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0252] One method for evaluating the degree of lattice mismatch is to use the lattice mismatch value shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, an indium oxide film) to the crystals of the seed layer is calculated as Δa = ((L1 - L2) / L2) × 100. Here, L1 is the length or lattice constant of the unit lattice vector of the crystals of the formed film, and L2 is the length or lattice constant of the unit lattice vector of the crystals of the seed layer.

[0253] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0254] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0255] The crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film with hexagonal or trigonal crystal structure can be used underneath an indium oxide film with cubic crystal structure. For example, by using a

[0001] crystal orientation on the surface of the seed layer and a

[0111] crystal orientation on the underside of the indium oxide film, the crystal orientation requirements for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include the wurtzite structure, YbFe2O4 structure, Yb2Fe3O7 structure, and modified structures thereof. An example of a crystal with the YbFe2O4 structure or Yb2Fe3O7 structure is IGZO. Note that indium oxide single crystal films can be formed not only on YSZ substrates but also on insulating films. On the other hand, it is difficult to form silicon single crystal films on insulating films. Note that silicon crystals have a diamond structure. As described above, indium oxide and silicon have similar properties in terms of single crystals. However, when comparing indium oxide and silicon in terms of whether they can form single crystals on an insulating film, they have different properties.

[0256] The semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors. For example, semiconductors made of simple elements or compound semiconductors can be used. Examples of semiconductors made of simple elements include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. These semiconductor materials may contain impurities as dopants.

[0257] Alternatively, the semiconductor layer 21 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0258] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (elements belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides applicable to the semiconductor layer of a transistor include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0259] The crystallinity of the semiconductor material used for the semiconductor layer 21 is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0260] <Gate insulating layer> The insulating layer 22 functions as a gate insulating layer of the transistor. When an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide insulating film for at least a film of the insulating layer 22 that is in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga-Zn oxide can be used. In addition, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can also be used for the insulating layer 22. Furthermore, the insulating layer 22 may have a stacked structure, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0261] Furthermore, the insulating layer 22 is preferably formed by laminating insulating materials made of high-k materials having a high relative dielectric constant, and preferably by using a laminate structure of a high-k material and a material having a higher dielectric strength than the high-k material. For example, the insulating layer 22 can be formed by laminating an insulating film (also referred to as ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order. Alternatively, the insulating film (also referred to as ZAZA) in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in this order can be used. Alternatively, the insulating film can be formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By laminating an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength can be improved, and electrostatic breakdown of the capacitor element can be suppressed.

[0262] Furthermore, a material exhibiting ferroelectricity may be used for the insulating layer 22. Examples of the material exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. X (X is a real number greater than 0). X Metal oxides with Y (yttrium) added to HfZrO can also be used. X The addition of Y to the compound can enhance the ferroelectricity.

[0263] When the insulating layer 22 has a two-layer structure, it is preferable to use an insulating film having a function of capturing or fixing hydrogen as the film in contact with the semiconductor layer 21, and to use an insulating film having a barrier property against hydrogen as the film located on the conductive layer 23 side that functions as the gate electrode. This makes it possible to suppress diffusion of hydrogen from the conductive layer 23 side to the semiconductor layer 21, thereby realizing a highly reliable transistor.

[0264] As an insulating film that captures or fixes hydrogen, it is preferable to use a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, etc. Furthermore, as an insulating film having a barrier property against hydrogen, it is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, etc.

[0265] Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film having a barrier property against hydrogen may be used as a film located on the conductive layer 23 side. Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film that has a function of capturing or fixing hydrogen may be used as a film located on the conductive layer 23 side.

[0266] When the insulating layer 22 has a three-layer structure, it is preferable to use an insulating film made of a material with a lower dielectric constant than the other films as the film in contact with the semiconductor layer 21, an insulating film with barrier properties against hydrogen and oxygen as the film located on the conductive layer 23 side, and an insulating film with the function of capturing or fixing hydrogen as the film located between them. Silicon oxide or silicon oxynitride can be used as the material with a low dielectric constant. With this configuration, oxygen can be supplied to the semiconductor layer 21 from the film in contact with the semiconductor layer 21. Furthermore, the film located on the conductive layer 23 side prevents oxygen from diffusing toward the conductive layer 23, thereby suppressing oxidation of the conductive layer 23.

[0267] As the insulating film having a barrier property against oxygen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, a hafnium silicate film, etc. As the insulating film having a barrier property against oxygen and hydrogen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, etc.

[0268] When the insulating layer 22 has a four-layer structure, it is preferable to use an insulating film having a barrier property against oxygen for the film in contact with the semiconductor layer 21, an insulating film made of a material having a lower dielectric constant than the other films for the film next closest to the semiconductor layer 21, an insulating film having a function of capturing or fixing hydrogen for the film next closest to the semiconductor layer 21, and an insulating film having a barrier property against hydrogen and oxygen for the film closest to the conductive layer 23. That is, in addition to the above-mentioned three-layer structure, a configuration can be obtained in which a film in contact with the semiconductor layer 21 is added. By using an insulating film having a barrier property against oxygen for the film in contact with the semiconductor layer 21, oxygen desorption from the semiconductor layer 21 can be suppressed. In this case, it is preferable to use an aluminum oxide film as the film in contact with the semiconductor layer 21. Aluminum oxide not only has a barrier property against oxygen but also has the function of capturing or fixing hydrogen, thereby preventing hydrogen from diffusing into the semiconductor layer 21.

[0269] When the insulating layer 22 has a laminated structure, each insulating film is preferably a thin film. For example, by making the thickness of the insulating layer 22 1 nm to 20 nm, preferably 3 nm to 10 nm, the subthreshold swing value (also referred to as the S value) of the transistor can be reduced. Furthermore, the thickness of each insulating film is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm.

[0270] A specific example of the insulating layer 22 is a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 21 side, and it is preferable that the thicknesses of these films are 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 21 side.

[0271] In this specification and the like, the barrier property means a property that makes it difficult for a target substance to diffuse, a property that has low permeability to a target substance, or a function that suppresses the diffusion of a target substance. When hydrogen is described as a target substance, it means, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. - Furthermore, unless otherwise specified, impurities when described as a target substance refer to impurities in the channel formation region or semiconductor layer, and refer to at least one of, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Furthermore, oxygen when described as a target substance refers to at least one of, for example, oxygen atoms, oxygen molecules, etc.

[0272] Here, a transistor using a metal oxide film can have stable electrical characteristics by being surrounded by an insulating film that has a function of suppressing the permeation of impurities and oxygen. The insulating film that has a function of suppressing the permeation of impurities and oxygen can be, for example, an insulating film containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer.

[0273] Specifically, examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include nitrides such as aluminum nitride, nitrides containing aluminum and titanium, silicon nitride oxide, and silicon nitride.

[0274] Incidentally, nitrides containing aluminum and titanium may be either insulating or conductive depending on the ratio of the aluminum and titanium contents.

[0275] Examples of insulating film materials capable of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or fix hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, silicon may be added to these oxides to achieve an amorphous structure. For example, an oxide containing hafnium and silicon (hafnium silicate) is preferably used. Metal oxides may have crystalline regions and / or grain boundaries.

[0276] This concludes the description of the components.

[0277] [Example of manufacturing method] An example of a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described below, taking as an example a semiconductor device including the memory cell 15 exemplified in the above structure example.

[0278] The thin films (insulating layers, semiconductor layers, conductive layers, etc.) that make up the semiconductor device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition method, etc.

[0279] Furthermore, thin films (insulating layers, semiconductor layers, conductive layers, etc.) constituting the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0280] Sputtering methods include RF sputtering, which uses a high-frequency power source for sputtering; DC sputtering, which uses a direct current power source; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is preferred for film formation using insulating targets. DC sputtering is primarily used for film formation using conductive targets. In addition to forming conductive layers, DC sputtering can also form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used to form films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0281] CVD methods can be classified into PECVD, thermal CVD (TCVD) which uses heat, and photo-CVD (Photo-CVD) which uses light. They can also be further divided into metal CVD (MCVD) and metal organic CVD (MOCVD) depending on the source gas used.

[0282] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is possible to minimize plasma damage to the workpiece. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0283] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0284] Unlike sputtering, CVD and ALD are film formation methods that are less affected by the shape of the workpiece and have good step coverage. ALD, in particular, has excellent step coverage and thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0285] In the CVD method, a film of any composition can be formed by adjusting the flow rate ratio of the source gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0286] In the ALD method, films of any composition can be formed by simultaneously introducing multiple different precursors. Alternatively, when multiple different precursors are introduced, films of any composition can be formed by controlling the number of cycles of each precursor. Also, like the CVD method, films with continuously changing compositions can be formed.

[0287] The thin film constituting the semiconductor device can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Alternatively, the island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0288] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0289] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed using immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as light for exposure. Instead of light for exposure, an electron beam can also be used. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0290] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0291] <Production method example 1> A manufacturing method of the semiconductor device shown in FIGS. 1 to 6B will be described with reference to FIGS.

[0292] 16A to 26D are top views or cross-sectional views corresponding to each step in the manufacturing method described below. In each figure, (A) shows a top view, and (B), (C), and (D) show cross-sectional views along the cutting lines AB, CD, and EF shown in the top view.

[0293] First, a substrate (not shown) is prepared, and an insulating layer 56 is formed on the substrate. Note that, although a conductive layer 53 is embedded in the insulating layer 56 in FIGS. 1 to 6B, a method for manufacturing a capacitor element 30 including the conductive layer 53 will be described later, and the conductive layer 53 will not be described here.

[0294] The substrate may be a substrate having heat resistance sufficient to withstand at least the subsequent heat treatment.

[0295] An inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used as the insulating layer 56. The insulating layer 56 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0296] Next, conductive layer 24g and conductive layer 24h on conductive layer 24g are formed as conductive layer 24 on insulating layer 56. Next, insulating layer 41 is formed on conductive layer 24 and insulating layer 56. Here, insulating layer 41 has a layered structure of insulating layer 41a, insulating layer 41b, and insulating layer 41c. After planarizing the top surface of insulating layer 41b, insulating layer 41c is formed, thereby making it possible to planarize the top surface of insulating layer 41.

[0297] The insulating layer 41 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0298] The insulating layer 41 is preferably an oxide film containing a large amount of oxygen to the extent that oxygen is released by heating, and a small amount of hydrogen. The insulating layer 41 can be formed by a film formation method such as PECVD, sputtering, or ALD, but is preferably formed by sputtering. In particular, by forming the insulating layer 41 using a gas containing oxygen instead of a gas containing hydrogen, an insulating film containing an extremely small amount of hydrogen and an excess amount of oxygen can be formed. By forming the insulating layer 41 in this manner, oxygen can be supplied from the insulating layer 41 to the channel formation region of the semiconductor layer 21, thereby reducing oxygen vacancies.

[0299] Subsequently, heat treatment may be performed. The heat treatment is preferably performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, and then in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for desorbed oxygen. By performing the above heat treatment, impurities such as water and hydrogen contained in the insulating layer 41 and the like can be reduced before the formation of an oxide semiconductor film to be a semiconductor layer.

[0300] Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is set to 1 ppb (0.001 ppm) or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being introduced into the insulating layer 41 and the like as much as possible.

[0301] A process for supplying oxygen may be performed after the insulating layer 41 is formed. This allows oxygen to be supplied from the insulating layer 41 to the semiconductor layer 21f by heat or the like applied after the semiconductor layer 21f is formed.

[0302] Examples of treatments for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating layer by forming an oxide film (preferably a metal oxide film) by sputtering in an oxygen-containing atmosphere. The formed oxide film may be removed immediately or may be left as is. Note that the oxygen-containing atmosphere includes not only oxygen (O2) but also atmospheres containing gases of oxygen-containing compounds such as ozone (O3) and dinitrogen monoxide (NO).

[0303] Next, a conductive layer 25g and a conductive layer 25h on the conductive layer 25g are formed on the insulating layer 41 as the conductive layer 25. The conductive layers 25g and 25h can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method. The conductive layer 25 is provided to extend in the X direction.

[0304] Next, an insulating film that will become the insulating layer 42 is formed on the conductive layer 25, and planarization is performed until the top surface of the conductive layer 25 is exposed, thereby forming the insulating layer 42 (FIGS. 16A to 16D). This allows the conductive layer 25 to be embedded in the insulating layer 42.

[0305] The insulating layer 42 may not be provided if it is not necessary.

[0306] Next, a mask MSK is formed on the conductive layer 25 and the insulating layer 42 (FIGS. 17A to 17D). The mask may have a three-layer structure including, for example, an SOC (Spin On Carbon) film, an SOG (Spin On Glass) film on the SOC film, and a resist on the SOG film. As shown in FIG. 17A, the mask MSK has an opening extending in the Y direction.

[0307] Next, the mask MSK is used to remove the conductive layer 25, the insulating layer 42, and a portion of the insulating layer 41 (FIGS. 18(A) to 18(D)). As a result, the slits 20 are formed in the insulating layer 41. Furthermore, the conductive layer 25 is divided by removing the regions of the conductive layer 25 that overlap with the slits 20. Furthermore, the insulating layer 42 is formed with slits that overlap with the slits 20. In plan view, the conductive layer 25 is divided into a plurality of conductive layers with the slits 20 sandwiched between them.

[0308] When forming the slit 20, it is preferable to etch a portion of the conductive layer 24 located at the bottom of the slit 20 to form a recess in the conductive layer 24. At this time, it is preferable to perform etching so that a concave curved surface is formed on the upper part of the conductive layer 24. It is also preferable that a concave curved surface is formed on the upper surface of the insulating layer 41 in the part where the conductive layer 24 is not provided.

[0309] Furthermore, when forming slits 20 in insulating layer 41, dividing conductive layer 25, and forming slits in insulating layer 42 at positions overlapping with slits 20, it is preferable to use anisotropic dry etching so that the side surfaces exposed by processing of each layer are perpendicular or approximately perpendicular to the top surface of insulating layer 56. Depending on the processing conditions, the side surfaces of slits 20 may be inclined relative to the direction perpendicular to the surface on which they are formed, resulting in a tapered shape.

[0310] Next, if the mask MSK remains, the mask MSK is removed. Note that the mask MSK may become thinner or disappear when processing the insulating layer 41, etc.

[0311] Subsequently, a semiconductor layer 21f that will become the semiconductor layer 21 is deposited to cover the upper and side surfaces of the conductive layer 25 and the upper and side surfaces of the insulating layer 41 (FIGS. 19(A) to 19(D)).

[0312] The semiconductor layer 21f may be a metal oxide (oxide semiconductor) film having semiconductor properties. The metal oxide film may be formed by a suitable method such as sputtering, CVD, MBE, PLD, or ALD. The metal oxide film is preferably formed in contact with a side surface of the insulating layer 41 that is perpendicular or substantially perpendicular to the upper surface of the insulating layer 56. Therefore, the metal oxide film is preferably formed by a method with good coverage, and more preferably by ALD.

[0313] The metal oxide film preferably has crystallinity. In particular, the metal oxide film of one embodiment of the present invention preferably contains a metal oxide having a CAAC structure.

[0314] It is preferable to perform a treatment to enhance the crystallinity of the metal oxide film during or after the formation of the metal oxide film. Examples of treatments to enhance the crystallinity of the metal oxide film include heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. A plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0315] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the metal oxide film multiple times during the formation of the metal oxide film. For example, when forming a metal oxide film by the ALD method, it is preferable to perform a microwave plasma treatment after each atomic layer is formed. Alternatively, it is preferable to perform a treatment for increasing the crystallinity after each metal oxide film having a thickness within a predetermined range is formed, which can improve productivity. Specifically, it is preferable to form a first metal oxide film having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second metal oxide film having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment.

[0316] The deposition method for the first metal oxide film and the second metal oxide film is not particularly limited, and ALD or sputtering can be used for each. In particular, forming the first metal oxide film by ALD is preferable because it can prevent elements from the layer constituting the surface to be formed from being mixed into the first metal oxide film and the second metal oxide film (also called "mixing"). This is particularly suitable when the element contained in the layer constituting the surface to be formed inhibits crystallization of the metal oxide (for example, when the layer contains silicon, carbon, or the like). The first metal oxide film and the second metal oxide film may have different compositions. While a stacked structure of the first metal oxide film and the second metal oxide film is illustrated here, the present invention is not limited to this. The same process can be applied to a single-layer or a stacked structure of three or more layers of metal oxide films.

[0317] Furthermore, a treatment for increasing the crystallinity of a metal oxide film may be performed after the metal oxide film is formed. Specifically, the treatment may be performed directly on the formed metal oxide film, or may be performed through another film, such as an insulating film, formed on the metal oxide film. For example, a microwave plasma treatment may be performed after the metal oxide film is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc.) may be formed after the metal oxide film is formed, and then a heat treatment or a microwave plasma treatment may be performed on the metal oxide film through the insulating film.

[0318] The above-described treatment for increasing the crystallinity of a metal oxide film can also serve as a treatment for removing impurities contained in the metal oxide film. For example, carbon, hydrogen, nitrogen, and the like contained in the metal oxide film can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of a metal oxide film in an oxygen gas atmosphere, oxygen vacancies in the metal oxide film can be reduced.

[0319] When performing a process to enhance the crystallinity of a metal oxide film, it is preferable to set the substrate temperature to room temperature (e.g., 25°C) or higher, 100°C or higher and 700°C or lower, 100°C or higher and 600°C or lower, or 300°C or higher and 450°C or lower.

[0320] By increasing the crystallinity of the metal oxide film, a highly reliable transistor can be realized.

[0321] The metal oxide film can be formed by, for example, a sputtering method using a metal oxide target.

[0322] The metal oxide film is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film is preferably a high-purity film with as few impurities as possible, such as hydrogen and water, as reduced as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film.

[0323] Furthermore, when forming a metal oxide film, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film can be, and a transistor with a higher on-state current can be obtained.

[0324] When forming a metal oxide film, the higher the substrate temperature, the higher the crystallinity and density of the metal oxide film, whereas the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film.

[0325] The conditions for forming the metal oxide film include a substrate temperature of room temperature or higher and 250° C. or lower, preferably room temperature or higher and 200° C. or lower, and more preferably room temperature or higher and 140° C. or lower. For example, a substrate temperature of room temperature or higher and lower than 140° C. is preferred because it increases productivity. Furthermore, by forming the metal oxide film at room temperature or without intentional heating, the crystallinity can be reduced.

[0326] When using the ALD method, it is preferable to use a film formation method such as thermal ALD or PEALD. Thermal ALD is preferable because it exhibits extremely high step coverage. PEALD is also preferable because it exhibits high step coverage and allows for low-temperature film formation.

[0327] For example, when a metal oxide is used for the semiconductor layer 21, the semiconductor layer 21 can be formed by the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0328] For example, when forming an In-Ga-Zn oxide film, three precursors can be used: an indium-containing precursor, a gallium-containing precursor, and a zinc-containing precursor. Alternatively, two precursors can be used: an indium-containing precursor and a gallium- and zinc-containing precursor.

[0329] Examples of precursors that can be used that contain indium include trimethylindium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.

[0330] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.

[0331] Furthermore, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0332] As the oxidizing agent, for example, ozone, oxygen, water, etc. can be used.

[0333] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, and the order in which the source gases are flowed. By adjusting these, it is also possible to deposit a film whose composition changes continuously. It is also possible to deposit two or more films with different compositions consecutively.

[0334] After the metal oxide film is formed, heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the metal oxide film does not polycrystallize, preferably 250°C to 650°C, more preferably 400°C to 600°C. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen.

[0335] The gas used in the heat treatment is preferably highly purified. For example, the moisture content of the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas for the heat treatment, moisture and the like can be prevented from being incorporated into the metal oxide film as much as possible.

[0336] Although the semiconductor layer 21f is shown as a single layer in the drawings, it may have a laminated structure. For example, it may have a two-layer structure formed by the ALD method, a three-layer structure formed by the ALD method, a two-layer structure in which the first layer is formed by the ALD method and the second layer is formed by sputtering, or a three-layer structure in which the first layer is formed by the ALD method, the second layer is formed by sputtering, and the third layer is formed by either the ALD method or the sputtering method. Forming the first layer by the ALD method is preferable because it can suppress mixing, but it can also be formed by sputtering. Note that the semiconductor layer 21f may have a laminated structure of four or more layers.

[0337] Next, a portion of the semiconductor layer 21f is removed by etching to form the semiconductor layer 21 (FIGS. 20(A) to 20(D)). When etching the semiconductor layer 21, it is difficult to remove the portion in contact with the side surface of the insulating layer 41 by anisotropic dry etching alone, so it is preferable to perform etching by combining isotropic dry etching and wet etching. Alternatively, a region of the semiconductor layer 21f that is not covered by the resist mask may be treated in advance to modify a portion of the semiconductor layer 21f to make it easier to etch. Examples of such treatment include plasma treatment, doping (including ion implantation), and wet treatment.

[0338] Subsequently, the insulating layer 22 is formed to cover the semiconductor layer 21 and the insulating layer 41. The insulating layer 22 can be formed by a film formation method such as sputtering, ALD, or CVD. It is preferable that the insulating layer 22 be provided with as uniform a thickness as possible on the surface of the portion of the semiconductor layer 21 that covers the side surface of the insulating layer 41. For this reason, it is particularly preferable to form the insulating layer 22 by the ALD method, which is a film formation method with extremely excellent coverage. Note that when the side surface of the insulating layer 41 is tapered, the insulating layer 22 can be formed by a film formation method such as sputtering or CVD.

[0339] Next, a conductive layer 23f, which will later become the conductive layer 23, is formed to cover the insulating layer 22 (FIGS. 21(A) to 21(D)). The conductive layer 23f can be formed by a CVD method, an ALD method, a sputtering method, or the like. From the viewpoint of coverage, it is particularly preferable to form the conductive layer 23f by a CVD method.

[0340] Subsequently, the conductive layer 23f is processed by anisotropic etching to form the conductive layer 23 along the side surface of the slit 20 (FIGS. 22(A) to 22(D)). By using a film that is formed isotropically on the surface to be formed as the conductive layer 23f, the conductive layer 23 can be formed on the side surface of the slit 20 by anisotropic etching.

[0341] At this time, it is preferable to process conductive layer 23f so that the upper end of conductive layer 23 is located higher than the lower surface of conductive layer 25g. If the height of the upper end of conductive layer 23 is lower than the height of the lower surface of conductive layer 25g, a so-called offset region is formed where no gate electric field is applied to semiconductor layer 21. On the other hand, if the height of the upper end of conductive layer 23 is higher than the lower surface of conductive layer 25g, no offset region is formed, and a transistor with a large on-current can be realized.

[0342] Subsequently, an insulating layer 59f is formed so as to cover the insulating layer 22 and the conductive layer 23 (FIGS. 22A to 22D). The insulating layer 59f has a portion located on the insulating layer 42 with the insulating layer 22 sandwiched therebetween, a portion facing the side surfaces of the insulating layer 42 and the insulating layer 41 with the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 sandwiched therebetween, and a portion facing the upper surface of the conductive layer 24 with the semiconductor layer 21 and the insulating layer 22 sandwiched therebetween.

[0343] Subsequently, the insulating layer 59f is processed by anisotropic etching to form the insulating layer 59 (FIGS. 23(A) to 23(D)).

[0344] It is preferable to remove at least the portion of insulating layer 59f that covers the bottom of slit 20. At this time, the upper end of insulating layer 59 is processed so that it is lower than the upper end of conductive layer 23, for example. If insulating layer 59f remains in the portion that covers the bottom of slit 20, there is a concern that etching may be insufficient in the subsequent step of dividing conductive layer 24, semiconductor layer 21, and insulating layer 22.

[0345] Next, an insulating layer 44a is formed on the insulating layer 22, the conductive layer 23, and the insulating layer 59. Next, a hard mask HM and a mask MSK2 are stacked on the insulating layer 44a (FIGS. 24(A) to 24(D)). The hard mask HM is less likely to change shape during etching, so changes in the width of the opening due to mask recession can be suppressed. Here, tungsten is used as an example. As shown in FIG. 24(A), the mask MSK2 has an opening extending in the Y direction, the width of the opening is narrower than the width of the slit 20, and the X-direction end of the opening is arranged so as to be contained within the slit 20. The hard mask HM is processed using the mask MSK2.

[0346] Next, if the mask MSK2 remains, the mask MSK2 is removed. Note that the mask MSK2 may become thin or disappear when processing the hard mask HM.

[0347] Next, a hard mask HM is used to form slits 28 in the insulating layer 44a (FIGS. 25(A) to 25(D)). In FIGS. 25(A) to 25(C), the insulating layer 59 is exposed by forming the slits 28 in the insulating layer 44a.

[0348] Next, the insulating layer 22, the semiconductor layer 21, and the conductive layer 24 are processed using the hard mask HM and the insulating layer 59 as masks, and the insulating layer 22, the semiconductor layer 21, and the conductive layer 24 are divided inside the slit 20. Thereafter, the hard mask HM is removed (FIGS. 26(A) to 26(D)).

[0349] Through the above steps, the transistor 10 can be formed.

[0350] <Production method example 2> A manufacturing method of the semiconductor device shown in Figures 7A to 7C will be described with reference to Figures 27A to 30D. The semiconductor device shown in Figures 7A to 7C does not have an insulating layer 42.

[0351] 27A to 30D are top views or cross-sectional views corresponding to each step in the manufacturing method described below. In each figure, (A) shows a top view, and (B), (C), and (D) show cross-sectional views along the cutting lines AB, CD, and EF shown in the top view.

[0352] First, a substrate (not shown) is prepared, and an insulating layer 56 is formed on the substrate. Next, a conductive layer 24 is formed on the insulating layer 56. Next, an insulating layer 41 is formed on the conductive layer 24. Next, a conductive layer 25f is formed on the insulating layer 41. Next, a mask MSK is formed on the conductive layer 25f (FIGS. 27(A) to 27(D)). The conductive layer 25f is a conductive layer that will later become the conductive layer 25. The conductive layer 25f has a conductive layer 25f2 and a conductive layer 25f1 on the conductive layer 25f2, and the conductive layer 25f1 and the conductive layer 25f2 are conductive layers that will later become the conductive layer 25g and the conductive layer 25h, respectively.

[0353] Subsequently, the slits 20 are formed in the conductive layer 25f and the insulating layer 41 using the mask MSK (FIGS. 28(A) to 28(D)).

[0354] Next, a semiconductor layer 21f is formed so as to cover the upper surface of the conductive layer 24, the side surfaces of the insulating layer 41 and the conductive layer 25 of the slit 20, and the upper surface of the conductive layer 25 (FIGS. 29(A) to 29(D)). The semiconductor layer 21f is a semiconductor layer that will later become the semiconductor layer 21.

[0355] Next, the semiconductor layer 21f and the conductive layer 25f are processed using a mask or the like to form the semiconductor layer 21 and the conductive layer 25 (FIGS. 30(A) to 30(D)). Because the semiconductor layer 21 and the conductive layer 25 can be formed using the same mask, the Y-direction ends of the semiconductor layer 21 and the conductive layer 25 shown in FIG. 30(D) can be aligned.

[0356] 21(A) to 24(D), the insulating layer 22, the conductive layer 23, the insulating layer 59, the insulating layer 44a, etc. are formed. Next, referring to FIGS. 25(A) to 26(D), the insulating layer 22, the semiconductor layer 21, and the conductive layer 24 are divided to form the transistors 10a and 10b.

[0357] <Production method example 3> An example of a manufacturing method of the semiconductor device shown in FIGS. 1 to 6B, including the capacitor 30, will be described with reference to FIGS.

[0358] First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate.

[0359] The substrate may be a substrate having heat resistance sufficient to withstand at least the subsequent heat treatment.

[0360] An inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used as insulating layer 11. The insulating layer 11 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. If the surface on which insulating layer 11 is to be formed is not flat, a planarization process may be performed after insulating layer 11 is formed so that the upper surface of insulating layer 11 becomes flat.

[0361] Next, a conductive layer that will become the conductive layer 55 is formed on the insulating layer 11. The conductive layer can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method. Next, a resist mask is formed on the conductive layer, and unnecessary portions of the conductive layer are removed by etching, thereby forming the conductive layer 55. The conductive layer 55 can be formed in a plate-like, line-like, or lattice-like shape.

[0362] Next, an insulating film that will become the insulating layer 35 is formed to cover the conductive layer 55, and then planarization treatment is performed until the top surface of the conductive layer 55 is exposed. This allows the conductive layer 55 to be embedded in the insulating layer 35. Note that here, an example in which the insulating layer 35 is formed after the conductive layer 55 has been shown, but the conductive layer 55 and the insulating layer 35 may also be formed by forming the insulating layer 35, forming openings (or recesses) in the insulating layer 35 for embedding the conductive layer 55, then forming a conductive layer that will become the conductive layer 55, and then performing planarization treatment until the surface of the insulating film is exposed. For example, CMP, dry etching, or the like can be used for the planarization treatment.

[0363] Subsequently, the insulating layer 46 is formed on the conductive layer 55 and the insulating layer 35. The insulating layer 46 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0364] In addition, when the conductive layer 55 is not embedded in the insulating layer 35, after the insulating layer 46 is formed, an uneven shape reflecting the shape of the conductive layer 55 may be formed on the upper surface of the insulating layer 46. In this case, it is preferable to perform a planarization treatment on the upper surface of the insulating layer 46.

[0365] Next, an opening is formed in the insulating layer 46, reaching the conductive layer 55. At this time, part of the upper surface of the conductive layer 55 may be etched. It is preferable to perform etching so that a curved surface is formed on the upper part of the conductive layer 55.

[0366] Next, a conductive layer that will become conductive layer 51 is formed to cover the upper surface of insulating layer 46, the side surfaces of insulating layer 46 inside the openings of insulating layer 46, and the upper surface of conductive layer 55. The conductive layer can be formed by a CVD method, an ALD method, a sputtering method, or the like. From the viewpoint of coverage, it is particularly preferable to form the conductive layer by a CVD method.

[0367] Next, a sacrificial layer is formed on the conductive layer that will become conductive layer 51 so as to fill the inside of the opening of insulating layer 46. Next, a planarization process is performed until the top surface of insulating layer 46 is exposed, and the sacrificial layer is removed, thereby forming conductive layer 51 that is located only inside the opening of insulating layer 46 (FIG. 31(A)).

[0368] Here, during the planarization process or removal of the sacrificial layer, the height of the upper surface of the conductive layer 51 may become lower than the upper surface of the insulating layer 46. Furthermore, the corners of the upper ends of the conductive layer 51 and the upper ends of the openings in the insulating layer 46 may be scraped off and rounded.

[0369] Next, an insulating layer 52 is formed along the surfaces of the insulating layer 46 and the conductive layer 51. The insulating layer 52 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method, but the ALD method is preferable from the viewpoint of coverage. Next, a conductive layer 53 is formed on the insulating layer 52 so as to fill the recesses in the slits 40 of the insulating layer 46. This allows a plurality of capacitive elements 30 arranged in a matrix to be formed on the insulating layer 11. The conductive layer 53 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0370] Next, an insulating layer that will become the insulating layer 56 is formed on the conductive layer 53 and the insulating layer 52, and the conductive layer 53 is exposed using a planarization process, so that the portion of the conductive layer 53 that is located above the opening of the insulating layer 46 can be embedded in the insulating layer 56.

[0371] Next, a conductive layer 24 is formed on the conductive layer 53 and the insulating layer 56 (FIG. 31(B)). The conductive layer 24 is formed so as to overlap the two capacitance elements 30. In a later process, the conductive layer 24 is divided into two, with one of the divided conductive layers 24 being disposed on one capacitance element 30 and the other of the divided conductive layers 24 being disposed on the other capacitance element 30.

[0372] Next, using the example manufacturing method shown in Figures 16(A) to 25(D), an insulating layer 41 is formed on the conductive layer 24, then a semiconductor layer 21 and an insulating layer 22 are formed sequentially inside the slit 20 in the insulating layer 41 and on the insulating layer 41, and then a conductive layer 23 and an insulating layer 59 are formed sequentially inside the slit 20 in the insulating layer 41 (Figure 31(C)).

[0373] Next, an insulating layer 44a is formed on the insulating layer 22, the conductive layer 23, and the insulating layer 59. Next, a slit is formed in the insulating layer 44a. Next, the insulating layer 22, the semiconductor layer 21, and the conductive layer 24 are processed using the insulating layer 44a and the insulating layer 59 as a mask, and the insulating layer 22, the semiconductor layer 21, and the conductive layer 24 are each divided inside the slit 20 (FIG. 32(A)). Here, after the conductive layer 24 is divided using an etching process, the insulating layer 56 may be subsequently etched, thereby forming a recess in the insulating layer 56. The side surface of the recess is, for example, roughly aligned with the divided surface of the conductive layer 24.

[0374] Subsequently, an insulating layer 44b is formed so as to cover the upper and side surfaces of the insulating layer 44a, the side surfaces of the insulating layer 59, the divided insulating layer 22, the side surfaces of the semiconductor layer 21 and the conductive layer 24, and the upper surface of the insulating layer 56. Subsequently, an insulating layer 44c is formed on the insulating layer 44b (FIG. 32(B)).

[0375] The insulating layer 44 can function as an interlayer insulating layer that reduces the parasitic capacitance between the conductive layer 25 and the conductive layer 26, and the parasitic capacitance between the conductive layer 23 and the conductive layer 26. The upper surface of the insulating layer 44 is preferably flattened. This can prevent the distance between the conductive layer 25 and the conductive layer 26, and the distance between the conductive layer 23 and the conductive layer 26, from becoming significantly short, thereby reducing the parasitic capacitance between the conductive layers.

[0376] In forming the insulating layer 44, it is preferable to planarize the upper surface of the insulating layer 44a, so that the upper surface of the portion of the insulating layer 44b located on the insulating layer 44a can also be planarized.

[0377] Furthermore, by forming an insulating layer that becomes insulating layer 44c inside the slits of insulating layer 44a and on insulating layer 44b, and then processing the insulating layer so that the top surface of insulating layer 44b is exposed by planarization, the height of the top surface of insulating layer 44c and the height of the top surface of insulating layer 44b can be roughly aligned, thereby flattening the top surface of the entire insulating layer 44.

[0378] The insulating layers that will become the insulating layer 44a, the insulating layer 44b, and the insulating layer 44c can be formed by a CVD method, an ALD method, a sputtering method, or the like.

[0379] Next, an opening reaching the conductive layer 25g is formed in the insulating layer 44, the insulating layer 22, the semiconductor layer 21, and the conductive layer 25h. After that, a conductive layer is formed to fill the opening, and a planarization process is performed until the upper surface of the insulating layer 44 is exposed, thereby forming the plug 27.

[0380] Subsequently, a conductive layer is formed on the insulating layer 44 and the plugs 27, and unnecessary portions are removed by etching to form the conductive layer .

[0381] Through the above steps, a semiconductor device including a memory cell 15 including the transistor 10 and the capacitor 30 as shown in FIG. 3A can be manufactured.

[0382] The above is a description of an example of the manufacturing method.

[0383] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0384] (Embodiment 2) In this embodiment, a semiconductor device 900 according to one embodiment of the present invention, which is different from the above embodiment, will be described. The semiconductor device 900 can function as a memory device.

[0385] Fig. 33 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 33 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 33 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0386] The memory cell 15 exemplified in the above embodiment can be applied to the memory cell 950 .

[0387] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0388] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0389] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0390] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0391] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0392] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0393] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0394] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0395] The PSW 931 has a function of controlling the supply of VDD to the peripheral circuit 915. The PSW 932 has a function of controlling the supply of VHM to the row driver 923. In this example, the high power supply voltage of the semiconductor device 900 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW 931 is controlled by a signal PON1, and the on / off of the PSW 932 is controlled by a signal PON2. In FIG. 33, the number of power domains to which VDD is supplied in the peripheral circuit 915 is one, but multiple domains may also be used. In this case, it is preferable to provide a power switch for each power domain.

[0396] FIG. 34 illustrates a configuration example that can be applied to a memory array of one embodiment of the present invention.

[0397] The memory cell array 1470 shown in FIG. 34 has memory cells 1480 arranged in a matrix of m / 2 rows and n columns (m is an even number greater than or equal to 1, and n is an integer greater than or equal to 1). The memory cell array 1470 shown in FIG. 34 can be applied to the memory array 920 described above. The memory cell 1480 is a memory circuit applicable to the memory cell 950 described above, and is an example of a circuit configuration of a memory cell using a ferroelectric capacitor. FIG. 34 also shows a row circuit 1420 and a column circuit 1430. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, a plate line driver circuit, etc., and can select a row to access. The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has a function of precharging wiring.

[0398] 34, a memory cell 1480 includes a transistor M9 and a capacitor Cfe. In the memory cell 1480, the transistor M9 can correspond to the transistor 10 described in the first embodiment, and the capacitor Cfe can correspond to the capacitor 30 described in the first embodiment.

[0399] In the memory cell array 1470 of FIG. 34, m memory cells 1480 are connected to one wiring BL.

[0400] In the following, the description will be focused on one of the memory cells 1480 shown in FIG.

[0401] One of the source or drain of the transistor M9 is connected to a wiring BL (for example, one of the wirings BL[1] to BL[n]). The other of the source or drain of the transistor M9 is connected to one of a pair of electrodes of a capacitor Cfe. The gate of the transistor M9 is connected to a wiring WL (for example, one of the wirings WL[1] to WL[m]). The other of the pair of electrodes of the capacitor Cfe is connected to a wiring PL (for example, one of the wirings PL[1] to PL[m]).

[0402] The wiring WL functions as a word line, and can control switching between an on state and an off state of the transistor M9 by applying a potential to the wiring WL as a select signal or a non-select signal. For example, the transistor M9 can be turned on by setting the select signal applied to the wiring WL to a high potential (H), and the transistor M9 can be turned off by setting the non-select signal applied to the wiring WL to a low potential (L). The wiring WL is connected to a word line driver circuit included in the row circuit 1420, and the word line driver circuit can apply a select signal or a non-select signal to the wiring WL.

[0403] The wiring BL functions as a bit line, and when the transistor M9 is on, a potential corresponding to a data signal applied to the wiring BL is applied to one of a pair of electrodes of the capacitor Cfe. The wiring BL is connected to a bit line driver circuit included in the column circuit 1430. The bit line driver circuit has a function of generating a data signal to be written to the memory cell 1480. The bit line driver circuit also has a function of reading data output from the memory cell 1480. Specifically, the bit line driver circuit is provided with a sense amplifier, and the data output from the memory cell 1480 can be read using the sense amplifier.

[0404] The wiring PL functions as a plate line. A predetermined potential is applied to the wiring PL to the other of the pair of electrodes of the capacitor Cfe. The wiring PL is connected to a plate line driver circuit included in the row circuit 1420. The plate line driver circuit is, for example, a circuit that can apply the potential to the wiring PL during a write operation or a read operation.

[0405] The capacitor element Cfe has a dielectric layer between two electrodes made of a material that can have ferroelectric properties. By using a ferroelectric layer that can be thinned as the dielectric layer of the capacitor element and combining it with miniaturized transistors, a highly integrated memory device can be achieved. Hereinafter, the dielectric layer of the capacitor element Cfe will be referred to as the ferroelectric layer.

[0406] The ferroelectric layer of the capacitor Cfe has a hysteresis characteristic. Fig. 35(A) is a graph showing an example of the hysteresis characteristic. In Fig. 35(A), the horizontal axis represents the voltage applied to the ferroelectric layer. The voltage can be, for example, the difference between the potential of one of the pair of electrodes of the capacitor Cfe and the potential of the other of the pair of electrodes of the capacitor Cfe.

[0407] 35(A), the vertical axis represents the polarization of the ferroelectric layer, and a positive value indicates that positive charges are biased toward one of the pair of electrodes of the capacitance element Cfe, and negative charges are biased toward the other of the pair of electrodes of the capacitance element Cfe. On the other hand, a negative value indicates that positive charges are biased toward the other of the pair of electrodes of the capacitance element Cfe, and negative charges are biased toward one of the pair of electrodes of the capacitance element Cfe.

[0408] 35A。 In addition, the voltage shown on the horizontal axis of the graph in Fig. 35A may be the difference between the potential of the other electrode of the pair of electrodes of the capacitor Cfe and the potential of one of the pair of electrodes of the capacitor Cfe. In addition, the polarization shown on the vertical axis of the graph in Fig. 35A may be a positive value when positive charges are biased toward the other electrode of the pair of electrodes of the capacitor Cfe and negative charges are biased toward one of the pair of electrodes of the capacitor Cfe, and a negative value when positive charges are biased toward one of the pair of electrodes of the capacitor Cfe and negative charges are biased toward the other electrode of the pair of electrodes of the capacitor Cfe.

[0409] 35(A), the hysteresis characteristic of the ferroelectric layer can be expressed by a curve 61 and a curve 62. The voltages at the intersections of the curve 61 and the curve 62 are defined as VSP and −VSP. It can be said that VSP and −VSP have opposite polarities.

[0410] When a voltage equal to or less than -VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is increased, the polarization of the ferroelectric layer increases according to curve 61. On the other hand, when a voltage equal to or greater than VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is decreased, the polarization of the ferroelectric layer decreases according to curve 62. Therefore, VSP and -VSP can each be referred to as saturation polarization voltages. Note that, for example, VSP may be referred to as the first saturation polarization voltage, and -VSP may be referred to as the second saturation polarization voltage. Also, while FIG. 35(A) shows a case where the absolute values ​​of the first and second saturation polarization voltages are equal, the absolute values ​​of the two may be different.

[0411] Here, Vc denotes the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to curve 61 and the polarization of the ferroelectric layer is 0. Furthermore, -Vc denotes the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to curve 62 and the polarization of the ferroelectric layer is 0. Vc and Vc can be referred to as coercive voltages, respectively. The values ​​of Vc and Vc can be referred to as values ​​between -VSP and VSP. Note that, for example, Vc may be referred to as the first coercive voltage and -Vc may be referred to as the second coercive voltage. Furthermore, in FIG. 35(A), the absolute values ​​of the first coercive voltage and the second coercive voltage are equal, but the absolute values ​​of the two may be different.

[0412] When no voltage is applied to the ferroelectric layer, the maximum value of polarization is called the "remnant polarization Pr" and the minimum value is called the "remnant polarization -Pr." The difference between the remnant polarization Pr and the remnant polarization -Pr is called the "remnant polarization 2Pr."

[0413] As described above, the voltage applied to the ferroelectric layer of the capacitor Cfe can be expressed as the difference between the potential of one of the pair of electrodes of the capacitor Cfe and the potential of the other of the pair of electrodes of the capacitor Cfe. Also, as described above, the other of the pair of electrodes of the capacitor Cfe is connected to the wiring PL. Therefore, by controlling the potential of the wiring PL, the voltage applied to the ferroelectric layer of the capacitor Cfe can be controlled.

[0414] An example of a method for driving the memory cell 1480 shown in Fig. 34 will be described. In the following description, the voltage applied to the ferroelectric layer of the capacitor Cfe is the difference (potential difference) between the potential of one of the pair of electrodes of the capacitor Cfe and the potential of the other of the pair of electrodes (wiring PL) of the capacitor Cfe. In addition, the transistor M9 is an n-channel transistor.

[0415] Figure 35B is a timing chart showing an example of a method for driving the memory cell 1480. Figure 35B shows an example of writing and reading binary digital data to the memory cell 1480. Specifically, Figure 35B shows an example of writing data "1" to the memory cell 1480 from time T01 to time T02, reading and rewriting from time T03 to time T05, reading from time T11 to time T13 and writing data "0" to the memory cell 1480, reading and rewriting from time T14 to time T16, and reading from time T17 to time T19 and writing data "1" to the memory cell 1480.

[0416] A reference potential Vref is supplied to the sense amplifier connected to the line BL. In the read operation shown in Figure 35(B), when the potential of the line BL is higher than Vref, data "1" is read by the bit line driver circuit. On the other hand, when the potential of the line BL is lower than Vref, data "0" is read by the bit line driver circuit.

[0417] Between time T01 and time T02, the word line driver circuit applies a high potential to the line WL as a selection signal. This turns on transistor M9. The potential of the line BL is set to Vw. Because transistor M9 is on, the potential of one of the pair of electrodes of the capacitance element Cfe becomes Vw. Furthermore, GND is applied to the line PL by the plate line driver circuit. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "Vw-GND." This allows data "1" to be written to memory cell 1480. Therefore, the period from time T01 to time T02 can be said to be the period during which the write operation is performed.

[0418] Here, Vw is preferably equal to or greater than VSP, for example. Furthermore, although GND is a ground potential in this specification, it is not necessarily required to be a ground potential as long as the memory cell 1480 can be driven to satisfy the spirit of one embodiment of the present invention. For example, if the absolute values ​​of the first and second saturation polarization voltages are different and the absolute values ​​of the first and second coercive voltages are different, GND can be a potential other than ground.

[0419] Between time T02 and time T03, the bit line driver circuit applies GND to the line BL, and the plate line driver circuit applies GND to the line PL. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes 0V. Between time T01 and time T02, the voltage "Vw-GND" applied to the ferroelectric layer of the capacitance element Cfe can be made equal to or higher than VSP, and therefore, between time T02 and time T03, the polarization amount of the ferroelectric layer of the capacitance element Cfe changes according to curve 62 shown in FIG. 35(A). As a result, between time T02 and time T03, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe.

[0420] After applying GND to both the lines BL and PL, the word line driver circuit applies a low potential to the line WL as a non-selection signal, turning off the transistor M9. This completes the write operation, and data "1" is stored in the memory cell 1480. The potentials of the lines BL and PL can be set to any potential as long as no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe, i.e., the voltage applied to the ferroelectric layer of the capacitance element Cfe is equal to or greater than the second coercive voltage, -Vc.

[0421] Between time T03 and time T04, the word line driver circuit applies a high potential to the line WL as a selection signal. This turns on transistor M9. Furthermore, the plate line driver circuit applies Vw to the line PL. By setting the potential of the line PL to Vw, the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes "GND-Vw." As described above, the voltage applied to the ferroelectric layer of the capacitive element Cfe is "Vw-GND" between time T01 and time T02. Therefore, polarization reversal occurs in the ferroelectric layer of the capacitive element Cfe. During polarization reversal, current flows through the line BL, and the potential of the line BL becomes higher than Vref. This allows the bit line driver circuit to read the data "1" stored in memory cell 1480. Therefore, the period from time T03 to time T04 can be considered a period during which a read operation is performed. Note that although Vref is higher than GND and lower than Vw, it may also be higher than Vw, for example.

[0422] Since the above read is a destructive read, the data "1" held in memory cell 1480 is lost. Therefore, from time T04 to time T05, Vw is applied to the line BL by the bit line driver circuit, and GND is applied to the line PL by the plate line driver circuit. This rewrites the data "1" to memory cell 1480. Therefore, the period from time T04 to time T05 can be said to be the period during which the rewrite operation is performed.

[0423] From time T05 to time T11, the bit line driver circuit applies GND to the line BL, and the plate line driver circuit applies GND to the line PL. Then, the word line driver circuit applies a low potential as a non-selection signal to the line WL. This completes the rewrite operation, and data "1" is retained in the memory cell 1480.

[0424] Between time T11 and time T12, the word line driver circuit applies a high potential to the line WL as a selection signal. Also, the plate line driver circuit applies a potential Vw to the line PL. Since the memory cell 1480 holds data "1," the potential of the line BL becomes higher than Vref, and the data "1" held in the memory cell 1480 is read. Therefore, the period from time T11 to time T12 can be said to be a period during which a read operation is performed.

[0425] Between time T12 and time T13, the bit line driver circuit applies GND to the line BL. Because the transistor M9 is on, the potential of one of the pair of electrodes of the capacitance element Cfe becomes GND. In addition, the plate line driver circuit applies a potential Vw to the line PL. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw." This allows data "0" to be written to the memory cell 1480. Therefore, the period from time T12 to time T13 can be said to be a period during which a write operation is performed.

[0426] Between time T13 and time T14, the bit line driver circuit applies GND to the line BL, and the plate line driver circuit applies GND to the line PL. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes 0V. Since the voltage "GND-Vw" applied to the ferroelectric layer of the capacitance element Cfe between time T12 and time T13 can be set to -VSP or less, the polarization amount of the ferroelectric layer of the capacitance element Cfe between time T13 and time T14 changes according to the curve 61 shown in FIG. 35(A). As a result, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe between time T13 and time T14.

[0427] After applying GND to both the lines BL and PL, the word line driver circuit applies a low potential to the line WL as a non-selection signal. This turns off the transistor M9. This completes the write operation, and data "0" is stored in the memory cell 1480. The potentials of the lines BL and PL can be set to any potential as long as no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe, i.e., the voltage applied to the ferroelectric layer of the capacitance element Cfe is equal to or lower than the first coercive voltage Vc.

[0428] Between times T14 and T15, the word line driver circuit applies a high potential to the line WL as a selection signal. This turns on the transistor M9. The plate line driver circuit also applies a potential Vw to the line PL. By setting the potential of the line PL to Vw, the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes “GND-Vw.” As described above, the voltage applied to the ferroelectric layer of the capacitive element Cfe is “GND-Vw” between times T12 and T13. Therefore, no polarization reversal occurs in the ferroelectric layer of the capacitive element Cfe. Therefore, the amount of current flowing through the line BL is smaller than when polarization reversal occurs in the ferroelectric layer of the capacitive element Cfe. As a result, the increase in the potential of the line BL is smaller than when polarization reversal occurs in the ferroelectric layer of the capacitive element Cfe. Specifically, the potential of the line BL is below Vref. Therefore, the bit line driver circuit can read the data “0” stored in the memory cell 1480. Therefore, the period from time T14 to time T15 can be said to be a period during which a read operation is performed.

[0429] From time T15 to time T16, the bit line driver circuit applies GND to the line BL, and the plate line driver circuit applies potential Vw to the line PL, thereby rewriting data "0" to the memory cell 1480. Therefore, the period from time T15 to time T16 can be said to be a period during which a rewrite operation is performed.

[0430] Between time T16 and time T17, the bit line driver circuit applies GND to the line BL, and the plate line driver circuit applies GND to the line PL. Then, the word line driver circuit applies a low potential to the line WL as a non-selection signal. This completes the rewrite operation, and data "0" is retained in the memory cell 1480.

[0431] Between time T17 and time T18, the word line driver circuit applies a high potential to the line WL as a selection signal. Furthermore, the plate line driver circuit applies a potential Vw to the line PL. Since data "0" is stored in the memory cell 1480, the potential of the line BL becomes lower than Vref, and the data "0" stored in the memory cell 1480 is read out. Therefore, the period from time T17 to time T18 can be considered a period during which a read operation is performed.

[0432] Between time T18 and time T19, the bit line driver circuit applies a potential Vw to the line BL. Because the transistor M9 is on, the potential of one electrode of the capacitance element Cfe becomes Vw. In addition, the plate line driver circuit applies a potential GND to the line PL. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "Vw-GND." This allows data "1" to be written to the memory cell 1480. Therefore, the period from time T18 to time T19 can be said to be the period during which the write operation is performed.

[0433] After time T19, the bit line driver circuit applies GND to the line BL, and the plate line driver circuit applies GND to the line PL. Then, the word line driver circuit applies a low potential to the line WL as a non-selection signal. This completes the write operation, and data "1" is stored in the memory cell 1480.

[0434] A semiconductor device using a ferroelectric layer for the capacitance element Cfe functions as a nonvolatile memory element that can retain written information even when the power supply is stopped.

[0435] Furthermore, DRAM requires periodic refresh operations, which increases power consumption. However, a semiconductor device using a ferroelectric layer for the capacitance element Cfe does not require refresh operations, which reduces power consumption.

[0436] In this specification and the like, a memory element or a memory circuit including a ferroelectric layer may be referred to as a "ferroelectric memory" or an "FE memory." Therefore, a semiconductor device according to one embodiment of the present invention is both a ferroelectric memory and an FE memory. The FE memory has a capacitance of 1×10 10 or more, preferably 1 × 10 12 or more, more preferably 1×10 15 Furthermore, the FE memory can be expected to achieve an operating frequency of 10 MHz or more, preferably 1 GHz or more.

[0437] Furthermore, in FE memory, there is a correlation between the remanent polarization 2Pr and data retention capacity, and as the remanent polarization 2Pr decreases, the data retention capacity decreases. In this specification, the period until the remanent polarization 2Pr decreases by 5% (the data retention capacity decreases by 5%) is called the "memory retention period." FE memory can be expected to achieve a memory retention period of at least one day, preferably at least ten days, more preferably at least one year, and even more preferably at least ten years in a temperature environment of 150°C or 200°C.

[0438] FE memory can also be applied to cache memory and registers of CPUs (Central Processing Units) and GPUs (Graphics Processing Units). By combining FE memory with cache memory and registers of a CPU, a normally-off CPU (NoffCPU (registered trademark)) can be realized. By combining FE memory with cache memory and registers of a GPU, a normally-off GPU (NoffGPU (registered trademark)) can be realized.

[0439] Other examples of the structure of a memory cell that can be applied to the memory cell 950 will be described with reference to FIGS.

[0440] [DOSRAM] 36A shows an example of a circuit configuration of a memory cell of a dynamic random access memory (DRAM). In this specification and the like, a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0441] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and the back gate may be connected to each other.

[0442] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. A second terminal of the capacitance element CA is connected to the wiring CAL.

[0443] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.

[0444] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitance element CA into a conductive state (a state in which current can flow).

[0445] The transistor M1, the capacitor CA, the wiring BIL, the wiring WOL, and the wiring CAL can correspond to the transistor 10, the capacitor 30, the wiring BL, the wiring WL, and the wiring PL in FIG. 2B, respectively.

[0446] Furthermore, the memory cell that can be used for the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 952 shown in FIG. 36B can also be used. The memory cell 952 does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0447] In the memory cell 952, the potential written via the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0448] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of having an extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely low. That is, written data can be held by the transistor M1 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0449] [NOSRAM] 36C shows an example of a circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and elsewhere, a memory device having a gain cell type memory cell in which an OS transistor is used as the transistor M2 is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0450] A first terminal of transistor M2 is connected to a first terminal of capacitance element CB, a second terminal of transistor M2 is connected to line WBL, and a gate of transistor M2 is connected to line WOL. A second terminal of capacitance element CB is connected to line CAL. A first terminal of transistor M3 is connected to line RBL, a second terminal of transistor M3 is connected to line SL, and a gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0451] The line WBL functions as a write bit line, the line RBL functions as a read bit line, and the line WOL functions as a word line. The line CAL functions as a line for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the line CAL.

[0452] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0453] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of the transistor M3, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0454] Further, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example of the circuit configuration of such a memory cell is shown in Figure 36(D). The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0455] 36(E) is an example of a memory cell 955 in which the capacitor CB and the wiring CAL are omitted from the memory cell 953. Also, FIG. 36(F) is an example of a memory cell 956 in which the capacitor CB and the wiring CAL are omitted from the memory cell 954. With such a configuration, the degree of integration of the memory cells can be increased.

[0456] Note that it is preferable to use an OS transistor for at least the transistor M2, and particularly preferable to use an OS transistor for the transistors M2 and M3.

[0457] Since the OS transistor has an extremely small off-state current, written data can be retained for a long time by the transistor M2, thereby reducing the frequency of refreshing the memory cells. Alternatively, the refresh operation of the memory cells can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be retained in the memory cells 953, 954, 955, and 956.

[0458] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, in which an OS transistor is used as the transistor M2, are one aspect of NOSRAM.

[0459] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, which increases the degree of freedom in circuit design.

[0460] Furthermore, when an OS transistor is used as the transistor M3, the memory cell can be configured using only n-type transistors.

[0461] 36G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 includes transistors M4 to M6 and a capacitor CC.

[0462] A first terminal of the transistor M4 is connected to a first terminal of the capacitor CC, a second terminal of the transistor M4 is connected to the wiring BIL, and a gate of the transistor M4 is connected to the wiring WOL. A second terminal of the capacitor CC is connected to a first terminal of the transistor M5 and the wiring GNDL. A second terminal of the transistor M5 is connected to a first terminal of the transistor M6, and a gate of the transistor M5 is connected to the first terminal of the capacitor CC. A second terminal of the transistor M6 is connected to the wiring BIL, and a gate of the transistor M6 is connected to the wiring RWL.

[0463] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low level potential.

[0464] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0465] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0466] It is preferable to use an OS transistor for at least the transistor M4.

[0467] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0468] Furthermore, when OS transistors are used as transistors M5 and M6, the memory cell can be configured using only n-type transistors.

[0469] [OS-SRAM] FIG. 36H shows an example of an SRAM (Static Random Access Memory) using OS transistors. In this specification and elsewhere, an SRAM using OS transistors is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 36H is a memory cell of an SRAM that can be backed up.

[0470] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0471] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. A gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. A gate of transistor M8 is connected to wiring WOL.

[0472] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0473] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0474] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0475] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the on / off states of the transistors M9 and M10.

[0476] The wiring VDL is a wiring that applies a high level potential, and the wiring GNDL is a wiring that applies a low level potential.

[0477] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to information to be written is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0478] In the memory cell 958, the transistors MS1 and MS2 form an inverter loop, and therefore an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is on, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Because the transistors M9 and M10 are on, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Then, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL, turning off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0479] Data is read by precharging the wirings BIL and BILB to a predetermined potential beforehand, and then applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL, so that the potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. Also, the potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. In the wirings BIL and BILB, the potentials change from the precharged potentials to the potential of the first terminal of the capacitor CD2 and the potential of the first terminal of the capacitor CD1, respectively, so that the potential held in the memory cell can be read from the potential of the wiring BIL or the wiring BILB.

[0480] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held for a long time by the transistors M7 to M10, which reduces the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be eliminated.

[0481] Note that Si transistors may be used as the transistors MS1 to MS4.

[0482] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 37(A), the driver circuit 910 and the memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and the memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 37(B), the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0483] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0484] Fig. 38 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in Fig. 38 can be applied to, for example, a CPU. The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), or an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0485] The arithmetic device 960 shown in FIG. 38 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. A rewritable ROM and a ROM interface may be provided. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0486] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991 or register 996, etc. via the bus interface 998.

[0487] As will be described later, a memory array 920 can be provided stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999. In this case, it is preferable that a drive circuit 910 be included as part of the cache interface 989.

[0488] It is also possible to use only the memory array 920 as a cache without providing the cache 999.

[0489] The arithmetic device 960 shown in FIG. 38 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 38 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle via its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.

[0490] An instruction input to the arithmetic unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, the interrupt controller 994, the register controller 997, and the timing controller 995.

[0491] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 997 generates an address for a register 996 and performs read and write operations on the register 996 depending on the state of the arithmetic unit 960.

[0492] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0493] In the arithmetic unit 960 shown in FIG. 38, the register controller 997 selects the holding operation of the register 996 in accordance with an instruction from the ALU 991. That is, it selects whether the memory cells in the register 996 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, a power supply voltage is supplied to the memory cells in the register 996. If holding data using capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply voltage to the memory cells in the register 996 can be stopped.

[0494] The memory array 920 and the arithmetic device 960 can be provided overlapping each other. Figures 39(A) and (B) show perspective views of a semiconductor device 970A. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic device 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic device 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, Figure 39(B) shows the arithmetic device 960 and the layer 930 separated from each other.

[0495] By stacking the memory array layer 930 and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0496] The layer 930 having the memory array and the arithmetic device 960 may be stacked by stacking the layer 930 having the memory array directly on the arithmetic device 960 (also called monolithic stacking), or by forming the arithmetic device 960 and the layer 930 on different substrates, bonding the two substrates together, and connecting them using through-vias or conductive film bonding technology (such as Cu-Cu bonding). The former method does not require consideration of misalignment during bonding, and therefore not only can it reduce the chip size but also the manufacturing cost.

[0497] Here, the arithmetic unit 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also called a level 1 cache), the memory array 920L2 can be used as an L2 cache (also called a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also called a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and is accessed least frequently. Furthermore, the memory array 920L1 has the smallest capacity and is accessed most frequently.

[0498] When the cache 999 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0499] 39(B), a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0500] Although the number of memory arrays functioning as caches is three in this example, it is also possible to have one or two, or four or more.

[0501] When the memory array 920L1 is used as a cache, the driver circuit 910L1 may function as part of the cache interface 989, or may be configured to be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 989, or may be configured to be connected thereto.

[0502] Whether the memory array 920 functions as a cache or a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0503] The semiconductor device 900 can cause some of the multiple memory cells 950 to function as a cache and the other part to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one aspect of the present invention can function as, for example, a universal memory.

[0504] Furthermore, a layer 930 having one memory array 920 may be provided overlapping the arithmetic device 960. Figure 40A shows a perspective view of a semiconductor device 970B.

[0505] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Figure 40(A) shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0506] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if you want to increase the capacity of the L1 cache, you can achieve this by increasing the area of ​​the area L1. This configuration makes it possible to improve the efficiency of calculation processing and increase the processing speed.

[0507] Moreover, a plurality of memory arrays may be stacked. Figure 40(B) shows a perspective view of a semiconductor device 970C.

[0508] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0509] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0510] (Embodiment 3) In this embodiment, an application example of a semiconductor device of one embodiment of the present invention will be described. The semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). The electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0511] [Electronic Components] FIG. 41(A) shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 41(A) has a semiconductor device 710 inside a mold 711. FIG. 41(A) omits some parts in order to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are connected to electrode pads 713, and electrode pads 713 are connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and connected on printed circuit board 702 to complete mounting substrate 704.

[0512] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved, in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0513] Furthermore, by configuring on-chip memory, the size of connection wiring can be reduced compared to technologies that use through-electrodes such as TSV, and it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0514] Furthermore, it is preferable that the memory cell arrays included in the storage layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By configuring the memory cell arrays as a monolithic stack, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used in the storage layer 716, it is more difficult to achieve a monolithic stack configuration than OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stack configuration.

[0515] The semiconductor device 710 may also be referred to as a die. In this specification and the like, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0516] 41(B) shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on interposer 731.

[0517] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a CPU, a GPU, an NPU, or an FPGA (Field Programmable Gate Array).

[0518] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used for the package substrate 732. For example, a silicon interposer or a resin interposer can be used for the interposer 731.

[0519] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are connected using the through electrodes. In addition, with a silicon interposer, TSVs can also be used as through electrodes.

[0520] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0521] Furthermore, SiPs and MCMs that use silicon interposers are less likely to experience a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is less likely to occur. It is particularly preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on an interposer.

[0522] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSVs, or the like, space is required to accommodate the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the terminal pitch becomes an issue, making it difficult to provide the large number of interconnects required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may also be used that combines a memory cell array stacked using TSVs with a monolithic stacked memory cell array.

[0523] A heat sink (heat sink) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0524] Electrodes 733 may be provided on the bottom of the package substrate 732 in order to mount the electronic component 730 on another substrate. FIG. 41(B) shows an example in which the electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 may be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0525] The electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0526] [Large computer] 42A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0527] 42(B) shows a perspective view of an example of a computer 5620. The computer 5620 has a motherboard 5630. The motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, which are each connected to the motherboard 5630.

[0528] Fig. 42(C) shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622 and a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, an electronic component 5626, an electronic component 5627, an electronic component 5628, a connection terminal 5629, etc., which are mounted on the board 5622. Note that Fig. 42(C) illustrates components other than the electronic component 5626, the electronic component 5627, and the electronic component 5628.

[0529] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of a motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0530] Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Examples of standards for outputting video signals from connection terminals 5623, 5624, and 5625 include HDMI (registered trademark).

[0531] The electronic component 5626 has a terminal (not shown) for inputting and outputting signals, and the electronic component 5626 and the board 5622 can be connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0532] The electronic component 5627 and the electronic component 5628 have a plurality of terminals, and can be mounted on wiring provided on the board 5622 by, for example, reflow soldering the terminals. Examples of the electronic component 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the electronic component 5627. For example, the electronic component 5628 includes a storage device. For example, the electronic component 700 can be used as the electronic component 5628.

[0533] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0534] [Space equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0535] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space. Specifically, the OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron rays. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification includes one or more of the thermosphere, the mesosphere, and the stratosphere.

[0536] 43(A) shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 includes a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that in FIG. 43(A), a planet 6804 is shown in space.

[0537] 43A, a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it has low power consumption and high reliability even in space.

[0538] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0539] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is recommended to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may also be called a solar cell module.

[0540] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0541] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a memory device. Note that a semiconductor device including an OS transistor according to one embodiment of the present invention is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0542] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0543] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0544] As described above, compared to Si transistors, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance.

[0545] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to accommodate the installation of storage devices and servers for storing a huge amount of data, a stable power source for storing the data, or cooling equipment required for storing the data.

[0546] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0547] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0548] Figure 43(B) shows a storage system applicable to a data center. The storage system 6000 shown in Figure 43(B) has multiple servers 6001sb as hosts 6001. It also has multiple storage devices 6003md as storage 6003. The host 6001 and storage 6003 are shown connected via a storage area network 6004 and a storage control circuit 6002.

[0549] The host 6001 corresponds to a computer that accesses data stored in the storage 6003. The hosts 6001 may be connected to each other via a network.

[0550] Although the storage 6003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 6003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0551] The cache memory described above is used in the storage control circuit 6002 and the storage 6003. Data exchanged between the host 6001 and the storage 6003 is stored in the cache memory in the storage control circuit 6002 and the storage 6003, and then output to the host 6001 or the storage 6003.

[0552] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, thereby lowering power consumption.Furthermore, by using a stacked memory cell array, miniaturization is possible.

[0553] Note that the application of a semiconductor device of one embodiment of the present invention to one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or integration of semiconductor devices, the use of a semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases such as carbon dioxide (CO). Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming due to its low power consumption.

[0554] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification. [Explanation of symbols]

[0555] ADDR: signal, BIL: wiring, BILB: wiring, BL: wiring, BRL: wiring, BW: signal, CA: capacitor, CAL: wiring, CB: capacitor, CC: capacitor, CE: signal, Cfe: capacitor, CLK: signal, GNDL: wiring, GW: signal, HM: hard mask, M10: transistor, MSK: mask, PL: wiring, RBL: wiring, RDA: signal, RWL: wiring, SL: wiring, VDL: wiring, WAKE: signal, WBL: wiring, WDA: signal, WL: wiring, WOL: wiring, 10: transistor, 10a: transistor, 10b: transistor, 11: Insulating layer, 15: memory cell, 20: slit, 21: semiconductor layer, 21f: semiconductor layer, 22: insulating layer, 23: conductive layer, 23a: conductive layer, 23b: conductive layer, 23f: conductive layer, 24: conductive layer, 24a: conductive layer, 24b: conductive layer, 24g: conductive layer, 24h: conductive layer, 25: conductive layer, 25a: conductive layer, 25b: conductive layer, 25f: conductive layer, 25f1: conductive layer, 25f2: conductive layer, 25g: conductive layer, 25h: conductive layer, 26: conductive layer, 26a: conductive layer, 26b: conductive layer, 27: plug, 28: slit, 30: capacitance element, 35: insulating layer, 40: slit, 41: insulating layer, 41a: insulating layer, 41a_1: insulating layer, 41a_2: insulating layer, 41b: insulating layer, 41c: insulating layer, 42: insulating layer, 44: insulating layer, 44a: insulating layer, 44b: insulating layer, 44c: insulating layer, 45: insulating layer, 46: insulating layer, 50: semiconductor device, 51: conductive layer, 52: insulating layer, 53: conductive layer, 55: conductive layer, 56: insulating layer, 59: insulating layer, 59f: insulating layer, 80[1]: layer, 80[2]: layer, 80: layer, 81: conductive layer, 82: plug, 83: plug, 84: conductive layer, 85: plug, 86: insulating layer, 87: insulating layer, 88: insulating layer, 89: plug, 90: transistor , 91: substrate, 92: semiconductor region, 93: insulating layer, 94: conductive layer, 95a: low resistance region, 95b: low resistance region, 96: insulating layer, 98: element isolation layer, 700: electronic component, 702: printed circuit board, 704: mounting substrate, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 900: semiconductor device, 910: drive circuit, 911: peripheral circuit, 912: control circuit,915: Peripheral circuit, 920: Memory array, 923: Row driver, 924: Column driver, 925: Input circuit, 926: Output circuit, 927: Sense amplifier, 928: Voltage generation circuit, 930: Layer, 931: PSW, 932: PSW, 941: Row decoder, 942: Column decoder, 950: Memory cell, 951: Memory cell, 952: Memory cell, 953: Memory cell, 954: Memory cell, 955: Memory cell, 956: Memory cell, 957: Memory cell, 958: Memory cell, 960: Arithmetic unit, 970A: Semiconductor device, 970B: Semiconductor device, 970C: Semiconductor device, 989: Cache interface, 990: Substrate, 991: ALU, 992: ALU controller, 993: Instruction decoder, 994: Interrupt controller, 995: Timing controller, 996: register, 997: register controller, 998: bus interface, 999: cache, 1480: memory cell, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: electronic component, 5627: electronic component, 5628: electronic component, 5629: connection terminal, 5630: Motherboard, 5631: slot, 6000: storage system, 6001: host, 6001sb: server, 6002: storage control circuit, 6003: storage, 6003md: storage device, 6004: storage area network, 6800: satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device,

Claims

1. a first transistor, a first insulating layer, and a second insulating layer; the first transistor has a first conductive layer, a second conductive layer, a first semiconductor layer, a third insulating layer, and a third conductive layer; the first insulating layer is located on the first conductive layer and has a slit reaching the first conductive layer; the second conductive layer is located on the first insulating layer; the first insulating layer has, within the slit, a first side surface and a second side surface opposite to the first side surface; the first semiconductor layer has a first portion in contact with the second conductive layer, a second portion along the first side surface, and a third portion in contact with a first top surface of the first conductive layer; the first upper surface overlaps with the slit in a plan view, the third conductive layer has a portion facing the second portion with the third insulating layer interposed therebetween, the second insulating layer has a portion facing the second portion with the third insulating layer and the third conductive layer sandwiched therebetween, and a portion overlapping the first upper surface with the third portion sandwiched therebetween. Semiconductor device.

2. 2. The semiconductor device according to claim 1, further comprising: a second transistor; and a fourth insulating layer; the second transistor has a fourth conductive layer, a fifth conductive layer, a second semiconductor layer, a fifth insulating layer, and a sixth conductive layer; the first insulating layer is positioned on the fourth conductive layer such that the second side overlaps a first region of the second top surface of the fourth conductive layer; the fifth conductive layer is located on the first insulating layer; the second semiconductor layer has a fourth portion in contact with the fifth conductive layer, a fifth portion along the second side surface, and a sixth portion in contact with a second region of the second top surface of the fourth conductive layer; the second region of the second upper surface overlaps with the slit in a plan view, the sixth conductive layer has a portion facing the fifth portion with the fifth insulating layer interposed therebetween, the fourth insulating layer has a portion facing the fifth portion with the fifth insulating layer and the sixth conductive layer sandwiched therebetween, and a portion overlapping with the second region of the second top surface with the second semiconductor layer sandwiched therebetween. Semiconductor device.

3. In claim 1, the third conductive layer and the second insulating layer each extend in a first direction in a plan view; Semiconductor device.

4. In claim 1, the first semiconductor layer comprises indium oxide; Semiconductor device.

5. In claim 1, a capacitance element, a sixth insulating layer, and a seventh conductive layer; the capacitive element has an eighth conductive layer, a ninth conductive layer, and a seventh insulating layer; the sixth insulating layer is located on the seventh conductive layer and has an opening reaching the seventh conductive layer; the eighth conductive layer contacts a side surface of the sixth insulating layer and an upper surface of the seventh conductive layer in the opening; the seventh insulating layer is located on the eighth conductive layer; the ninth conductive layer is located on the seventh insulating layer; the first conductive layer contacts an upper surface of the ninth conductive layer; Semiconductor device.

6. In claim 2, The slit extends in a first direction in a plan view, the first side surface and the second side surface are each aligned along the first direction; the third conductive layer, the sixth conductive layer, the second insulating layer, and the fourth insulating layer each extend in the first direction; Semiconductor device.

7. In claim 2, an eighth insulating layer and a ninth insulating layer; a third side surface of the first conductive layer and a fourth side surface of the fourth conductive layer face each other; the eighth insulating layer has a seventh portion covering the third side surface, an eighth portion covering the fourth side surface, a ninth portion covering the side surface of the second insulating layer, and a tenth portion covering the side surface of the fourth insulating layer; the ninth insulating layer has a portion sandwiched between the seventh portion and the eighth portion, and a portion sandwiched between the ninth portion and the tenth portion. Semiconductor device.

8. In claim 7, the second insulating layer and the fourth insulating layer each include one or more of silicon nitride and silicon oxynitride; the eighth insulating layer comprises one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate; the ninth insulating layer includes one or more of silicon oxide, silicon oxynitride, silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen; Semiconductor device.

9. forming a first conductive layer; forming a first insulating layer on the first conductive layer; forming a second conductive layer on the first insulating layer; removing a portion of the second conductive layer and a portion of the first insulating layer using a first mask; the removal using the first mask forms a slit in the first insulating layer that reaches the first conductive layer, thereby forming a first side surface and a second side surface that face each other within the slit in a cross-sectional view in the first insulating layer, and the second conductive layer is divided across the slit in a plan view; forming a first semiconductor layer so as to cover an upper surface of the first conductive layer and a first side surface and a second side surface of the first insulating layer inside the slit; forming a second insulating layer on the first semiconductor layer; forming a third conductive layer on the second insulating layer; removing a portion of the third conductive layer using anisotropic etching to form a fourth conductive layer along the first side and a fifth conductive layer along the second side; forming a third insulating layer so as to cover the first conductive layer, the second insulating layer, the fourth conductive layer, and the fifth conductive layer; removing a portion of the third insulating layer using anisotropic etching to form a fourth insulating layer along the first side surface with the fourth conductive layer therebetween and a fifth insulating layer along the second side surface with the fifth conductive layer therebetween; dividing the second insulating layer inside the slit to form an eighth insulating layer and a ninth insulating layer; dividing the first semiconductor layer inside the slit to form a second semiconductor layer and a third semiconductor layer; dividing the first conductive layer inside the slit to form a sixth conductive layer and a tenth conductive layer; The slit extends in a first direction in a plan view, the first side and the second side each extend in the first direction; the second semiconductor layer has a portion covering the first side surface and a portion covering an upper surface of the sixth conductive layer, the third semiconductor layer has a portion covering the second side surface and a portion covering an upper surface of the tenth conductive layer. A method for manufacturing a semiconductor device.

10. In claim 9, the dividing of the second insulating layer, the dividing of the first semiconductor layer, and the dividing of the first conductive layer are performed using the fourth insulating layer and the fifth insulating layer as masks, respectively; A method for manufacturing a semiconductor device.

11. In claim 9, the first semiconductor layer comprises indium oxide; A method for manufacturing a semiconductor device.

12. In claim 9, the third insulating layer comprises one or more of silicon nitride and silicon oxynitride; A method for manufacturing a semiconductor device.

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