Image sensor

Abstract

To provide an image sensor with improved reliability.SOLUTION: A first chip including a pixel array region, a pad region, and an inter-chip connection region between the pixel array region and the pad region, a second chip disposed on a lower surface of the first chip, a plurality of through-via structures penetrating the first chip and extending into the second chip in the inter-chip connection region of the first chip, a surface insulation layer disposed on the first chip, a color filter disposed on the surface insulation layer in the pixel array region of the first chip, a microlens layer including a microlens disposed on the color filter, and a first protective layer disposed on at least the inter-chip connection region of the first chip and having a plurality of first patterns covering at least one through-via structure among the plurality of through-via structures; And a second protective layer disposed on the microlens layer and the first protective layer and having a plurality of second patterns located on the plurality of first patterns in the inter-chip connection region of the first chip.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to an image sensor, and more particularly to an image sensor with improved reliability. [Background technology]

[0002] An image sensor is a semiconductor-based sensor that receives light and generates an electrical signal, and includes a pixel array having a plurality of pixels and a logic circuit for driving the pixel array to generate an image. Each pixel includes a photodiode and pixel circuitry that converts the charge generated by the photodiode into an electrical signal.

[0003] With image sensors constantly evolving and being developed, improving reliability is a constant challenge. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above-mentioned problems with conventional image sensors, and an object of the present invention is to provide an image sensor with improved reliability. [Means for solving the problem]

[0005] The image sensor according to the present invention, which has been made to achieve the above-mentioned object, is characterized by comprising: a first chip including a pixel array region, a pad region, and an inter-chip connection region between the pixel array region and the pad region; a second chip arranged on the underside of the first chip; a plurality of through-via structures extending through the first chip into the second chip in the inter-chip connection region of the first chip; a surface insulating layer arranged on the first chip; a color filter arranged on the surface insulating layer in the pixel array region of the first chip; a microlens layer including microlenses arranged on the color filter; a first protective layer arranged on at least the inter-chip connection region of the first chip, the first protective layer having a plurality of first patterns each covering at least one of the plurality of through-via structures; and a second protective layer arranged on the microlens layer and the first protective layer, the second protective layer having a plurality of second patterns each positioned on the plurality of first patterns in the inter-chip connection region of the first chip.

[0006] Further, an image sensor according to the present invention, which has been made to achieve the above object, includes a first substrate including a pixel array region in which photoelectric conversion elements are arranged, a pad region, and an inter-chip connection region between the pixel array region and the pad region, the first substrate having a first surface including a light-receiving surface of the photoelectric conversion element and a second surface opposite to the first surface, a first wiring structure disposed on the second surface of the first substrate and including a first wiring and a first inter-wiring insulating film, a second substrate disposed on the first wiring structure and including a third surface facing the second surface and a fourth surface opposite to the third surface, a second wiring structure on the third surface of the second substrate in contact with the first wiring structure and including a second wiring and a second inter-wiring insulating film, and a second wiring structure penetrating the first substrate and the first wiring structure in the inter-chip connection region, The pixel array region of the first substrate includes a plurality of through-via structures extending into the second wiring structure and electrically connected to the second wiring; a surface insulating layer disposed on the first surface of the first substrate; a color filter disposed on the surface insulating layer within the pixel array region of the first substrate; a microlens layer disposed on the color filter and including a microlens; a first protective layer integrated with the microlens layer, extending over the chip-to-chip connection region and the pad region, and having a plurality of first patterns covering at least one of the plurality of through-via structures; and a second protective layer disposed on the microlens layer and the first protective layer, and having a plurality of second patterns each positioned on the plurality of first patterns and separated from each other.

[0007] In addition, an image sensor according to the present invention, which has been made to achieve the above-mentioned object, comprises: a first chip including a pixel array region, a pad region, and an inter-chip connection region between the pixel array region and the pad region; a second chip disposed on the underside of the first chip; a plurality of through-via structures extending through the first chip into the second chip in the inter-chip connection region of the first chip; a surface insulating layer disposed on the first chip; a color filter disposed on the surface insulating layer in the pixel array region of the first chip; a microlens layer disposed on the color filter and including a microlens; a first protective layer disposed on the inter-chip connection region and the pad region of the first chip; and a second protective layer disposed on the microlens layer and the first protective layer, wherein in the inter-chip connection region, the first and second protective layers each have a plurality of patterns covering at least one of the plurality of through-via structures. [Effects of the Invention]

[0008] According to the image sensor of the present invention, the first and second protective layers are separated into a plurality of patterns in the inter-chip connection region of the image sensor, thereby minimizing the influence of thermal stress and effectively preventing damage such as cracks. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is an exploded perspective view showing a schematic configuration of an image sensor according to an embodiment of the present invention; [Figure 2] 2 is a cross-sectional view of the image sensor of FIG. 1 taken along line II'. [Figure 3] 2 is a cross-sectional view of the image sensor of FIG. 1 taken along line II-II'. [Figure 4] 3 is a cross-sectional view of the image sensor of FIG. 1 taken along line III-III'. [Figure 5] 4 is a cross-sectional view of the image sensor of FIG. 1 taken along line IV-IV'. [Figure 6]2 is a plan view showing an inter-chip connection region of the image sensor of FIG. 1. FIG. [Figure 7a] 1 is a plan view showing a protective layer pattern array of an image sensor according to an embodiment of the present invention; [Figure 7b] 1 is a plan view showing a protective layer pattern array of an image sensor according to an embodiment of the present invention; [Figure 7c] 1 is a plan view showing a protective layer pattern array of an image sensor according to an embodiment of the present invention; [Figure 8] 1 is a cross-sectional view showing a schematic configuration of an image sensor package according to an embodiment of the present invention; [Figure 9] 1 is a cross-sectional view showing a schematic configuration of an image sensor according to an embodiment of the present invention. [Figure 10] 1 is a cross-sectional view showing a schematic configuration of an image sensor according to an embodiment of the present invention. [Figure 11] 1 is a cross-sectional view showing a schematic configuration of an image sensor according to an embodiment of the present invention. [Figure 12] 1 is a cross-sectional view showing a schematic configuration of an image sensor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Next, specific examples of embodiments for carrying out the image sensor according to the present invention will be described with reference to the drawings.

[0011] FIG. 1 is an exploded perspective view showing a schematic configuration of an image sensor according to one embodiment of the present invention, and FIGS. 2 to 5 are cross-sectional views showing a schematic configuration of an image sensor according to one embodiment of the present invention. 2 and 3 are cross-sectional views of the image sensor of FIG. 1 taken along lines I-I' and II-II', respectively, and FIGS. 4 and 5 are cross-sectional views of the image sensor of FIG. 1 taken along lines III-III' and IV-IV', respectively.

[0012] Referring to FIG. 1, an image sensor 300 includes a first chip 100 and a second chip 200 that are stacked and electrically connected to each other. The first chip 100 includes a pixel array area PA in which a plurality of pixels are arranged in a two-dimensional array structure, and the second chip 200 includes a logic area LA in which logic elements are arranged. The logic elements included in the logic region LA are electrically connected to the pixels in the pixel array region to provide signals to the pixels or process signals output from the pixels. For example, the logic area LA may include at least one of a control register block, a timing generator, a ramp signal generator, a row driver, a readout circuit, and a buffer.

[0013] Referring to FIG. 1, the first chip 103 includes, in order from a pixel array region PA, a light-shielding region OB, an inter-chip connection region CR, and a pad region PR. The pixel array area PA and the light-shielding area OB can also be called a sensor array area SAR. In the pixel array area PA, active pixels that receive light and generate active signals are arranged. Optical black pixels that block light and generate optical black signals are arranged in the light blocking area OB. The light-shielding area OB is arranged, for example, along the periphery of the pixel array area PA, but this is merely an example. In one embodiment, dummy pixels may also be placed in the pixel array area PA adjacent to the light blocking area OB.

[0014] The inter-chip connection region CR is arranged in the sensor array region, particularly around the optical black (OB) region. The inter-chip connection region CR is disposed on at least one side of the light-shielding region OB, but this is merely an example, and the inter-chip connection region CR may be disposed across all four corners as in this embodiment. In the inter-chip connection region CR, wiring is arranged and configured to transmit and receive electrical signals to and from the sensor array region SAR.

[0015] The pad region PR is arranged around the chip connection region CR. In one embodiment, the pad region PR is located adjacent to the edge of the image sensor 10 . In this embodiment, the pad region PR is illustrated as being arranged along the four edges of the image sensor 10, but it can also be arranged on opposite edges or so as to surround almost the entire first chip 100. The pad region PR includes a plurality of pads for connection to an external device, and is configured to transmit and receive electrical signals between the image sensor 10 and the external device.

[0016] In this embodiment, the inter-chip connection region CR is shown as being located between the sensor array region SAR and the pad region PR, but this is merely an example. The arrangement of the pixel array region PA, the light-shielding region OB, the inter-chip connection region CR, and the pad region PR may be variously changed as needed.

[0017] 2 to 5 are cross-sectional views of the image sensor of FIG. 1 taken along lines II', II-II', III-III', and IV-IV', respectively. 2 to 5, the first chip 100 of the image sensor 10 according to this embodiment includes a first substrate 110 having a lower surface 110a and an upper surface 110b, an isolation layer 111 defining an active region on the lower surface 110a of the first substrate 110, a first circuit element 120 on the active region on the lower surface 110a of the first substrate 110, and a first wiring structure 150 between the lower surface of the first substrate 110 and the second chip 200.

[0018] The top surface 110b of the first substrate 110 may be referred to as a first surface or back side, and the bottom surface 110a of the first substrate 110 may be referred to as a second surface or front side. The upper surface 110b of the first substrate 110 is a light-receiving surface onto which light is incident. The image sensor according to this embodiment is a backside illuminated (BSI) image sensor.

[0019] As shown in FIG. 2, in the pixel array region PA, the first chip 100 includes a surface insulating layer 140 on the upper surface 110b of the first substrate 110, a grid pattern 150 on the surface insulating layer 140, a color filter 160 covering the surface insulating layer 140 and the grid pattern 150, and a microlens 280L on the color filter 160. In addition, as shown in Figure 3, the first chip 100 further includes, in the light-shielding region OB, a conductive layer 355L on the horizontal insulating layer 140, a light-shielding layer 165 on the conductive layer 355L, and a first protective layer 280 and a second protective layer 240 covering the light-shielding layer 165.

[0020] The second chip 200 is disposed on the lower surface of the first chip 100 . Referring to Figures 2 and 3, the second chip 200 includes a second substrate 210, an isolation layer 211 defining an active region 215 on the second substrate 210, a second circuit element 220 on the second substrate 210, and a second wiring structure 250 electrically connected to the second circuit element 220. Logic element 220 may include an element such as a transistor including a gate 225 and a source / drain 222 .

[0021] The first substrate 110 is a semiconductor substrate. For example, the first substrate 110 can be bulk silicon or silicon-on-insulator (SOI). The first substrate 110 may be a silicon substrate or may include other materials such as silicon-germanium (SiGe), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the first substrate 110 may have a structure in which an epitaxial layer is formed on a base substrate. A plurality of unit pixels are arranged on the first substrate 110 in the sensor array area SAR. For example, in the pixel array region PA, a plurality of pixels are formed that are arranged two-dimensionally (for example, in a matrix) on a plane including the first direction X and the second direction Y.

[0022] Each unit pixel includes a photoelectric conversion element PD. The photoelectric conversion elements PD are disposed in the first substrate 110 in the pixel array area PA. The photoelectric conversion element PD generates electric charges in proportion to the amount of light incident from the outside. For example, the photoelectric conversion element PD may include at least one of a photodiode, a phototransistor, a photogate, a pinned photodiode, an organic photodiode, a quantum dot, and combinations thereof, but is not limited to these.

[0023] The first circuit element 120 includes a transfer gate TG and an active element 125 . Each active element 125 includes a gate 125a and a source / drain 125b. The transfer gate TG transfers charges from an adjacent photoelectric conversion element PD to an adjacent floating diffusion region, and the active element 125 is connected to the photoelectric conversion layer PD and can be at least one of a source follower transistor, a reset transistor, and a selection transistor as a transistor for processing an electrical signal. The transfer gate TG is a vertical transfer gate including a portion extending from the lower surface 110b of the first substrate 106 into the inside of the first substrate 110.

[0024] The pixel separating pattern 130 is disposed in the first substrate 110 in the sensor array area SAR. The pixel separation pattern 130 defines a plurality of unit pixels. The pixel separating pattern 130 is disposed so as to surround each photoelectric conversion element PD. The pixel separating patterns 130 are arranged in a grid pattern in a plan view, and separate a plurality of pixels from one another.

[0025] In this embodiment, the pixel separating pattern 130 penetrates at least a portion of the first substrate 110 . In one embodiment, the pixel separating pattern 130 includes a trench 130H extending from the lower surface 110a to the upper surface 110b, and an insulating material is filled in the trench 130H. The pixel isolation pattern 130 includes an isolation insulating layer 131 formed on the sidewall of the trench 130H and a filling portion 135 surrounded by the isolation insulating layer 130a. For example, the isolation insulating layer 131 includes silicon dioxide, and the filling portion 135 includes polysilicon.

[0026] In this embodiment, the pixel isolation pattern 130 is connected to the device isolation film 111 . As described above, the isolation film 111 is disposed on the lower surface 110a of the first substrate 110 and defines an active region. For example, the element isolation film 110 includes an insulating material such as silicon oxide.

[0027] Meanwhile, referring to FIG. 3, the light-shielding region OB is provided with a first reference region (or dummy photoelectric conversion element) PD' formed in the same manner as the photoelectric conversion element PD, and a second reference region NPD in which the photoelectric conversion element PD is not formed. The second reference region NPD is a comparison region that does not include the photoelectric conversion element PD or a comparison region that does not include the photodiode of the photoelectric conversion element PD. For example, the dummy photoelectric conversion elements PD' are arranged in the first substrate 110 in the light-shielding region OB adjacent to the pixel array region PA, but are not arranged in the first substrate 110 in the light-shielding region OB separated from the pixel array region PA. In the light-shielding area OB, the first reference area PD′ and the second reference area NPD are disposed in the first substrate 110 and are separated by the pixel separating pattern 130 .

[0028] The first wiring structure 150 is disposed on the lower surface of the first substrate 110 . The first substrate 110 and the first wiring structure 150 constitute a first chip 100, which is also referred to herein as a "sensor chip." The first wiring structure 150 includes a first inter-wiring insulating layer 151 and a plurality of first wirings 155 on the first inter-wiring insulating layer 151 . The number of layers of wiring constituting the first wiring structure 150 and their arrangement shown in the figure are merely illustrative.

[0029] The plurality of first wirings 155 include wiring patterns on different levels and vias that electrically connect the wiring patterns to the first circuit elements 120 . The first inter-wiring insulating layer 120 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide. The first wiring 155 may include, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof.

[0030] The second substrate 210, like the first substrate 110, is bulk silicon or silicon-on-insulator (SOI). The second substrate 210 may be a silicon substrate or may include other materials such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the second substrate 210 may be a base substrate on which an epitaxial layer is formed. On the second substrate 210, a second circuit element 220 is disposed. For example, the second circuit element 220 may include transistors that constitute a control register block, a timing generator, a ramp signal generator, a row driver, a readout circuit, a buffer, or the like.

[0031] The second wiring structure 250 is disposed on the second substrate 210 . For example, the second wiring structure 250 is disposed between the first wiring structure 150 of the first chip 100 and the second substrate 210 . The second substrate 210 and the second wiring structure 250 constitute the second chip 200 . Here, the second chip 200 can also be called a "logic chip." The second wiring structure 250 includes a second inter-wiring insulating layer 251 and a plurality of second wirings 255 on the second inter-wiring insulating layer 251 . The number of layers of wiring constituting the second wiring structure 250 and their arrangement shown in the figure are merely illustrative.

[0032] The plurality of first wirings 255 include wiring patterns on different levels and vias that electrically connect the wiring patterns to the second circuit elements 220 . The second wiring structure 250 provides a path for transmitting and receiving electrical signals between the second circuit element 220 and each unit pixel of the sensor array area SAR. The second inter-wiring insulating film 220 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide. The second wiring 255 may include, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof. In this embodiment, the first wiring structure 150 is joined to the second wiring structure 250 . In one embodiment, a bonding insulating film may be included at the interface between the first and second wiring structures (150, 250). The bonding insulating film may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride (SiCN), but is not limited thereto.

[0033] The surface insulating layer 140 is disposed on substantially the entire upper surface 110b of the first substrate 110. The surface insulating layer 140 extends along the upper surface 110b of the first substrate 110 not only in the sensor array region SAR but also in the peripheral region, ie, the chip-to-chip connection region CR and the pad region PR. The surface insulating layer 140 includes an insulating material. For example, the surface insulating layer 140 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and combinations thereof.

[0034] In one embodiment, the surface insulating layer 140 may be a multi-layer film. The surface insulating layer 140 functions as an anti-reflection film and prevents reflection of light incident on the first substrate 110, thereby improving the light receiving efficiency of the photoelectric conversion layer PD. Furthermore, the surface insulating layer 140 functions as a planarizing film, and allows the color filter 160 and the microlens layer 280L, which will be described later, to be formed with a uniform height. For example, the surface insulating layer 140 includes an aluminum oxide film, a hafnium oxide film, a silicon oxide film, a silicon nitride film, and a hafnium oxide film that are sequentially stacked on the upper surface 110b of the first substrate 110.

[0035] The color filter 160 is disposed on the surface insulating layer 140 . The color filters 160 are arranged to correspond to the respective unit pixels of the pixel array area PA. The color filter 160 has various color filters according to the unit pixel. For example, the color filter 160 includes a red color filter 160R, a green color filter 160G, and a blue color filter 160B. In one embodiment, the color filters 160 are arranged in a Bayer pattern. However, this is merely an example, and the color filter 160 may also include a yellow filter, a magenta filter, and a cyan filter, and may further include a white filter.

[0036] In this embodiment, a grid pattern 150 is disposed between color filters 160 . A grid pattern 150 is disposed on the surface insulating layer 140 . The grid pattern 150 is interposed between the color filters 160 . In one embodiment, the grid pattern 150 is arranged to overlap the pixel separation pattern 130 in the perpendicular third direction Z. In one embodiment, the grid pattern 150 includes a conductive pattern and a low refractive index pattern. The conductive pattern can prevent charges generated by ESD or the like from accumulating on the surface of the first substrate 110, thereby effectively preventing ESD failures. The low refractive index pattern can improve the light collection efficiency by refracting or reflecting obliquely incident light, thereby improving the quality of the image sensor.

[0037] For example, the conductive pattern may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), and copper (Cu), and the low refractive index pattern includes a low refractive index material having a refractive index lower than that of silicon (Si). For example, the low refractive index pattern may include at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof.

[0038] The microlens layer 280L is disposed on the color filter 160. The microlens layer 280 includes microlenses arranged to correspond to each unit pixel of the pixel array area PA. Each microlens has a convex shape and a predetermined radius of curvature. This allows the microlens to condense the light incident on the photoelectric conversion element PD. The microlens layer 280 includes, for example, a light-transmitting resin. In one embodiment, the microlens layer 280 extends into a portion of the peripheral region (eg, the light blocking region OB).

[0039] Referring to FIG. 3, the first chip 100 further includes a light-shielding filter layer 165. The light-shielding filter layer 165 is disposed on the conductive layer 355L in the light-shielding region OB. In one embodiment, the light-shielding filter layer 165 extends on the conductive layer 355L from the light-shielding region OB to at least a portion of the chip-to-chip connection region CR (see FIG. 12), but is not limited to this. The light-shielding filter layer 165, together with the conductive layer 355L, constitutes a light-shielding pattern that blocks light. The light-shielding filter layer 165 is formed together with the color filter 160 and has substantially the same thickness as the color filter 160, but is not limited to this. The light-shielding filter layer 165 may include a blue color filter or a black filter.

[0040] In one embodiment, the light blocking area OB may be used to remove noise signals due to dark current. For example, in a state where light is blocked by the conductive layer 355L and the light-shielding filter layer 165, the first reference area PD' including the photodiode can be used as a reference pixel for noise removal by the photodiode. In addition, the second reference region NPD, which does not include a photodiode and is shielded from light by the conductive layer 355L and the light-shielding filter layer 165, may be a region for checking process noise to remove noise caused by other components other than the photodiode.

[0041] The image sensor 10 according to this embodiment includes a plurality of through-via structures 350A that partially penetrate the first chip 100 and extend into the second chip 200 in the inter-chip connection region CR. As shown in FIG. 6, the plurality of through-via structures 350A are arranged in a first direction X and a second direction Y intersecting the first direction X in a plan view. In this embodiment, each of the plurality of through-via structures 350A includes a via conductive layer 355a, a filling insulating film 356a, and a capping pattern 359a. The via hole H1 exposes the first or second pad (155P1, 155P2) of the first wiring structure 150 and the first pad 255P1 of the second wiring structure 250. The plurality of through-via structures 350A are formed in the plurality of first via holes H1, respectively.

[0042] The via conductive layer 355a is conformally formed on the sidewall and bottom surface of the first via hole H1 in the inter-chip connection region CR. The via conductive layer 355a electrically connects the first or second pad (155P1, 155P2) of the first wiring structure 150 to the first pad 255P1 of the second wiring structure 250. The via conductive layer 355a is disposed in the first via hole H1 and connects the first wiring 155 and the second wiring 255. The via conductive layer 355a extends along the profile of the side and bottom surfaces of the first via hole H1.

[0043] In one embodiment, the via conductive layer 355a is formed with a conductive layer 355L extended from the top surface 110b of the first substrate 110, and is either connected to the conductive layer 355L or is a layer separated from the conductive layer 355L and other via conductive layers. For example, the via conductive layer 355a may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu), and combinations thereof.

[0044] In one embodiment, a filling insulating film 356a is disposed on the via conductive layer 355a to fill at least a portion of the first via hole H1. In one embodiment, the top surface of the filling insulating film 356a is concave. This is due to, but not limited to, the characteristics of the process of forming the filling insulating film 356a (for example, the deposition process and / or the planarization process). For example, the filling insulating film 356a may include silicon-based insulating materials (eg, silicon nitride, silicon oxide, and silicon oxynitride) and high-k materials (eg, hafnium oxide and aluminum oxide).

[0045] In one embodiment, the capping pattern 359a is disposed on the via conductive layer 355a and the filling insulating layer 356a. For example, a portion of the capping pattern 359a protrudes from the upper surface of the via conductive layer 355a. In one embodiment, the capping pattern 359a may be omitted. The first protective layer 165 covers the plurality of connection structures 450 . For example, the first protective film 165 extends along the profile of the connection structure 450 .

[0046] The image sensor 10 according to this embodiment further includes a first protective layer 280 extending from the microlens layer 280 and disposed on the peripheral region, that is, the light-shielding region OB, the inter-chip connection region CR, and the pad region PR. The first protective layer 280 extends over the light-shielding region OB, the inter-chip connection region CR, and the pad region PR to provide a flat upper surface. Here, the first protective layer 280 can also be called a planarization layer. In one embodiment, the first protective layer 280 is extended to cover the light-shielding filter layer 165 in the light-shielding region OB and the multiple through-via structures in the inter-chip connection region, providing a flat top surface, and extending over the pad region PR. The first protective layer 280 is formed so that the bonding pad 390 is exposed in the pad region PR.

[0047] In one embodiment, the first protective layer 280 is a layer formed together on the light-shielding region OB, the chip-to-chip connection region CR, and the pad region PR during the deposition process for forming the microlens layer 280L in the pixel array region PA. The first protective layer 280 contains the same material as the microlens layer 280L. For example, the first protective layer 280 includes a light-transmitting resin, such as a transparent photoresist material or a transparent thermosetting resin material.

[0048] The image sensor according to this embodiment further includes a second protective layer 290 formed on the microlens layer 280L and the first protective layer 280. The second protective layer 290 is formed on the upper surface of the first protective layer 280 by extending along the surface of the microlens layer 280L. The second protective layer 290 is formed relatively conformally. The second protective layer 290 has a thickness that is less than the thickness of the first protective layer 280 . The second protective layer 290 comprises low temperature oxide (LTO).

[0049] The second protective layer 290 may include an inorganic oxide such as, for example, silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, or a combination thereof. The second protective layer 290 protects the microlens layer 280L from the outside. For example, the second protective layer 290 can protect the microlens layer 280L containing an organic material by including an inorganic oxide film. In addition, the second protective layer 290 can improve the quality of the image sensor 10 by improving the light collection efficiency of the microlenses of the microlens layer 280L. For example, the second protective layer 290 can be formed in the area between the microlenses to reduce reflection, refraction, scattering, etc. of incident light that reaches the space between the microlenses.

[0050] In the inter-chip connection region CR of the image sensor 100 according to this embodiment, the first and second protective layers (280, 290) are separated into a plurality of patterns (P1, P2), thereby minimizing the effect of thermal stress and effectively preventing damage such as cracks.

[0051] FIG. 6 is a plan view showing a part ("A") of the inter-chip connection region CR of the image sensor of FIG. 1, and FIG. 4 can be understood as a cross section seen by cutting the plane of FIG. 6 in the X direction. Referring to FIG. 6 in conjunction with FIG. 4, a plurality of through-via structures 350A are arranged in the first direction X and the second direction Y in the inter-chip connection region CR. The plurality of through-via structures 350A are arranged in a first direction X at a first interval d1 and in a second direction Y at a second interval d2.

[0052] The first and second protective layers 280 and 290 according to this embodiment are separated by a groove G1 extending in the second direction Y in each of the first and second patterns P1 and P2. This reduces the unit area of ​​the first and second protective layers (280, 290), thereby alleviating the thermal stress applied to the first and second protective layers (280, 290) when they come into contact with external structures such as glue dams at the package level (see Figure 8).

[0053] The first protective layer 280 has a plurality of first patterns P1 that cover each column of the through-via structures 350A arranged in the second direction Y. Moreover, the second protective layer 290 has a plurality of second patterns P2 corresponding to the plurality of first patterns P1, respectively, in the inter-chip connection region CR. In this embodiment, the plurality of first patterns P1 are completely separated from each other. The second patterns P2 are disposed on the upper surfaces 280T of the first patterns P1, respectively, and extend to the side surfaces 280S adjacent to the upper surfaces 280T. Furthermore, the plurality of second patterns P2 each have a pattern that is separated from one another. The surface insulating layer 140 is exposed between the plurality of first and second patterns (P1, P2), that is, at the bottom of the groove G1. In one embodiment, a portion of the conductive layer 355L may be exposed at the bottom of the groove G1.

[0054] In this embodiment, the first and second patterns (P1, P2) are formed by forming a first protective layer 280 on the upper surface of the first chip 100, then performing a first etching process to separate the first protective layer 280 into a desired first pattern in the inter-chip connection region CR, and then conformally forming a second protective layer 290 on the first protective layer 280 and the microlens layer 280L, and then performing a second etching process to separate the second protective layer 290 into a second pattern corresponding to the first pattern in the inter-chip connection region CR.

[0055] In the pad region PR, the bonding pad 390 is connected to the pad via structure 350B by the conductive layer 355L. In this embodiment, the pad-via structure 350B is similar to the plurality of through-via structures 350A, and includes a via conductive layer 355b, a filling insulating film 356b, and a capping pattern 359b. The second via hole H2 exposes the second pad 255P2 of the second wiring structure 250. The pad through-via structures 350B are formed in the second via holes H2, respectively.

[0056] The via conductive layer 355b is conformally formed on the sidewall and bottom surface of the second via hole H2 in the pad region PR. The via conductive layer 355b is electrically connected to the second pad 255P2 of the second wiring structure 250. The via conductive layer 355b is disposed in the second via hole H2 and is connected to the second wiring 255.

[0057] As shown in FIG. 5, the first substrate 110 has a recess extending inward from the top surface in the pad region PR. The via conductive layer 355b extends onto the top surface of the surface insulating layer 140 to cover the sidewalls and bottom surface of the recess. A bonding pad 390 is disposed on the via conductive layer 355b within the recess. The bonding pad 390 is embedded in a recess in the second substrate 110 .

[0058] In one embodiment, the via conductive layer 355b may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu), and combinations thereof. For example, the filling insulating film 356b may include silicon-based insulating materials (eg, silicon nitride, silicon oxide, and silicon oxynitride) and high-k materials (eg, hafnium oxide and aluminum oxide). The bonding pad 390 includes a different conductive material than the via conductive layer 355b, for example, aluminum (Al). The image sensor 10 according to this embodiment further includes an isolation pattern 140P penetrating the first substrate 110 within the pad region PR. In one example, the isolation pattern 140P extends from at least a portion of the surface insulating layer 140.

[0059] The image sensor 100 described above can also be realized in various modified forms. In particular, the first and second protective layers can be patterned in various forms. 7a to 7c are plan views illustrating protective layer pattern arrays of image sensors according to various embodiments of the present invention.

[0060] First, referring to FIG. 7a, the first and second protective layers 280 and 290 according to this embodiment are separated by a groove G2 extending in a first direction X in first and second patterns P1a and P2a, respectively. The first protective layer 280 has a plurality of first patterns P1a that cover each row of the through-via structures 350A arranged in the first direction X among the plurality of through-via structures 350A. Moreover, the second protective layer 290 has, in the inter-chip connection region CR, a plurality of second patterns P2b corresponding to the plurality of first patterns P1a, respectively.

[0061] Similar to the example shown in FIG. 6, the plurality of through-via structures 350A may be arranged such that the spacing in the second direction Y is greater than the spacing in the first direction X, and the plurality of first and second patterns (P1a, P2a) may be separated by a groove G2 along the first direction X. In this way, by forming the grooves G2 along a relatively large interval, the process of separating the first and second protective layers (280, 290) into a plurality of first and second patterns (P1a, P2a), respectively, can be more easily performed. For example, the plurality of first and second patterns (P1a, P2a) employed in this embodiment are separated by a gap g2 that is larger than the gap g1 in the previous embodiment (FIG. 6).

[0062] Referring to FIG. 7b, the first and second protective layers (280, 290) according to this embodiment are separated by a groove G2 extending in the first direction X in the first and second patterns (P1'a, P2'a), respectively, similar to the example shown in FIG. 7a. However, the first and second protective layers (280, 290) are arranged in the first direction X among the plurality of through-via structures 350A, but have a plurality of first and second patterns (P1'a, P2'a) covering the through-via structures in units of two rows. In this manner, the first and second protective layers (280, 290) are separated in various patterns that each cover a plurality of rows and / or columns of through-via structures 350A.

[0063] Referring to FIG. 7c, the first and second protective layers (280, 290) according to this embodiment are separated into first and second patterns (P1b, P2b) by a first groove G1 extending in the second direction Y and a second groove G2 extending in the first direction X, respectively. As a result, each of the plurality of first patterns P1b can be configured to cover one through-via structure 350A.

[0064] FIG. 8 is a cross-sectional view showing a schematic configuration of an image sensor package according to one embodiment of the present invention. Referring to FIG. 8, the image sensor package 500 of this embodiment includes a package substrate 510, an image sensor 10, bonding wires 530, a transparent cover 540, an encapsulant 550, and a dam 560.

[0065] The package substrate 510 includes a substrate body 511, an upper pad 515, a lower pad 518, and upper and lower passivation layers (512a, 512b). For example, the substrate body 511 may include silicon, ceramic, organic, glass, epoxy resin, and the like. In one embodiment, the package substrate 510 may be a printed circuit board (PCB). The substrate body 511 includes single or multiple layer wiring. The wiring electrically connects the upper pad 515 and the lower pad 518 .

[0066] The top pads 515 are located along both sides of the image sensor 10 mounted on the package substrate 510 . The lower pads 518 are disposed on the lower surface of the package substrate 510, and external connection terminals 580 such as solder balls are disposed on the lower pads 518. The image sensor 10 is mounted on a package substrate 510 using a wire bonding structure. The image sensor 10 is mounted with the pixel array area PA facing upward, and is adhered onto a package substrate 510 by an adhesive layer 520. The bonding pads 390 of the image sensor 10 are electrically connected to the corresponding top pads 113 of the package substrate 510 via wires 530 .

[0067] A transparent cover 540 is placed over the image sensor 10 . A dam 560 is placed on the peripheral area of ​​the image sensor 10 , and the transparent cover 540 is placed on the dam 560 . The dam 560 supports the transparent cover 540 over the image sensor 10 . The transparent cover 540 is disposed at a distance from the upper surface of the image sensor 520 by the height of the dam 560 . A space C may exist between the transparent cover 540 and the image sensor 100 . For example, the transparent cover 540 may include transparent glass, transparent resin, or translucent ceramic.

[0068] The encapsulant 550 is disposed on the package substrate 510 and encapsulates the image sensor 10 , the wires 530 , and the transparent cover 140 . Specifically, the sealing material 550 is formed to cover the upper surface of the package substrate 110 , the image sensor 10 , and the side surface of the transparent cover 540 . The encapsulant 510 also covers the wires 530 and covers the outer surface of the dam 160 . In this embodiment, the encapsulant 550 has sides that are substantially coplanar with the sides of the package substrate 510 . For example, the sealing material 550 is made of EMC (Epoxy Molding Compound).

[0069] The dam 560 employed in this embodiment may have a rectangular ring shape that surrounds the peripheral region of the upper surface of the image sensor 10 . The dam 560 is disposed in a peripheral region on the top surface of the image sensor 10, for example, in the pad region PR. The dam 560 is formed to cover the bonding pads 390 and wires 530 of the image sensor 10 . Such a dam 560 is extended to the inter-chip connection region CR and bonded to the second protective layer 290.

[0070] Dam 560 may cause cracks in second protective layer 290 due to thermal stress caused by the difference in thermal expansion coefficients between the first and second protective layers (280, 290), resulting in defects in appearance. Furthermore, such cracks may cause peeling, which may lead to a decrease in the reliability of image sensor 10 due to external moisture or foreign matter. In order to prevent defects caused by such thermal stress, the first and second protective layers (280, 290) are separated into multiple patterns (P1, P2) in the inter-chip connection region CR of the image sensor 10, thereby minimizing the impact of thermal stress and effectively preventing damage such as cracks.

[0071] 9 to 12 are cross-sectional views showing schematic configurations of image sensors according to various embodiments of the present invention. 9 to 12 are cross sections of the inter-chip connection region CR of image sensors 10A, 10B, 10C, and 10D according to various embodiments, and can be understood as cross sections corresponding to FIG.

[0072] Referring to Figure 9, the image sensor 10A according to this embodiment can be understood to have a structure similar to that of the image sensor 10 shown in Figures 1 to 6 (especially Figure 4), except that the first protective layer 280 is composed of a first pattern P1' covering two or two columns of through-via structures 350A in the inter-chip connection region CR, and the second protective layer 290 is not separated but is formed as a single layer. Furthermore, unless otherwise specified, the components of this embodiment can be understood as referring to the descriptions of the same or similar components of the image sensor 10 shown in FIGS.

[0073] In the inter-chip connection region CR, the first protective layer 280 is configured with a first pattern P1' by grooves Ga in the second direction Y, and the first pattern P1' is configured to cover two or two columns of through-via structures 350A, respectively. If necessary, grooves in the first direction X may be additionally formed (see FIGS. 7a to 7c). Unlike the previous embodiment, the second protective layer 290 is formed along the top and side surfaces of the first pattern P1' so as to be connected to each other. The second protective layer 290 forms a pattern with the first protective layer 280, but is not separated from each other. In this case, the first and second protective layers (280, 290) are also separated into small blocks, so that the thermal stress generated in the contact area with the dam (560 in FIG. 8) can be reduced.

[0074] The first and second protective layers (280, 290) according to this embodiment are formed by forming the first protective layer 280 on the upper surface of the first chip 100, then performing an etching process to separate the first protective layer 280 into the desired first pattern P1' in the inter-chip connection region CR, and then conformally forming the second protective layer 290 on the first protective layer 280 and the microlens layer 280L.

[0075] Referring to FIG. 10, the image sensor 10B according to this embodiment can be understood to have a similar structure to the image sensor 10 shown in FIGS. 1 to 6 (particularly FIG. 4), except that the first protective layer 280 is composed of a first pattern P1″ covering one or one row of through-via structures 350A in the inter-chip connection region CR, the first pattern P1″ is partially separated, and the second protective layer 290 is provided with a second pattern P2′ corresponding to the upper surface of the first pattern P1″. Furthermore, unless otherwise specified, the components of this embodiment can be understood as referring to the descriptions of the same or similar components of the image sensor 10 shown in FIGS.

[0076] In the inter-chip connection region CR, the first protective layer 280 is configured with a first pattern P1" by grooves Gb in the second direction Y, and the first pattern P1" is configured to cover one or one row of through-via structures 350A, respectively. The groove Gb does not completely separate the first patterns P1' but has a depth that partially separates them. In addition, the second protective layer 290 is formed to have a second pattern P2' corresponding to the top surface 280T of the first pattern P1''. In this embodiment, the second pattern P2' does not extend to the side surface 280S' of the first pattern P1'' exposed by the groove Gb.

[0077] The first and second protective layers (280, 290) in this embodiment are formed by forming a first protective layer 280 having a flat upper surface on the upper surface of the first chip 100, subsequently forming a second protective layer 290 conformally on the first protective layer 280 and the microlens layer 280L, and then etching a portion of the second protective layer 290 and the first protective layer 280 in the inter-chip connection region CR.

[0078] Referring to FIG. 11, the image sensor 10C according to this embodiment can be understood to have a similar structure to the image sensor 10 shown in FIGS. 1 to 6 (particularly FIG. 4), except that the first protective layer 280 is configured with a first pattern P1′ covering two or two rows of through-via structures 350A in the inter-chip connection region CR, and the second protective layer 290 is provided with a second pattern P2′ corresponding to the upper surface of the first pattern P1″. Furthermore, unless otherwise specified, the components of this embodiment can be understood as referring to the descriptions of the same or similar components of the image sensor 10 shown in FIGS.

[0079] In the inter-chip connection region CR, the first protective layer 280 is configured with a first pattern P1' by grooves Gc in the second direction Y, and the first pattern P1' is configured to cover two or two rows of through-via structures 350A, respectively. The groove Gc has a depth that completely separates the first patterns P1'. The second protective layer 290 is formed to have a second pattern P2' corresponding to the top surface 280T of the first pattern P1''. In this embodiment, the second pattern P2' does not extend to the side surface 280S of the first pattern P1'' exposed by the groove Gc.

[0080] The first and second protective layers (280, 290) according to this embodiment are formed by forming a first protective layer 280 having a flat upper surface on the upper surface of the first chip 100, subsequently forming a second protective layer 290 conformally on the first protective layer 280 and the microlens layer 280L, and then performing an etching process to completely separate both the second protective layer 290 and the first protective layer 280 in the inter-chip connection region CR.

[0081] Referring to Figure 12, the image sensor 10D according to this embodiment can be understood to have a structure similar to that of the image sensor 10 shown in Figures 1 to 6 (particularly Figure 4), except that the light-shielding filter layer 165 extends to the inter-chip connection region CR and the first protective layer 280 is composed of a first pattern P1' covering two or two rows of through-via structures 350A in the inter-chip connection region CR. Furthermore, unless otherwise specified, the components of this embodiment can be understood as referring to the descriptions of the same or similar components of the image sensor 10 shown in FIGS.

[0082] In this embodiment, the light-shielding filter layer 165 located in the light-shielding region (see "OB" in FIG. 3) is extended to the inter-chip connection region CR. The light-shielding filter layer 165 is formed on the surface insulating layer 140 so as to cover the plurality of through-via structures 350A. The first protective layer 280 is configured in a first pattern P1' by grooves Gd in the second direction Y, and the first patterns P1' are configured to cover two or two rows of through-via structures 350A, respectively. Similar to the previous embodiment (see FIG. 4), the second protective layer 290 is formed along the top and side surfaces of the first pattern P1'.

[0083] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0084] 10, 100 image sensors 110 First board 111 Element isolation film 120 First circuit element 125 Active Elements Gate 125a 125b Source / Drain 130 pixel isolated pattern 130H Trench 131 Separation insulating layer 135 Filling Section 140 Surface insulating layer 140P Separation Pattern 150 1st wiring structure 151 First inter-wiring insulating layer 155 1st wiring 155P2 2nd pad 160 color filters 160R, 160G, 160B (red, green, blue) color filters 165 Light-blocking layer (light-blocking filter layer) 200 2nd chip 210 Second board 211 Element isolation membrane 215 Active region 220 Second circuit element 222 Source / Drain Gate 225 240 Second protective layer 250 2nd wiring structure 251 Second inter-wiring insulating layer 255 2nd wiring 255P1 1st pad 255P2 2nd pad 280 1st protective layer 280L microlens (layer) 290 Second protective layer 350A Through Via Structure 350B Pad Via Structure 355a, 355b via conductive layer 355L conductive layer 356a, 356b Filling insulating film 359a, 359b Capping Pattern 390 Bonding Pad CR inter-chip connection area NPD 2nd Reference Area OB shading area PA Pixel Array Area PD, photoelectric conversion element PD' dummy photoelectric conversion element PR pad area TG Transfer Gate

Claims

1. a first chip including a pixel array area, a pad area, and an inter-chip connection area between the pixel array area and the pad area; a second chip disposed on the underside of the first chip; a plurality of through-via structures extending through the first chip into the second chip in the inter-chip connection region of the first chip; a surface insulating layer disposed on the first chip; a color filter disposed on the surface insulating layer within a pixel array region of the first chip; a microlens layer including microlenses disposed on the color filter; a first protection layer disposed on at least the inter-chip connection region of the first chip, the first protection layer having a plurality of first patterns each covering at least one of the plurality of through-via structures; an image sensor comprising: a second protective layer disposed on the microlens layer and the first protective layer, the second protective layer having a plurality of second patterns each positioned on the plurality of first patterns in the inter-chip connection region of the first chip.

2. The image sensor of claim 1 , wherein the first protective layer is connected to the microlens layer and contains the same material as the microlens layer.

3. A plurality of pads are arranged in the pad area; The image sensor of claim 1 , wherein the first protection layer extends over the pad area and has openings that expose the pads.

4. The image sensor according to claim 1 , wherein the plurality of through-via structures are arranged in a first direction and a second direction intersecting the first direction in a plan view.

5. The image sensor of claim 4 , wherein the first patterns and the second patterns are separated by grooves along the first direction or the second direction.

6. The image sensor of claim 4 , wherein the first patterns and the second patterns are separated by a first groove along the first direction and a second groove along the second direction.

7. The image sensor of claim 1 , wherein the plurality of first patterns are configured to cover two or more adjacent through-via structures among the plurality of through-via structures.

8. The image sensor of claim 1 , wherein each of the plurality of first patterns is configured to cover one of the plurality of through-via structures.

9. The image sensor of claim 1 , wherein the second patterns are disposed on the upper surfaces of the first patterns, respectively, and extend to a portion of a side surface adjacent to the upper surfaces.

10. The image sensor of claim 1 , wherein the second patterns are disposed on top surfaces of the first patterns and do not extend to side surfaces adjacent to the top surfaces.

11. The image sensor of claim 1 , wherein the plurality of first patterns are separated from each other.

12. The image sensor of claim 11 , wherein the second patterns cover upper and side surfaces of the first patterns, respectively, and are separated from one another.

13. The image sensor of claim 1 , wherein the first protective layer has a thickness greater than a thickness of the second protective layer.

14. An image sensor, a first substrate including a pixel array region in which photoelectric conversion elements are arranged, a pad region, and an inter-chip connection region between the pixel array region and the pad region, the first substrate having a first surface including a light receiving surface of the photoelectric conversion elements, and a second surface opposite to the first surface; a first wiring structure disposed on the second surface of the first substrate and including a first wiring and a first inter-wiring insulating film; a second substrate disposed on the first wiring structure and including a third surface facing the second surface and a fourth surface opposite the third surface; a second wiring structure on the third surface of the second substrate, the second wiring structure being in contact with the first wiring structure and including a second wiring and a second inter-wiring insulating film; a plurality of through-via structures in the inter-chip connection region, which penetrate the first substrate and the first wiring structure, extend into the second wiring structure, and are electrically connected to the second wiring; a surface insulating layer disposed on the first surface of the first substrate; a color filter disposed on the surface insulating layer in the pixel array region of the first substrate; a microlens layer disposed on the color filter and including microlenses; a first protection layer integrated with the microlens layer, extending over the inter-chip connection region and the pad region, and having a plurality of first patterns covering at least one of the plurality of through-via structures; and a second protective layer disposed on the microlens layer and the first protective layer, the second protective layer having a plurality of second patterns respectively positioned on the plurality of first patterns and separated from one another.

15. the plurality of through-via structures are arranged in a first direction and a second direction intersecting the first direction in a plan view, the plurality of through-via structures are arranged such that the intervals in the second direction are greater than the intervals in the first direction; The image sensor of claim 14 , wherein the plurality of first patterns are separated by grooves along the first direction.

16. The image sensor of claim 14, wherein the second protective layer has a thickness less than a thickness of the first protective layer.

17. the plurality of first patterns have patterns separated from one another; The image sensor of claim 16, wherein the second patterns are disposed on the upper surfaces of the first patterns, respectively, and extend to a portion of a side surface adjacent to the upper surfaces.

18. the first substrate further includes a light-shielding region between the pixel array region and the inter-chip connection region; The image sensor of claim 14 , further comprising a light-shielding pattern disposed on the light-shielding region between the surface insulating layer and the first protective layer.

19. a first chip including a pixel array area, a pad area, and an inter-chip connection area between the pixel array area and the pad area; a second chip disposed on the underside of the first chip; a plurality of through-via structures extending through the first chip into the second chip in the inter-chip connection region of the first chip; a surface insulating layer disposed on the first chip; a color filter disposed on the surface insulating layer within a pixel array region of the first chip; a microlens layer disposed on the color filter and including microlenses; a first protection layer disposed on the inter-chip connection region and the pad region of the first chip; a second protective layer disposed on the microlens layer and the first protective layer; In the inter-chip connection region, the first and second protective layers each have a plurality of patterns that cover at least one of the plurality of through-via structures.

20. 20. The image sensor of claim 19, wherein the plurality of patterns are separated by grooves having a depth that penetrates the second passivation layer and extends to a portion of the first passivation layer.

Images