Solar cell

Abstract

To provide a solar cell in which the structural design of the rear surface of the cell is improved.SOLUTION: A solar cell, comprising: a silicon substrate having a front surface and a back surface opposite to each other, wherein the back surface of the silicon substrate has a first region, a second region, and a spacer region between the first region and the second region, wherein the back surface of the second region of the silicon substrate is recessed relative to the back surface of the first region of the silicon substrate toward the front surface of the silicon substrate; a first doping structure provided in the first region, which is a diffusion region formed by a dopant diffusing inward from the back surface of the silicon substrate; a second doping structure provided in the second region, which is a tunnel passivation contact structure having a doping type opposite to that of the diffusion region; a first electrode located on the back surface of the first doping structure; and a second electrode located on the back surface of the second doping structure.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to the photovoltaic field, and in particular to solar cells. [Background technology]

[0002] In a back contact (BC) battery, both the positive and negative electrodes are on the back side of the battery, reducing the current transmission path and lowering resistance. There are no grid lines on the front side, which improves light absorption efficiency and enhances battery performance.

[0003] However, although BC batteries have advantages over other battery technology routes, the structural design of the battery will affect the progress of mass production.

[0004] In view of this, there is a need to provide an improved solar cell that solves the above technical problems. Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention provides a solar cell, improves the structural design of the back surface of the cell, and is advantageous for industrialization. [Means for solving the problem]

[0006] In order to achieve one of the above objects of the invention, the present invention adopts the following technical solutions.

[0007] A solar cell, a first doping structure provided in the first region, which is a diffusion region formed by diffusing a dopant inward from the back surface of the silicon substrate; a second doping structure provided in the second region, which is a tunnel passivation contact structure having a doping type opposite to that of the diffusion region; a first electrode provided on the back surface of the first doping structure; and a second electrode provided on the back surface of the second doping structure.

[0008] In this embodiment, the front surface of the silicon substrate is the primary light-receiving surface of the silicon substrate, and the back surface of the silicon substrate is the secondary light-receiving surface of the silicon substrate. The first doping structure and the second doping structure each include a front surface and a back surface facing each other. The front surface of the first doping structure is the surface of the first doping structure facing the front surface of the silicon substrate. The back surface of the first doping structure is the surface of the first doping structure facing away from the front surface of the silicon substrate. The front surface of the second doping structure is the surface of the second doping structure facing toward the silicon substrate. The back surface of the second doping structure is the surface of the second doping structure facing away from the silicon substrate.

[0009] In this embodiment, the first electrode provided on the back surface of the first doping structure refers to the first electrode being provided on one side of the back surface of the first doping structure. The second electrode provided on the back surface of the second doping structure refers to the second electrode being provided on one side of the back surface of the second doping structure. In actual application, both the first electrode and the second electrode extend inward from the back surface of the silicon substrate, with a portion of the first electrode extending into the first doping structure to establish electrical contact with the first doping structure, and a portion of the second electrode extending into the second doping structure to establish electrical contact with the second doping structure.

[0010] In one alternative embodiment, the back surface of the silicon substrate in the spacer region is recessed toward the front surface of the silicon substrate relative to the back surface of the silicon substrate in the second region, and the recess depth of the back surface of the silicon substrate in the first region toward the front surface of the silicon substrate and / or the recess depth of the back surface of the silicon substrate in the spacer region toward the front surface of the silicon substrate is equal to or greater than the diffusion depth of the diffusion region.

[0011] In one alternative embodiment, the width of the spacer region is 10 μm to 150 μm.

[0012] In one alternative embodiment, the distance from the rear surface of the spacer region of the silicon substrate to the rear surface of the first doping structure is 1 μm to 20 μm.

[0013] In one alternative embodiment, the distance from the back surface of the second doping structure to the front surface of the silicon substrate is equal to or less than the distance from the back surface of the first doping structure to the front surface of the silicon substrate.

[0014] In one alternative embodiment, the dimension of the second doping structure in the thickness direction of the silicon substrate is equal to or less than the depth of a recess formed by recessing the back surface of the silicon substrate in the spacer region toward the front surface of the silicon substrate.

[0015] In one alternative embodiment, the distance between the back surface of the first doping structure and the back surface of the second doping structure in the thickness direction of the silicon substrate is 1 μm to 10 μm.

[0016] In one alternative embodiment, the first doping structure includes a gate line region and a non-gate line region, the doping concentration of the gate line region is greater than the doping concentration of the non-gate line region, and the first electrode is in contact with the gate line region.

[0017] In one alternative embodiment, the gate line region has a square resistance of 80 ohm / sq to 130 ohm / sq, and the non-gate line region has a square resistance of 200 ohm / sq to 400 ohm / sq.

[0018] In one alternative embodiment, the tunnel passivation contact structure includes a tunnel layer and a doped polysilicon layer disposed on a side of the tunnel layer remote from the silicon substrate, and the second electrode is in contact with the doped polysilicon layer.

[0019] In this embodiment, the tunnel passivation contact structure includes a tunnel layer and a doped polysilicon layer, and correspondingly, the reverse doping type of the tunnel passivation contact structure and the diffusion region refers to the reverse doping type of the diffusion region and the doping type of the doped polysilicon layer in the tunnel passivation contact structure.

[0020] In one alternative embodiment, the number of the tunnel layers and the number of the doped polysilicon layers are both n, where n≧2, and one doped polysilicon layer of the n doped polysilicon layers is provided on the side of each tunnel layer of the n tunnel layers away from the silicon substrate, and the second electrode is in contact with at least one of the second to n doped polysilicon layers of the n doped polysilicon layers in a direction from the front surface to the back surface of the silicon substrate.

[0021] In one alternative embodiment, the first doping structure is a P-type diffusion region and the doped polysilicon layer is an N-type doped polysilicon layer, or the first doping structure is an N-type diffusion region and the doped polysilicon layer is a P-type doped polysilicon layer.

[0022] In one alternative embodiment, the first doping structure is higher than the second doping structure along a direction from the front side to the back side of the silicon substrate.

[0023] In one alternative embodiment, the step between the rear surface of the first doping structure and the rear surface of the second doping structure is 0.5 to 1.5 times the diffusion depth of the diffusion region.

[0024] In one alternative embodiment, the dimension of the rear surface of the silicon substrate in the spacer region is 15 μm to 30 μm, or the roughness of the rear surface of the silicon substrate in the spacer region is 10 nm or less.

[0025] In an alternative embodiment, all areas of the rear surface of the solar cell other than the spacer area have a textured structure.

[0026] In one alternative embodiment, the solar cell further includes a passivation film layer, and the passivation film layer in the spacer region includes a first charge film layer in contact with the silicon substrate and a second charge film layer provided on the side of the first charge film layer away from the silicon substrate, wherein the charge type of the first charge film layer is similar to the charge type of the silicon substrate, and the charge type of the first charge film layer is opposite to the charge type of the second charge film layer.

[0027] In one alternative embodiment, the thickness of the first charge film layer is less than the thickness of the second charge film layer.

[0028] In one alternative embodiment, the silicon substrate is N-type silicon, the first charged film layer is a negatively charged film layer, and the second charged film layer is a positively charged film layer, or the silicon substrate is P-type silicon, the first charged film layer is a positively charged film layer, and the second charged film layer is a negatively charged film layer.

[0029] In one alternative embodiment, the negatively charged film layer includes a silicon oxide film layer in contact with the silicon substrate and an alumina film layer disposed on the side of the silicon oxide film layer away from the silicon substrate.

[0030] In one alternative embodiment, the silicon oxide film layer has a thickness of 0.5 nm to 2 nm, and the alumina film layer has a thickness of 1 nm to 20 nm.

[0031] In one alternative embodiment, the positively charged film layer is selected from at least one of a SiNx film layer and a SiOxNy film layer.

[0032] In one alternative embodiment, the thickness of the positively charged film layer is 10 nm to 100 nm. [Effects of the Invention]

[0033] The beneficial effects of the present invention are as follows: By providing both the first electrode and the second electrode on the back surface of the solar cell according to the present invention, there is no shielding by the metal electrode on the front surface, the light receiving area is large, the light conversion efficiency is high, and the cell efficiency is improved. The solar cell has a front surface and a back surface facing each other, the back surface of the silicon substrate including a first region, a second region, and a spacer region between the first region and the second region, the back surface of the silicon substrate in the second region being recessed relative to the back surface of the silicon substrate in the first region toward the front surface of the silicon substrate, a first doping structure being disposed in the first region, the first doping structure being a diffusion region formed by dopant diffusing inward from the back surface of the silicon substrate, a second doping structure being disposed in the second region, and the second doping structure being a tunnel passivation contact structure disposed on the back surface of the silicon substrate in the second region, the first doping structure being formed by diffusion and removing the diffusion junction in a portion of the region, and then the tunnel passivation contact structure being deposited, which is highly compatible with the process flow of TOPCon batteries and suitable for promoting industrialization. [Brief explanation of the drawings]

[0034] [Figure 1] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 2] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 3]1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 4] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 5] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 6] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 7] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 8] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 9] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 10] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 11] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 12] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 13] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 14] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0035] The present invention will be described in detail below based on specific embodiments shown in the accompanying drawings, but these embodiments do not limit the present invention, and any structural, method, and functional modifications made by those skilled in the art based on these embodiments are within the scope of protection of the present invention.

[0036] In each drawing of the present invention, for ease of illustration, the dimensions of some of the structures or parts are exaggerated relative to other structures or parts, and are therefore used to illustrate only the basic structures of the subject matter of the present invention.

[0037] As shown in Figures 1 to 14, this is a solar cell 100 according to a preferred embodiment of the present invention, and comprises a silicon substrate 1, a first doping structure 2 on the back surface of the silicon substrate 1, a second doping structure 3 on the back surface of the silicon substrate 1, a spacer region 4 between the first doping structure 2 and the second doping structure 3, a first electrode 91 on the back surface of the first doping structure 2, and a second electrode 92 on the back surface of the second doping structure 3.

[0038] The silicon substrate 1 includes a front surface and a back surface facing each other. The front surface of the silicon substrate 1 is the primary light-receiving surface of the silicon substrate 1, and the back surface of the silicon substrate 1 is the secondary light-receiving surface of the silicon substrate. The silicon substrate 1 is an N-type silicon wafer having a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 2 Ω·cm to 3.5 Ω·cm. In one alternative embodiment, the front surface of the silicon substrate 1 has a textured structure, which provides an excellent light-limiting effect and improves light utilization efficiency.

[0039] The first doping structure 2 and the second doping structure 3 each include a front surface and a back surface facing each other. The front surface of the first doping structure 2 is the surface of the first doping structure facing the front of the silicon substrate 1. The back surface of the first doping structure 2 is the surface of the first doping structure facing away from the front of the silicon substrate 1. The front surface of the second doping structure 3 is the surface of the second doping structure 3 facing toward the silicon substrate 1. The back surface of the second doping structure 3 is the surface of the second doping structure 3 facing away from the silicon substrate 1.

[0040] In this embodiment, the first electrode 91 provided on the rear surface of the first doping structure 2 refers to the first electrode 91 being provided on the rear side of the first doping structure 2. The second electrode 92 provided on the rear surface of the second doping structure 3 refers to the second electrode 92 being provided on one side of the rear surface of the second doping structure 3. In actual application, the first electrode 91 and the second electrode 92 both extend inward from the rear surface of the silicon substrate, with a portion of the first electrode 91 extending into the first doping structure 2 to establish electrical contact therewith, and a portion of the second electrode 92 extending into the second doping structure 3 to establish electrical contact therewith.

[0041] The first doping structure 2 and the second doping structure 3 have opposite doping types: one is a P-type doping structure and the other is an N-type doping structure. The first doping structure 2 and the second doping structure 3 are alternately arranged, and the two regions are separated by a spacer region 4. The first doping structure 2 and the second doping structure 3 are both arranged on the back surface of the battery sheet (i.e., the secondary light-receiving surface of the battery sheet), which reduces the current transmission path between the P-type doping structure and the N-type doping structure and reduces resistance. In addition, by arranging the first electrode 91 and the second electrode 92 on the back surface of the battery sheet, there is no shielding by metal electrodes on the front surface of the battery sheet (i.e., the primary light-receiving surface of the battery sheet), which increases the light-receiving area and improves battery efficiency.

[0042] The first doping structure 2 is a diffusion region formed by diffusing a dopant directly inward (i.e., toward the front surface) from the rear surface of the silicon substrate 1. Here, the diffusion depth of the dopant along the thickness direction of the silicon substrate 1 is called the junction depth.

[0043] In the first embodiment, as shown in FIGS. 1 to 8, the first doping structure 2 is a P-type diffusion region, and the second doping structure 3 is an N-type tunnel passivation contact structure.

[0044] The first doping structure 2 is a P-type doping structure, specifically a P-type diffusion region formed by diffusing P-type dopants from the rear surface of the silicon substrate 1 inward. In this case, a PN junction is located within the silicon substrate 1, which is advantageous for carrier separation and collection, thereby improving cell efficiency. P-type dopants include, but are not limited to, boron, aluminum, gallium, etc.

[0045] As shown in Figures 1, 3, 5 and 7, the doping concentration throughout the diffusion region is consistent.

[0046] As shown in FIGS. 2, 4, 6 and 8, the first doping structure 2 includes a gate line region 21 and a non-gate line region 22, and the doping concentration of the gate line region 21 is greater than that of the non-gate line region 22.

[0047] The gate line region 21 has a high doping concentration, which forms an ohmic contact with the first electrode 91, reducing the battery's series resistance and increasing the battery's fill factor FF. The non-gate line region 22 has a low doping concentration, which reduces the carrier surface recombination probability and lowers the battery's reverse saturation current, thereby improving the battery's open circuit voltage Voc and short circuit current Isc. Furthermore, the gate line region 21 and the non-gate line region 22 can laterally form P++ / P+ or N++ / N+ high and low junctions, which are beneficial for improving carrier collection and further increasing the short circuit current Isc.

[0048] In one alternative embodiment, the doping concentration of the gate line region 21 is 5E18 cm -3 ~1E20cm -3 The corner resistance of the non-gate line region 22 is 80 ohm / sq to 130 ohm / sq, and the corner resistance of the non-gate line region 22 is 200 ohm / sq to 400 ohm / sq.

[0049] The second doping structure 3 is a tunnel passivation contact structure located in a region recessed from the back surface to the front surface of the silicon substrate 1. The tunnel passivation contact structure includes at least one tunnel layer 31 and a doped polysilicon layer 32 on the side of each tunnel layer 31 facing away from the silicon substrate 1, and the second electrode 92 is in contact with the doped polysilicon layer 32.

[0050] The tunnel layer 31 is selected from a silicon oxide layer (SiOx) or a silicon carbide layer (SiC), and has a thickness of 1 nm to 3 nm, preferably 1 nm to 2.5 nm, and more preferably 1 nm to 2 nm or 1.5 nm to 2.5 nm. The present invention optimizes the thickness depending on the density of the tunnel layer 31, and when the tunnel layer 31 is SiOx, the thickness is 1.4 nm to 2.3 nm, and when the tunnel layer 31 is SiC, the film layer becomes denser and the thickness is 1 nm to 1.8 nm.

[0051] The doped polysilicon layer 32 is an N-doped polysilicon layer, and the following description will be given taking phosphorus doping as an example. The doping concentration is 1E19 cm -3 ~1E21cm -3 and preferably 1E20cm -3 ~9E20cm -3 The thickness is 80 nm to 120 nm, and can be set to 90 nm, or 85 nm, or 100 nm, or 105 nm, or 110 nm, or 115 nm.

[0052] In one embodiment, the passivation contact structure includes one tunnel layer 31 and one doped polysilicon layer 32, and the second electrode 92 is in contact with the doped polysilicon layer 32, which avoids direct contact between the second electrode 92 and the silicon substrate 1 and improves cell efficiency.

[0053] In another embodiment, the tunnel passivation contact structure includes n tunnel layers 31 and a doped polysilicon layer 32 on the side of each tunnel layer 31 facing away from the silicon substrate 1, where n≧2. The multiple tunnel layers 31 can have the effect of inhibiting the diffusion of metallic silver into the silicon substrate, preventing it from forming a silicon-silver alloy when in contact with the silicon substrate.

[0054] In the direction from the silicon substrate 1 toward the back surface, the second electrode 92 is in contact with at least one of the second to nth doped polysilicon layers 32, i.e., the second electrode 92 is in contact with some or all of the doped polysilicon layers 2 other than the doped polysilicon layer 32 closest to the silicon substrate 1, and does not reach the innermost doped polysilicon layer, thereby avoiding direct contact between silver and the silicon substrate.

[0055] In one embodiment, the passivation contact structure includes two doped polysilicon layers, with the second electrode 92 contacting only the doped polysilicon layer 32 that is furthest from the silicon substrate 1 .

[0056] In another embodiment, the passivation contact structure includes three doped polysilicon layers 32, and the second electrode 92 contacts only the outermost doped polysilicon layer 32, or the second electrode 92 contacts only the first and second doped polysilicon layers 32 from the outside to the inside. It should be understood that in this embodiment, the second doping structure 3 is a tunnel passivation contact structure including multiple film layers. The above-mentioned reversal of the doping types of the first doping structure 2 and the second doping structure 3 refers to the reversal of the doping type of the first doping structure 2 and the doping type of the doped polysilicon layer 32 in the tunnel passivation contact structure as the second doping structure 3. For example, in this embodiment, the first doping structure 1 is a P-type diffusion region, and the doped polysilicon layer is an N-type doped polysilicon layer. For example, in other embodiments (for example, the second embodiment below), the first doping structure 1 is an N-type diffusion region, and the doped polysilicon layer is a P-type doped polysilicon layer.

[0057] 9 to 14, the first doping structure 2 is an N-type diffusion region. The main difference between an N-type diffusion region and a P-type diffusion region is that an N-type diffusion region is formed by diffusing an N-type dopant inward from the rear surface of the silicon substrate 1. N-type dopants include, but are not limited to, phosphorus, arsenic, antimony, etc.

[0058] The second doping structure 3 is a P-type doping structure. The difference between the P-type doping structure and the N-type doping structure is only that the doped polysilicon layer 32 is a P-type doped polysilicon layer and the dopant is a P-type dopant.

[0059] In addition, the width of the P-type doped structure is larger than that of the N-type doped structure, and the area of ​​the region where the PN junction is located is larger than the area of ​​the N-N+ region, which is advantageous for the generation, separation, and collection of photocarriers and can improve cell efficiency.

[0060] In one embodiment, the width of the P-type doped structure 2 is 1.5 to 2 times the width of the N-type doped structure.

[0061] 1 to 8 and 12 to 14, the first doping structure 2 is higher than the second doping structure 3 in the direction from the front to the back of the silicon substrate 1. By making the first doping structure 2 higher than the second doping structure 3, the overall surface area of ​​the back surface is increased, widening the light-receiving area, while both the back surface and side surfaces of the first doping structure 2 are exposed to the outside, improving the light-absorbing area of ​​the first doping structure 2 and allowing more carriers to be generated and collected successfully, thereby improving cell efficiency.

[0062] Of course, as shown in Figures 9 to 11, the rear surface area can also be increased by making the second doping structure 3 higher than the first doping structure 2 along the direction from the front to the back of the silicon substrate 1, thereby increasing the rear light-receiving area in a double-sided assembly and improving cell efficiency.

[0063] Preferably, as shown in Figures 1 to 11, the P-type doping structure is higher than the N-type doping structure, and the larger the step, the larger the area of ​​the P-type diffusion region exposed to the outside, which is more advantageous for absorbing light and increases the efficiency of the battery.

[0064] 1 to 8, the first doping structure 2 is a P-type diffusion region, and the second doping structure 3 is an N-type passivation contact structure. The step between the back surface of the N-type doping structure (i.e., the second doping structure 3) and the back surface of the P-type doping structure (i.e., the first doping structure 2) is 0.5 to 1.5 times the diffusion depth of the P-type diffusion region.

[0065] 9 to 11, the first doping structure 2 is an N-type diffusion region, and the second doping structure 3 is a P-type passivation contact structure. The step between the back surface of the N-type doping structure (i.e., the first doping structure 2) and the back surface of the P-type doping structure (i.e., the first doping structure 3) is 0.5 to 1.5 times the thickness of the P-type passivation contact structure.

[0066] The spacer region 4 is located between the first doping structure 2 and the second doping structure 3 and is used to separate the first doping structure 2 and the second doping structure 3, thereby preventing electrical leakage problems caused by contact between the two. The width of the spacer region 4 refers to the width of the gap between the first doping structure 2 and the second doping structure 3. For example, in FIGS. 1 and 9, the width of the spacer region 4 is represented by D.

[0067] In one embodiment, the width of the spacer region 4 is 10 μm to 150 μm. Assuming that leakage current is isolated, the narrower the width of the spacer region 4, the smaller the carrier recombination in this region, resulting in higher cell efficiency. Preferably, the width is 50 μm to 100 μm.

[0068] In the present invention, the spacer region 4 is recessed from the back surface of the silicon substrate 1 toward the front surface, and the recess depth of the position where the second doping structure 2 is located and / or the spacer region 4 is equal to or greater than the diffusion depth of the diffusion region, ensuring that the spacer region 4 completely separates the first doping structure 2 from the second doping structure 3. The recess depth at the position where the second doping structure 2 is located refers to the depth to which the back surface of the silicon substrate is recessed toward the front surface of the silicon substrate at the position where the second doping structure 2 is located. The recess depth of the spacer region 4 refers to the depth to which the back surface of the silicon substrate is recessed toward the front surface of the silicon substrate at the spacer region, i.e., the depth to which the silicon substrate is recessed from the back surface of the spacer region toward the front surface of the spacer region.

[0069] In one embodiment, the recess depth at the location of the second doping structure 2 is smaller than the recess depth of the spacer region 4, completely separating the diffusion region and the silicon substrate 1 of the passivation contact structure in both the extension direction and thickness direction, thereby achieving good isolation effect.

[0070] The distance from the rear surface of the spacer region 4 (the surface of the spacer region 4 facing the front surface of the silicon substrate 1) to the rear surface of the first doping structure 2 is called the depth of the spacer region 4. The depth of the spacer region 4 is 1 μm to 20 μm, preferably 5 μm to 10 μm. Alternatively, the depth of the spacer region 4 preferably exceeds the diffusion depth of the diffusion region, ensuring that the spacer region 4 completely separates the P-type doping structure 2 and the N-type doping structure 3. In one embodiment, the depth of the spacer region 4 is 1 to 1.5 times the diffusion depth of the P-type diffusion region.

[0071] In one embodiment, the distance from the rear surface of the second doping structure 3 to the front surface of the silicon substrate 1 is equal to or less than the distance from the rear surface of the first doping structure 2 to the front surface of the silicon substrate 1. Alternatively, the dimension of the second doping structure 3 in the thickness direction of the silicon substrate 1 is equal to or less than the recess depth of the spacer region 4.

[0072] By designing in this way, the first doping structure 2 and the second doping structure 3 form a step on the back surface of the silicon substrate 1, which increases the surface area of ​​the back surface, i.e., increases the light absorption area, and improves the efficiency of the battery sheet.

[0073] In one embodiment, the distance between the rear surface of the first doping structure 2 and the rear surface of the second doping structure 3 in the thickness direction of the silicon substrate 1 is 1 μm to 10 μm, which not only increases the surface area of ​​the rear surface but also creates a stepped structure, allowing light to be reflected multiple times on the rear surface, which is more advantageous for light absorption. Preferably, the step difference is 4 μm to 10 μm.

[0074] In addition, the surface of the spacer region 4 facing the silicon substrate 1 has a textured structure, which improves light absorption there, helps improve cell efficiency, and simplifies the overall cell manufacturing process. The back surface of the spacer region 4 facing the front of the silicon substrate 1 is flat, which significantly reduces dangling bonds on the surface compared to a textured structure, lowering the probability of carrier recombination there, thereby improving cell efficiency. Furthermore, the flat spacer region 4 is useful for forming a subsequent continuous passivation film layer, achieving a good passivation effect and improving cell efficiency by 0.1 to 0.2% without changing other structures.

[0075] It is important to note that "the surface is flat" means that the dimensions of the tower-shaped base on the surface of the spacer region 4 are 15 μm to 30 μm, or the surface roughness of the spacer region 4 is equivalent to the roughness of a flat silicon wafer, generally not exceeding 10 nm.

[0076] Based on the planar spacer region 4, a continuous passivation film can be formed on its surface, thereby enhancing the passivation effect of the area where the spacer region 4 is located and improving the battery efficiency by 0.1% to 0.2% without changing other structures.

[0077] Based on the above arbitrary structural design, the areas on the back surface of the battery other than the spacer region 4 are all textured, which can enhance light absorption and improve battery efficiency. When the other areas on the back surface, and even the front surface, are all textured, how to keep the surface of the spacer region 4 flat is a technical challenge, which will be explained in the manufacturing method of the present invention below.

[0078] In addition, a passivation layer 5 and an anti-reflection layer 6 are further provided on the back surface of the solar cell 100. For ease of understanding, the passivation layer 5 and the anti-reflection layer 6 are also referred to as the back surface passivation layer 5 and the back surface anti-reflection layer 6 hereinafter. The first electrode 91 penetrates the back surface anti-reflection layer 6 and the back surface passivation layer 5 to contact the gate line region 21, and the second electrode 92 penetrates the back surface anti-reflection layer 6 and the back surface passivation layer 5 to contact the doped polysilicon layer 32.

[0079] In one embodiment, the back surface passivation layer 5 is preferably an alumina layer, which provides excellent field passivation effect for the first doping structure 2 and excellent interface passivation effect for the second doping structure 3. In the present invention, the thickness of the back surface passivation layer 5 is preferably 3 nm to 6 nm.

[0080] In another embodiment, the rear surface passivation layer 5, particularly the rear surface passivation layer 5 in the spacer region 4, includes a first charge film layer in contact with the silicon substrate 1 and a second charge film layer located on the side of the first charge film layer away from the silicon substrate 1. The charge type of the first charge film layer matches the charge type of the silicon substrate 1, and the charge type of the first charge film layer is opposite to that of the second charge film layer.

[0081] Floating bonds exist on the surface of the silicon substrate 1, and by performing interface passivation with the first charge film layer of the same charge and field passivation with the second charge film layer of the opposite charge, the passivation effect of the entire passivation film layer can be enhanced.

[0082] In the present invention, the silicon substrate is an N-type silicon wafer, the first charge film layer is a negative charge film layer, and the second charge film layer is a positive charge film layer. As can be understood by those skilled in the art, if the silicon substrate is a P-type silicon wafer, the first charge film layer is a positive charge film layer, and the second charge film layer is a negative charge film layer.

[0083] In one embodiment, the negative charge layer includes a silicon oxide layer and an alumina layer on the side of the silicon oxide layer facing away from the silicon substrate. Because the silicon oxide layer is denser than the alumina layer, the silicon oxide layer is first formed on the surface of the spacer region 4, and then the alumina layer is formed to achieve optimal passivation.

[0084] The silicon oxide film layer has a thickness of 0.5 nm to 2 nm (for example, 1 nm), and the alumina film layer has a thickness of 1 nm to 20 nm.

[0085] In one embodiment, the positive charge film layer is selected from at least one of a SiNx film layer and a SiOxNy film layer.

[0086] The thickness of the positively charged film layer is 10 nm to 100 nm.

[0087] The thickness of the first charge film layer is smaller than that of the second charge film layer. The first charge film layer only needs to achieve interface passivation, and if it is too thick, it will affect the formation of field passivation of the second charge film layer. Furthermore, the second charge film layer needs to overcome the influence of the intermediate first charge film layer to form a field passivation effect, so it needs to be set to a relatively large thickness.

[0088] In one embodiment, the thickness of the first charge film layer is 0.5 nm to 25 nm, preferably 2 nm to 10 nm, and the thickness of the second charge film layer is 10 nm to 100 nm, preferably 20 nm to 50 nm.

[0089] The surface of the spacer region 4 is flat, and in combination with the passivation film layer, the passivation effect of the region can be optimized to an optimum state.

[0090] The back surface antireflection layer 6 is selected from one or more laminated films of silicon nitride, silicon oxynitride, and silicon oxide, has a thickness of 60 nm to 130 nm, reduces reflectance, and improves light utilization efficiency.

[0091] In one alternative embodiment, the solar cell 100 further comprises a front passivation layer 7 and a front anti-reflection layer 8, which are sequentially disposed on the front surface of the silicon substrate 1, to passivate defects on the front surface. In the present invention, the front passivation layer 7 and the back passivation layer 5 are identical in material and thickness and can be deposited together, and the front anti-reflection layer 8 and the back anti-reflection layer 6 are identical in material and thickness and can be deposited by the same process.

[0092] In the solar cell 100 of the present invention, the first doping structure 2 is a diffusion region formed by dopant diffusion inward from the back surface of the silicon substrate 1, and the second doping structure 3 is located in a region recessed from the back surface of the silicon substrate 1 toward the front surface, and is a tunnel passivation contact structure. This structural design first forms the first doping structure 2 by diffusion into the back surface of the silicon substrate, then removes the diffusion junction in a partial region, and then deposits the tunnel passivation contact structure, which is highly applicable to the process flow of TOPCon batteries and is suitable for promoting industrialization.

[0093] Hereinafter, as shown in Figures 1 to 8, a method for manufacturing a first type of solar cell will be provided, taking as an example the case where the first doping structure 2 is a boron-doped P-type diffusion region and the second doping structure is a phosphorus-doped N-type tunnel passivation contact structure.

[0094] S1, a diffusion region (boron junction) and a BSG layer are formed on the back surface of the silicon substrate 1 by a boron diffusion process.

[0095] S11: First, a boron source is formed over the entire back surface of the silicon substrate 1. The silicon substrate 1 is fixed to a quartz boat and transferred into a tube furnace. A boron source and oxygen gas are then introduced to deposit a layer of the boron source (also called a passing source) on the back surface of the silicon substrate 1. Here, the boron source is boron trichloride (BCl3), the flow rate of boron trichloride is 90 sccm to 150 sccm, the flow rate of oxygen gas reacting with BCl3 is 100 sccm to 500 sccm, and the flow rate of oxygen gas for generating an oxide layer is 1 slm to 10 slm; alternatively, the boron source is boron tribromide (BBr3), the flow rate of boron trichloride is 90 sccm to 150 sccm, the flow rate of oxygen gas reacting with BBr3 is 100 sccm to 500 sccm, and the flow rate of oxygen gas for generating an oxide layer is 1 slm to 10 slm.

[0096] S12: A highly doped gate line region 21 is formed in the gate line region of the first doping structure 2 by laser scanning. Laser parameters: laser gas output 120 W, set at 63% power, laser frequency 100 kHz, scanning speed 25 m / s.

[0097] S13, and further diffuses in the non-gate line region.

[0098] In one alternative embodiment, the heavily doped silicon substrate 1 is placed in a tube furnace, and oxygen gas is introduced into the tube furnace at a temperature of 950°C to 1000°C with an oxygen gas flow rate of 10 slm to 15 slm. At high temperature, boron in the non-gate line regions diffuses inward to form non-gate line regions 22, and a BSG layer is formed over the entire surface.

[0099] In one alternative embodiment, the square resistivity of the boron source deposition is 120 ohm / sq to 170 ohm / sq, and the doping concentration of the gate line region 21 after laser scanning is 5E18 cm -3 ~1E20cm -3 and the corner resistance is 80 ohm / sq to 130 ohm / sq, and after high temperature oxidation, the corner resistance of the non-gate line region 22 is 200 ohm / sq to 400 ohm / sq.

[0100] In the present invention, the boron diffusion depth (boron junction depth) is 0.5 μm to 1.0 μm, and by controlling the boron diffusion depth, the present invention optimizes the passivation effect of the P region and metal contact. The boron diffusion depth is designed to be 0.5 μm to 1.0 μm, and the dark saturation current density J0 of the diffusion region is set to 2 fA / cm. 2 ~4fA / cm 2 The dark saturation current density J0 can be set to 1 fA / cm 2 ~3fA / cm 2 This allows for a balanced passivation effect with the second doping structure 3 that provides a boron diffusion depth of 1 μm. If the boron diffusion depth exceeds 1 μm, Auger recombination increases, reducing the lifespan of the silicon wafer. If the boron diffusion depth is less than 0.5 μm, Ag may penetrate the PN junction region during the fabrication of the metal electrode. The present invention employs a boron junction depth of 0.5 μm to 1.0 μm, which provides advantages in the bifaciality and efficiency of the battery.

[0101] S2, removing the BSG layer and boron junction outside the first doping structure 2; S21, remove the BSG layer except for the first doping structure 2 by laser grooving.

[0102] The laser grooving referred to in the present invention can alternatively adopt one of the following methods. In one embodiment, laser grooving is performed with an ultraviolet picosecond laser, with a spot power of 3W-20W, a spot diameter of 100μm-150μm, a frequency of 500kHz-600kHz, and a scanning speed of 40m / s-80m / s. In another embodiment, laser grooving is performed with a green picosecond laser, with a spot power of 5W-50W, a spot diameter of 100μm-500μm, a frequency of 500kHz-600kHz, and a scanning speed of 40m / s-80m / s.

[0103] S22, removing the boron junction outside the first doping structure 2;

[0104] First, an HF solution is used to remove the BSG layer on the front and side of the silicon substrate 1. In an alternative embodiment, this step is completed in a chain machine.

[0105] In the present invention, when removing a mask layer such as a BSG layer, a PSG layer, or a silicon oxide layer formed by plating or deposition, an HF solution having a volume concentration of 5% to 20% or 0.01 mol / L to 0.03 mol / L can be used, and no further explanation will be given below.

[0106] A polishing process is then performed to remove the boron junctions outside the first doping structure 2 and also remove the boron junctions that have bypassed the front side, leaving both the boron junctions of the first doping structure 2 and the BSG layer. In an alternative embodiment, this step is completed in a tank-type tool.

[0107] This step removes the boron junction outside the first doping structure 2, and also removes the BSG layers on the front and side, and the boron junction that has bypassed and diffused to the front side, making the process simple and laying a good foundation for the fabrication of subsequent processes.

[0108] S3, rear surface tunnel passivation contact structure and mask layer: A tunnel layer 31 and a phosphorus-doped amorphous silicon layer are grown on the entire rear surface by PECVD in-situ doping, and a mask layer is further grown on the outermost surface. Here, by alternately depositing multiple tunnel layers 31 and multiple phosphorus-doped amorphous silicon layers, a tunnel passivation contact structure including multiple tunnel layers 31 and multiple doped polysilicon layers 32 can be formed.

[0109] In one embodiment, the tunnel layer 31 is preferably made of SiOx and has a thickness of 1.4 nm to 2.3 nm.

[0110] In another embodiment, the tunnel layer 31 is made of SiC, is denser, and preferably has a thickness of 1 nm to 1.8 nm.

[0111] The thickness of the N-poly layer is preferably 80 nm to 120 nm.

[0112] The mask layer is preferably a silicon oxide layer, and the thickness is controlled within the range of 10 nm to 50 nm.

[0113] S4: A high-temperature annealing furnace is used, and the annealing temperature can be matched according to the tunneling conditions. The thicker the tunnel layer 31, the higher the annealing temperature. In one alternative embodiment, the annealing temperature is 850°C to 950°C, which is well matched with the typical tunnel layer 31. The doping concentration in the n-poly region in the electrochemical doping concentration test (ECV test) is 1E19 cm -3 ~1E21cm -3 It can be guaranteed that

[0114] In this process, a BSG layer is left in the tunnel layer 31 of the first doping structure 2 to inhibit the internal diffusion of phosphorus, and outside the first doping structure 2, phosphorus penetrates the tunnel layer 31 and diffuses into the silicon substrate 1 to form a phosphorus-doped region.

[0115] The annealing temperature is related to the density and thickness of the tunnel layer 31. In one alternative embodiment, if the tunnel layer 31 is silicon oxide, the thickness is 1.4 nm to 2.3 nm and the annealing temperature is 880°C to 950°C. If the tunnel layer 31 is a silicon carbide layer, the thickness is 1 nm to 1.8 nm and the annealing temperature is 850°C to 900°C, ensuring that the phosphorus outside the first doping structure 2 diffuses inward into the silicon substrate 1.

[0116] In step S5, the mask layer, the doped polysilicon layer 32 and the tunnel layer 31 outside the second doping structure 3 spaced apart from the first doping structure 2 are removed. S51: Remove the mask layer outside the second doping structure 3 by a laser process to expose the underlying doped polysilicon layer 32. Laser parameters: laser power 50W-120W, preferably ultraviolet picosecond or green picosecond laser, with less damage being more advantageous for film opening.

[0117] S52: Remove the mask layer that has bypassed the front side with an HF solution, preferably using a chain machine.

[0118] S53: Re-texturing: The doped polysilicon layer 32 and the tunnel layer 31 outside the second doping structure 3 on the back surface (the laser grooved area) are removed using an alkaline solution, and at the same time, the front surface of the silicon substrate 1 is etched with alkaline solution to form a textured tower-shaped base on the exposed silicon substrate 1, and finally, the silicon substrate 1 is washed.

[0119] Preferably, a texturing alkaline solution is added in a tank-type device to remove the P-type doped polysilicon layer that has diffused around to the front side and the P-type doped polysilicon layer in the backside laser grooved region, thereby forming a textured structure in the front side and backside laser grooved region of the silicon substrate 1.

[0120] The texturing alkaline solution used in the present invention is selected from texturing alkaline solutions commonly used in this field, and may be selected from 0.2 mol / L to 0.5 mol / L NaOH solution or 0.2 mol / L to 0.5 mol / L KOH solution.

[0121] In step S5, the film layer where the second doping structure 3 and the spacer region 4 are located may be patterned and removed, so that the recess depths where the second doping structure 3 and the spacer region 4 are located are different.

[0122] Compared with the related art, which "first forms a textured structure on the surface of the silicon substrate 1, and then produces other film layers," in the present invention, after the production of the key structures and film layers, such as the first doping structure 2 and the second doping structure 3, is completed, a pyramid structure is further formed on the front surface, eliminating the need to polish the back surface before boron diffusion. Meanwhile, step S53 removes the back-doped polysilicon layer 32 and the tunnel layer 31, while simultaneously forming a pyramid structure on the front surface, achieving multi-faceted effects. Furthermore, if the front surface is flat, it is advantageous for the deposition and cleaning of film layers in each of the above steps.

[0123] In addition, the boron junction, the tunnel layer 31, and the doped polysilicon layer 32 between the first doping structure 2 and the second doping structure 3 are all removed to form a spacer region 4, which prevents leakage current from occurring between the first doping structure 2 and the second doping structure 3.

[0124] In the present invention, the width, depth, etc. of the spacer region 4 are as described above, and will not be further described here.

[0125] S6, forming a passivation layer on both sides, which is an optional process step.

[0126] In one embodiment, the backside passivation layer and the frontside passivation layer are alumina layers. The alumina is deposited on the front side by an ALD process, preferably with a thickness of 3 nm to 6 nm. The Al2O3 provides excellent field passivation for the first doping structure 2 and excellent interface passivation for the second doping structure 3.

[0127] In another embodiment, the back passivation layer and the front passivation layer include a first charge film layer and a second charge film layer on the side of the first charge film layer away from the silicon substrate, and the materials and thicknesses of the first charge film layer and the second charge film layer are as described above and will not be further described here.

[0128] The first charge layer includes a silicon oxide layer and an alumina layer on the side of the silicon oxide layer facing away from the silicon substrate, and the deposition method thereof includes, but is not limited to, the following:

[0129] In one embodiment, deposition by ALD process is employed. A silicon substrate is placed in an ALD apparatus. Water is first introduced into the ALD apparatus with a pulse time of 5 to 10 seconds and a treatment cycle of 3 to 15 times to form a silicon oxide layer with a thickness of 0.5 to 2 nm. Next, an alumina membrane layer with a thickness of 1 to 20 nm is deposited by conventional processes.

[0130] In another embodiment, a PECVD method is used to deposit a layer of ultra-thin silicon oxide on the front surface, at a temperature of 200°C to 500°C, preferably 350°C to 450°C.

[0131] In another embodiment, a single silicon oxide layer is formed on the surface of a silicon substrate by a high temperature method in an oxygen gas atmosphere or an air atmosphere, the temperature being 300°C to 900°C, preferably 500°C to 600°C.

[0132] The second charge-carrying layer may include a SiNx film layer or a SiOxNy film layer, and may be formed by depositing the second charge-carrying layer using a PECVD method.

[0133] The front passivation layer also includes a silicon oxide layer, an alumina layer, a SiNx layer or a SiOxNy layer. The increased silicon oxide layer not only improves the front passivation effect, but also improves the UV resistance of the battery sheet, preventing the passivation effect from being damaged under sunlight irradiation, and improving the overall performance of the battery.

[0134] S7: Forming an anti-reflection layer on both sides (this is an optional process step). A laminated film made of one or more of silicon nitride, silicon oxynitride, and silicon oxide is formed by chemical vapor deposition. The thickness of the anti-reflection layer is 60nm to 130nm.

[0135] S8, electrode fabrication: fabricating electrodes by screen printing + sintering, including fabricating the rear main gate electrode, and fabricating the rear first doping structure 2 and second doping structure 3 sub-gate electrodes.

[0136] S9: Laser-enhanced contact optimization (LECO) technology is used to perform laser sintering on the first electrode 91 and the second electrode 92, improving the contact between the silver and silicon in the electrodes, thereby improving battery efficiency by 0.2% to 0.3% or more. The electrode paste can also be changed to a silver-coated copper paste with a lower silver content, thereby saving costs.

[0137] In the present invention, the laser wavelength used in the LECO technology is 1064 nm or 532 nm, and the laser width is 100 microns or 1 mm to 2 mm.

[0138] The present invention further provides a method for manufacturing a second type of solar cell, to form a solar cell as shown in Figures 9 to 11, in which the first doping structure 2 is an N-type diffusion region formed by phosphorus diffusion, and the second doping structure is a boron-doped P-type tunnel passivation contact structure, and in the direction from the front side to the back side of the silicon substrate, the P-type tunnel passivation contact structure exceeds the N-type diffusion region.

[0139] The method for manufacturing the second type of solar cell includes the following steps.

[0140] S1, Silicon wafer processing: Select an N-type silicon wafer with a resistivity of 0.3 Ω·cm to 7 Ω·cm and polish or texture it.

[0141] Polishing: Alkaline polishing using KOH or NaOH and additives, or first texture the surface of the silicon substrate 1 and then polish it. After the polishing process, the surfaces of the first doping structure 2 and the second doping structure 3 are flat, and the tower-shaped base is 15 μm to 30 μm.

[0142] Texturing: The surface of the silicon substrate 1 is textured, so that the surfaces of the first doping structure 2 and the second doping structure 3 are textured surfaces, and the tower-shaped base is 3 μm to 15 μm.

[0143] S2. A P-type tunnel passivation contact structure and a BSG layer are fabricated on the entire back surface of the silicon substrate 1. The tunnel layer and the intrinsic silicon layer (i-Poly) are alternately deposited at least once. BCl3 or BBr3 is used as the diffusion source, and the diffusion temperature is 850°C to 960°C. Boron is diffused into the i-Poly to form a P-type doped polysilicon layer, and a BSG layer is formed on the surface.

[0144] S21, depositing a tunnel layer / i-Poly by LPCVD process: first, growing one layer of tunnel layer 31 on the back surface with a thickness of 1.2-2 nm, followed by growing one layer of i-poly layer with a thickness of 200-400 nm.

[0145] "Alternating at least once" means that 0, 1, 2....n tunnel layers can be grown between the i-poly layers. Specifically, in the case of n alternating times, (n-1) tunnel layers can be grown between the i-poly layers.

[0146] S22, boron doping: by tube diffusion method, using BCl3 or BBr3 as diffusion source, temperature 850℃~960℃, angular resistivity 50ohm / sq~500ohm / sq, surface concentration 1E18cm -3 ~1E20cm -3 The thickness of the BSG layer is controlled to be 30 nm to 200 nm.

[0147] S3, remove the BSG layer and the P-type tunnel passivation contact structure outside the P region.

[0148] S31: Remove the BSG layer. The BSG layer outside the P region on the backside of the silicon substrate is removed by laser grooving, and the edge of the silicon substrate is the laser grooved region. The BSG layer that has bypassed and diffused to the front and sides is removed using a hydrofluoric acid (HF) solution. Preferably, the HF solution is added to a chain machine to remove the BSG layer on the front and sides of the silicon wafer.

[0149] S32, removing the P-type tunnel passivation contact structure.

[0150] The P-type doped polysilicon layer in the laser grooved region on the backside and the P-type doped polysilicon layer that has been diffused around the front and sides are removed with a texturing alkaline solution, while at the same time forming a textured tower-shaped base in these regions.

[0151] The polishing alkali solution may be used to remove the P-type doped polysilicon layer in the backside laser grooved region and the P-type doped polysilicon layer that has been diffused around the front and sides, while forming a flat tower base in these regions.

[0152] The polishing alkaline solution of the present invention is selected from polishing alkaline solutions commonly used in this field, and may be 0.2 mol / L to 0.5 mol / L sodium hydroxide (NaOH), 0.2 mol / L to 0.5 mol / L potassium hydroxide (KOH), or 0.4 mol / L to 0.8 mol / L tetramethylammonium hydroxide (TMAH), and the polishing time is 100 s to 300 s.

[0153] S4 is diffused into an area outside the P region to form an N-type diffusion area and a PSG layer.

[0154] A high-temperature diffusion furnace was used to perform phosphorus diffusion in the area outside the P region to form an N-type diffusion region and a PSG layer. The temperature was 850°C to 950°C, and the doping concentration of the N-type diffusion region for the ECV test was 1E15 cm. -3 ~1E22cm -3 Keep it at 1E20cm -3 ~1E21cm -3In this step, a double sided diffusion may be performed, thus forming an n+ field on the front side and an N+ field on the backside N region.

[0155] S5: The PSG layer and the N-type diffusion region outside the N region are removed.

[0156] S51: Remove the PSG layer. The PSG layer outside the N region (where the spacer region 4 is located) is removed by laser grooving, and the edge of the silicon substrate 1 is the laser grooving region.

[0157] In the present invention, by setting the edge of the silicon substrate 1 as the laser grooving area, a spacer area 4 can be formed at the edge of the silicon substrate 1, thereby insulating the back surface, side surfaces, and front surface. In other embodiments, all laser grooving steps can either groove the edge of the silicon substrate 1 or not, thereby achieving insulation of the back surface, side surfaces, and front surface.

[0158] S52, remove the N-type diffusion region in the laser grooving area.

[0159] An abrasive alkali solution is used to remove the N-type diffusion region in the laser grooved area, forming a planar tower base spacer region 4 between the P and N regions.

[0160] Specifically, in the tank-type device, a polishing alkaline solution is added to perform the polishing process, removing the N-type diffusion region in the backside laser grooved region and forming a flat surface in the spacer region 4. The surface of the spacer region 4 facing the front side of the silicon substrate 1 is flat, and the dimension of the flat tower base is 15 μm to 30 μm, or the roughness of the flat surface is 10 nm or less.

[0161] In this step, the N regions on the front and back sides are protected by a PSG layer mask, and the P regions on the back side are protected by a BSG layer mask, so the corresponding poly layers are not destroyed.

[0162] Alternatively, the polishing alkali solution is replaced with a texturing alkali solution to remove the N-type diffusion region in the laser grooving region and form a planar tower-shaped base spacer region 4 between the P and N regions.

[0163] In addition, before polishing or texturing, an HF solution may be added using a chain machine to remove the PSG layer on the side, so that the N-type diffusion region that has diffused to the side is simultaneously removed during polishing or texturing.

[0164] Finally, the BSG layer in the P region and the PSG layer in the N region are removed by washing with an HF solution.

[0165] S8: Form a passivation layer on both sides (see S6 in the first solar cell manufacturing method).

[0166] S9: Form an anti-reflection layer on both sides (see S7 in the manufacturing method of the first type solar cell).

[0167] S10, electrode fabrication: fabricating electrodes by screen printing + sintering method, including fabricating the rear main gate electrode, fabricating the rear P-type tunnel passivation contact structure and the sub-gate electrode of N-type doping structure 3.

[0168] S11: Laser sinter the first electrode 91 and the second electrode 92 using LECO technology (see S9 in the manufacturing method of the first type solar cell).

[0169] The present invention further provides a third type of solar cell manufacturing method, to form a solar cell as shown in Figures 12 to 14, in which the first doping structure 2 is an N-type diffusion region formed by phosphorus diffusion, and the second doping structure is a boron-doped P-type tunnel passivation contact structure, and the N-type diffusion region exceeds the P-type tunnel passivation contact structure in the direction from the front side to the back side of the silicon substrate.

[0170] The method for manufacturing the third type of solar cell includes the following steps.

[0171] S1, Polishing: Select an N-type silicon wafer and polish it with KOH or NaOH and additives, or first texture and polish the surface of the silicon substrate 1, so that the tower base in the area where the P-type tunnel passivation contact structure is located is 3 μm to 15 μm.

[0172] S2: Phosphorus diffusion is performed to form an N-type diffusion region (phosphorus junction) and a PSG layer.

[0173] A high-temperature diffusion furnace was used to diffuse phosphorus over the entire back surface to form an N-type diffusion region and a PSG layer. The diffusion temperature was 850°C to 950°C, and the doping concentration of the N-type diffusion region during ECV testing was 1E15cm. -3 ~1E22cm -3 Ensure that the distance is 1E20cm. -3 ~1E21cm -3 is.

[0174] In one embodiment, a phosphorus diffusion is performed on the front side of the silicon substrate 1 at the same time as the backside phosphorus diffusion is performed, forming an N+ field on the front side of the silicon substrate 1.

[0175] S3: The PSG layer and the phosphorus junction outside the first doping structure 2 (N region) on the rear surface are removed.

[0176] S31, laser groove the outside of the first doping structure 2 to remove the PSG layer outside the first doping structure 2;

[0177] S32, removing the phosphorus junction outside the first doping structure 2; The PSG layer on the side surface of the silicon substrate 1 is removed, preferably by an etching process in which an HF solution is applied to the side surface or by a laser process.

[0178] Then, a polishing process is performed to remove the phosphorus junction outside the first doping structure 2 on the back surface, and at the same time, remove the phosphorus junction that has bypassed the side surface, leaving the phosphorus diffusion layer on the front surface, the phosphorus junction of the first doping structure 2, and the BSG layer. This step is preferably completed in a tank-type apparatus.

[0179] S4, fabricate a P-type tunnel passivation contact structure.

[0180] S41: Form the tunnel layer / i-Poly by LPCVD process. First, grow one layer of tunnel layer 31 on the back surface with a thickness of 1.2-2nm. Next, grow one layer of i-poly layer with a thickness of 200-400nm. 0, 1, 2...n layers of tunnel layer 31 can be grown in between the poly layers.

[0181] S42. Boron doping: By using the tube diffusion method, BCl3 or BBr3 is used as the diffusion source, and the temperature is controlled at 850°C to 1100°C, preferably 850°C to 960°C. Boron is diffused into the intrinsic layer to form a P-type doped polysilicon layer, and a BSG layer is formed on the surface.

[0182] The square resistivity of the P-type doped polysilicon layer is 50 ohm / sq~500 ohm / sq, and the surface concentration is 1E18 cm -3 ~1E20cm -3 The thickness of the BSG layer is 30 to 200 nm.

[0183] S5, removing the BSG layer outside the second doping structure 3 and the P-type passivation contact structure.

[0184] S51, remove the BSG layer outside the second doping structure 3 by laser grooving to expose the doped polysilicon layer 32 underneath.

[0185] S52, a chain machine, and an HF solution are used to remove the BSG layer on the front surface and the side of the silicon wafer.

[0186] S53, removing the P-type passivation contact structure.

[0187] In one embodiment, a textured alkaline solution is added in a tank-type device to remove the doped polysilicon layer 32 that has diffused to the front side and the doped polysilicon layer 32 in the backside laser grooved region, and at the same time, alkaline etching is performed on the front side of the silicon substrate 1 to form a pyramidal structure on the exposed silicon substrate 1, and the surface of the spacer region 4 also has a textured structure.

[0188] In another embodiment, a polishing alkaline solution is first used to remove the P-type doped polysilicon layer in the laser grooved area, front surface, and side surfaces to form a flat tower-shaped substrate. Next, a back surface mask layer is formed on the back surface, which is a silicon oxide layer with a thickness of 30 nm to 100 nm. Under the protection of the back surface mask layer, the solution is exchanged for a texturing alkaline solution to form a textured tower-shaped substrate on the front surface of the silicon substrate 1, improving the optical limiting property of the front surface. Finally, a hydrofluoric acid solution is used to remove the back surface mask layer on the back surface.

[0189] S6: Form a passivation layer on both sides (see S6 in the manufacturing method of the first type solar cell).

[0190] S7: Forming an anti-reflection layer on both sides (see S7 in the manufacturing method of the first type solar cell).

[0191] S8, electrode manufacturing: Electrode manufacturing by screen printing + sintering method, including rear main gate electrode manufacturing, rear P-type tunnel passivation contact structure and N-type doping structure 3 sub-gate electrode manufacturing.

[0192] In step S9, the first electrode 91 and the second electrode 92 are laser sintered using LECO technology. (See step S9 in the manufacturing method for the first type of solar cell.) As described above, the solar cell 100 of the present invention has both the first electrode 91 and the second electrode 92 on the back surface, which eliminates the shielding of the metal electrode on the front surface, resulting in a large light-receiving area, high light conversion efficiency, and improved cell efficiency. By providing an SE structure in the first doping structure 2, the open-circuit voltage and short-circuit current of the cell are improved, and by providing a passivation contact structure in the second doping structure 3, the surface is passivated, improving the short-circuit current and overall cell efficiency.

[0193] It should be understood that although the present specification will be described according to embodiments, each embodiment does not include only independent technical means, and such description in the specification is for the purpose of clarity only, and those skilled in the art should consider the specification as a whole, and the technical means in each embodiment can be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0194] The above detailed description is merely a specific description of the feasible embodiments of the present invention, and does not limit the protection scope of the present invention. Any equivalent embodiments or modifications that do not deviate from the technical spirit of the present invention should be included in the protection scope of the present invention. Cross-reference to related applications

[0195] The present invention is proposed based on the following patent applications, application number 202410917310.3, filed on July 10, 2024; application number 202411097317.1, filed on August 9, 2024; application number 202411095535.1, filed on August 9, 2024; and application number 202411209958.1, filed on August 2, 2024. The application number is 202411205043.3, filed on August 29, 2024; the application number is 202411204726.7, filed on August 29, 2024; and the application number is 202411204287.X, filed on August 29, 2024, and the priority of these Chinese patent applications is claimed, the entire contents of which are incorporated herein by reference.

Claims

1. A solar cell, a silicon substrate having a front surface and a back surface facing each other, the back surface of the silicon substrate being partitioned into a first region, a second region, and a spacer region between the first region and the second region; a first doping structure provided in the first region, the first doping structure being a diffusion region formed by diffusing a dopant from the rear surface of the silicon substrate toward the interior of the silicon substrate; a second doping structure disposed in the second region, the second doping structure being a tunnel passivation contact structure having an opposite doping type to that of the diffusion region; a first electrode provided on a back surface of the first doping structure; a second electrode provided on a back surface of the second doping structure.

2. a back surface of the silicon substrate in the second region is recessed toward a front surface of the silicon substrate relative to a back surface of the silicon substrate in the first region, and a back surface of the silicon substrate in the spacer region is recessed toward a front surface of the silicon substrate relative to a back surface of the silicon substrate in the first region, 2. The solar cell according to claim 1, wherein the depth of the recess of the back surface of the silicon substrate in the second region toward the front surface of the silicon substrate and / or the depth of the recess of the back surface of the silicon substrate in the spacer region toward the front surface of the silicon substrate is equal to or greater than the diffusion depth of the diffusion region.

3. the width of the spacer region is between 10 μm and 150 μm; and / or 2. The solar cell according to claim 1, wherein the distance from the rear surface of the spacer region of the silicon substrate to the rear surface of the first doping structure is 1 μm to 20 μm.

4. a distance from the back surface of the second doping structure to the front surface of the silicon substrate is equal to or less than a distance from the back surface of the first doping structure to the front surface of the silicon substrate; or The dimension of the second doping structure in the thickness direction of the silicon substrate is equal to or less than the recess depth of the spacer region, or 2. The solar cell according to claim 1, wherein the distance between the rear surface of the first doping structure and the rear surface of the second doping structure in the thickness direction of the silicon substrate is 1 μm to 10 μm.

5. 2. The solar cell of claim 1, wherein the first doping structure includes a gate line region and a non-gate line region, the doping concentration of the gate line region is greater than the doping concentration of the non-gate line region, and the first electrode is in contact with the gate line region, and preferably, the gate line region has a square resistance of 80 ohm / sq to 130 ohm / sq, and the non-gate line region has a square resistance of 200 ohm / sq to 400 ohm / sq.

6. The tunnel passivation contact structure comprises: A tunnel layer; 2. The solar cell according to claim 1, further comprising: a doped polysilicon layer provided on a side of said tunnel layer remote from said silicon substrate, said second electrode being in contact with said doped polysilicon layer.

7. the number of the tunnel layers and the number of the doped polysilicon layers are both n, where n≧2, and one doped polysilicon layer of the n doped polysilicon layers is provided on a side of each tunnel layer of the n tunnel layers that is away from the silicon substrate; The solar cell according to claim 6, wherein the second electrode is in contact with at least one of the n-layer doped polysilicon layers, the second to n-layer doped polysilicon layers being in contact with the n-layer doped polysilicon layers in a direction from the front surface to the back surface of the silicon substrate.

8. the tunnel passivation contact structure includes a tunnel layer and a doped polysilicon layer disposed on a side of the tunnel layer remote from the silicon substrate; the first doping structure is a P-type diffusion region and the doped polysilicon layer is an N-type doped polysilicon layer; or 8. The solar cell according to claim 1, wherein the first doping structure is an N-type diffusion region, and the doped polysilicon layer is a P-type doped polysilicon layer.

9. 2. The solar cell according to claim 1, wherein the first doping structure is higher than the second doping structure along a direction from the front surface to the back surface of the silicon substrate, and preferably, the step between the back surface of the first doping structure and the back surface of the second doping structure is 0.5 to 1.5 times the diffusion depth of the diffusion region.

10. 2. The solar cell according to claim 1, wherein the dimension of the rear surface of the silicon substrate in the spacer region is 15 μm to 30 μm, or the roughness of the rear surface of the silicon substrate in the spacer region is 10 nm or less.

11. The solar cell further includes a passivation film layer, and the passivation film layer in the spacer region includes a first charge film layer in contact with the silicon substrate and a second charge film layer provided on a side of the first charge film layer away from the silicon substrate; 2. The solar cell according to claim 1, wherein the charge type of the first charge film layer is similar to the charge type of the silicon substrate, and the charge type of the first charge film layer is opposite to the charge type of the second charge film layer.

12. The solar cell of claim 11 , wherein the thickness of the first charge film layer is less than the thickness of the second charge film layer.

13. the silicon substrate is N-type silicon, the first charged film layer is a negatively charged film layer, and the second charged film layer is a positively charged film layer; or 12. The solar cell of claim 11, wherein the silicon substrate is P-type silicon, the first charged film layer is a positively charged film layer, and the second charged film layer is a negatively charged film layer.

14. The negatively charged film layer includes a silicon oxide film layer in contact with the silicon substrate and an alumina film layer disposed on the side of the silicon oxide film layer away from the silicon substrate; and / or 14. The solar cell according to claim 13, wherein the positively charged film layer is selected from at least one of a SiNx film layer and a SiOxNy film layer.

15. the silicon oxide film layer has a thickness of 0.5 nm to 2 nm, and the alumina film layer has a thickness of 1 nm to 20 nm; and / or 15. The solar cell according to claim 14, wherein the thickness of the positively charged film layer is 10 nm to 100 nm.

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