Structure for reducing electron concentration and process for reducing electron concentration

Abstract

There is a need to address high gate-drain capacitance, high gate-source capacitance, and / or other capacitance induced by high electron concentration around the gate.SOLUTION: The device includes a substrate, a buffer layer on the substrate, a barrier layer on the buffer layer, a source electrically coupled to the barrier layer, a gate electrically coupled to the barrier layer, and a drain electrically coupled to the barrier layer. The device further includes an electron concentration reduction structure disposed in at least one of the following manners: in the barrier layer and on the barrier layer. The electron concentration reduction structure is configured to perform at least one of the following: reduce electron concentration around the gate, reduce electron concentration around an edge of the gate, reduce electron concentration, increase power gain, increase efficiency, decouple the gate from the drain, decouple the gate from the source, and reduce capacitance.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a transistor having a structure for reducing gate-adjacent electron concentration to increase power gain and efficiency. The present disclosure also relates to a process for reducing gate-adjacent electron concentration to increase power gain and efficiency in a transistor. [Background technology]

[0002] Because the material properties of III-nitrides, such as gallium nitride (GaN) and its alloys, enable the achievement of high voltages, high currents, and high RF gain and linearity for RF applications, III-nitride-based high-electron mobility transistors (HEMTs) are highly promising candidates for high-power amplifiers, radio frequency (RF) applications, and also for low-frequency, high-power switching applications. A typical III-nitride HEMT comprises a substrate, a III-nitride (e.g., GaN) buffer or channel layer formed on the substrate, and a higher-bandgap III-nitride (e.g., AlGaN) formed on the buffer or channel layer. Respective source, drain, and gate contacts are electrically coupled to the barrier layer. HEMTs rely on a two-dimensional electron gas (2DEG) formed at the interface between the higher-bandgap barrier layer and the lower-bandgap buffer or channel layer, where the lower-bandgap material has a higher electron affinity. The 2DEG is an accumulation layer within a lower bandgap material and can contain high electron concentrations and high electron mobility.

[0003] HEMTs fabricated in the III-nitride material system have the potential to generate large amounts of RF power due to a combination of material properties including high breakdown field, wide bandgap, large conduction band offset, and / or high saturated electron drift velocity. However, III-nitride HEMTs can be limited by high gate-drain capacitance, high gate-source capacitance, and / or other capacitances induced by high electron concentration around the gate.

[0004] Thus, there is a need to address the high gate-drain capacitance, high gate-source capacitance, and / or other capacitances induced by the high electron concentration around the gate. Summary of the Invention

[0005] One general aspect includes a device including a substrate. The device also includes a buffer layer on the substrate. The device also includes a barrier layer on the buffer layer. The device also includes a source electrically coupled to the barrier layer. The device also includes a gate electrically coupled to the barrier layer. The device also includes a drain electrically coupled to the barrier layer and an electron concentration reduction structure disposed in at least one of the following manners: within and on the barrier layer, the electron concentration reduction structure configured to do at least one of the following: reduce electron concentration around the gate, reduce electron concentration around an edge of the gate, reduce electron concentration, such as between the gate and drain and / or between the gate and source, increase power gain, increase efficiency, decouple the gate from the drain, decouple the gate from the source, and reduce capacitance, such as capacitance between the gate and drain and / or between the gate and source.

[0006] One general aspect includes a process for forming a device including providing a substrate. The process also includes disposing a buffer layer on the substrate. The process also includes disposing a barrier layer on the buffer layer. The process also includes electrically coupling a source to the barrier layer. The process also includes electrically coupling a gate to the barrier layer. The process also includes electrically coupling a drain to the barrier layer and forming an electron concentration reduction structure in and / or on the barrier layer, the electron concentration reduction structure configured to at least one of: reduce electron concentration around the gate, reduce electron concentration around an edge of the gate, reduce electron concentration, such as between the gate and drain and / or between the gate and source, increase power gain, increase efficiency, decouple the gate from the drain, decouple the gate from the source, and reduce capacitance, such as capacitance between the gate and drain and / or between the gate and source.

[0007]

[0013] Further features, advantages, and aspects of the present disclosure will be described or may become apparent from consideration of the following detailed description, drawings, and claims. Moreover, it is to be understood that both the foregoing summary of the present disclosure and the following detailed description are exemplary and intended to provide further explanation without limiting the scope of the present disclosure as claimed.

[0008] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate aspects of the disclosure and, together with the detailed description, serve to explain the principles of the disclosure. No attempt is made to show structural details of the disclosure in more detail than may be necessary for a fundamental understanding of the disclosure and various ways in which it may be practiced. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view of one embodiment of a transistor according to the present disclosure. [Figure 2]1 is a cross-sectional view of one embodiment of a transistor according to the present disclosure. [Figure 3] FIG. 2 is a partial cross-sectional view of another embodiment of a transistor according to the present disclosure. [Figure 4] FIG. 2 is a partial cross-sectional view of another embodiment of a transistor according to the present disclosure. [Figure 5] FIG. 2 is a partial cross-sectional view of another embodiment of a transistor according to the present disclosure. [Figure 6] FIG. 2 is a partial cross-sectional view of another embodiment of a transistor according to the present disclosure. [Figure 7] FIG. 2 is a cross-sectional view of another embodiment of a transistor according to the present disclosure. [Figure 8] FIG. 2 is a cross-sectional view of another embodiment of a transistor according to the present disclosure. [Figure 9] 1A-1D illustrate a process for fabricating a transistor according to the present disclosure. [Figure 10] 1A-1D illustrate a process for fabricating a transistor according to the present disclosure. [Figure 11] FIG. 1 shows a simulated comparison between a prior art transistor and a transistor according to the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] Aspects of the present disclosure, and their various features and advantageous details, will be more fully described with reference to non-limiting embodiments and examples described and / or illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale, and that features of one embodiment may be employed in other embodiments, even if not explicitly stated herein, as those skilled in the art will recognize. Descriptions of well-known components and processing techniques may be omitted so as not to unnecessarily obscure aspects of the present disclosure. The examples used herein are merely intended to facilitate an understanding of how the present disclosure may be implemented and to enable those skilled in the art to implement aspects of the present disclosure. Therefore, the examples and embodiments herein should not be construed as limiting the scope of the present disclosure, which is defined solely by the appended claims and applicable law. Furthermore, it should be noted that like reference numerals represent similar parts throughout the several views of the drawings.

[0011] While the terms first, second, etc. may be used herein to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0012] When an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it is understood that it can be directly on or extending directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Similarly, when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it is understood that it can be directly on or extending directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0013] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It will be understood that these terms, and those described above, are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0014] The terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that the terms "comprises," "comprising," "includes," and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0015] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. Terms used herein should be interpreted to have a meaning that is consistent with their meaning in the context of this specification and related art, and should not be interpreted in an ideal or overly formal sense unless expressly defined herein.

[0016] In addition to the type of structure, the properties of the semiconductor material from which a transistor is formed can also affect its operating parameters. Among the properties that affect the operating parameters of a transistor, capacitance, power gain, and efficiency can have an impact on the operating characteristics of a transistor.

[0017] Capacitance can be the ratio of the change in charge in a system to the corresponding change in the system's potential. Reducing the capacitance between the output and input of a transistor can result in improved performance.

[0018] Power gain may be a measure of the ability to increase the power or amplitude of a signal from an input to an output port by adding energy converted from a power source to the signal. It may be defined as the average ratio of the signal amplitude or power at the output to the amplitude or power at the input. Increasing the power gain of a transistor may result in improved performance. Other known power gain measures and characteristics are also contemplated.

[0019] Efficiency may be defined as the output power dissipated in the load divided by the total power drawn from the source. Increasing the efficiency of a transistor may result in improved performance. Other known efficiency measures and characteristics are also contemplated.

[0020] The present disclosure includes both extrinsic and intrinsic semiconductors. Intrinsic semiconductors are undoped (pure). Extrinsic semiconductors are doped, i.e., an agent has been introduced to change the electron and hole carrier concentrations of the semiconductor at thermal equilibrium. Both p-type and n-type semiconductors are disclosed. P-type has a hole concentration greater than the electron concentration, and n-type has an electron concentration greater than the hole concentration.

[0021] Silicon carbide (SiC) has excellent physical and electronic properties that, in theory, should enable the fabrication of electronic devices capable of operating at higher temperatures, higher powers, and higher frequencies than devices fabricated from silicon (Si) or gallium arsenide (GaAs). Its high electrical breakdown field of approximately 4×E6 V / cm, high saturated electron drift velocity of approximately 2.0×E7 cm / sec, and high thermal conductivity of approximately 4.9 W / cm-°K indicate that it would be suitable for high frequency and high power applications.

[0022] As used herein, the term "Group III nitrides" refers to those semiconductor compounds formed between nitrogen and one or more elements in Group III of the periodic table, typically aluminum (Al), gallium (Ga), and indium (In). The term also refers to binary, ternary, and quaternary compounds such as GaN, AlGaN, and AlInGaN. Group III elements can combine with nitrogen to form binary (e.g., GaN), ternary (e.g., AlGaN), and quaternary (e.g., AlInGaN) compounds. These compounds may have an empirical formula in which one mole of nitrogen is combined with one mole of a total Group III element. Thus, chemical formulas such as AlxGa1-xN, where 1>x>0, are often used to describe these compounds.

[0023] III-nitride HEMTs require improved power gain and efficiency, which are typically limited by high gate-drain capacitance induced by high electron concentration around the gate edge. This disclosure presents a number of different aspects for improving power gain, efficiency, and / or other performance characteristics by selectively reducing the electron concentration around the drain-side gate and / or the drain-side gate edge.

[0024] FIG. 1 shows a cross-sectional view of one embodiment of a transistor according to the present disclosure.

[0025] Specifically, FIG. 1 shows a cross-sectional view of a transistor 100. The transistor 100 may include a substrate layer 102 and a buffer layer 104. The transistor 100 may further include a barrier layer 108 disposed on the buffer layer 104. In one embodiment, the barrier layer 108 may be disposed directly on the buffer layer 104. The transistor 100 may further include a source 110, a gate 114, and a drain 112. In one embodiment, the bandgap of the buffer layer 104 may be less than the bandgap of the barrier layer 108 to form a two-dimensional electron gas (2DEG) at a heterointerface 152 between the buffer layer 104 and the barrier layer 108 when biased at an appropriate level. In one embodiment, the buffer layer 104 is a III-nitride material, such as GaN, and the barrier layer 108 is a III-nitride material, such as AlGaN or AlN. In some embodiments, an intervening layer or region, such as a nucleation layer 136, is present between the substrate layer 102 and the buffer layer 104. In one embodiment, there is an intervening layer or region (not shown) between the buffer layer 104 and the barrier layer 108. In one embodiment, the barrier layer 108 is made of multiple layers, such as an AlN barrier layer on the buffer layer 104 and an AlGaN layer on the AlN barrier layer. In one embodiment, there is an intervening layer or region between the barrier layer 108 and the protective layer 116 and / or the source 110, gate 114, and / or drain 112. In one embodiment, the composition of these layers can be graded, either stepwise or continuously. In one embodiment, the barrier layer 108 can start with a higher percentage of Al near the buffer layer 104, and the percentage of Al can decrease away from the buffer layer 104.

[0026] Additionally, transistor 100 may include electron concentration reduction structure 199. In one embodiment, electron concentration reduction structure 199 may be located on the gate-drain side of transistor 100. In one embodiment, electron concentration reduction structure 199 may be located on the gate-drain side of transistor 100, closer to gate 114 than to drain 112. In one embodiment, electron concentration reduction structure 199 may be located anywhere within transistor 100, including above the interface between barrier layer 108 and buffer layer 104. In one embodiment, electron concentration reduction structure 199 may be located anywhere within transistor 100, including within, on, and / or between barrier layer 108 and / or buffer layer 104.

[0027] In one embodiment, the electron concentration reduction structure 199 may be structured and disposed in the barrier layer 108. In one embodiment, the electron concentration reduction structure 199 may be structured and disposed in the protective layer 116. In one embodiment, the electron concentration reduction structure 199 may be structured and disposed in the buffer layer 104. In one embodiment, the electron concentration reduction structure 199 may be structured and disposed partially in the protective layer 116 and partially in the barrier layer 108. In one embodiment, the electron concentration reduction structure 199 may be structured and disposed partially in the protective layer 116, partially in the barrier layer 108, and partially in the buffer layer 104. In other embodiments, the electron concentration reduction structure 199 may be disposed in one or more other layers of the transistor 100.

[0028] In particular, the electron concentration reduction structure 199 may be configured as a device, structure, arrangement, or the like for reducing gate-adjacent electron concentration as described in more detail herein. In this regard, the electron concentration reduction structure 199 reduces the gate-adjacent electron concentration in an area adjacent to the gate 114. In an aspect, the electron concentration reduction structure 199 may be configured as an electron concentration control and / or reduction feature, component, element, section, portion, structure, and / or the like as disclosed herein. In particular, the electron concentration reduction structure 199 may be configured as a device, structure, arrangement, or the like for reducing gate-adjacent electron concentration compared to prior art transistors.

[0029] In one aspect, the electron concentration reduction structure 199 may reduce the electron concentration around the gate 114, reduce the electron concentration around the edges of the gate 114, reduce the electron concentration, increase power gain, increase efficiency, decouple the gate 114 from the drain 112, decouple the gate 114 from the source 110, reduce the electron concentration, such as in portions of the barrier layer 108 between the gate 114 and the drain 112 and / or the gate 114 and the source 110, reduce capacitance, such as the capacitance between the gate 114 and the drain 112 and / or the gate 114 and the source 110, and the like. Additionally, as described herein, the electron concentration reduction structure 199 may be utilized in III-nitride based high electron mobility transistors (HEMTs), as well as HEMTs of other material systems. However, the present disclosure is not limited to this particular application of the electron concentration reduction structure 199. The electron concentration reduced structure 199 can be utilized with similar performance improvements in other similar semiconductor-based transistor devices. For simplicity, the electron concentration reduced structure 199 will be generally described in its application, which may be a III-nitride based high electron mobility transistor (HEMT).

[0030] In one embodiment, the electron concentration reduction structure 199 may utilize one or more of the embodiments described below with reference to Figures 3, 4, 5, and 6. In one embodiment, the electron concentration reduction structure 199 may utilize a combination of two of the embodiments described below with reference to Figures 3, 4, 5, and 6. In one embodiment, the electron concentration reduction structure 199 may utilize a combination of three of the embodiments described below with reference to Figures 3, 4, 5, and 6. In one embodiment, the electron concentration reduction structure 199 may utilize a combination of all of the embodiments described below with reference to Figures 3, 4, 5, and 6. Additionally, any of the specific embodiments described for any of the figures may be utilized in any of the other figures.

[0031] FIG. 2 shows a cross-sectional view of one embodiment of a transistor according to the present disclosure.

[0032] 2 is a transistor 100 that can include one or more of the features of the present disclosure. FIG. 2 further illustrates that the electron concentration reduction structure 199 can be included in other locations in the transistor 100, including between the source 110 and the gate 114, adjacent to the gate 114, adjacent to the source 110, or the like. In one embodiment, the electron concentration reduction structure 199 can be located anywhere in the transistor 100, including above the interface between the barrier layer 108 and the buffer layer 104. In one embodiment, the electron concentration reduction structure 199 can be located anywhere in the transistor 100, including within, on, and / or between the barrier layer 108 and / or the buffer layer 104. However, for simplicity of disclosure, the electron concentration reduction structure 199 will be shown and described with respect to exemplary locations. With this in mind, the present disclosure contemplates other locations, such as those shown in FIG. 2 and elsewhere, in which various implementations of the electron concentration reduction structure 199 described herein may be constructed based on the present disclosure.

[0033] In one aspect, the electron concentration reduction structure 199 may reduce the electron concentration around the gate 114, may reduce the electron concentration around the edges of the gate 114, may reduce the electron concentration, may increase power gain, may increase efficiency, may decouple the gate 114 from the source 110, may decouple the gate 114 from the drain 112, may reduce the electron concentration, such as in portions of the barrier layer 108 between the gate 114 and the source 110 and / or between the gate 114 and the drain 112, may reduce capacitance, such as the capacitance between the gate 114 and the source 110 and / or between the gate 114 and the drain 112, and the like.

[0034] FIG. 3 shows a partial cross-sectional view of another embodiment of a transistor according to the present disclosure.

[0035] 3 illustrates a first embodiment of an electron concentration reduction structure 199. In this regard, the electron concentration reduction structure 199 illustrated in FIG. 3 may include an implanted portion 200. The implanted portion 200 may be implanted in the barrier layer 108. However, the implanted portion 200 may also be implanted elsewhere within the transistor 100. For example, the implanted portion 200 may be at least partially implanted in the protective layer 116, at least partially implanted in the buffer layer 104, partially implanted in the substrate layer 102, or the like.

[0036] In one embodiment, implantation portion 200 can include an implantation of a P dopant. In one embodiment, implantation portion 200 can include an implantation of fluorine. In one embodiment, implantation portion 200 can include an implantation of fluorine ions. In one embodiment, implantation portion 200 can include an implantation of negatively charged fluorine. In one embodiment, implantation portion 200 can include an implantation of negatively charged fluorine ions. In one embodiment, implantation portion 200 can include an implantation of fluorine in barrier layer 108. In one embodiment, implantation portion 200 can include an implantation of fluorine ions in barrier layer 108. In one embodiment, barrier layer 108 can be a III-nitride barrier layer, such as an AlGaN or AlN barrier layer. Other p-type dopants can also be used.

[0037] In one embodiment, implantation portion 200 can include implantation of a material to damage barrier layer 108. In one embodiment, implantation portion 200 can include implantation of ions to damage barrier layer 108. In one embodiment, implantation portion 200 can include implantation of argon. In one embodiment, implantation portion 200 can include implantation of argon ions. In one embodiment, implantation portion 200 can include implantation of argon in barrier layer 108 to damage barrier layer 108. In one embodiment, implantation portion 200 can include implantation of argon ions in barrier layer 108 to damage barrier layer 108. In one embodiment, barrier layer 108 can be an AlGaN or AlN barrier layer. Other implants are possible.

[0038] In one embodiment, referring to arrow 202, implanted portion 200 can have a depth of less than 14 nm, less than 12 nm, less than 10 nm, and / or less than 8 nm. In one embodiment, implanted portion can have a depth of 2 nm to 14 nm, 2 nm to 4 nm, 4 nm to 6 nm, 6 nm to 8 nm, 8 nm to 12 nm, 8 nm to 10 nm, 9 nm to 11 nm, 10 nm to 12 nm, and / or 12 nm to 14 nm. In one embodiment, implanted portion 200 can extend at least partially into buffer layer 104.

[0039] In one embodiment, implanted portion 200 may have a depth of 20% to 70% of barrier layer 108, 20% to 40% of barrier layer 108, 40% to 60% of barrier layer 108, 50% to 60% of barrier layer 108, and / or 60% to 70% of barrier layer 108.

[0040] In one embodiment, referring to arrow 204, injection portion 200 can have a length of 200 nm to 2000 nm, 200 nm to 300 nm, 300 nm to 400 nm, 400 nm to 500 nm, 500 nm to 600 nm, 600 nm to 700 nm, 700 nm to 800 nm, 800 nm to 1200 nm, 1200 nm to 1400 nm, 1400 nm to 1600 nm, 1600 nm to 1800 nm, and / or 1800 nm to 2000 nm.

[0041] In one embodiment, implanted portion 200 may extend continuously along the edges of gate 114 perpendicular to arrows 204 and 202. In one embodiment, implanted portion 200 may extend discontinuously along the edges of gate 114 perpendicular to arrows 204 and 202. In one embodiment, implanted portion 200 may extend partially along the edges of gate 114 perpendicular to arrows 204 and 202. In one embodiment, implanted portion 200 may extend only in selected areas along the edges of gate 114 perpendicular to arrows 204 and 202. In one embodiment, protective layer 116 may be disposed over implanted portion 200. In one embodiment, implanted portion may have a uniform, non-uniform, and / or varying distribution of implant.

[0042] The implanted portion 200 as disclosed may reduce the electron concentration around the gate 114, may reduce the electron concentration around the edges of the gate 114, may reduce the electron concentration, may increase power gain, may increase efficiency, may decouple the gate 114 from the drain 112, may decouple the gate 114 from the source 110, may reduce the electron gas concentration, may reduce capacitance such as gate-drain capacitance and / or gate-source capacitance, and the like. In one aspect, these properties may be manifested in an area 220 adjacent to, within, or near the heterointerface 152.

[0043] FIG. 4 shows a partial cross-sectional view of another embodiment of a transistor according to the present disclosure.

[0044] 4 illustrates a second embodiment of the electron concentration reduction structure 199. In this regard, the electron concentration reduction structure 199 illustrated in FIG. 4 may include a first portion 300 and a second portion 306. The first portion 300 may be disposed within the barrier layer 108. However, the first portion 300 may also be disposed elsewhere within the transistor 100. For example, the first portion 300 may be at least partially within the protective layer 116, at least partially within the buffer layer 104, partially within the substrate layer 102, or the like.

[0045] In one embodiment, first portion 300 can comprise the same material as barrier layer 108. In one embodiment, first portion 300 can comprise a different material than barrier layer 108. In one embodiment, first portion 300 can comprise a III-nitride material, such as AlGaN, that is regrown and can have the same composition as barrier layer 108. In one embodiment, first portion 300 can comprise a III-nitride material, such as AlGaN, that is regrown and can have a different composition than barrier layer 108.

[0046] In one embodiment, first portion 300 may include regrown AlGaN with 5% to 18% aluminum, and barrier layer 108 may include AlGaN with 18% to 25% aluminum.

[0047] In one embodiment, first portion 300 may include AlGaN with 5% to 18% aluminum, AlGaN with 5% to 10% aluminum, AlGaN with 8% to 13% aluminum, AlGaN with 10% to 15% aluminum, and / or AlGaN with 15% to 18% aluminum.

[0048] In one embodiment, the barrier layer 108 may include AlGaN with 18% to 25% aluminum, AlGaN with 18% to 20% aluminum, AlGaN with 19% to 21% aluminum, AlGaN with 20% to 22% aluminum, and / or AlGaN with 23% to 25% aluminum.

[0049] In one embodiment, referring to arrow 302, first portion 300 can have a depth of less than 22 nm, less than 18 nm, less than 14 nm, less than 10 nm, less than 8 nm, and / or less than 6 nm. In one embodiment, first portion 300 can have a depth of 6 nm to 20 nm, 6 nm to 8 nm, 8 nm to 12 nm, 10 nm to 14 nm, 12 nm to 16 nm, and / or 14 nm to 20 nm. In one embodiment, first portion 300 can extend at least partially into buffer layer 104.

[0050] In one embodiment, first portion 300 may have a depth of 30% to 100% of barrier layer 108, 30% to 50% of barrier layer 108, 50% to 70% of barrier layer 108, 60% to 80% of barrier layer 108, 70% to 90% of barrier layer 108, and / or 80% to 100% of barrier layer 108.

[0051] In one embodiment, referring to arrow 304, first portion 300 can have a length of 200 nm to 2000 nm, 200 nm to 300 nm, 300 nm to 400 nm, 400 nm to 500 nm, 500 nm to 600 nm, 600 nm to 700 nm, 700 nm to 800 nm, 800 nm to 1200 nm, 1200 nm to 1400 nm, 1400 nm to 1600 nm, 1600 nm to 1800 nm, and / or 1800 nm to 2000 nm.

[0052] In one embodiment, first portion 300 may extend continuously along the edge of gate 114 perpendicular to arrows 304 and 302. In one embodiment, first portion 300 may extend discontinuously along the edge of gate 114 perpendicular to arrows 304 and 302. In one embodiment, first portion 300 may extend partially along the edge of gate 114 perpendicular to arrows 304 and 302. In one embodiment, first portion 300 may extend only in selected areas along the edge of gate 114 perpendicular to arrows 304 and 302. In some embodiments, first portion 300 may extend uniformly, non-uniformly, and / or in a manner that varies with respect to composition, doping, and / or thickness.

[0053] In a further embodiment, second portion 306 can be disposed on first portion 300. In one embodiment, second portion 306 can be disposed directly on first portion 300. In a further embodiment, second portion 306 can be configured with a recess 308, such that the top surface of second portion 306 is below the top surface of protective layer 116. In one embodiment, the depth of recess 308 can be 10% to 80% of the depth of protective layer 116, 10% to 30% of the depth of protective layer 116, 30% to 50% of the depth of protective layer 116, 50% to 70% of the depth of protective layer 116, and / or 60% to 80% of the depth of protective layer 116. In one embodiment, second portion 306 can be a protective layer. In one embodiment, second portion 306 can be a protective layer having the same composition as protective layer 116. In one embodiment, second portion 306 can be protective layer 116.

[0054] In one embodiment, prior to the formation of first portion 300, barrier layer 108 may be etched, for example, down to buffer layer 104, to form recess 310. First portion 300 may then be regrown within recess 310.

[0055] First portion 300 as disclosed may reduce the electron concentration around gate 114, may reduce the electron concentration around the edges of gate 114, may reduce the electron concentration, for example, in at least a portion between gate 114 and drain 112 and / or between gate 114 and source 110, may increase power gain, may increase efficiency, may decouple gate 114 from drain 112, may decouple gate 114 from source 110, may reduce the electron gas concentration, may reduce capacitance, and the like. In one aspect, these properties may be manifested in area 320 adjacent to, within, or near heterointerface 152.

[0056] FIG. 5 shows a partial cross-sectional view of another embodiment of a transistor according to the present disclosure.

[0057] 5 illustrates a third embodiment of an electron concentration reduction structure 199. In this regard, the electron concentration reduction structure 199 illustrated in FIG. 5 may include a recessed portion 400. The recessed portion 400 may be disposed in the barrier layer 108. However, the recessed portion 400 may also be disposed elsewhere in the transistor 100. For example, the recessed portion 400 may be at least partially in the protective layer 116, at least partially in the buffer layer 104, partially in the substrate layer 102, or the like.

[0058] In one embodiment, referring to arrow 402, recessed portion 400 can have a depth of less than 22 nm, less than 18 nm, less than 14 nm, and / or less than 10 nm. In one embodiment, first portion 300 can have a depth of 8 nm to 20 nm, 8 nm to 12 nm, 10 nm to 14 nm, 12 nm to 16 nm, and / or 14 nm to 20 nm.

[0059] In one embodiment, the recessed portion 400 may have a depth of 40% to 100% of the barrier layer 108, 40% to 60% of the barrier layer 108, 60% to 80% of the barrier layer 108, 70% to 90% of the barrier layer 108, and / or 80% to 100% of the barrier layer 108.

[0060] In one embodiment, referring to arrow 404, recessed portion 400 can have a length of 200 nm to 2000 nm, 200 nm to 300 nm, 300 nm to 400 nm, 400 nm to 500 nm, 500 nm to 600 nm, 600 nm to 700 nm, 700 nm to 800 nm, 800 nm to 1200 nm, 1200 nm to 1400 nm, 1400 nm to 1600 nm, 1600 nm to 1800 nm, and / or 1800 nm to 2000 nm.

[0061] In one embodiment, recessed portion 400 may extend continuously along the edge of gate 114 perpendicular to arrows 404 and 402. In one embodiment, recessed portion 400 may extend discontinuously along the edge of gate 114 perpendicular to arrows 404 and 402. In one embodiment, recessed portion 400 may extend partially along the edge of gate 114 perpendicular to arrows 404 and 402. In one embodiment, recessed portion 400 may extend only in selected areas along the edge of gate 114 perpendicular to arrows 404 and 402. In some embodiments, recessed portion 400 may be uniform, non-uniform, and / or the like in shape and / or thickness. In some embodiments, recessed portion 400 may be empty, filled, or partially filled with a material or different materials, such as a dielectric or insulating material. In one embodiment, recessed portion 400 may be formed using a material made up of single or multiple layers and / or regions. In some embodiments, the loaded material can be of uniform, non-uniform, or varying composition.

[0062] In one embodiment, prior to the formation of recessed portion 400, barrier layer 108 can be etched to form recess 410. Thereafter, recessed portion 400 can be formed. In one embodiment, recessed portion 400 can be a protective layer. In one embodiment, recessed portion 400 can be a protective layer having the same composition as protective layer 116. In one embodiment, recessed portion 400 can be protective layer 116.

[0063] The recessed portion 400 as disclosed may reduce the electron concentration around the gate 114, may reduce the electron concentration around the edges of the gate 114, may reduce the electron concentration, may increase power gain, may increase efficiency, may decouple the gate 114 from the drain 112, may decouple the gate 114 from the source 110, may reduce the electron gas concentration, may reduce capacitance, such as the capacitance between the gate 114 and the drain 112 and / or the gate 114 and the source 110, and the like. In one aspect, these properties may be manifested in an area 420 adjacent to, within, or near the heterointerface 152.

[0064] FIG. 6 shows a partial cross-sectional view of another embodiment of a transistor according to the present disclosure.

[0065] 6 illustrates a fourth embodiment of the electron concentration reduction structure 199. In this regard, the electron concentration reduction structure 199 illustrated in FIG. 6 may include a portion 500. In one embodiment, the portion 500 may be disposed on the barrier layer 108. In one embodiment, the portion 500 may be adjacent to the protective layer 116. In one embodiment, the portion 500 may be disposed on the barrier layer 108 and adjacent to the protective layer 116. However, the portion 500 may be disposed elsewhere within the transistor 100. For example, the portion 500 may be at least partially within the buffer layer 104, partially within the substrate layer 102, or the like.

[0066] In one embodiment, portion 500 can be a III-nitride, such as GaN. In one embodiment, portion 500 can be P-GaN. In one embodiment, portion 500 can be 0.5e12 / cm 2 ~2e12 / cm 2 , .8e12 / cm 2 ~1.2e12 / cm 2 , 1.2e12 / cm 2 ~2e12 / cm 2In one embodiment, the P dopant may include zinc, iron, carbon, magnesium, and the like. In other embodiments, portion 500 may include different materials, different P dopant concentrations, and different P dopants. In one embodiment, portion 500 may be grown by epitaxial growth. In one embodiment, portion 500 may be grown by epitaxial growth over the entire length of barrier layer 108 and selectively removed.

[0067] In one embodiment, referring to arrow 502, portion 500 can have a depth of less than 22 nm, less than 18 nm, less than 14 nm, and / or less than 10 nm. In one embodiment, portion 500 can have a depth of 8 nm to 20 nm, 8 nm to 12 nm, 10 nm to 14 nm, 12 nm to 16 nm, and / or 14 nm to 20 nm.

[0068] In one embodiment, referring to arrow 504, portion 500 can have a length of 200 nm to 2000 nm, 200 nm to 300 nm, 300 nm to 400 nm, 400 nm to 500 nm, 500 nm to 600 nm, 600 nm to 700 nm, 700 nm to 800 nm, 800 nm to 1200 nm, 1200 nm to 1400 nm, 1400 nm to 1600 nm, 1600 nm to 1800 nm, and / or 1800 nm to 2000 nm.

[0069] In one embodiment, portion 500 may extend continuously along the edge of gate 114 perpendicular to arrows 504 and 502. In one embodiment, portion 500 may extend discontinuously along the edge of gate 114 perpendicular to arrows 504 and 502. In one embodiment, portion 500 may extend partially along the edge of gate 114 perpendicular to arrows 504 and 502. In one embodiment, portion 500 may extend only in selected areas along the edge of gate 114 perpendicular to arrows 504 and 502.

[0070] Portion 500 as disclosed may reduce the electron concentration around gate 114, may reduce the electron concentration around the edges of gate 114, may reduce the electron concentration, may increase power gain, may increase efficiency, may decouple gate 114 from drain 112, may decouple gate 114 from source 110, may reduce the electron gas concentration, may reduce capacitance, such as the capacitance between gate 114 and drain 112 and / or between gate 114 and source 110, and the like. In one aspect, these properties may be manifested in area 520 adjacent to, within, or near heterointerface 152.

[0071] FIG. 7 shows a cross-sectional view of another embodiment of a transistor according to the present disclosure.

[0072] 7 is a transistor 100 that may include one or more of the features of the present disclosure. FIG. 7 further illustrates that transistor 100 may include a spacer layer 117 and may include a nucleation layer 136.

[0073] In embodiments of the transistor 100 of the present disclosure, the substrate layer 102 may be made of silicon carbide (SiC) or sapphire. In some embodiments, the substrate layer 102 may be a semi-insulating SiC substrate, a p-type substrate, an n-type substrate, and / or the like. In some embodiments, the substrate layer 102 may be very lightly doped. In one embodiment, the background impurity level may be low. In one embodiment, the background impurity level may be 1E15 / cm 3 In one embodiment, the substrate layer 102 may be formed of SiC selected from the group of 6H, 4H, 15R, 3C SiC, or the like. In another embodiment, the substrate layer 102 may be GaAs, GaN, or other material suitable for the applications described herein. In another embodiment, the substrate layer 102 may include sapphire, spinel, ZnO, silicon, or any other material capable of supporting the growth of III-nitride materials.

[0074] A buffer layer 104 and / or a nucleation layer 136 may be formed on the substrate layer 102. In one embodiment, the buffer layer 104 is formed on the substrate layer 102. In one embodiment, the buffer layer 104 is formed directly on the substrate layer 102. In one embodiment, the nucleation layer 136 may be formed on the substrate layer 102. In one embodiment, the nucleation layer 136 may be formed directly on the substrate layer 102. Intervening layers and / or regions are possible throughout the structures described.

[0075] In embodiments of the transistor 100 of the present disclosure, a nucleation layer 136 may be formed on the substrate layer 102 to reduce the lattice mismatch between the substrate layer 102 and the next layer in the transistor 100. The nucleation layer 136 may comprise many different materials, such as III-nitride materials, with a preferred material being Al. z Ga 1-z N (0<=z<=1). Nucleation layer 136 may be formed on substrate layer 102 using well-known semiconductor growth techniques such as Metal Oxide Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), or the like. In further embodiments, an intervening layer may be present between nucleation layer 136 and substrate layer 102. In further embodiments, an intervening layer may be present between nucleation layer 136 and buffer layer 104.

[0076] The buffer layer 104 may be made of GaN, aluminum gallium nitride (AlGaN), aluminum nitride (AlN), or Al x Ga y In (1-x-y) N (where 0<=x<=1, 0<=y<=1, x+y<=1), Al x In y Ga 1-x-yThe buffer layer 104 may be a III-nitride, such as GaN (where 0<=x<=1 and 0<=y<=1), and the like, or another suitable material, and may also include a nucleation layer 136 of a III-nitride material, such as AlN. In one embodiment, the buffer layer 104 is formed of AlGaN. The buffer layer 104 may be a p-type material, or alternatively, may be undoped. In one embodiment, the AlN nucleation layer 136 may be used to adhere to the substrate layer 102 and may aid in growing the buffer layer 104. The buffer layer 104 may be bonded to the substrate layer 102. In one embodiment, the nucleation layer 136 may be AlGaN.

[0077] In one embodiment, the buffer layer 104 can be high-purity GaN. In one embodiment, the buffer layer 104 can be high-purity GaN, which can be lightly doped n-type. In one embodiment, the buffer layer 104 can also use a higher bandgap III-nitride layer as a back barrier, such as an AlGaN back barrier, on the side of the buffer layer 104 opposite the barrier layer 108 to achieve better electron confinement.

[0078] In embodiments of the transistor 100 of the present disclosure, a barrier layer 108 may be formed on the buffer layer 104. In one embodiment, the barrier layer 108 may be formed directly on the buffer layer 104. The barrier layer 108 may provide an additional layer between the buffer layer 104 and the source 110, drain 112, and gate 114. The barrier layer 108 may be AlGaN, AlN, III-nitrides, InAlGaN, or other suitable materials. In one embodiment, the barrier layer 108 may be AlGaN. In one embodiment, the barrier layer 108 may be undoped. In one embodiment, the barrier layer 108 may be doped. In one embodiment, the barrier layer 108 may be an n-type material. In some embodiments, the barrier layer 108 may have multiple layers of n-type materials with different carrier concentrations. In one embodiment, the barrier layer 108 may be a III-nitride or a combination thereof. In one embodiment, the bandgap of the buffer layer 104 may be less than the bandgap of the barrier layer 108. In one embodiment, the bandgap of the buffer layer 104 can be less than the bandgap of the barrier layer 108 to form a two-dimensional electron gas (2DEG) at the heterointerface 152 between the buffer layer 104 and the barrier layer 108 when biased at an appropriate level. In one embodiment, additional III-nitride layers or regions, and / or other layers or regions of different materials are possible on the barrier layer 108 and / or within the overall structure. Any of the layers and / or regions can have uniform, non-uniform, graded, and / or varying composition, thickness, and / or doping.

[0079] In embodiments of the transistor 100 of the present disclosure, the source 110 and / or the drain 112 can be directly connected to the barrier layer 108. In one embodiment, the source 110 and / or the drain 112 can be indirectly connected to the barrier layer 108. In one embodiment, the barrier layer 108 can include regions beneath the source 110 and / or the drain 112 that are N+ material. In one embodiment, the barrier layer 108 can include regions beneath the source 110 and / or the drain 112 that are doped with Si.

[0080] In embodiments of the transistor 100 of the present disclosure, the source 110 and / or the drain 112 can be directly connected to the buffer layer 104. In one embodiment, the source 110 and / or the drain 112 can be indirectly connected to the buffer layer 104. In one embodiment, the buffer layer 104 can include regions beneath the source 110 and / or the drain 112 that are N+ material. In one embodiment, the buffer layer 104 can include regions beneath the source 110 and / or the drain 112 that are doped with Si.

[0081] A protective layer 116 may be disposed on the barrier layer 108 adjacent to the gate 114 and the drain 112, opposite the buffer layer 104, to protect and isolate the gate 114 and the drain 112. The protective layer 116 may be a passivation layer made of SiN, AlO, SiO, SiO, AlN, or the like, or a combination incorporating multiple layers thereof. In one embodiment, the protective layer 116 is a passivation layer made of SiN. In one embodiment, the protective layer 116 may be deposited using MOCVD, plasma-enhanced chemical vapor deposition (CVD), hot-filament CVD, or sputtering. In one embodiment, the protective layer 116 may include a deposition of SiN. In one embodiment, the protective layer 116 forms an insulating layer. In one embodiment, the protective layer 116 forms an insulator. In one embodiment, the protective layer 116 may be a dielectric.

[0082] In embodiments of the transistor 100 of the present disclosure, a non-conductive spacer layer 117 can be formed over the gate 114 between the source 110 and the drain 112. In one embodiment, the spacer layer 117 can include a layer of a non-conductive material, such as a dielectric. In one embodiment, the spacer layer 117 can include multiple different layers of a dielectric or a combination of dielectric layers. In one embodiment, the spacer layer 117 can be of many different thicknesses, with a preferred range of thickness being approximately 0.05 to 2 μm.

[0083] In one embodiment, the spacer layer 117 can include a material such as a dielectric or insulating material, such as SiN, SiO, etc. In some embodiments, the spacer layer 117 can be a passivation layer, such as SiN, AlO, SiO, SiO, AlN, or the like, or a combination incorporating multiple layers thereof.

[0084] In embodiments of the transistor 100 of the present disclosure, the buffer layer 104 can be designed to be of a high-purity type with a Fermi level in the upper half of the bandgap, which minimizes the slow trapping effects typically observed in GaN HEMTs. In this regard, traps below the Fermi level can be always filled, thus preventing slow transient events. In some embodiments, the buffer layer 104 can be as thin as possible consistent with achieving good crystalline quality. Applicants have already demonstrated a 0.4 μm layer with good quality.

[0085] In embodiments of the transistor 100 of the present disclosure, the III-nitride nucleation layer 136 and / or buffer layer 104 may be grown on the substrate layer 102 via epitaxial crystal growth methods, such as MOCVD (Metalorganic Chemical Vapor Deposition), HVPE (Hydride Vapor Phase Epitaxy), or MBE (Molecular Beam Epitaxy). The formation of the nucleation layer may depend on the material of the substrate layer 102.

[0086] In embodiments of the transistor 100 of the present disclosure, the buffer layer 104 can be formed using lateral epitaxial overgrowth (LEO). LEO can, for example, improve the crystalline quality of the GaN layer. When the semiconductor layers of a HEMT are epitaxial, the layer on which each epitaxial layer is grown can affect the device's performance. For example, LEO can reduce dislocation density in the epitaxial GaN layer.

[0087] In embodiments of the transistor 100 of the present disclosure, the buffer layer 104 can include nonpolar GaN. In one embodiment, the buffer layer 104 can include semipolar GaN. In one embodiment, the buffer layer 104 can include hot wall epitaxy. In one embodiment, the buffer layer 104 can include hot wall epitaxy having a thickness in the range of 0.15 μm to 0.25 μm, 0.2 μm to 0.3 μm, 0.25 μm to 0.35 μm, 0.3 μm to 0.35 μm, 0.35 μm to 0.4 μm, 0.4 μm to 0.45 μm, 0.45 μm to 0.5 μm, 0.5 μm to 0.55 μm, or 0.15 μm to 0.55 μm.

[0088] In embodiments of the transistor 100 of the present disclosure, a gate contact may be provided for the gate 114 between the source 110 and the drain 112. Additionally, in certain embodiments of the present disclosure, the gate contact may be disposed on the barrier layer 108. In one embodiment, the gate contact may be disposed directly on the barrier layer 108.

[0089] The gate 114 may be formed of platinum (Pt), nickel (Ni), and / or gold (Au). However, other metals known to those skilled in the art for achieving the Schottky effect may also be used. In one embodiment, the gate 114 may include a Schottky gate contact, which may have a three-layer structure. Such a structure may be advantageous due to the high adhesion of some materials. In one embodiment, the gate 114 may further include a highly conductive metallization layer. In one embodiment, the gate 114 may be configured as a T-gate.

[0090] In embodiments of the transistor 100 of the present disclosure, one or more metal cladding layers may be provided on one or more of the source 110, drain 112, and gate 114. The cladding layers may be Au, silver (Ag), Al, Pt, Ti, Si, Ni, Al, and / or copper (Cu). Other suitable highly conductive metals may also be used for the cladding layers.

[0091] FIG. 8 shows a cross-sectional view of another embodiment of a transistor according to the present disclosure.

[0092] 8, a transistor 100 that may include one or more of the features of the present disclosure. FIG. 8 further illustrates that the transistor 100 may include a field plate 132.

[0093] In one embodiment, the field plate 132 may be disposed on a spacer layer 117 between the gate 114 and the drain 112. In one embodiment, the field plate 132 may be deposited on the spacer layer 117 between the gate 114 and the drain 112. In some embodiments, the field plate 132 may be adjacent to the gate 114, and an additional spacer layer 117 of dielectric material may be included to at least partially cover the gate 114 to isolate the gate 114 from the field plate 132. In some embodiments, the field plate 132 may overlap the gate 114, and an additional spacer layer 117 of dielectric material may be included to at least partially cover the gate 114 to isolate the gate 114 from the field plate 132.

[0094] The field plate 132 can extend different distances from the edge of the gate 114, with a preferred range of distances being approximately 0.1 to 2 μm. In some embodiments, the field plate 132 can comprise many different conductive materials, with preferred materials being metals or combinations of metals deposited using standard metallization methods. In one embodiment, the field plate 132 can comprise titanium, gold, nickel, titanium / gold, nickel / gold, or the like.

[0095] In one embodiment, the field plate 132 may be formed on the spacer layer 117 between the gate 114 and the drain 112, with the field plate 132 being proximate to but not overlapping the gate 114. In one embodiment, the space between the gate 114 and the field plate 132 may be wide enough to isolate the gate 114 from the field plate 132, while being small enough to maximize the electric field effect provided by the field plate 132.

[0096] In certain embodiments, field plate 132 may reduce the peak operating electric field in transistor 100. In certain embodiments, field plate 132 may reduce the peak operating electric field in transistor 100, which may increase the breakdown voltage of transistor 100. In certain embodiments, field plate 132 may reduce the peak operating electric field in transistor 100, which may reduce trapping in transistor 100. In certain embodiments, field plate 132 may reduce the peak operating electric field in transistor 100, which may reduce leakage current in transistor 100.

[0097] In embodiments of the transistor 100 of the present disclosure, the source 110 and the drain 112 may be symmetrical with respect to the gate 114. In some embodiments of the switch device application, the source 110 and the drain 112 may be symmetrical with respect to the gate 114.

[0098] FIG. 9 illustrates a process for fabricating a transistor according to the present disclosure.

[0099] 9 illustrates an exemplary process 800 for fabricating the transistor 100 of the present disclosure. Note that process 800 is merely exemplary and may be modified without contradicting various aspects disclosed herein.

[0100] The process 800 may begin in step 802 by forming a substrate layer 102. The substrate layer 102 may be made of silicon carbide (SiC) or sapphire. In some embodiments, the substrate layer 102 may be a semi-insulating SiC substrate, a p-type substrate, an n-type substrate, and / or the like. In some embodiments, the substrate layer 102 may be very lightly doped. In one embodiment, the background impurity level may be low. In one embodiment, the background impurity level may be 1E15 / cm 3The substrate layer 102 may be formed of SiC selected from the group of 6H, 4H, 15R, 3C SiC, or the like. Alternatively, the substrate layer 102 may be GaAs, GaN, or other material suitable for the applications described herein. Alternatively, the substrate layer 102 may include spinel, ZnO, silicon, or any other material capable of supporting the growth of III-nitride materials.

[0101] In step 804, a buffer layer 104 may be formed on the substrate layer 102. The buffer layer 104 may be grown or deposited on the substrate layer 102. In one embodiment, the buffer layer 104 may be GaN. In another embodiment, the buffer layer 104 may be formed using LEO. In one embodiment, a nucleation layer 136 may be formed on the substrate layer 102, and in step 806, the buffer layer 104 may be formed on the nucleation layer 136. The buffer layer 104 may be grown or deposited on the nucleation layer 136. In one embodiment, the buffer layer 104 may be GaN. In another embodiment, the buffer layer 104 may be formed using LEO.

[0102] In step 806, a barrier layer 108 may be formed on the buffer layer 104. The barrier layer 108 may be an n-type conductivity layer or may be undoped. In one embodiment, the barrier layer 108 may be AlGaN. In one embodiment, the barrier layer 108 may be formed directly on the buffer layer 104. The barrier layer 108 may provide an additional layer between the buffer layer 104 and the source 110, drain 112, and gate 114. The barrier layer 108 may be AlGaN, AlN, III-nitrides, InAlGaN, or other suitable materials. In one embodiment, the barrier layer 108 may be AlGaN. In one embodiment, the barrier layer 108 may be undoped. In one embodiment, the barrier layer 108 may be doped. In one embodiment, the barrier layer 108 may be an n-type material. In some embodiments, the barrier layer 108 may have multiple layers of n-type materials with different carrier concentrations. In one embodiment, the barrier layer 108 may be a III-nitride or a combination thereof. In one embodiment, the bandgap of the buffer layer 104 can be less than the bandgap of the barrier layer 108. In one embodiment, the bandgap of the buffer layer 104 can be less than the bandgap of the barrier layer 108 to form a two-dimensional electron gas (2DEG) at the heterointerface 152 between the buffer layer 104 and the barrier layer 108 when biased at an appropriate level. In one embodiment, additional III-nitride layers or regions, and / or other layers or regions of different materials are possible on the barrier layer 108 and / or within the overall structure. Any of the layers and / or regions can have uniform, non-uniform, graded, and / or varying composition, thickness, and / or doping.

[0103] In step 808, electron concentration reduction structures 199 may be formed. In one aspect, electron concentration reduction structures 199 may be formed along with one or more of implanted portion 200, first portion 300, recessed portion 400, and / or portion 500, consistent with this disclosure.

[0104] In one embodiment, implantation portion 200 may include an implantation of a P dopant. In one embodiment, implantation portion 200 may include an implantation of fluorine. In one embodiment, implantation portion 200 may include an implantation of negatively charged fluorine. In one embodiment, implantation portion 200 may include an implantation of fluorine in barrier layer 108. In one embodiment, implantation portion 200 may include an implantation of fluorine ions. In one embodiment, implantation portion 200 may include an implantation of negatively charged fluorine ions. In one embodiment, implantation portion 200 may include an implantation of fluorine ions in barrier layer 108. In one embodiment, barrier layer 108 may be an AlGaN barrier layer. In one embodiment, implantation portion 200 may include an implantation of a material to damage barrier layer 108. In one embodiment, implantation portion 200 may include an implantation of argon. In one embodiment, implantation portion 200 may include an implantation of argon in barrier layer 108 to damage barrier layer 108. In one embodiment, implantation portion 200 can include an implantation of ions to damage barrier layer 108. In one embodiment, implantation portion 200 can include an implantation of argon ions. In one embodiment, implantation portion 200 can include an implantation of argon ions in barrier layer 108 to damage barrier layer 108. In one embodiment, barrier layer 108 can be an AlGaN barrier layer. In one embodiment, implantation portion 200 can have a uniform, non-uniform, and / or varying distribution of implants.

[0105] In one embodiment, prior to the formation of first portion 300, barrier layer 108 may be etched down to buffer layer 104 to form recess 310. First portion 300 may then be regrown in recess 310. In one embodiment, first portion 300 may comprise the same material as barrier layer 108. In one embodiment, first portion 300 may comprise a different material than barrier layer 108. In one embodiment, first portion 300 may be regrown and comprise a III-nitride material, such as AlGaN, that may have the same composition as barrier layer 108. In one embodiment, first portion 300 may be regrown and comprise a III-nitride material, such as AlGaN, that may have a different composition of AlGaN than barrier layer 108. In some embodiments, first portion 300 may extend uniformly, non-uniformly, and / or in a manner that varies with respect to composition, doping, and / or thickness.

[0106] In one embodiment, prior to the formation of recessed portion 400, barrier layer 108 may be etched to form recess 410. Recessed portion 400 may then be formed. In one embodiment, recessed portion 400 may be a protective layer. In one embodiment, recessed portion 400 may be a protective layer having the same composition as protective layer 116. In one embodiment, recessed portion 400 may be protective layer 116. In some embodiments, recessed portion 400 may be uniform and / or non-uniform in shape and / or thickness. In some embodiments, recessed portion 400 may be empty, filled, or partially filled with a material or different materials, such as a dielectric or insulating material. In one embodiment, such material in recessed portion 400 is made up of single or multiple layers and / or regions. In some embodiments, the filled material may be uniform, non-uniform, or of varying composition.

[0107] In one embodiment, portion 500 can be a III-nitride, such as GaN. In one embodiment, portion 500 can be P-GaN. In one embodiment, portion 500 can be P-GaN with a P-dopant concentration in the range of 0.5e12 / cm2 to 2e12 / cm2, 0.8e12 / cm2 to 1.2e12 / cm2, or 1.2e12 / cm2 to 2e12 / cm2. In one embodiment, the P-dopant can include zinc, iron, carbon, magnesium, and the like. In other embodiments, portion 500 can include different materials, different P-dopant concentrations, and different P-dopants. In one embodiment, portion 500 can be grown by epitaxial growth. In one embodiment, portion 500 can be grown by epitaxial growth over the entire length of barrier layer 108 and selectively removed.

[0108] In step 810, a protective layer 116 may be formed. The protective layer 116 may be a passivation layer, such as SiN, AlO, SiO, SiO, AlN, or the like, or a combination incorporating multiple layers thereof, that may be deposited over the exposed surfaces of the barrier layer 108 and / or the electron concentration reduction structures 199.

[0109] Further, additional process steps 812 may be performed during process 800. For example, source 110 may be disposed on barrier layer 108. Source 110 may be an ohmic contact of a suitable material that may be annealed. For example, source 110 may be annealed at a temperature between about 500° C. and about 800° C. for about 2 minutes. However, other times and temperatures may also be utilized. Times between about 30 seconds and about 10 minutes may be acceptable, for example. In some embodiments, source 110 may include Al, Ti, Si, Ni, and / or Pt. In one embodiment, a region below source 110 that is an N+ material may be formed within barrier layer 108. In one embodiment, a region below drain 112 may be doped with Si.

[0110] Additionally, during process 812, the drain 112 may be disposed on the barrier layer 108. Like the source 110, the drain 112 may be an ohmic contact of Ni or another suitable material and may also be annealed in a similar manner. In one embodiment, an n+ implant may be used in conjunction with the barrier layer 108 to make contact to the implant. In one embodiment, the region under the drain 112 may be an N+ material formed in the barrier layer 108. In one embodiment, the region under the drain 112 may be doped with Si.

[0111] Additionally, during process 812, a gate 114 may be disposed on the barrier layer 108 between the source 110 and the drain 112. A layer of Ni, Pt, Au, or the like may be formed for the gate 114 by evaporation or another technique. The gate structure may then be completed by deposition of Pt and Au, or other suitable materials. In some embodiments, the contacts to the gate 114 may include Al, Ti, Si, Ni, and / or Pt.

[0112] The source 110 and drain 112 electrodes can be formed to create an ohmic contact, which allows current to flow between the source 110 and drain 112 electrodes through a two-dimensional electron gas (2DEG) induced at the heterointerface 152 between the buffer layer 104 and the barrier layer 108 when the gate 114 electrode is biased at an appropriate level. In one embodiment, the heterointerface 152 can be in the ranges of 0.005 μm to 0.007 μm, 0.007 μm to 0.009 μm, and 0.009 μm to 0.011 μm.

[0113] The gate 114 may extend over a spacer or protective layer 116. The protective layer 116 may be etched, and the gate 114 may be deposited such that the bottom of the gate 114 rests on the surface of the barrier layer 108. The metal forming the gate 114 may be patterned to extend across the protective layer 116, thereby forming a top portion of the gate 114 to form a field plate 132.

[0114] Additionally, during some embodiments of process 812, the field plate 132 may be disposed on top of another protective layer and may be isolated from the gate 114. In one embodiment, the field plate 132 may be deposited on the spacer layer 117 between the gate 114 and the drain 112. In some embodiments, the field plate 132 may comprise many different conductive materials, with preferred materials being metals or combinations of metals deposited using standard metallization methods. In one embodiment, the field plate 132 may comprise titanium, gold, nickel, titanium / gold, nickel / gold, or the like. In one embodiment, multiple field plates 132 may be used. In one embodiment, multiple field plates 132 may be used, each stacked with a dielectric material between them. In one embodiment, the field plate 132 extends toward the edge of the gate 114 toward the drain 112. In one embodiment, the field plate 132 extends toward the source 110. In one embodiment, the field plate 132 extends toward the drain 112 and toward the source 110. In another embodiment, the field plate 132 does not extend to the edges of the gate 114. Finally, the structure may be covered with a dielectric spacer layer 117, such as silicon nitride. The dielectric spacer layer 117 may also be implemented similarly to the protective layer 116. Furthermore, it should be noted that the cross-sectional shape of the gate 114 shown in the figures is exemplary. For example, the cross-sectional shape of the gate 114 in some embodiments may not include a T-shaped extension. Other structures for the gate 114 may be utilized.

[0115] It should be noted that the steps of process 800 may be performed in a different order without being inconsistent with the aspects described above. Additionally, process 800 may be modified to have more or fewer process steps without being inconsistent with various aspects disclosed herein.

[0116] FIG. 10 illustrates a process for fabricating a transistor according to the present disclosure.

[0117] 10 shows process 800 consistent with FIG. 9 with modifications to steps 908 and 910. Step 908 may be performed after steps 802, 804, and 806 are performed as described above. In step 908, protective layer 116 may be formed. Protective layer 116 may be a passivation layer, such as SiN, AlO, SiO, SiO, AlN, or the like, or a combination incorporating multiple layers thereof, that may be deposited on the exposed surface of barrier layer 108.

[0118] In step 910, the electron concentration reduction structures 199 may be formed. In one aspect, recesses for the electron concentration reduction structures 199 may be formed in the protective layer 116. Thereafter, the electron concentration reduction structures 199 may be formed. In one aspect, the electron concentration reduction structures 199 may be formed with one or more of the injection portion 200, the first portion 300, the recessed portion 400, and / or the portion 500, consistent with this disclosure. Each of these aspects of the electron concentration reduction structures 199 is described in detail above. Thereafter, an additional protective layer may be formed on the electron concentration reduction structures 199. The additional protective layer may be a passivation layer, such as SiN, AlO, SiO, SiO, AlN, or the like, or a combination incorporating multiple layers thereof, that may be deposited on the exposed surfaces of the barrier layer 108 and / or the electron concentration reduction structures 199. Thereafter, the process 800 may perform steps consistent with step 812 as described above.

[0119] It should be noted that the steps of process 800 may be performed in a different order without being inconsistent with the aspects described above. Additionally, process 800 may be modified to have more or fewer process steps without being inconsistent with various aspects disclosed herein.

[0120] FIG. 11 shows a simulated comparison between a prior art transistor and a transistor according to the present disclosure.

[0121] 11 is a comparison of simulated gate-drain capacitance (Cgd) between a prior art transistor (POR) and the transistor 100 of the present disclosure implementing a first aspect of the present disclosure. The Y-axis refers to gate-drain capacitance (Cgd) in Farads per millimeter (F / mm), and the X-axis refers to voltage at the drain (Vd) in Volts (V).

[0122] Specifically, Figure 11 shows that the transistor 100 of the present disclosure, embodying a first embodiment of the present disclosure, exhibits an approximately 50% reduction in Cgd at lower voltage values ​​(Vd) at the drain. Thus, Figure 11 illustrates the unexpected result that implementing the electron concentration reduction structure 199 to reduce the electron concentration in the gate-adjacent area results in a lower gate-drain capacitance and improved power gain and efficiency. While these simulated results are for the transistor 100 of the present disclosure, embodying a first embodiment of the present disclosure, other embodiments of the transistor 100 should similarly yield similar results.

[0123] Thus, this disclosure has described a transistor 100 having an electron concentration reduction structure 199 that can reduce the electron concentration around the gate 114, reduce the electron concentration around the edges of the gate 114, reduce the electron concentration, increase power gain, increase efficiency, decouple the gate 114 from the drain 112, decouple the gate 114 from the source 110, reduce the electron gas concentration, reduce capacitance, and the like. Additionally, as described herein, the electron concentration reduction structure 199 can be utilized in gallium nitride (GaN)-based high electron mobility transistors (HEMTs). However, the present disclosure is not limited to this particular application of the electron concentration reduction structure 199. The electron concentration reduction structure 199 can be utilized in other similar microelectronic devices with similar operational improvements.

[0124] In certain aspects, the transistor 100 of the present disclosure may be utilized in an amplifier. In further aspects, the transistor 100 of the present disclosure may be utilized in an amplifier implemented by a wireless base station that connects to a wireless device. In further aspects, the transistor 100 of the present disclosure may be utilized in an amplifier implemented in a wireless device.

[0125] It should be understood that in this disclosure, references to wireless devices are intended to encompass electronic devices such as mobile phones, tablet computers, gaming systems, MP3 players, personal computers, PDAs, and the like. A "wireless device" is intended to encompass any adapted mobile technology computing device capable of connecting to a wireless communications network, such as a mobile phone, mobile appliance, mobile station, user equipment, cellular phone, smartphone, handset, wireless dongle, remote alarm device, Internet of Things (IoT)-based wireless device, or other mobile computing device that can be supported by a wireless network.

[0126] While the present disclosure has been described with reference to exemplary embodiments, those skilled in the art will recognize that the present disclosure can be practiced with modification within the spirit and scope of the appended claims. These examples given above are merely illustrative and are not intended to be an exhaustive list of all possible designs, embodiments, applications, or modifications of the present disclosure.

Claims

1. A device, A substrate; a buffer layer on the substrate; a barrier layer on the buffer layer; a source electrically coupled to the barrier layer; a gate electrically coupled to the barrier layer; a drain electrically coupled to the barrier layer; The following aspects: an electron concentration reduction structure disposed in the barrier layer and / or on the barrier layer; Equipped with the electron concentration reduction structure is configured to at least one of the following: reduce electron concentration around the gate, reduce electron concentration around an edge of the gate, reduce electron concentration, increase power gain, increase efficiency, decouple the gate from the drain, decouple the gate from the source, and reduce capacitance.

2. 10. The device of claim 1, wherein the electron concentration reduction structure comprises at least one of the following: an implanted portion in the barrier layer, an etched-regrowth portion in the barrier layer, a selective recess in the barrier layer, and an additional portion disposed on the barrier layer.

3. The device of claim 2 , wherein the reduced electron concentration structure comprises the implanted portion in the barrier layer.

4. 4. The device of claim 3, wherein the implanted portion in the barrier layer comprises at least one of the following: an implant of a P dopant in the barrier layer; and an implant of a material to damage the barrier layer.

5. The device of claim 2 , wherein the reduced electron concentration structure comprises the etch-regrowth portion in the barrier layer.

6. 6. The device of claim 5, wherein the electron concentration reduced structure includes the etch-regrowth portion and comprises a recess in the barrier layer and regrowth material disposed in the recess.

7. The device of claim 2 , wherein the electron concentration reduction structure comprises the selective recess in the barrier layer.

8. The device of claim 7 , wherein the electron concentration reduction structure comprises the selective recess in the upper surface of the barrier layer.

9. The device of claim 2 , wherein the electron concentration reduction structure comprises the additional portion disposed on the barrier layer.

10. The device of claim 9 , wherein the additional portion is disposed on an upper surface of the barrier layer.

11. 1. A process for forming a device, comprising: Preparing the substrate; disposing a buffer layer on the substrate; disposing a barrier layer on the buffer layer; electrically coupling a source to the barrier layer; electrically coupling a gate to the barrier layer; electrically coupling a drain to the barrier layer; forming an electron concentration reduction structure in at least one of the following manners: within the barrier layer and on the barrier layer; Including, A process for forming a device wherein the electron concentration reduction structure is configured to do at least one of the following: reduce electron concentration around the gate, reduce electron concentration around an edge of the gate, reduce electron concentration, increase power gain, increase efficiency, decouple the gate from the drain, decouple the gate from the source, and reduce capacitance.

12. 12. The process for forming a device of claim 11 , wherein the electron concentration reduction structure comprises at least one of the following: an implanted portion in the barrier layer, an etched-regrowth portion in the barrier layer, a selective recess in the barrier layer, and an additional portion disposed on the barrier layer.

13. The process for forming a device according to claim 12 , wherein the reduced electron concentration structure comprises the implanted portion in the barrier layer.

14. 14. The process for forming a device of claim 13, wherein the implanted portion in the barrier layer comprises at least one of the following: an implant of a P dopant in the barrier layer, and an implant of a material to damage the barrier layer.

15. The process for forming a device according to claim 12, wherein said electron concentration reduced structure comprises said etch-regrowth portion in said barrier layer.

16. 16. The process for forming a device of claim 15, wherein the electron concentration reduced structure comprises the etch-regrowth portion and comprises a recess in the barrier layer and regrowth material disposed in the recess.

17. The process for forming a device according to claim 12 , wherein the electron concentration reduction structure comprises the selective recess in the barrier layer.

18. 20. The process for forming a device according to claim 17, wherein said electron concentration reduction structure comprises said selective recess in an upper surface of said barrier layer.

19. The process for forming a device of claim 12 wherein the electron concentration reduction structure comprises the additional portion disposed on the barrier layer.

20. 20. The process for forming a device of claim 19, wherein the additional portion is disposed on an upper surface of the barrier layer.

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