Semiconductor device

Abstract

To provide a thin film transistor device having high electric characteristics and reliability, and to provide a method of manufacturing the same with high mass productivity.SOLUTION: The thin film transistor includes an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source electrode layer and a drain electrode layer. A metal oxide layer is intentionally provided as a buffer layer between a source electrode layer and a semiconductor layer and between a drain electrode layer and the semiconductor layer, whereby an ohmic contact is formed.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a thin film transistor (hereinafter referred to as TFT) using an oxide semiconductor film in a channel formation region. The present invention relates to a semiconductor device having a circuit configured with a liquid crystal display device (hereinafter referred to as a liquid crystal display device) and a manufacturing method thereof. Electro-optical devices such as display panels and light-emitting display devices with organic light-emitting elements are used as components. Regarding the electronic devices installed.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term "semiconductor device" refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all semiconductor devices. [Background technology]

[0003] In recent years, a switching element consisting of a TFT has been installed for each display pixel arranged in a matrix. Active matrix display devices (liquid crystal display devices, light-emitting display devices, and electrophoretic display devices) Active matrix display devices are being actively developed. ) and has a switching element for each pixel, which increases pixel density compared to the simple matrix method. This is advantageous because it can be driven at a low voltage when

[0004] In addition, thin film transistors (TFTs) can be fabricated using oxide semiconductor films in the channel formation region. The technology of fabricating oxide semiconductors and applying them to electronic and optical devices is attracting attention. TFTs that use zinc oxide (ZnO) as the film, and InGaO3 (ZnO) m T using TFTs using these oxide semiconductor films are mounted on a light-transmitting substrate. The technology for forming the semiconductor device and using it as a switching element for an image display device is described in Patent Documents 1 and 2. It is disclosed in. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0006] Thin film transistors that use an oxide semiconductor film in a channel formation region have high operating speed and The manufacturing process is relatively simple and sufficient reliability is required.

[0007] In forming a thin film transistor, the source electrode and the drain electrode are made of a low-resistance metal material. In particular, when manufacturing a display device that displays a large area, the resistance of the wiring can cause a signal Therefore, gold, which has a low electrical resistance, is used as the material for wiring and electrodes. It is desirable to use a metal material for the source electrode and the drain electrode. When a thin film transistor structure is used in which the dopant electrode and the oxide semiconductor film are in direct contact with each other, The cause of the high contact resistance is the One of the reasons is that a Schottky junction is formed at the contact surface between the electrode and the oxide semiconductor film. It is possible.

[0008] In addition, capacitance is generated at the portions where the source electrode and drain electrode are in direct contact with the oxide semiconductor film. This results in a lower frequency characteristic (called f characteristic), enabling high-speed operation of thin-film transistors. There is a risk of obstruction.

[0009] One aspect of the present invention is an acid containing indium (In), gallium (Ga), and zinc (Zn). In a thin film transistor using a nitride semiconductor film, the contact of the source electrode or the drain electrode One of the objects of the present invention is to provide a thin film transistor having reduced tact resistance and a method for manufacturing the same. do.

[0010] Furthermore, the operating characteristics of a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn Improving the reliability and efficiency of the system is also one of the challenges.

[0011] In addition, the electrical characteristics of a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn In particular, in a liquid crystal display device, it is necessary to reduce the variations in the individual If there is a large variation between elements, the variation in TFT characteristics will cause display irregularities. There is a risk that this may happen.

[0012] In addition, in a display device having a light-emitting element, the pixel electrode is arranged so that a constant current flows through it. The TFT (which supplies current to the driver circuit or the light-emitting element arranged in the pixel) current (I on If the variation in the brightness of the display screen is large, the brightness may vary. There is a problem.

[0013] An object of one embodiment of the present invention is to solve at least one of the above problems. [Means for solving the problem]

[0014] One embodiment of the present invention is a semiconductor layer using an oxide semiconductor film containing In, Ga, and Zn, An inverted staggered type in which a buffer layer is provided between the semiconductor layer and the source and drain electrode layers The gist is that the present invention includes a thin film transistor with a bottom gate structure.

[0015] In this specification, a semiconductor formed using an oxide semiconductor film containing In, Ga, and Zn is The semiconductor layer is also referred to as the "IGZO semiconductor layer."

[0016] The source electrode layer and the IGZO semiconductor layer must have an ohmic contact. It is desirable to reduce the contact resistance as much as possible. An ohmic contact with the semiconductor layer is required, and the contact resistance is extremely low. It is desirable to reduce the force.

[0017] Therefore, an IGZO semiconductor is formed between the source electrode layer, the drain electrode layer and the IGZO semiconductor layer. By intentionally providing a buffer layer with a higher carrier concentration than the layer, an ohmic contact is obtained. Form contact.

[0018] The buffer layer is a metal oxide layer having n-type conductivity. , titanium oxide, molybdenum oxide, zinc oxide, indium oxide, tungsten oxide, ma oxide Magnesium oxide, calcium oxide, tin oxide, gallium oxide, etc. can be used. , an oxide containing indium, gallium, and zinc used in the active layer instead of a metal oxide layer An oxide semiconductor containing indium, gallium, and zinc with a higher carrier concentration than the semiconductor layer Layers may also be used. The buffer layer may contain an impurity element that imparts n-type or p-type conductivity. Examples of such elements include indium, gallium, zinc, magnesium, aluminum, and titanium. Iron, tin, calcium, scandium, yttrium, zirconium, hafnium, boron These impurity elements can be used as impurities. When contained in the buffer layer, oxygen is prevented from escaping from the semiconductor layer during heat treatment after film formation. In addition, the carrier concentration in the metal oxide can be increased by adding impurities. do.

[0019] The buffer layer is + These layers act as drain and source regions. do.

[0020] A semiconductor device according to one aspect of the present invention includes a gate electrode layer, a gate insulating layer on the gate electrode layer, and a gate insulating layer. A semiconductor layer is formed on the gate insulating layer, and a buffer layer having an n-type conductivity is formed on the semiconductor layer. a thin film transistor including a source electrode layer and a drain electrode layer on the semiconductor layer; is an oxide semiconductor layer containing indium, gallium, and zinc, and the buffer layer is a metal oxide The semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer via a buffer layer. Connect to.

[0021] A semiconductor device according to one aspect of the present invention includes a gate electrode layer, a gate insulating layer on the gate electrode layer, and a gate insulating layer. A semiconductor layer is formed on the gate insulating layer, and a buffer layer having an n-type conductivity is formed on the semiconductor layer. a thin film transistor including a source electrode layer and a drain electrode layer on the semiconductor layer; is an oxide semiconductor layer containing indium, gallium, and zinc, and the semiconductor layer is a source electrode a thin region between the buffer layer and the drain electrode layer, the buffer layer being a metal oxide layer; The semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer via a buffer layer.

[0022] In one embodiment of the present invention, the metal oxide layer may be titanium oxide, molybdenum oxide, or zinc oxide. , indium oxide, tungsten oxide, magnesium oxide, calcium oxide, tin oxide or Gallium oxide is preferably used, and titanium oxide is particularly suitable.

[0023] In the above structure, a carrier concentration between the semiconductor layer and the buffer layer is higher than that of the semiconductor layer, and A second buffer layer may be provided that is lower than the n-type buffer layer. - Layer as machine The second buffer layer is a layer of an oxide semiconductor containing In, Ga, and Zn and a metal oxide The metal oxide layer contained in the second buffer layer may be a mixed layer containing a metal oxide layer. The same material as the metal oxide layer that can be used for the buffer layer can be used.

[0024] As the carrier concentration of an oxide semiconductor film containing In, Ga, and Zn (IGZO film) increases, Therefore, the hole mobility increases with increasing concentration of In, Ga, and Zn. The relationship between the carrier concentration and the hole mobility of the oxide semiconductor film is as shown in FIG. In one embodiment, the carrier concentration range (ch) of the IGZO film suitable for the channel of the semiconductor layer is The concentration range for the channel 1) is 1 x 10 17 atoms / cm 3 Less than (more preferably 1 × 10 11 atoms / cm 3 On the other hand, it is preferable to use an IGZO film as a buffer layer. When used as a buffer layer, the carrier concentration range of the IGZO film (buffer layer concentration range 2) is 1× 10 18 atoms / cm 3 or more (1×10 22 atoms / cm 3 (below) When the IGZO film is used as a semiconductor layer, the carrier concentration is preferably 500 vol% at room temperature. The values ​​are those with no source, drain, or gate voltages applied.

[0025] If the carrier concentration range of the IGZO film for the channel exceeds the above range, the thin film transistor Therefore, in the carrier concentration range of one embodiment of the present invention, By using a ZO film as the channel of the semiconductor layer, a more reliable thin film transistor can be achieved. It is possible.

[0026] It is preferable to use a titanium film for the source electrode layer and the drain electrode layer. The use of a laminate of a tantalum film, an aluminum film, and a titanium film results in low resistance, and the aluminum film Hillocks are less likely to occur.

[0027] A method for manufacturing a semiconductor device according to one embodiment of the present invention includes forming a gate electrode layer over a substrate, A gate insulating layer is formed on the electrode layer, a semiconductor layer is formed on the gate insulating layer, and an n-type semiconductor layer is formed on the semiconductor layer. a buffer layer having a conductivity type of 1000; and a source electrode layer and a drain electrode layer on the buffer layer. The semiconductor layer is an oxide semiconductor layer containing indium, gallium, and zinc. The buffer layer is formed using a metal oxide layer, and the semiconductor layer, the source electrode layer, and the drain electrode layer are formed using a metal oxide layer. The gate electrode layer is electrically connected to the gate electrode layer via a buffer layer.

[0028] A gate insulating layer, a semiconductor layer, a buffer layer having n-type conductivity, a source electrode layer, and a drain electrode layer. The electrode layer can be formed continuously without being exposed to the atmosphere. This can reduce defects caused by impurities in the air being mixed into the interface.

[0029] A gate insulating layer, a semiconductor layer, a buffer layer having n-type conductivity, a source electrode layer, and a drain electrode layer. The electrode layer may be formed by a sputtering method. The gate insulating layer and the semiconductor layer are formed in an oxygen atmosphere. (or oxygen 90% or more, rare gas (argon or helium) 10% or less), n-type conductivity The buffer layer having the above structure is preferably formed in a rare gas (argon or helium) atmosphere. stomach.

[0030] By using the sputtering method to form films continuously, productivity is high and the reliability of the thin film interface is high. In addition, the gate insulating layer and semiconductor layer are formed in an oxygen atmosphere, and the If the temperature is too high, the reliability may be reduced due to deterioration, and the normally-on characteristics of the thin film transistor may be affected. This can reduce the shift to the on side.

[0031] A method for manufacturing a semiconductor device according to one embodiment of the present invention includes forming a gate electrode layer over a substrate, A gate insulating layer is formed on the electrode layer, a semiconductor layer is formed on the gate insulating layer, and an n-type semiconductor layer is formed on the semiconductor layer. a buffer layer having a conductivity type of 1000; and a source electrode layer and a drain electrode layer on the buffer layer. The semiconductor layer is an oxide semiconductor layer containing indium, gallium, and zinc. The buffer layer is formed using a metal oxide layer, and the semiconductor layer, the source electrode layer, and the drain electrode layer are formed using a metal oxide layer. The gate electrode layer is electrically connected via a buffer layer, and the gate insulating layer, semiconductor layer, and buffer layer The source electrode layer and the drain electrode layer are formed successively without exposure to the air. [Effects of the Invention]

[0032] According to one aspect of the present invention, a thin film transistor having a small photocurrent, a small parasitic capacitance, and a high on-off ratio can be obtained. Therefore, a thin film transistor having good dynamic characteristics can be fabricated. Thus, a semiconductor device having a thin film transistor with high electrical characteristics and high reliability can be provided. can be done. [Brief explanation of the drawings]

[0033] [Figure 1] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 2] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 3] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 4] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 5] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 6] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 12] FIG. 1 is a schematic top view of a multi-chamber manufacturing apparatus according to one embodiment of the present invention. [Figure 13] FIG. 1 is a block diagram illustrating a display device according to one embodiment of the present invention. [Figure 14] FIG. 1 illustrates a configuration of a signal line driver circuit according to one embodiment of the present invention. [Figure 15] 10 is a timing chart illustrating the operation of a signal line driver circuit according to one embodiment of the present invention. [Figure 16] 10 is a timing chart illustrating the operation of a signal line driver circuit according to one embodiment of the present invention. [Figure 17] FIG. 1 illustrates a structure of a shift register according to one embodiment of the present invention. [Figure 18] FIG. 18 is a diagram for explaining the connection configuration of the flip-flop shown in FIG. 17. [Figure 19]1A and 1B illustrate an active matrix liquid crystal display device according to one embodiment of the present invention. [Figure 20] 1A and 1B illustrate a liquid crystal display panel according to one embodiment of the present invention. [Figure 21] 1A and 1B illustrate a liquid crystal display module according to one embodiment of the present invention. [Figure 22] 1A and 1B illustrate an active matrix light-emitting display device according to one embodiment of the present invention. [Figure 23] FIG. 23 is a diagram illustrating an equivalent circuit of the light-emitting display device shown in FIG. 22. [Figure 24] 1A and 1B illustrate a structure of a light-emitting element according to one embodiment of the present invention. [Figure 25] 1A and 1B illustrate a light-emitting display panel according to one embodiment of the present invention. [Figure 26] 1A and 1B illustrate active matrix electronic paper according to one embodiment of the present invention. [Figure 27] 10A and 10B are graphs showing the relationship between the carrier concentration and the hole mobility in an oxide semiconductor film containing In, Ga, and Zn. [Figure 28] 1A and 1B are diagrams illustrating examples of usage of electronic paper. [Figure 29] FIG. 1 is an external view showing an example of an electronic book. [Figure 30] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 31] FIG. 1 is an external view showing an example of a gaming machine. [Figure 32] FIG. 1 is an external view showing an example of a mobile phone. DETAILED DESCRIPTION OF THE INVENTION

[0034] The present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the above, and various modifications and variations in form and detail are possible without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in the following manner. It should be noted that the present invention is not limited to the following description. In the structure, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. The following explanations may be omitted.

[0035] (Embodiment 1) In this embodiment mode, a thin film transistor and a manufacturing process thereof will be described with reference to FIGS. explain.

[0036] FIG. 1 shows thin film transistors 170a, 170b, and 170c of a bottom gate structure according to this embodiment. 1 and 2. FIG. 1(A1) is a plan view, and FIG. 1(A2) is a view of FIG. 1(A1). FIG. 1(B1) is a cross-sectional view taken along line A1-A2. FIG. 1(B2) is a plan view. 2(A1) is a cross-sectional view taken along line B1-B2 in FIG. 2(A2). FIG. 3 is a cross-sectional view taken along line C1-C2 in FIG. 2(A1).

[0037] In FIG. 1, a gate electrode layer 101, a gate insulating layer 102, a semiconductor layer 103, and a gate insulating layer 104 are formed on a substrate 100. 03, buffer layers 104a and 104b having n-type conductivity, a source electrode layer or a drain electrode layer Thin film transistors 170a and 170b having electrode layers 105a and 105b are provided. do.

[0038] The semiconductor layer 103 is an oxide semiconductor film containing In, Ga, and Zn, and the source electrode layer or between the drain electrode layers 105a, 105b and the semiconductor layer 103 which is an IGZO semiconductor layer. In addition, buffer layers 104a and 104b having a higher carrier concentration than the semiconductor layer 103 are intentionally formed. By providing the thin film transistor with the ohmic contact, an ohmic contact is formed. In order to reduce the variation in the oxide semiconductor layer containing In, Ga, and Zn, It is preferable that the substrate is in a non-transitory state.

[0039] The buffer layers 104a and 104b are made of a metal oxide layer having n-type conductivity. The metal oxide layer may be titanium oxide, molybdenum oxide, zinc oxide, indium oxide, or titanium oxide. tin oxide, magnesium oxide, calcium oxide, tin oxide, gallium oxide, etc. In place of the metal oxide layer, an indium ion implantation layer having a higher carrier concentration than the semiconductor layer 103 can be used. An oxide semiconductor layer containing indium, gallium, and zinc can also be used. The buffer layer may contain an impurity element that imparts n-type or p-type conductivity. Examples of such elements include indium, gallium, zinc, magnesium, aluminum, and titanium. Iron, tin, calcium, etc. can be used as impurity elements in the buffer layer. When the semiconductor layer is contained, oxygen is prevented from escaping from the semiconductor layer due to heat treatment after film formation. Furthermore, the carrier concentration in the metal oxide can be increased by adding impurities.

[0040] The buffer layers 104a and 104b are n + layer, which acts as a drain or source region It can also be called.

[0041] The thin film transistor 170a of FIGS. 1A1 and 1A2 includes buffer layers 104a and 104b. The source and drain electrode layers 105a and 105b are etched using different masks. This is an example of processing the buffer layers 104a and 104b and the source electrode layer or the drain electrode layer 1. The shape is different from 05a and 105b.

[0042] The thin film transistor 170b of FIGS. 1B1 and 1B2 includes buffer layers 104a and 104b. The source and drain electrode layers 105a and 105b are etched using the same mask. This is an example of processing the buffer layers 104a and 104b and the source electrode layer or the drain electrode layer 1. It reflects a similar shape to 05a and 105b.

[0043] In addition, the thin film transistors 170a and 170b in FIGS. On the semiconductor layer 103, the ends of the source and drain electrode layers 105a and 105b are The end of the buffer layer 104a and the end of the buffer layer 104b do not match. This is an example where some of the material is exposed.

[0044] On the other hand, the thin film transistor 170c of FIGS. 2A1 and 2A2 has a semiconductor layer 103 and a buffer layer. This is an example in which the layers 104a and 104b are etched using the same mask. The edges of the buffer layers 104a and 104b are aligned with each other. The thin film transistor 170c has a source electrode layer or a drain electrode layer on the semiconductor layer 103. In this example, the ends of the electrode layers 105a and 105b are aligned with the ends of the buffer layers 104a and 104b. be.

[0045] Furthermore, a thin film transistor 170d in which the source electrode layer or the drain electrode layer has a stacked structure is 11. The thin film transistor 170d has a source electrode layer or a drain electrode layer 105a1 , 105a2, and 105a3, and the source or drain electrode layers 105b1 and 105 For example, the source electrode layer or the drain electrode layer 105 Titanium films as a1 and 105b1, aluminum films as 105a2 and 105b2, Titanium films can be used as 5a3 and 105b3.

[0046] In the thin film transistor 170d, the source and drain electrode layers 105a1 and 105b 1 as an etching stopper, the source or drain electrode layer 105a2, Formed by wet etching 105a3, 105b2, and 105b3 The source electrode layer or the drain electrode layer is then removed using the same mask as in the wet etching. 105a1, 105b1, and the buffer layers 104a, 104b are etched by dry etching. It is formed by etching.

[0047] Therefore, the source or drain electrode layer 105a1 is connected to the end of the buffer layer 104a. The source electrode layer or drain electrode layer 105b1 is aligned with an end of the buffer layer 104b. The source electrode layer or drain electrode layer 105a2, 105a3, and the source electrode layer or The drain electrode layers 105b2 and 105b3 are the source or drain electrode layers 105a 1, the end is set back from 105b1.

[0048] In this way, the conductive film used for the source electrode layer and the drain electrode layer, the buffer layer, and the semiconductor If the layer has a low selectivity in the etching process, it functions as an etching stopper. To achieve this, a conductive film having a different thickness may be stacked and an etching process may be performed multiple times under different etching conditions.

[0049] The manufacturing method of the thin film transistor 170a of FIGS. 1A1 and 1A2 will be described with reference to FIGS. This will be used to explain.

[0050] A gate electrode layer 101, a gate insulating layer 102, and a semiconductor film 111 are formed on a substrate 100 ( See FIG. 3(A). The substrate 100 is made of barium borosilicate glass, aluminoborosilicate glass, or the like. Glass or aluminosilicate glass, made by the fusion or float process. In addition to alkali-free glass substrates and ceramic substrates, we also offer heat-resistant substrates that can withstand the processing temperatures of this manufacturing process. A plastic substrate having a metal substrate such as a stainless steel alloy can also be used. A substrate having an insulating film on the surface of the plate may be used. The size of the substrate 100 is 320 mm x 100 mm. 400mm, 370mm×470mm, 550mm×650mm, 600mm×720m m, 680mm x 880mm, 730mm x 920mm, 1000mm x 1200mm, 1100mm x 1250mm, 1150mm x 1300mm, 1500mm x 1800m m, 1900mm x 2200mm, 2160mm x 2460mm, 2400mm x 280 0mm, or 2850mm x 3050mm, etc. can be used.

[0051] An insulating film may be formed as a base film on the substrate 100. The base film may be formed by a CVD method or the like. A silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a nitride film is formed by using a sputtering method or the like. The insulating film 11 may be formed of a single layer or a multilayer of silicon dioxide films.

[0052] The gate electrode layer 101 may be formed of titanium, molybdenum, chromium, tantalum, tungsten, or aluminum. The gate electrode layer 101 is formed using a metal material such as silicon or an alloy material thereof. A conductive film is formed on the substrate 100 by a sputtering method or a vacuum deposition method, and a photolithography is formed on the conductive film. A mask is formed by a lithography technique or an inkjet method, and a conductive film is formed using the mask. It can be formed by etching a film. It can also be formed by etching a conductive nano-film such as silver, gold, or copper. The paste is ejected by an ink jet method and baked to form the gate electrode layer 101. In addition, it is possible to improve the adhesion of the gate electrode layer 101 and prevent diffusion into the substrate or the underlying film. As a barrier metal, a nitride film of the above metal material is formed on the substrate 100 and the gate electrode layer 101. The gate electrode layer 101 may have a single layer structure or a stacked layer structure. For example, a molybdenum film and an aluminum film are stacked from the substrate 100 side, Lamination of aluminum and neodymium alloy film, lamination of titanium film and aluminum film, titanium film Alternatively, a laminate of an aluminum film and a titanium film can be used.

[0053] Since a semiconductor film and a wiring are formed on the gate electrode layer 101, the edge It is desirable to process it so that it has a tapered shape.

[0054] The gate insulating layer 102 and the semiconductor film 111 can be formed successively without exposure to the air. When films are formed continuously, they can be contaminated by atmospheric components and impurity elements floating in the air. Each lamination interface can be formed without any problem.

[0055] In an active matrix display device, the electrical properties of the thin film transistors that make up the circuit The electrical characteristics are important, and these characteristics determine the performance of the display device. Among the electrical properties of the semiconductor, the threshold voltage (Vth) is important. If the threshold voltage is high or negative, the circuit cannot control it. It is difficult to achieve this. In the case of a thin film transistor, when the driving voltage is low, it performs the switching function of a thin film transistor. If the threshold voltage is negative, Even if the gate voltage is 0V, current flows between the source and drain electrodes, which is called normally-on transistor. It's easy to become like this.

[0056] In the case of an n-channel thin film transistor, the channel is first generated when a positive voltage is applied to the gate. A transistor in which a channel is formed and a drain current flows out is desirable. There are transistors in which a channel does not form unless a negative voltage is applied, and transistors in which a channel forms even under negative voltage conditions. A transistor that allows drain current to flow is not suitable for use as a thin-film transistor in a circuit. be.

[0057] Therefore, the gate of a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn It is desirable to form a channel with a positive threshold voltage as close to 0V as possible.

[0058] The threshold voltage of the thin film transistor is determined at the interface between the oxide semiconductor layer, that is, the interface between the oxide semiconductor layer and the gate electrode. This is thought to have a significant effect on the interface of the gate insulating layer.

[0059] Therefore, by forming these interfaces in a clean state, the electrical characteristics of the thin film transistor can be improved. This improves productivity and prevents the manufacturing process from becoming complicated, achieving both mass production and high performance. A thin film transistor having the above structure is realized.

[0060] In particular, if moisture in the air is present at the interface between the oxide semiconductor layer and the gate insulating layer, the thin film transistor Deterioration of the electrical characteristics of the transistor, variations in threshold voltage, and tendency to become normally on By successively forming the oxide semiconductor layer and the gate insulating layer, such hydrogen The compound can be eliminated.

[0061] Therefore, the gate insulating layer 102 and the semiconductor film 111 are formed by sputtering without being exposed to the air. By continuously forming the film under reduced pressure, it is possible to obtain a good interface, low leakage current, and A thin film transistor with high driving capability can be realized.

[0062] The gate insulating layer 102 and the semiconductor film which is an oxide semiconductor film containing In, Ga, and Zn are also used. The film 111 is formed in an oxygen atmosphere (or 90% or more oxygen and 10% or less rare gas (argon)). It is preferable to do so.

[0063] By using the sputtering method to form films continuously, productivity is high and the reliability of the thin film interface is high. In addition, the gate insulating layer and semiconductor layer are formed in an oxygen atmosphere, and the Doing so may result in a decrease in reliability due to deterioration, or the thin film transistor may become normally on. This can reduce the risk of this happening.

[0064] The gate insulating layer 102 is formed by depositing a silicon oxide film or a silicon nitride film using a CVD method, a sputtering method, or the like. The insulating film can be formed of a silicon oxynitride film, a silicon nitride oxide film, or a silicon nitride oxide film. The thin film transistor 170c shown in 2) is an example in which the gate insulating layer 102 is stacked.

[0065] The gate insulating layer 102 is made of a silicon nitride film or a silicon nitride oxide film and a silicon oxide film or an oxide film. The gate insulating layer can be formed by laminating a silicon nitride film and a silicon nitride film in that order. From the substrate side, a silicon nitride film or a silicon nitride oxide film, a silicon oxide film or a silicon oxynitride film, and a nitride film are formed. The gate electrode can be formed by laminating three layers in this order: a silicon nitride film, a silicon oxide nitride film, and a silicon nitride film. The insulating layer is a single layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. It can be formed.

[0066] Further, a gate insulating layer 102 is formed by nitriding a nitride film on the gate electrode layer 101 by plasma CVD. A silicon film may be formed, and then a silicon oxide film may be laminated on the silicon nitride film by sputtering. A silicon nitride film and a silicon oxide film are sequentially stacked on the gate electrode layer 101 by plasma CVD. A silicon oxide film may be further laminated on the silicon oxide film by sputtering.

[0067] Here, the silicon oxynitride film is a film whose composition contains more oxygen than nitrogen. The concentration ranges are 55 to 65 atomic % for oxygen, 1 to 20 atomic % for nitrogen, and 25 to 30 atomic % for silicon. 35 atomic % and hydrogen in the range of 0.1 to 10 atomic %. The bare film has a composition in which the nitrogen content is greater than the oxygen content, and the concentration range is Oxygen is 15-30 atomic %, nitrogen is 20-35 atomic %, Si is 25-35 atomic %, and hydrogen is This refers to a content in the range of 15 to 25 atomic %.

[0068] The gate insulating layer 102 may be formed of aluminum, yttrium, magnesium, or hafnium. The oxide, nitride, oxynitride, or oxynitride of cerium or a compound thereof is used. A compound containing at least two kinds of these may also be used.

[0069] The gate insulating layer 102 may contain a halogen element such as chlorine or fluorine. The concentration of halogen elements in the insulating layer 102 is 1×10 15 atoms / cm 3 More than 1×10 20 atoms / cm 3 The following would suffice.

[0070] The semiconductor film 111 is an oxide semiconductor film containing In, Ga, and Zn. The thickness of the thin region of the body film 111 after etching is 2 nm or more and 200 nm or less ( Preferably, the thickness of the insulating film is 20 nm or more and 150 nm or less. For example, The semiconductor film 111 is formed by sputtering an oxide film containing In, Ga, and Zn. The semiconductor film should be formed to a thickness of 50 nm. Using an oxide semiconductor target containing n, Ga, and Zn, Distance 170 mm, pressure 0.4 Pa, direct current (DC) power 0.5 kW, argon or oxygen atmosphere Film formation can be performed under atmospheric conditions. In addition, dust can be reduced by using a pulsed direct current (DC) power supply. This is preferable because it allows for a uniform film thickness distribution.

[0071] Next, the semiconductor film 111 is processed by etching using a mask 113, and the semiconductor layer 103 is The semiconductor layer 103 is formed by photolithography or droplet deposition. A mask 113 is formed by a discharge method, and the semiconductor film 111 is etched using the mask 113. It can be formed by applying

[0072] The edge of the semiconductor layer 103 is etched into a tapered shape, and the step shape This can prevent the wiring from breaking.

[0073] Next, a metal oxide film 11 having n-type conductivity is formed on the gate insulating layer 102 and the semiconductor layer 103. 3(C) , a mask is formed on the metal oxide film 114 having n-type conductivity. The mask 116 is formed by photolithography or inkjet printing. The metal oxide film 114 having n-type conductivity is formed by etching using a mask 116. The metal oxide film 115 is then processed by etching to form an n-type conductive metal oxide film 115 (FIG. 3(D)). The metal oxide film 115 having n-type conductivity has a thickness of 2 nm to 100 nm ( Preferably, the thickness is 20 nm or more and 50 nm or less. The film 114 is preferably formed under a rare gas (preferably argon) atmosphere. In this case, a titanium oxide film is used as the metal oxide film 114. As an example of the etching method, Hydrofluoric acid, hydrochloric acid, or sulfuric acid, or ammonia water, hydrogen peroxide, and pure water in a ratio of 1:1:5 The solution mixed in the specified volume ratio can be used as an etchant.

[0074] The semiconductor film 111 and the metal oxide film 115 having n-type conductivity are deposited by a method other than sputtering. Other deposition methods include pulsed laser deposition (PLD) and electron beam deposition. Among the gas phase methods, the following can be used in terms of ease of controlling the composition of the material system: The PLD method is suitable, and from the viewpoint of mass production, the sputtering method is suitable, as described above.

[0075] A conductive film 117 is formed over the metal oxide film 115 having n-type conductivity (see FIG. 3(E)). .).

[0076] The conductive film 117 is made of aluminum, copper, silicon, titanium, neodymium, scandium, or the like. Aluminum to which elements for improving heat resistance or elements for preventing hillocks, such as aluminum or molybdenum, are added. It is preferable to form the layer by a single layer or a multilayer of a metal alloy. The film on the side in contact with the oxide film is made of titanium, tantalum, molybdenum, tungsten, or any of these. A laminate formed of nitrides of the above elements and aluminum or aluminum alloy formed on top of them. Furthermore, the upper and lower surfaces of the aluminum or aluminum alloy may be Laminated layers sandwiched between tantalum, molybdenum, tungsten, or nitrides of these elements Here, the conductive film 117 may be formed of a titanium film, an aluminum film, or a titanium nitride film. This laminated conductive film is etched with hydrogen peroxide or heated hydrochloric acid. It can be etched as a substitute.

[0077] When a titanium film, an aluminum film, and a titanium film are stacked, the resistance is low and the aluminum Hillocks are less likely to occur on the film.

[0078] The conductive film 117 is formed by sputtering or vacuum evaporation. Conductive nanopastes such as gold and copper are used for the screen printing method, inkjet method, etc. Alternatively, the layer may be formed by discharging the material and firing it.

[0079] Next, a mask 118 is formed over the conductive film 117. Etching and separation are performed to form source and drain electrode layers 105a and 105b. (See FIG. 3(F)). As shown in FIG. 3(F) of this embodiment, the conductive film 117 is formed by wet etching. When etching is performed, the conductive film 117 is isotropically etched, so that the source electrode layer or the drain electrode layer The edges of the electrode layers 105a and 105b do not coincide with the edges of the mask 118 and are set back. Next, the metal oxide film 115 having n-type conductivity is etched using the mask 118. Then, buffer layers 104a and 104b are formed (see FIG. 3(G)). Depending on the conditions, in the etching process of the metal oxide film 115 having n-type conductivity, The exposed region of the layer 103 may also be partially etched. In this case, the buffer layer 1 The channel region of the semiconductor layer 103 between 104a and 104b is a region with a thin film thickness. In this embodiment, the buffer layers 104a and 104b are formed, and the source electrode layer and the drain electrode layer are formed. Since the inner electrode layers 105a and 105b are formed separately, the buffer layers 104a and 104b and the non-overlapping regions at the ends of the source and drain electrode layers 105a and 105b. The length can be easily controlled.

[0080] Furthermore, plasma treatment may be performed on the semiconductor layer 103. This plasma treatment can repair damage to the semiconductor layer 103 caused by etching. It is preferable to carry out the reaction in an atmosphere of O2, N2O, preferably oxygen-containing N2, He, or Ar. Alternatively, the plasma treatment may be carried out in an atmosphere containing Cl2 and CF4. The process is preferably performed without bias.

[0081] The end portions of the source electrode layer or the drain electrode layer 105a and 105b on the semiconductor layer 103 and the back electrode layer 105b are The ends of the layers 104a and 104b are not aligned but are offset, and the source electrode layer or the drain electrode The edges of the buffer layers 104a and 104b are formed outside the edges of the layers 105a and 105b. do.

[0082] After this, the mask 118 is removed. Through the above steps, a thin film transistor 170a is formed. It is possible.

[0083] Next, a manufacturing process of the thin film transistor 170b shown in FIGS. 1B1 and 1B2 is shown in FIGS.

[0084] 4A shows the state after removing the mask 113 in the step of FIG. A metal oxide film 114 having n-type conductivity and a conductive film 121 are laminated in this order on the substrate 103 (FIG. 4(B). In this case, the metal oxide film 114 and the conductive film 121 have n-type conductivity. The film can be continuously formed by sputtering without exposure to the atmosphere.

[0085] A mask 122 is formed on the metal oxide film 114 having n-type conductivity and the conductive film 121. The conductive film 121 is wet-etched using a mask 122 to form a source electrode layer or a drain electrode layer. Then, the conductive electrode layers 105a and 105b are formed (see FIG. 4(C)).

[0086] Next, the metal oxide film 114 having n-type conductivity is dry-etched to form a buffer layer As shown in FIG. 4, the buffer layer 104 104a and 104b, and the source and drain electrode layers 105a and 105b. If the same mask is used for both processes, the number of masks can be reduced, simplifying the process and reducing costs. It is possible to measure the efficiency.

[0087] An insulating film may be formed as a protective film on the thin film transistors 170a and 170b. The protective film can be formed in the same manner as the gate insulating layer. It is a dense membrane that prevents the intrusion of polluting impurities such as organic matter, metals, and water vapor. For example, a silicon oxide film is formed on the thin film transistors 170a and 170b as a protective film. A laminate with a silicon nitride film may be formed.

[0088] In addition, the semiconductor layer 103 is preferably subjected to heat treatment after deposition. However, it may be performed immediately after the film formation, after the formation of the conductive film 117, after the formation of the protective film, etc. It can be carried out at a temperature of 300°C. The temperature may be set to 400° C. or higher, preferably 350° C. As shown in FIG. When the buffer layers 104a and 104b are successively formed, a heat treatment may be performed after the lamination. The heat treatment is preferably performed multiple times in separate steps for the semiconductor layer 103 and the buffer layers 104a and 104b. That's fine.

[0089] The end portions of the source electrode layer or the drain electrode layer 105a and the buffer layer 104a and the buffer layer 104b are The ends of the source electrode layer or the drain electrode layer 10 Since the distance between the ends of the source electrode layer 105a and the drain electrode layer 105b is large, This prevents leakage current and short circuits between the first and second terminals 105b. In addition, a thin film transistor with high withstand voltage can be manufactured.

[0090] Also, as in the thin film transistor 170c of FIGS. 2(A1) and 2(A2), the buffer layer 104a, The end of 104b may be formed to coincide with the end of the source electrode and the drain electrode. Etching and buffing for forming source and drain electrode layers 105a and 105b When the etching for forming the layers 104a and 104b is performed by dry etching, the film shown in FIG. A1) (A2) can be made into a shape similar to the thin film transistor 170c. The metal oxide film 114 having the conductivity type is etched using the source electrode and the drain electrode as a mask. Even if the buffer layers 104a and 104b are formed by etching, the thin film transistors shown in FIGS. 2(A1) and 2(A2) are not formed. It can be shaped like transistor 170c.

[0091] A gate electrode layer, a gate insulating layer, and a gate insulating layer are not provided with a buffer layer (a metal oxide layer having n-type conductivity). The insulating layer, the semiconductor layer (oxide semiconductor layer containing In, Ga, and Zn), the source electrode layer, and the drain electrode layer In the case of a laminated structure called a gate electrode layer, a source electrode layer or a drain electrode layer, The distance between the two becomes closer, and the parasitic capacitance between them increases. This becomes more pronounced as the semiconductor layer is made thinner. A buffer layer with a high carrier concentration, such as a metal oxide layer, is provided. The layer structure is a stack of a gate insulating layer, a semiconductor layer, a buffer layer, a source electrode layer, and a drain electrode layer. Since the thin film transistor has a parasitic capacitance, even if the semiconductor layer is thin, It can be controlled.

[0092] According to this embodiment, a thin film transistor with a small photocurrent, a small parasitic capacitance, and a high on-off ratio can be obtained. Therefore, a thin film transistor having good dynamic characteristics can be obtained. As a result, it is possible to provide a semiconductor device having a thin film transistor with excellent electrical characteristics and high reliability. can.

[0093] (Embodiment 2) This embodiment is an example of a thin film transistor having a multi-gate structure according to one embodiment of the present invention. Therefore, other aspects can be carried out in the same manner as in the first embodiment, and the same or similar parts as in the first embodiment can be used. Descriptions of parts having special functions and repetitive steps will be omitted.

[0094] In this embodiment, a thin film transistor used in a semiconductor device will be described with reference to FIGS. Explain using A)(B).

[0095] FIG. 5(A) is a plan view showing the thin film transistor 171a, and FIG. 5(B) is a plan view showing the thin film transistor 171a. 1 corresponds to a cross-sectional view showing the thin film transistor 171a taken along line E1-E2 in FIG.

[0096] As shown in FIGS. 5A and 5B, gate electrode layers 151a and 151b, semiconductor layers 151a and 151b, and a semiconductor layer 151b are formed on a substrate 150. Conductor layers 153a, 153b, buffer layers 154a, 154b, 154c, source electrode layers or The thin film transistor 171 has a multi-gate structure including drain electrode layers 155a and 155b. a is provided.

[0097] The semiconductor layers 153a and 153b are oxide semiconductor layers containing In, Ga, and Zn. The buffer layers 154a, 154b, and 154c are metal oxide layers having n-type conductivity. Source or drain region (n + Buffer layers 154a, 154b, 154c, 154d, 154e, 154f, 154g, 154h, 154i, 154j ... The semiconductor layers 54c have a higher carrier concentration than the semiconductor layers 153a and 153b.

[0098] The semiconductor layer 153a and the semiconductor layer 153b are electrically connected to each other via a buffer layer 154c. On the other hand, the semiconductor layer 153a is connected to the source electrode 152 via the buffer layer 154a. The pole layer or drain electrode layer 155a and the semiconductor layer 153b are connected via a buffer layer 154b. The source electrode layer or drain electrode layer 155b is electrically connected to the source electrode layer or drain electrode layer 155c.

[0099] FIG. 6 shows a thin film transistor 171b having a multi-gate structure with another configuration. 6(B) is a plan view showing the thin film transistor 171b, and FIG. 6(B) is a plan view showing the thin film transistor 171b along the line F in FIG. 6(A). 1-F2 corresponds to a cross-sectional view of the thin film transistor 171b in FIG. In 171b, a source or drain electrode layer 155a is formed on a buffer layer 154c. A wiring layer 156 is formed in the same process as the semiconductor layer 155b. The buffer layer 154c and the wiring layer 156 electrically connect to the wiring layer 156.

[0100] FIG. 7 shows a thin film transistor 171c having a multi-gate structure with another configuration. 7B is a plan view showing the thin film transistor 171c, and FIG. 7B is a plan view showing the thin film transistor 171c along the line G in FIG. 1-G2 corresponds to a cross-sectional view of the thin film transistor 171c of FIG. In 171c, the semiconductor layer 153a and the semiconductor layer 153b are connected to form a single semiconductor layer. The semiconductor layer 153 is formed as a gate insulating layer 152. The gate electrode layer 151a is provided so as to straddle the gate electrode layers 151a and 151b.

[0101] As described above, in the thin film transistor having a multi-gate structure according to one embodiment of the present invention, each The semiconductor layer formed on the gate electrode layer may be provided continuously, or may be provided as a buffer layer and a wiring layer. A plurality of semiconductor layers may be provided so as to be electrically connected via a line layer or the like.

[0102] A thin film transistor with a multi-gate structure according to one embodiment of the present invention has a small off-state current. A semiconductor device including such a thin film transistor can have high electrical characteristics and high reliability. can

[0103] In this embodiment, a double gate structure having two gate electrode layers is used as the multi-gate structure. However, the present invention is also applicable to a triple gate structure having more gate electrode layers. It is possible.

[0104] (Embodiment 3) This embodiment describes a method for stacking a buffer layer in a thin film transistor according to one embodiment of the present invention. Therefore, the other steps can be performed in the same manner as in the first or second embodiment. The same parts as those in the first or second embodiment, or parts having similar functions, and repetition of steps The explanation will be omitted.

[0105] In this embodiment, a thin film transistor 173 used in a semiconductor device will be described with reference to FIG. and explain.

[0106] As shown in FIG. 8, a gate electrode layer 101, a semiconductor layer 103, a buffer layer 104, and a semiconductor layer 105 are formed on a substrate 100. 106a, 106b, buffer layers 104a, 104b, source electrode layer or drain electrode layer A thin film transistor 173 including 105a and 105b is provided.

[0107] The thin film transistor 173 of this embodiment is made up of a semiconductor layer 103 and buffer layers 104a and 104b. Buffer layers 106a and 106b are provided between the first and second buffer layers 106a and 106b, respectively. are.

[0108] The semiconductor layer 103 is an oxide semiconductor layer containing In, Ga, and Zn. 4a and 104b are metal oxide layers, and buffer layers 106a and 106b are made of In, Ga, and The buffer layer 106a is a mixed layer of an oxide semiconductor layer containing Zn and a metal oxide layer. 06b is a metal oxide target and an oxide semiconductor target containing In, Ga, and Zn. The metal oxide layer can be formed by co-sputtering of titanium oxide, oxide, and the like. Molybdenum oxide, zinc oxide, indium oxide, tungsten oxide, magnesium oxide, oxide Calcium oxide, tin oxide, gallium oxide, etc. can be used, but titanium oxide is particularly suitable. The buffer layers 104a, 104b and the buffer layers 106a, 106b are n-type or The impurity element may contain p-type impurity elements, such as indium and gallium. , zinc, magnesium, aluminum, titanium, iron, tin, calcium, scandium, Examples include tritium, zirconium, hafnium, boron, thallium, germanium, and lead. The carrier concentration in the metal oxide can be increased by using a different metal.

[0109] A second buffer layer ( The buffer layers 106a and 106b have a higher carrier concentration than the semiconductor layer 103. The buffer layers 104a and 104b are lower than the layers 104a and 104b. + Acting as a layer On the other hand, the second buffer layer (buffer layers 106a and 106b) is n - Acting as a layer do.

[0110] In this way, the buffer layer provided between the semiconductor layer and the source electrode layer or the drain electrode layer The carrier concentration may be varied from the semiconductor layer to the source electrode layer or the drain electrode layer. It is controlled so that it increases towards the polar layer.

[0111] A thin film transistor including a stacked buffer layer according to one embodiment of the present invention has a low off-state current. A semiconductor device including such a thin film transistor can provide high electrical characteristics and high reliability. In addition, the capacitance can be increased from the semiconductor layer 103 toward the source electrode layer or the drain electrode layer. By providing a gradient so that the rear density increases, the semiconductor layer 103 and the source electrode layer or The contact resistance between the drain electrode layer and the second buffer layer can be reduced. By doing so, the electric field concentrated at the junction interface with the semiconductor layer 103 can be further alleviated. .

[0112] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0113] (Fourth embodiment) In this embodiment, the shape and manufacturing method of the thin film transistor are partially different from those in Embodiment 1. Therefore, the other steps can be performed in the same manner as in the first embodiment, and the same Repetitive descriptions of parts or parts having similar functions and steps will be omitted.

[0114] In this embodiment mode, a thin film transistor 174 used in a display device and a manufacturing process thereof will be described. 9 and 10. FIG. 9(A1) is a plan view of the thin film transistor 174. 9(A2) and 10 are the thin film transistors and the thin film transistors of the line D1-D2 in FIG. 9(A1). 1A and 1B are cross-sectional views showing the manufacturing process thereof.

[0115] As shown in FIGS. 9A and 9B, a gate electrode layer 101, a semiconductor layer 103, and a gate electrode layer 104 are formed on a substrate 100. , buffer layers 104a and 104b, source and drain electrode layers 105a and 105b A thin film transistor 174 including:

[0116] The semiconductor layer 103 is an oxide semiconductor layer containing In, Ga, and Zn. The reference numerals 4a and 104b denote metal oxide layers having n-type conductivity. Area(n + The buffer layers 104a and 104b functioning as a buffer layer are capacitively coupled to the semiconductor layer 103. The rear concentration is high.

[0117] The semiconductor layer 103 is connected to a source electrode layer or a drain electrode layer 105a via a buffer layer 104a. The source electrode layer or the drain electrode layer 105b is electrically connected to the buffer layer 104b. It continues.

[0118] The manufacturing process of the thin film transistor 174 will be described with reference to FIG. Next, a gate electrode layer 101 is formed on the gate electrode layer 101. Next, a gate insulating layer 102, In, G a semiconductor film 131 which is an oxide semiconductor film containing Zn, and a metal oxide film having n-type conductivity. A nitride film 132 and a conductive film 133 are formed in this order (see FIG. 10(A)).

[0119] A gate insulating layer 102, a semiconductor film 131 which is an oxide semiconductor film containing In, Ga, and Zn, The metal oxide film 132 and the conductive film 133 having n-type conductivity are then heated without being exposed to the air. By continuously forming films without exposing them to the atmosphere, atmospheric deposition is possible. The interfaces of the layers can be formed without being contaminated by impurity elements floating in the atmosphere or by chemicals. Therefore, variations in the characteristics of the thin film transistors can be reduced.

[0120] In this embodiment, an example is given in which exposure is performed using a high-contrast mask to form the mask 135. A resist is formed to form a mask 135. The resist may be a positive resist or A positive resist is used here.

[0121] Next, a multi-tone mask is used as a photomask to irradiate the resist with light. Expose to light.

[0122] A multi-tone mask has three exposure levels: exposed, intermediately exposed, and unexposed. This mask can produce multiple (typically two types) Therefore, it is possible to form a resist mask having a region of thickness of 1000 nm. By using a photomask, it is possible to reduce the number of photomasks.

[0123] Typical examples of multi-tone masks include gray-tone masks and half-tone masks.

[0124] The gray-tone mask is a mask that includes a light-transmitting substrate, a light-shielding portion formed thereon, and a diffraction grating. The light transmittance is 0% in the light-shielding area. The spacing between light-transmitting parts such as dots, meshes, etc. is set to be equal to or less than the resolution limit of the light used for exposure. By doing so, it is possible to control the light transmittance. Use slits, dots, meshes, or non-periodic slits, dots, or meshes. It is possible.

[0125] The light-transmitting substrate may be a light-transmitting substrate such as quartz. The diffraction grating can be formed using a light-absorbing, light-shielding material such as chromium or chromium oxide. do.

[0126] When the gray-tone mask is irradiated with exposure light, the light transmittance in the light-shielding area is 0%. Therefore, the light transmittance is 100% in the area where the light blocking portion and the diffraction grating are not provided. In the case of a diffraction grating, the light transmittance can be adjusted in the range of 10 to 70%. The transmittance can be adjusted by adjusting the spacing and pitch of the slits, dots, or meshes of the diffraction grating. It is more possible.

[0127] The halftone mask is a mask that includes a light-transmitting substrate and a semi-transmitting portion and a light-shielding portion formed thereon. The semi-transparent part is made up of MoSiN, MoSi, MoSiO, MoSiON, and Cr The light-shielding part is made of a light-shielding material that absorbs light, such as chromium or chromium oxide. It can be formed using materials.

[0128] When exposure light is irradiated onto a half-tone mask, the light transmittance is 0% in the light-shielding area. Therefore, the light transmittance is 100% in the area where no light-shielding portion or semi-transparent portion is provided. In the semi-transparent portion, the light transmittance can be adjusted in the range of 10 to 70%. The transmittance can be adjusted by adjusting the material of the semi-transparent portion.

[0129] After exposure using a multi-tone mask, development is performed to obtain a film thickness of 100 μm, as shown in FIG. 10(B). A mask 135 can be formed with different regions.

[0130] Next, the semiconductor film 131, the metal oxide film 132, and the conductive film 133 are etched using a mask 135. As a result, the semiconductor layer 103 and the metal oxide film 13 having n-type conductivity are separated. 7 and a conductive film 138 can be formed (see FIG. 10B).

[0131] Next, the mask 135 is ashed. As a result, the area of ​​the mask is reduced and the thickness is reduced. At this time, the resist of the mask in the thin film region (which overlaps with a part of the gate electrode layer 101) is The regions (which are to be removed) can be removed to form the isolated mask 139 (see FIG. 10(C)). Light. ).

[0132] The conductive film 138 is etched using the mask 139, and the source or drain electrode layer 1 As in the present embodiment, the conductive film 138 is formed by wet etching. Then, the conductive film 138 is isotropically etched, and the edge of the mask 139 and the source The ends of the source electrode layer or drain electrode layer 105a, 105b are not aligned and are set back. The metal oxide film 1 having n-type conductivity is formed on the outside of the drain electrode layer 105a, 105b. 37 and the semiconductor layer 103 are formed in a protruding shape. The metal oxide film 137 having the pattern is etched to form the buffer layers 104a and 104b. (See FIG. 10(D)). Note that the etching of the metal oxide film 137 with respect to the semiconductor layer 103 When the etching selectivity is small, the semiconductor layer 1 is etched away when the metal oxide film 137 is etched. The exposed area of ​​03 is partially etched to have a groove (not shown).

[0133] After this, the mask 139 is removed.

[0134] Through the above steps, the thin film transistor 174 shown in FIGS. 9(A) and 9(B) can be manufactured. .

[0135] As in this embodiment, a plurality of (typically two types of) thicknesses are formed using a multi-tone mask. By using a resist mask with regions, the number of resist masks can be reduced. This simplifies the process and reduces costs.

[0136] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0137] (Embodiment 5) Here, at least the gate insulating film and the oxide semiconductor layer are stacked without being exposed to the air. An example of fabricating an inverted staggered thin film transistor by successive film deposition is shown below. The steps up to the step of performing the above are shown, and the subsequent steps are in accordance with any one of the first to fourth embodiments. A thin film transistor can be fabricated by using the above method.

[0138] In this specification, continuous film formation refers to a process from a first film formation process performed by sputtering to a second film formation process performed by sputtering. During the series of processes up to the film formation process, the atmosphere in which the substrate is placed is contaminated, such as air. Always keep the device in a vacuum or inert gas atmosphere (nitrogen or rare gas atmosphere) without contact with the atmosphere. By performing continuous film formation, the quality of the processed substrate is improved. Film formation can be performed while avoiding re-adhesion of moisture and the like to the plate.

[0139] A series of processes from the first film formation process to the second film formation process are carried out in the same chamber. is considered to be within the scope of continuous film formation in this specification.

[0140] In addition, a series of processes from the first film formation process to the second film formation process are carried out in different chambers. In this case, after the first film formation step is completed, the substrate is transported between chambers without being exposed to the atmosphere. The application of a second film is also considered to be within the scope of successive film formation in this specification.

[0141] Between the first and second film-forming steps, a substrate transfer step, an alignment step, and a slow cooling step are performed. a step of heating or cooling the substrate to a temperature required for the first step or the second step, Even if the film thickness is small, it is considered to be within the scope of continuous film formation in this specification.

[0142] However, processes that use liquids, such as cleaning, wet etching, and resist formation, are the first If the film formation is performed between the first film formation process and the second film formation process, it does not fall within the scope of continuous film formation as defined in this specification. Let's say that doesn't happen.

[0143] When continuous film formation is performed without exposure to the atmosphere, a multi-chamber manufacturing system such as that shown in Figure 12 is used. It is preferable to use a manufacturing device.

[0144] The manufacturing equipment is provided at its center with a transport mechanism (typically a transport robot 81) for transporting substrates. The transfer chamber 80 is provided with a plurality of chambers for transferring substrates into and out of the transfer chamber 80. A cassette chamber 82 is connected to the cassette chamber 82, in which a cassette case for storing several discs is set.

[0145] Furthermore, the transfer chamber 80 is connected to a plurality of processing chambers via gate valves 84 to 88, respectively. Here, an example is shown in which five processing chambers are connected to a transfer chamber 80 having a hexagonal top surface. By changing the shape of the top surface of the transfer chamber, the number of process chambers that can be connected can be changed. For example, a square shape allows three processing chambers to be connected, and an octagonal shape allows seven processing chambers to be connected. do.

[0146] At least one of the five processing chambers is a sputtering chamber. The sputtering chamber has at least a sputtering target, The device includes a power application mechanism for sputtering the target, a gas introduction means, and a means for holding the substrate in a predetermined position. The sputtering chamber is equipped with a substrate holder and other components. The sputtering chamber is provided with a pressure control means for controlling the pressure inside the chamber.

[0147] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply for the sputtering power source, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used to deposit insulating films, while the DC sputtering method is mainly used to deposit metal films. It is used for.

[0148] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0149] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There are sputtering devices that use this method.

[0150] The sputtering chamber is suitably used for the various sputtering methods described above.

[0151] In addition, as a film formation method, a chemical reaction is caused between the target material and the sputtering gas components during film formation. The reactive sputtering method for forming these compound thin films and the application of voltage to the substrate during film formation are also used. There is also a bias sputtering method.

[0152] In addition, one of the five processing chambers is used for preheating the substrate before sputtering. a heating chamber for performing sputtering, a cooling chamber for cooling the substrate after sputtering, or This chamber is used for plasma processing.

[0153] Next, an example of the operation of the manufacturing apparatus will be described.

[0154] A substrate cassette containing substrates 94 with the film-forming surface facing downward is set in the cassette chamber 82. The cassette chamber 82 is decompressed by a vacuum exhaust means provided in the cassette chamber 82. The inside of each processing chamber and the transfer chamber 80 is depressurized in advance by the vacuum exhaust means provided therein. This prevents the substrate from coming into contact with the atmosphere while being transported between the processing chambers. It is possible to maintain a clean state without

[0155] The substrate 94 with the film-forming surface facing downward is provided with at least a gate electrode in advance. For example, a silicon nitride film or a nitriding oxide film obtained by plasma CVD between the substrate and the gate electrode A base insulating film such as a silicon dioxide film may be provided. When a silicon substrate is used, the insulating film under it is necessary to prevent mobile ions such as sodium from the substrate from It penetrates into the body region and has the effect of suppressing changes in the electrical characteristics of the TFT.

[0156] Here, a silicon nitride film covering the gate electrode is formed by plasma CVD, and the first gate layer is The silicon nitride film formed by the plasma CVD method is dense. By using it as the first gate insulating film, it is possible to prevent pinholes from occurring. Although an example in which the gate insulating film is a laminated film is shown here, it is not particularly limited, and may be a single layer or a three-layer The above stacked layers may also be used.

[0157] Next, the gate valve 83 is opened and the first substrate 94 is transferred to the cassette by the transfer robot 81. Then, the gate valve 84 is opened and the wafer is transferred into the first processing chamber 89. In the first processing chamber 89, the substrate is heated by a heater or a lamp. In particular, moisture on the gate insulating film can cause the TFT to malfunction. Since there is a risk of the thermal properties changing, it is effective to heat the cassette before sputtering. If the moisture is sufficiently removed when the substrate is set in the chamber 82, this heating process can be performed It is unnecessary.

[0158] In addition, a plasma processing means is provided in the first processing chamber 89, and a plasma is applied to the surface of the first gate insulating film. In addition, a heating means may be provided in the cassette chamber 82 to heat the water in the cassette chamber 82. Heating may be performed to remove the residue.

[0159] Next, the gate valve 84 is opened and the substrate is transported to the transport chamber 80 by the transport robot 81. The gate valve 85 is opened, the substrate is transferred into the second processing chamber 90, and the gate valve 85 is closed.

[0160] Here, the second processing chamber 90 is a sputtering chamber using an RF magnetron sputtering method. In the second processing chamber 90, a silicon oxide film (SiO As the second layer of gate insulating film, in addition to silicon oxide film, aluminum oxide Al2O3 film, magnesium oxide film (MgOx film), aluminum nitride film ( AlNx film), yttrium oxide film (YOx film), etc. can be used.

[0161] In addition, a small amount of halogen elements, such as fluorine or chlorine, is added to the second layer of gate insulating film. Alternatively, mobile ions such as sodium may be immobilized. Sputtering is performed by introducing a gas containing a halogen element into the chamber. When introducing a gas containing chlorine, it is necessary to provide a detoxification device in the exhaust means of the chamber. The concentration of halogen elements contained in the insulating film was measured using SIMS (Secondary Ion Mass Spectrometer). The concentration peak obtained by analysis is 1 x 10 15 cm -3 More than 1×10 20 cm -3 below It is preferable to set it within the range.

[0162] When obtaining an SiOx film, artificial quartz is used as the target, and a rare gas, typically argon, is used. A sputtering method using a silicon target and a chemical reaction with oxygen gas A reactive sputtering method can be used to obtain a SiOx film by sputtering oxygen. In order to include as much oxygen as possible in the SiOx film, artificial quartz is used as the target. Sputtering was performed in an atmosphere containing 90% or more oxygen and 10% or less Ar. The oxygen-excess SiOx film is formed by etching.

[0163] After the SiOx film is formed, the gate valve 85 is opened without exposing the substrate to the air. 1 to transfer the substrate to the transfer chamber 80, and then the gate valve 86 is opened to transfer the substrate into the third processing chamber 91. Then, the gate valve 86 is closed.

[0164] Here, the third processing chamber 91 is a sputtering chamber using a DC magnetron sputtering method. In the third processing chamber 91, an oxide semiconductor containing In, Ga, and Zn is formed as a semiconductor layer. Conductive film (IGZO film) is formed. Oxide semiconductor target containing In, Ga, and Zn The film can be formed using an oxygen gas under a rare gas atmosphere. In order to incorporate as many elements as possible into the IGZO film, In, Ga, and Z were used as targets. Using an oxide semiconductor containing n, under an atmosphere of only oxygen or an atmosphere containing 90% or more oxygen and A The sputtering was performed by pulse DC sputtering in an atmosphere with an oxygen content of 10% or less. An IGZO film is formed.

[0165] In this way, the oxygen-rich SiOx film and the oxygen-rich IGZO film are grown without contact with the air. By forming films continuously, the interface between the films containing excess oxygen is stabilized, improving the reliability of the TFT. If the substrate is exposed to the air before the IGZO film is formed, moisture and other Adhesion can adversely affect the interface state, resulting in variations in threshold voltage, deterioration of electrical characteristics, and This may cause symptoms such as the TFT turning on. By continuously depositing the film without contact with the atmosphere, hydrogen compounds exist at the interface. Therefore, by forming films continuously, the variation in threshold voltage can be reduced. It is also desirable to prevent deterioration of electrical characteristics and to reduce the shift of the TFT to the normally-on side. Or shifting can be eliminated.

[0166] In addition, a synthetic quartz target and In, Ga, and Zn-containing oxide semiconductor targets are placed, and stacked sequentially using a shutter. By using the shutter, it is possible to perform continuous film formation in the same chamber. The target is placed between the target and the substrate, and the shutter is opened to allow film deposition. The advantage of stacking in the same chamber is that This reduces the number of chambers used and reduces the number of parts required while transferring substrates between different chambers. The advantage is that it is possible to prevent tickles and the like from adhering to the substrate.

[0167] Next, the gate valve 86 is opened and the substrate is transported by the transport robot 81 without being exposed to the atmosphere. is transported to the transport chamber 80.

[0168] If it is not a process using a gray-tone mask, the mask is transferred from the manufacturing equipment via the cassette room at this stage. The substrate is then removed and the oxygen-rich IGZO film is patterned using photolithography. However, if a gray-tone mask is used, the following continuous film formation is performed. cormorant.

[0169] Next, the gate valve 87 is opened and the substrate is transferred into the fourth processing chamber 92 without being exposed to the atmosphere. , and close gate valve 87.

[0170] Here, the fourth processing chamber 92 is a sputtering chamber using a DC magnetron sputtering method. In the fourth processing chamber 92, a buffer layer is formed. Here is an example of forming a titanium oxide film (TiOx film) as a metal oxide film that exhibits n-type conductivity. Oxygen gas is introduced into the sputtering chamber of the fourth processing chamber 92, and the titanium target The TiOx film is formed by reactive sputtering using a titanium target. A target containing In, Ga, or Zn may be used. A target containing Mg or Al may be used as the get. This TiOx film is used as the source region. Or it functions as a drain region.

[0171] Note that a layer of a semiconductor layer is formed between the oxide semiconductor film containing In, Ga, and Zn and the buffer layer. The second buffer layer ( n - The second buffer layer may be formed by successive deposition of In, Ga, and When using a mixed layer of an oxide semiconductor layer containing Zn and a buffer layer, Both an oxide semiconductor target containing a and Zn and a titanium target were placed. First, close the shutter of the titanium target. Then, an oxide semiconductor film containing In, Ga, and Zn is formed. Open the shutter to simultaneously deposit an oxide semiconductor film containing In, Ga, and Zn and TiOx. Next, the shutter of the oxide semiconductor target containing In, Ga, and Zn is closed. By forming a TiOx film, n - layer, n + The layers can be formed in order. can.

[0172] Next, the gate valve 87 is opened and the substrate is transported by the transport robot 81 without being exposed to the atmosphere. The wafer is transferred to the transfer chamber 80, and the gate valve 88 is opened to transfer the wafer into the fifth processing chamber 93. Close valve 88.

[0173] Here, the fifth processing chamber 93 is a sputtering chamber using a DC magnetron sputtering method. In the fifth processing chamber 93, a metal multilayer film that will become a source electrode or a drain electrode is formed. The fifth processing chamber 93 is provided with a titanium target and an aluminum target in a sputtering chamber. By setting both the target and the shutter, the film is laminated in order and continuously formed. Therefore, the layers are stacked in the same chamber. Here, an aluminum film is stacked on a titanium film. Then, a titanium film is laminated on the aluminum film.

[0174] In this way, when a gray-tone mask is used, oxygen-rich Si It is possible to continuously form an Ox film, an oxygen-excess IGZO film, a metal oxide film, and a metal multilayer film. In particular, the interface state of the oxygen-excess IGZO film becomes more stable, improving the reliability of the TFT. If the substrate is exposed to the air before or after the IGZO film is formed, moisture may adhere to the substrate and cause problems. It adversely affects the surface condition, causing variations in threshold voltage, deterioration of electrical characteristics, and the normally-on TF Water is a hydrogen compound, and when it comes into contact with the air, it can cause symptoms such as By continuously depositing the film without any cracks, hydrogen compounds are present at the interface of the IGZO film. Therefore, by forming four layers in succession, the variation in threshold voltage can be eliminated. It reduces the risk of electric shock, prevents deterioration of electrical characteristics, and reduces the shift of TFT to the normally-on side. This can reduce, and preferably eliminate, shifting.

[0175] Furthermore, by successively depositing a metal oxide film and a metal multilayer film without exposure to the atmosphere, A good interface state can be achieved between the metal oxide film and the metal multilayer film, and contact resistance can be reduced.

[0176] In addition, the fourth processing chamber 92 is not used, and the fifth processing chamber 93 is used to form a TiOx film and a metal multilayer film. In this case, a shutter is used to sequentially stack the layers and form the films continuously. The lamination is performed in the same chamber by using a shutter. The target is shielded, oxygen gas is introduced and reactive sputtering is performed to produce titanium oxide. Next, oxygen gas is discharged from the fifth processing chamber 93, and an arsenic film (TiOx film) is formed. Then, a titanium film is formed by sputtering using a fluorine-containing gas. The target is shielded with a shutter, and an aluminum film is laminated on the titanium film. The aluminum target is shielded by a shield, and a titanium film is laminated on the aluminum film. The advantage of stacking in one chamber is that it reduces the number of chambers used and allows for different It is possible to prevent particles from adhering to the substrate while transferring the substrate between chambers. is.

[0177] The above process is repeated to process multiple substrates by performing film deposition on the substrates in the cassette case. After completion, the vacuum in the cassette chamber is released to the atmosphere, and the substrate and cassette are removed.

[0178] In addition, in the first processing chamber 89, a heat treatment after the formation of the oxygen-excessive IGZO film, specifically, 30 Heat treatment can be carried out at 0°C to 400°C, preferably at 350°C or higher. By performing the heat treatment, the electrical characteristics of the inverted staggered thin film transistor can be improved. This heat treatment is not particularly limited as long as it is performed after the formation of an oxygen-excess IGZO film. For example, it can be performed immediately after forming an oxygen-excessive IGZO film or immediately after forming a metal multilayer film.

[0179] Next, each laminated film is patterned using a gray-tone mask. It may be formed by wet etching, or by etching in a plurality of steps. Selective etching may also be performed.

[0180] The subsequent steps are the same as those of the fourth embodiment, and an inverted staggered thin film transistor can be fabricated. Cut.

[0181] Here, we have explained the multi-chamber manufacturing equipment as an example, but if you use a sputtering chamber, Using in-line manufacturing equipment connected in series, continuous film formation is carried out without exposure to the atmosphere. That's fine.

[0182] The apparatus shown in FIG. 12 is a so-called face-down type in which the substrate is set with the surface on which the film is to be formed facing downwards. However, the substrate may be placed vertically in the processing chamber. This processing chamber has the advantage of having a smaller footprint than a face-down type processing chamber. Furthermore, this is effective when using a large-area substrate that may bend due to its own weight.

[0183] (Embodiment 6) In this embodiment, at least a part of the driver circuit and a thin film disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0184] The thin film transistors disposed in the pixel portion are formed according to any one of Embodiments 1 to 4. The thin film transistors shown in the first to fourth embodiments are n-channel TFTs, so that the Among them, part of the driver circuit can be configured with n-channel TFTs. It is formed on the same substrate as the resistor.

[0185] An example of a block diagram of an active matrix liquid crystal display device is shown in FIG. The display device shown in (A) has a pixel section 5300 having a plurality of pixels each having a display element on a substrate 5300. 301, a scanning line driver circuit 5302 for selecting each pixel, and a video signal to the selected pixel. The pixel portion 5301 has a signal line driver circuit 5303 for controlling the input of the signal line driver circuit 5303. A plurality of signal lines S1 to Sm (not shown) are arranged extending from the circuit 5303 in the column direction. The signal line driver circuit 5303 is connected to the signal line driver circuit 5303 and extends in the row direction from the scanning line driver circuit 5302. The scanning line driving circuit 5302 is connected to the scanning line driving circuit 5303 by a plurality of scanning lines G1 to Gn (not shown). A plurality of electrodes arranged in a matrix corresponding to the signal lines S1 to Sm and the scanning lines G1 to Gn are provided. Each pixel is connected to a signal line Sj (one of the signal lines S1 to Sm). The scanning line Gi (any one of the scanning lines G1 to Gn) is connected to the scanning line Gi.

[0186] The thin film transistors described in Embodiments 1 to 4 are n-channel TFTs. A signal line driver circuit configured with channel type TFTs will be described with reference to FIG.

[0187] The signal line driver circuit shown in FIG. 14 includes a driver IC 5601 and a group of switches 5602_1 to 5602_56. 02_M, a first wiring 5611, a second wiring 5612, a third wiring 5613 and a wiring 56 Each of the switch groups 5602_1 to 5602_M includes: A first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor It has a transistor 5603c.

[0188] The driver IC 5601 is connected to a first wiring 5611, a second wiring 5612, and a third wiring 5613. and are connected to the wirings 5621_1 to 5621_M. 5602_M are connected to the first wiring 5611, the second wiring 5612, and the third wiring 561 3 and wiring 5621_1 to 5621_5 corresponding to the switch groups 5602_1 to 5602_M, respectively. Each of the wirings 5621_1 to 5621_M is connected to the first A thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor For example, the wiring 5621 in the Jth column is connected to three signal lines via a resistor 5603c. _J (one of the wirings 5621_1 to 5621_M) is connected to the switch group 5602 The first thin film transistor 5603a, the second thin film transistor 5603b, and and the third thin film transistor 5603c, the signal line Sj-1, the signal line Sj, the signal line S j+1 is connected to the

[0189] The first wiring 5611, the second wiring 5612, and the third wiring 5613 are each connected to a signal line. The number is entered.

[0190] It is desirable that the driver IC 5601 be formed on a single crystal substrate. The switch groups 5602_1 to 5602_M are the same as the pixel units shown in the first to fourth embodiments. It is desirable that the driver IC 5601 and the switch are formed on the board. The groups 5602_1 to 5602_M may be connected via an FPC or the like.

[0191] Next, the operation of the signal line driver circuit shown in FIG. 14 will be described with reference to the timing chart of FIG. The timing chart in FIG. 15 is explained with reference to the timing chart in FIG. 15 when the i-th scanning line Gi is selected. Furthermore, the timing chart shows the selection period of the i-th scanning line Gi. is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, when a scanning line of another row is selected, the signal line driving circuit of FIG. In this case, the same operation as in FIG. 15 is performed.

[0192] In the timing chart of FIG. 15, the wiring 5621_J in the Jth column is connected to the first thin-film transistor. a second thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor 560 When connected to signal line Sj-1, signal line Sj, and signal line Sj+1 via 3c It shows.

[0193] The timing chart of FIG. 15 shows the timing when the i-th scanning line Gi is selected, The on / off timing 5703a of the first thin film transistor 5603a, The on / off timing 5703b of the third thin film transistor 56 The on / off timing of 03c is input to 5703c and the J-th row wiring 5621_J. Illustrated is signal 5721_J.

[0194] The wirings 5621_1 to 5621_M are connected to the first sub-selection period T1 and the second sub-selection period T2. In the first sub-selection period T2 and the third sub-selection period T3, different video signals are input. For example, the video signal input to the wiring 5621_J in the first sub-selection period T1 is The signal is input to the signal line Sj-1 and input to the wiring 5621_J in the second sub-selection period T2. The video signal to be output is input to the signal line Sj, and the signal is output to the wiring 5621 during the third sub-selection period T3. The video signal input to the first sub-selection period is input to the signal line Sj+1. During the period T1, the second sub-selection period T2, and the third sub-selection period T3, the wiring 5621_ The video signals input to J are Data_j-1, Data_j, and Data_j+ Let's say it's 1.

[0195] As shown in FIG. 15, in the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c At this time, Data_j-1 input to the wiring 5621_J is turned off. The signal is input to the signal line Sj-1 via the transistor 5603a. Second sub-selection period T2 In this case, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a The third thin film transistor 5603c is turned off. The output Data_j is input to the signal line Sj via the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first The first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the third thin film transistor 56 It is input to the signal line Sj+1 via 03c.

[0196] From the above, the signal line driver circuit in FIG. 14 can achieve the following by dividing one gate selection period into three. During one gate selection period, a video signal is input from one wiring 5621 to three signal lines. Therefore, the signal line driver circuit of FIG. The number of connections between the substrate on which the display is mounted and the substrate on which the pixel section is formed is reduced to about one-third of the number of signal lines. By reducing the number of connections to about one-third, the signal line driver circuit of FIG. This can improve productivity and yield.

[0197] As shown in Figure 14, one gate selection period is divided into multiple sub-selection periods, and multiple sub-selection periods are During each selection period, a video signal is input from one line to each of multiple signal lines. As long as this can be achieved, there are no limitations on the arrangement, number, driving method, etc. of the thin film transistors.

[0198] For example, three or more signal lines are connected to one wiring in each of three or more sub-selection periods. When a video signal is input to each, a thin film transistor and a thin film transistor are controlled. However, it is necessary to divide one gate selection period into four or more sub-selection periods. Therefore, one gate selection period is divided into two or Preferably, it is divided into three sub-selection periods.

[0199] As another example, as shown in the timing chart of FIG. 16, one selection period is precharged. The first sub-selection period Tp, the second sub-selection period T2, the third sub-selection period T 3. Furthermore, in the timing chart of FIG. 16, the scanning line Gi of the i-th row is selected. the timing at which the first thin film transistor 5603a is turned on and off; 03a, the on / off timing 5803b of the second thin film transistor 5603b, The on / off timing 5803c of the thin film transistor 5603c and the J-th column wiring 5 16 shows the signal 5821_J input to the pre-channel 621_J. During the load period Tp, the first thin film transistor 5603a and the second thin film transistor 56 The third thin film transistor 5603b and the third thin film transistor 5603c are turned on. The precharge voltage Vp input to the first thin film transistor 5603a and the second thin film transistor 5603b is and the third thin film transistor 5603b and the third thin film transistor 5603c are connected to the signal line S j-1, signal line Sj, and signal line Sj+1. The first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned on. At this time, the thin film transistor 5603c is turned off. ata_j-1 is input to the signal line Sj-1 via the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first The first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, Data_j input to the wiring 5621_J is input to the second thin film transistor 5603 b is input to the signal line Sj. In the third sub-selection period T3, The first thin film transistor 5603a and the second thin film transistor 5603c are turned on. At this time, Data_j+1 input to the wiring 5621_J is , and is input to the signal line Sj+1 via the third thin film transistor 5603c.

[0200] From the above, the signal line driver circuit of FIG. 14 to which the timing chart of FIG. 16 is applied By providing a precharge selection period before the block selection period, the signal lines can be precharged. This allows for high-speed writing of video signals to the pixels. 15 are denoted by the same reference numerals, and the same parts or similar functions are shown. A detailed description of the portion having the symbol will be omitted.

[0201] The configuration of the scanning line driving circuit will be described. The scanning line driving circuit includes a shift register, a buffer, and a In some cases, a level shifter may be included. In the circuit, a clock signal (CLK) and a start pulse signal (SP) are input to the shift register. ) is input, the selection signal is generated. The generated selection signal is The signal is buffered and amplified in the scanning line and then supplied to the corresponding scanning line. The gate electrodes of the transistors are connected. Since they must all be turned on at the same time, the buffer must be able to pass a large current. It is used.

[0202] One form of a shift register used as part of a scanning line driving circuit is shown in FIGS. 17 and 18. I will explain.

[0203] The circuit configuration of the shift register is shown in Figure 17. The shift register shown in Figure 17 has multiple free The flip-flops are composed of flip-flops (flip-flops 5701_1 to 5701_n). The first clock signal, the second clock signal, the start pulse signal, and the reset signal are input. It works like this.

[0204] The connection relationship of the shift register in Fig. 17 will be explained. The shift register in Fig. 17 has i-stage The first flip-flop 5701_i (flip-flops 5701_1 to 5701_n) Either one) is the first wiring 5501 shown in FIG. 18 connected to the seventh wiring 5717_i-1. 18 is connected to the seventh wiring 5717_i+1, and 18 is connected to the seventh wiring 5717_i, and The sixth wiring 5506 is connected to the fifth wiring 5715 .

[0205] In addition, the fourth wiring 5504 shown in FIG. 18 is the second wiring in the odd-numbered flip-flops. 5712, and in the even-numbered flip-flops, it is connected to the third wiring 5713. The fifth wiring 5505 shown in FIG.

[0206] However, the first wiring 5501 shown in FIG. 18 of the first-stage flip-flop 5701_1 is 18 of the n-th stage flip-flop 5701_n. The second wiring 5502 is connected to the sixth wiring 5716 .

[0207] The first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 57 16 can be called the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fourth wiring 5714 and the fifth wiring 5715 are respectively connected to the first power supply line and the This may also be called the power line 2.

[0208] Next, the details of the flip-flop shown in FIG. 17 are shown in FIG. 18. The flip-flop includes a first thin film transistor 5571, a second thin film transistor 5572, A third thin film transistor 5573, a fourth thin film transistor 5574, a fifth thin film transistor a sixth thin film transistor 5575, a sixth thin film transistor 5576, a seventh thin film transistor 5577, and and an eighth thin film transistor 5578. A second thin film transistor 5572, a third thin film transistor 5573, a fourth thin film transistor a fifth thin film transistor 5574, a fifth thin film transistor 5575, a sixth thin film transistor 5576, The seventh thin film transistor 5577 and the eighth thin film transistor 5578 are n-channel A transistor in which the gate-source voltage (Vgs) exceeds the threshold voltage (Vth) When this occurs, the device is in a conductive state.

[0209] Next, the connection configuration of the flip-flop shown in FIG. 17 will be described below.

[0210] A first electrode (either a source electrode or a drain electrode) of the first thin film transistor 5571 is connected to a fourth wiring 5504, and a second electrode (source) of the first thin film transistor 5571 is connected to a The other of the source electrode and the drain electrode is connected to a third wiring 5503 .

[0211] A first electrode of the second thin film transistor 5572 is connected to the sixth wiring 5506, and A second electrode of the thin film transistor 5572 is connected to a third wiring 5503 .

[0212] A first electrode of the third thin film transistor 5573 is connected to a fifth wiring 5505. The second electrode of the thin film transistor 5573 is the gate electrode of the second thin film transistor 5572. , and the gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505. will be done.

[0213] A first electrode of the fourth thin film transistor 5574 is connected to a sixth wiring 5506, and The second electrode of the thin film transistor 5574 is the gate electrode of the second thin film transistor 5572. , and the gate electrode of the fourth thin film transistor 5574 is connected to the first thin film transistor 5 It is connected to the gate electrode of 571.

[0214] A first electrode of the fifth thin film transistor 5575 is connected to a fifth wiring 5505. The second electrode of the thin film transistor 5575 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501. will be done.

[0215] A first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506. The second electrode of the thin film transistor 5576 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the sixth thin film transistor 5576 is connected to the second thin film transistor 5 It is connected to the gate electrode of 572.

[0216] A first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506. The second electrode of the thin film transistor 5577 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502. A first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506. The second electrode of the eighth thin film transistor 5578 is connected to the gate of the second thin film transistor 5572. The gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 550. Connected to 1.

[0217] The gate electrode of the first thin film transistor 5571 and the gate electrode of the fourth thin film transistor 5574 the gate electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor The connection point of the second electrode of the seventh thin film transistor 5576 and the second electrode of the seventh thin film transistor 5577 is Further, the gate electrode of the second thin film transistor 5572, the gate electrode of the third thin film transistor 5573, and the gate electrode of the third thin film transistor 5574 are connected to the gate electrode of the second thin film transistor 5575. a second electrode of the fourth thin film transistor 5573; a second electrode of the fourth thin film transistor 5574; The gate electrode of the sixth thin film transistor 5576 and the gate electrode of the eighth thin film transistor 5578 The connection point of the two electrodes is designated as node 5544.

[0218] The first wiring 5501, the second wiring 5502, the third wiring 5503 and the fourth wiring 5504 are 504 are referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fifth wiring 5505 may be connected to a first power supply line, and the sixth wiring 5506 may be connected to a second power supply line. It can also be called a line.

[0219] In addition, the signal line driver circuit and the scanning line driver circuit are formed by using the n-channel TF The n-channel TFTs shown in Embodiments 1 to 4 can be fabricated using only T. The high mobility of the transistor allows the driving frequency of the driving circuit to be increased. In addition, the n-channel TFTs shown in Embodiments 1 to 4 have a buffer layer made of a metal oxide layer. The parasitic capacitance is reduced, resulting in high frequency characteristics (called f characteristics). The scanning line driver circuits using n-channel TFTs shown in the first to fourth embodiments are operated at high speed. This allows for a higher frame rate or the insertion of a black screen. It is possible.

[0220] Furthermore, the channel width of the transistor of the scanning line driving circuit can be increased, and multiple scanning lines can be formed. By arranging the drive circuit, it is possible to achieve an even higher frame frequency. When multiple scanning line driving circuits are arranged, the scanning line driving circuits for driving the even-numbered scanning lines are The circuit for driving the odd-numbered scanning lines is placed on one side, and the scanning line driving circuit for driving the odd-numbered scanning lines is placed on the other side. By placing the frame frequency at a higher level, it is possible to increase the frame frequency.

[0221] In addition, when an active matrix light-emitting display device is manufactured, multiple light-emitting devices are provided in at least one pixel. In order to arrange a large number of thin film transistors, it is preferable to arrange a plurality of scanning line driving circuits. FIG. 13B shows an example of a block diagram of an active matrix light-emitting display device.

[0222] The display device shown in FIG. 13B has a plurality of pixels each having a display element on a substrate 5400. A pixel section 5401, a first scanning line driver circuit 5402 for selecting each pixel, and a second scanning line driver circuit 5403 for selecting each pixel. circuit 5404 and a signal line driver circuit 540 for controlling the input of a video signal to a selected pixel. 3 and has.

[0223] When a video signal input to a pixel of the display device shown in FIG. 13(B) is in a digital format, Pixels emit or do not emit light by switching transistors on and off. Therefore, the gray scale can be displayed by using the area gray scale method or the time gray scale method. This method divides one pixel into multiple sub-pixels, and each sub-pixel is independently driven based on a video signal. The time gray scale method is a driving method that displays gray scales by changing the time when the pixel emits light. This is a driving method that displays gradation by controlling the interval.

[0224] Light-emitting elements have a higher response speed than liquid crystal elements, making them more suitable for time gray scale modulation than liquid crystal elements. Specifically, when displaying using the time gray scale method, one frame period is divided into multiple subframes. Then, in accordance with the video signal, the light emitting element of the pixel is By dividing the period into multiple subframes, The total length of the period during which pixels actually emit light during one frame is controlled by the video signal. It is possible to control the brightness and display gradation.

[0225] In the light-emitting device shown in FIG. 13(B), one pixel has a switching TFT and a current control TFT. When two TFTs are arranged, the first one is the gate wiring of the switching TFT. The signal input to the scan line is generated by the first scan line driver circuit 5402 and is input to the gate of the current control TFT. A signal to be input to the second scanning line, which is a light source wiring, is generated by a second scanning line driver circuit 5404. The example shows a signal input to the first scanning line and a signal input to the second scanning line. The signal and the signal may be generated by one scanning line driving circuit. The operation of the switching element is controlled by the number of transistors that the switching element has. In this case, a plurality of first scanning lines may be provided for each pixel. The signals input to the first scanning line may all be generated by one scanning line driver circuit, or may be generated by multiple scanning line driver circuits. Alternatively, the signals may be generated by a number of scanning line driving circuits.

[0226] In addition, the driving circuit of the light emitting device can be configured with n-channel TFTs. A part of the driver circuit can be formed on the same substrate as the thin film transistor of the pixel portion. In addition, the signal line driver circuit and the scanning line driver circuit may be formed by using the n-channel TFTs shown in Embodiments 1 to 4. It is also possible to fabricate it using only the above.

[0227] The above-mentioned driving circuit is not limited to liquid crystal display devices and light emitting devices, but may also be used for switching elements and electrical The present invention may also be used in electronic paper, which uses electrically connected elements to drive electronic ink. Paper is also called an electrophoretic display (electrophoretic display) and has the same reading quality as paper. It has the advantages of being easy to use, consuming less power than other display devices, and being able to be made thin and light. It has.

[0228] Electrophoretic displays can be of various forms, but the first one has a positive charge. The microcapsules containing the negatively charged particles and the negatively charged second particles are then mixed with a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to display only the color of the particles that have gathered on one side. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particle and the second particle have different colors (colorless). (including

[0229] Thus, electrophoretic displays are devices in which materials with high dielectric constants move to areas of high electric field. Electrophoretic displays are displays that utilize the so-called dielectrophoretic effect. The polarizing plate and counter substrate required for liquid crystal display devices are not required, and the thickness and weight are reduced by half.

[0230] The microcapsules dispersed in a solvent are called electronic ink. This electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Furthermore, color display is possible by using color filters or particles containing pigments.

[0231] In addition, the above-mentioned micro-electrodes are appropriately arranged on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. Display can be achieved by applying an electric field to the capsule.

[0232] The first particles and the second particles in the microcapsules are made of a conductive material and an insulating material. , semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of electrochromic materials, magnetophoretic materials, and composite materials of these. Just use

[0233] (Embodiment 7) A thin film transistor according to one embodiment of the present invention is manufactured, and the thin film transistor is used in a pixel portion, and A semiconductor device (also called a display device) having a display function can be manufactured by using the semiconductor device in a driver circuit. In addition, the thin film transistor according to one embodiment of the present invention can be used in part or the entirety of a driver circuit. It can be formed integrally on the same substrate as the pixel section to form a system-on-panel.

[0234] The display device includes a display element. The display element includes a liquid crystal element (also called a liquid crystal display element), a light-emitting element, A light-emitting element (also called a light-emitting display element) can be used. This category includes elements whose brightness is controlled by the light emitted from the light source, specifically inorganic EL (Electroluminescent) Also, electronic inks and other electronic devices are also included. A display medium whose contrast changes due to mechanical action can also be applied.

[0235] The display device also includes a panel in which a display element is sealed, and a controller for the panel. Furthermore, one aspect of the present invention is a module in which an IC or the like including the above-mentioned is mounted. In the process of manufacturing a display device, the element substrate corresponds to one form before the display element is completed. The element substrate includes a means for supplying a current to each of the plurality of pixels. Specifically, the substrate may be in a state where only pixel electrodes of the display element are formed, or After forming the conductive film that will become the electrode, but before etching to form the pixel electrode It's fine, and all forms apply.

[0236] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) Modules with printed wiring boards attached to the end of TAB tape or TCP or the display element is mounted on an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which the display device (circuit) is directly mounted.

[0237] In this embodiment, a liquid crystal display device will be described as an example of a semiconductor device according to one embodiment of the present invention.

[0238] 19A and 19B show an active matrix liquid crystal display device to which one embodiment of the present invention is applied. 19(A) is a plan view of the liquid crystal display device, and FIG. 19(B) is a plan view of the liquid crystal display device shown in FIG. 19(A). 1 is a cross-sectional view of a thin film transistor 201 used in a semiconductor device, taken along line VX in FIG. can be manufactured in the same manner as in the thin film transistor described in Embodiment 2, and The present invention relates to a highly reliable thin film transistor including a metal oxide layer having a conductivity type of 1. The thin film transistor shown in the first embodiment, the third embodiment, or the fourth embodiment can also be used in the thin film transistor of this embodiment. It can also be applied as a film transistor 201.

[0239] The liquid crystal display device of this embodiment shown in FIG. 19(A) includes a source wiring layer 202, a multi-gate structure The thin film transistor 201 includes a reverse staggered type, a gate wiring layer 203, and a capacitor wiring layer 204. .

[0240] In addition, in FIG. 19(B), the liquid crystal display device of this embodiment has a multi-gate structure thin film A transistor 201, an insulating layer 211 functioning as a protective film, and an insulating layer functioning as a protective film. 212, an insulating layer 213 that functions as a planarization film, an electrode layer 255 used in a display element, The substrate 200 is provided with an insulating layer 261 and a polarizer 268, which function as an alignment film. an insulating layer 263 that functions as a color filter; an electrode layer 265 that is used for a display element; A colored layer 264 and a substrate 266 on which a polarizing plate 267 is provided are opposed to each other with a liquid crystal layer 262 sandwiched therebetween. and has a liquid crystal display element 260.

[0241] Here, in order to reduce the surface irregularities of the thin film transistor 201 and In order to improve the reliability of 201, the thin film transistor obtained in the second embodiment is The insulating layer 213 functions as a planarization film. The protective film prevents the intrusion of polluting impurities such as organic matter, metals, and water vapor floating in the air. The protective film is a silicon oxide film made by using a CVD method or the like. The insulating film may be formed of a single layer or a stack of a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. In addition, as a protective film, plasma CV is performed using organic silane gas and oxygen as process gas. The silicon oxide film may be formed by the D method.

[0242] Organic silanes are ethyl silicate (TEOS: chemical formula Si(OC2H5)4), tetramethyl Tetramethylcyclotetrasiloxane (TMS: chemical formula Si(CH3)4), TMCTS), Octamethylcyclotetrasiloxane (OMCTS), Hexamethyldisiloxane Silane (HMDS), triethoxysilane (SiH(OC2H5)3), or tris(di)silane Compounds such as methylaminosilane (SiH(N(CH3)2)3).

[0243] An insulating layer 211 is formed as the first layer of the protective film. The insulating layer 211 is made of aluminum film. Here, the insulating layer 211 is formed by oxidizing the silicon dioxide using the plasma CVD method. A silicon film is formed. TEOS and O2 are used as the process gas for forming the silicon oxide film. The flow rate ratio is TEOS\O2=15(sccm)\750(sccm). The substrate temperature during the process is 300°C.

[0244] Further, an insulating layer 212 is formed as the second layer of the protective film. The silicon nitride film is formed using the plasma CVD method. The process gas for forming the silicon nitride film is , SiH4, N2, NH3 and H2 are used. A silicon nitride film is used as one layer of the protective film. When this happens, mobile ions such as sodium penetrate into the semiconductor region and change the electrical properties of the TFT. This can prevent this from happening.

[0245] After forming the protective film, the IGZO semiconductor layer is annealed (300°C to 400°C). It is also possible.

[0246] In addition, an insulating layer 213 is formed as an insulating film that functions as a planarization film. For example, heat-resistant materials such as polyimide, acrylic, benzocyclobutene, polyamide, and epoxy are used. In addition to the above organic materials, low dielectric constant materials (lo wk materials), siloxane resin, PSG (phosphorus glass), BPSG (boron phosphorus glass) Siloxane-based resins can have hydrogen as a substituent, as well as fluorine, alkyl, etc. The compound may have at least one of a hydroxyl group, a methyl group, or an aryl group. The insulating layer 213 may be formed by stacking a plurality of insulating films.

[0247] The siloxane resin is a Si-O- formed material that is made from a siloxane material as a starting material. It corresponds to a resin containing Si bonds. Siloxane resins have substituents that include hydrogen, fluorine, and alkane. The alkyl group may have at least one of an alkyl group, an alkyl group, or an aromatic hydrocarbon.

[0248] The insulating layer 213 can be formed by a CVD method, a sputtering method, a SOG method, a spin-on method, or the like, depending on the material. Coating, dipping, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater When the insulating layer 213 is formed using a material liquid, a baking process is performed. At the same time, annealing (300°C to 400°C) of the IGZO semiconductor layer may be performed. By combining the firing process of the layer 213 with the annealing of the IGZO semiconductor layer, a display device can be efficiently manufactured. It becomes possible to manufacture

[0249] Although FIG. 19 shows an example of a transmissive liquid crystal display device, one embodiment of the present invention is a reflective liquid crystal display device. The present invention can also be applied to semi-transmissive liquid crystal display devices.

[0250] In addition, in the liquid crystal display device of FIG. 19, a polarizing plate 267 is provided on the outer side (viewing side) of the substrate 266, In this example, a colored layer 264 and an electrode layer 265 used for a display element are provided in this order on the inside. The plate 267 may be provided inside the substrate 266. The laminated structure of the polarizing plate and the colored layer may also be the same as that shown in FIG. It is not limited to this, and may be appropriately set depending on the materials of the polarizing plate and the colored layer and the manufacturing process conditions. In addition, a light-shielding film that functions as a black matrix may be provided.

[0251] The electrode layers 255 and 265 functioning as pixel electrode layers are made of indium tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO) ), indium zinc oxide, indium tin oxide doped with silicon oxide, etc. A conductive material having such a property can be used.

[0252] The electrode layers 255 and 265 are made of a conductive material containing a conductive polymer. The pixel electrode formed using the conductive composition can be formed using the following: Sheet resistance is 10,000 Ω / □ or less, and light transmittance at a wavelength of 550 nm is 70% or more. It is also preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω cm. It is preferable that:

[0253] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0254] The liquid crystal material of the liquid crystal layer 262 may be a lyotropic liquid crystal, a thermotropic liquid crystal, a low molecular weight liquid crystal, or a crystalline liquid crystal. Polymer liquid crystals, discotic liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. are used. The liquid crystal material can be in a nematic phase, a cholesteric phase, a cholesteric blue phase, or a nematic phase, depending on the conditions. phase, smectic phase, smectic blue phase, cubic phase, smectic D phase, The cholesteric blue phase and smectic blue phase are shown. The helical pitch is relatively short, less than 500 nm, and the cholesteric or smectic phase The orientation of the liquid crystal material has a double twist structure. The orientational order changes when a voltage is applied, resulting in optical changes. The blue phase is optically isotropic, so it does not depend on the viewing angle and can be used to form an alignment film. This eliminates the need for a display, thereby improving the quality of the displayed image and reducing costs.

[0255] Through the above steps, a highly reliable liquid crystal display device can be manufactured as a semiconductor device. .

[0256] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0257] (Embodiment 8) In this embodiment, an example of electronic paper will be described as a semiconductor device according to one embodiment of the present invention.

[0258] FIG. 26 shows an example of an active matrix type semiconductor device to which one embodiment of the present invention is applied. The thin film transistor 581 used in the semiconductor device is It can be fabricated in the same way as the thin-film transistor shown in Example 2, and has an IGZO semiconductor layer and n-type conductivity. The thin film transistor is highly reliable and includes a metal oxide layer. The thin film transistor shown in the third embodiment or the fourth embodiment is also a thin film transistor of the present embodiment. It can also be applied as data 581.

[0259] The electronic paper in Figure 26 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. and a potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of spherical particles by generating a magnetic field.

[0260] The thin film transistor 581 on the substrate 580 is a multi-gate structure inverted staggered thin film transistor. The first electrode layer 587 and the insulating layer 588 are connected by a source electrode layer or a drain electrode layer. 85, the insulating layer 584, and the insulating layer 583 are in contact with each other through openings formed therein and are electrically connected. Between the first electrode layer 587 and the second electrode layer 588 provided on the substrate 596, a black A cavity 590 having a white area 590a and a white area 590b, surrounded by a liquid-filled cavity 590. The spherical particle 589 is surrounded by a filler 59 such as a resin. It is filled with 5 (see Figure 26).

[0261] Also, instead of the twist ball, an electrophoretic element can be used. and a diameter of 10 μm to 20 μm that contains positively charged white particles and negatively charged black particles. Microcapsules of about 0 μm in size are used. When an electric field is applied by the first and second electrode layers, the microcapsules turn white. White particles and black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is an electrophoretic display element, which is generally called electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display unit, the image that has been displayed can be retained. Therefore, the semiconductor device with a display function (simply a display device, or a device equipped with a display device) is The ability to preserve the displayed image even when the device (also known as a semiconductor device) is moved away This becomes possible.

[0262] Through the above steps, electronic paper with high reliability as a semiconductor device can be manufactured. .

[0263] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0264] (Embodiment 9) In this embodiment, an example of a light-emitting display device will be described as a semiconductor device according to one embodiment of the present invention. The display element of the display device is a light-emitting element that uses electroluminescence. The light-emitting element that uses electroluminescence is an organic compound that is used as the light-emitting material. Generally, the former is an organic EL element, and the latter is an inorganic compound. These are called inorganic EL elements.

[0265] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0266] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0267] 22A and 22B show an active matrix semiconductor device as an example of a semiconductor device to which one embodiment of the present invention is applied. 22(A) is a plan view of the light-emitting display device, and FIG. 22(B) is a cross-sectional view taken along the line YZ in FIG. 22(A). 1 shows an equivalent circuit of an optical display device.

[0268] The thin film transistors 301 and 302 used in the semiconductor device are the same as those in the first embodiment and the second embodiment. It can be fabricated in the same manner as the thin film transistor shown in the second embodiment, and the IGZO semiconductor layer and the metal oxide layer and a buffer layer having n-type conductivity, the buffer layer being made of The thin film transistor shown in the third embodiment or the fourth embodiment may also be used as the thin film transistor of the present embodiment. It can also be applied as the transistors 301 and 302.

[0269] The light-emitting display device of this embodiment mode shown in FIGS. 22A and 23 is a thin film transistor having a multi-gate structure. A transistor 301, a thin film transistor 302, a light emitting element 303, a capacitor element 304, a source The thin film transistor 301 includes a power wiring layer 305, a gate wiring layer 306, and a power supply line 308. 302 is an n-channel thin film transistor.

[0270] In addition, in FIG. 22(B), the light emitting display device of this embodiment includes a substrate 300, a thin film transistor, and a a resistor 302, an insulating layer 311, an insulating layer 312, an insulating layer 313, a partition wall 321, and a light-emitting element 303 includes a first electrode layer 320, an electroluminescent layer 322, and a second electrode layer 323. do.

[0271] The insulating layer 313 is made of an organic resin such as acrylic, polyimide, or polyamide, or siloxane. It is preferable to form it using

[0272] In this embodiment, the thin film transistor 302 of the pixel is an n-type transistor, so that the first It is desirable to use a cathode as the first electrode layer 320. Specifically, the cathode is Materials with small functions, such as Ca, Al, CaF, MgAg, and AlLi, can be used. can.

[0273] The partition wall 321 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. A photosensitive material is used to form an opening on the first electrode layer 320, and the sidewall of the opening is continuous. It is preferable to form the inclined surface with a continuous curvature.

[0274] The electroluminescent layer 322 may be composed of a single layer or a plurality of layers stacked together. It doesn't matter whether it's

[0275] A second electrode layer 323 used as an anode is formed so as to cover the electroluminescent layer 322. The electrode layer 323 is made of a light-transmitting conductive material listed as an example of the pixel electrode layer in Embodiment 7. In addition to the above-mentioned transparent conductive film, a titanium nitride film can be used. Alternatively, a titanium film may be used. The first electrode layer 320, the electroluminescent layer 322, and the second electrode layer 323 are overlapped to form the light emitting element 303. The second electrode layer 323 and the partition wall 324 are provided to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the substrate 3. A protective film may be formed on the surface of the substrate 321. Examples of the protective film include a silicon nitride film, a silicon nitride oxide film, and a D LC films and the like can be formed.

[0276] Furthermore, in practice, once the process is completed up to Figure 22(B), it is necessary to make the structure airtight to prevent it from being exposed to the outside air. High-performance protective film with low degassing (lamination film, UV-curable resin film, etc.) It is preferable to package (enclose) the product in a protective covering or cover material.

[0277] Next, the configuration of the light emitting element will be described with reference to FIG. 24. Here, the driving TFT is The cross-sectional structure of a pixel will be explained using the example of the type shown in Figures 24(A), (B), and (C). The driving TFTs 7001, 7011, and 7021 used in the semiconductor device are the same as those in the first embodiment. It can be fabricated in the same way as the thin-film transistor shown in Fig. 1, and has an IGZO semiconductor layer and a gold layer with n-type conductivity. The thin film transistor includes a metal oxide layer and is highly reliable. The thin film transistor shown in Embodiment 3 or 4 is used as the driving TFTs 7001, 7011, and 7021. It can also be applied as 021.

[0278] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and top emission. There is a light-emitting element having a dual emission structure in which light is extracted from the side surface. The composition can be applied to any light emitting device with any emission structure.

[0279] A light emitting element with a top emission structure will be described with reference to FIG.

[0280] In FIG. 24(A), the driving TFT 7001 is n-type, and the light emitted from the light emitting element 7002 is 24A shows a cross-sectional view of a pixel when the light emitting element 70 The cathode 7003 of the TFT 7002 is electrically connected to the driving TFT 7001. The cathode 7003 has a small work function. Various materials can be used as long as they are conductive and reflect light. The light-emitting layer 7004 is preferably made of a single material such as Al, CaF, MgAg, or AlLi. It may be configured as a layer or as a laminate of multiple layers. When the cathode 7003 is composed of a plurality of layers, an electron injection layer, an electron transport layer, an emitting layer, a hole transport layer, and a hole transport layer are formed on the cathode 7003. The hole transport layer and the hole injection layer are laminated in this order. Note that it is not necessary to provide all of these layers. The electrode 7005 is formed using a conductive material that transmits light, for example, tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium, indium tin oxide containing titanium oxide, indium tin oxide ITO, indium zinc oxide, indium doped with silicon oxide A light-transmitting conductive film such as a tin oxide film may also be used.

[0281] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 is the light-emitting element 7002. In the case of the pixel shown in FIG. 24(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as shown by the mark.

[0282] Next, a light emitting element with a bottom emission structure will be described with reference to FIG. When 011 is n-type and light emitted from the light emitting element 7012 is emitted to the cathode 7013 side, 24(B) shows a cross-sectional view of the pixel. A cathode 7013 of a light-emitting element 7012 is formed on a light-transmitting conductive film 7017. On the cathode 7013, a light-emitting layer 7014 and an anode 7015 are laminated in this order. When the 015 has a light-transmitting property, a shielding layer for reflecting or blocking light is applied to cover the anode. The cathode 7013 may have a film 7016 formed thereon, as in the case of FIG. Various conductive materials with small electrical conductivity can be used. The thickness is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, a 20 nm film An aluminum film having a thickness of 700 nm can be used as the cathode 7013. 014 is composed of a single layer, as in FIG. 24(A), but multiple layers are laminated. The anode 7015 does not need to transmit light, but as shown in FIG. As with 24(A), it can be formed using a light-transmitting conductive material. The shielding film 7016 may be made of, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin containing a black pigment can be used.

[0283] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 24B, the light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0284] Next, a light emitting element with a dual emission structure will be described with reference to FIG. Then, on the conductive film 7027 having light-transmitting properties and electrically connected to the driving TFT 7021, A cathode 7023 of the light-emitting element 7022 is formed as a film. A light-emitting layer 7024 is formed on the cathode 7023. The cathode 7023 is laminated in the same manner as in FIG. Various conductive materials with small electrical conductivity can be used. For example, Al having a thickness of 20 nm is used as the cathode 7023. The light-emitting layer 7024 can be formed of a single layer, as in FIG. The anode 70 may be formed by laminating a plurality of layers. 25 is formed using a light-transmitting conductive material, similar to FIG. 24(A). It is possible.

[0285] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 is the light-emitting element 70. In the case of the pixel shown in FIG. 24(C), the light emitted from the light emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as shown by the arrows.

[0286] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0287] In this embodiment, a thin film transistor (driving TFT) that controls driving of a light emitting element is Although an example in which the light emitting element is electrically connected has been shown, it is possible to prevent a current from flowing between the driving TFT and the light emitting element. A control TFT may be connected.

[0288] Note that the semiconductor device shown in this embodiment mode is not limited to the configuration shown in FIG. Various modifications based on the technical concept of the present invention are possible.

[0289] Through the above steps, a highly reliable light-emitting display device can be manufactured as a semiconductor device. .

[0290] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0291] (Embodiment 10) Next, a structure of a display panel, which is one embodiment of a semiconductor device of the present invention, will be described below. In the embodiment, a liquid crystal display panel is a type of liquid crystal display device having liquid crystal elements as display elements. A liquid crystal panel is one form of a semiconductor device having a light-emitting element as a display element. A light-emitting display panel (also called a light-emitting panel) will be described.

[0292] The appearance and cross section of a light-emitting display panel, which corresponds to one embodiment of a semiconductor device of the present invention, are shown in FIG. FIG. 25 shows an IGZO semiconductor layer and an n-type conductive layer formed on a first substrate. A highly reliable thin film transistor and a light emitting element including a metal oxide layer having an electrolytic type are 25(B) is a top view of the panel sealed with a sealing material between the panel and the substrate. This corresponds to the cross-sectional view at HI in 5(A).

[0293] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler material 4507 by the seal.

[0294] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b have a plurality of thin film transistors. In FIG. 25B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45 shows an example of a thin film transistor 4509 included in a line driver circuit 4503a.

[0295] The thin film transistors 4509 and 4510 are made of an IGZO semiconductor layer and a gold layer having n-type conductivity. This corresponds to a thin film transistor including a metal oxide layer, and is shown in the first embodiment, the second embodiment, and the third embodiment. The thin film transistor described in Embodiment 3 or 4 can be applied to this embodiment. In this example, the thin film transistors 4509 and 4510 are n-channel thin film transistors.

[0296] Further, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. Note that the structure of the light-emitting element 4511 is not limited to that shown in this embodiment mode. The structure of the light emitting element 4511 is adjusted to suit the direction of the light to be extracted from the light emitting element 4511. The composition can be changed as appropriate.

[0297] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0298] In this embodiment mode, the connection terminal 4515 is formed from the same conductive film as the second electrode layer 4512. The wiring 4516 is made of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. It is formed.

[0299] The connection terminal 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected.

[0300] The second substrate located in the direction of light extraction from the light emitting element 4511 must be transparent. In that case, use a glass plate, plastic plate, polyester film or acrylic A light-transmitting material such as a film is used.

[0301] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of oil or thermosetting resin, and PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. In this embodiment, filler 4507 Nitrogen was used as the gas.

[0302] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0303] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Alternatively, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted. In this embodiment, the structure shown in FIG. Not limited.

[0304] Next, the appearance and cross section of a liquid crystal display panel, which is one embodiment of a semiconductor device of the present invention, will be described. This will be explained using Figure 20. Figure 20 shows an IGZO semiconductor formed on a first substrate 4001. and a metal oxide layer having n-type conductivity. 4011 and a liquid crystal element 4013 are disposed between a second substrate 4006 and a sealant 4005. 20(A1) and 20(A2) are top views of the panel sealed by the above method. Equivalent to the cross-sectional view at -N.

[0305] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0306] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, Wire bonding or TAB method can be used. is an example of mounting a signal line driver circuit 4003 by the COG method, and FIG. 20(A2) is This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0307] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 20B, the thin film transistor included in the pixel portion 4002 is A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 The following are examples:

[0308] The thin film transistors 4010 and 4011 are made of an IGZO semiconductor layer and a gold layer having n-type conductivity. This corresponds to a thin film transistor including a metal oxide layer, and is the same as the thin film transistors shown in Embodiments 1 to 4. In this embodiment, thin film transistors 4010 and 401 1 is an n-channel thin film transistor.

[0309] The pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are The overlapping portion corresponds to the liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0310] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Aluminum foil can also be used with PVF film or polyester film. A sheet sandwiched between films can also be used.

[0311] 4035 is a columnar spacer obtained by selectively etching the insulating film. To control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 A spherical spacer may also be used.

[0312] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0313] In this embodiment, the connection terminal 4015 is connected to the pixel electrode layer 4030 of the liquid crystal element 4013. The wiring 4016 is formed from the same conductive film as the gate electrodes of the thin film transistors 4010 and 4011. It is formed from the same conductive film as the base electrode layer.

[0314] The connection terminal 4015 is electrically connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. are electrically connected.

[0315] In FIG. 20, a signal line driver circuit 4003 is separately formed and mounted on the first substrate 4001. However, this embodiment is not limited to this configuration. Alternatively, a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed separately and mounted. Alternatively, the circuit board may be formed separately and mounted.

[0316] FIG. 21 shows a semiconductor device using a TFT substrate 2600 manufactured according to one embodiment of the present invention. 1 shows an example of a liquid crystal display module.

[0317] FIG. 21 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate is fixed by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate and the bonding material 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is required for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. The wiring board 2609 is connected to the wiring circuit section 2608 of the TFT substrate 2600, and the controller It also incorporates external circuits such as a polarizing plate and a power supply circuit. The layers may be laminated with a retardation film interposed therebetween.

[0318] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment), ASM(Axially Symmetric aligned Mic) ro-cell) mode, OCB(Optical Compensated Bire) fringence mode, FLC (Ferroelectric Liquid Crystal Crystal mode, AFLC (AntiFerroelectric Liquid Crystal) can be used.

[0319] Through the above steps, a highly reliable display panel can be manufactured as a semiconductor device.

[0320] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0321] (Embodiment 11) A semiconductor device according to one embodiment of the present invention can be applied to electronic paper. The display can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, and vehicles such as trains. The present invention can be applied to in-car advertisements, displays on various cards such as credit cards, etc. An example of the electronic device is shown in FIG. 28 and FIG.

[0322] FIG. 28(A) shows a poster 2631 made of electronic paper. In the case of printed matter, the advertisements are exchanged manually. By using electronic paper that uses semiconductor devices, advertisement displays can be changed in a short time. In addition, the display is stable and the image is not distorted. It may be configured to be capable of transmitting and receiving.

[0323] FIG. 28(B) shows an advertisement 2632 inside a vehicle such as a train. In the case of paper printouts, the advertisements are exchanged manually. By using electronic paper that uses semiconductor devices, advertising can be displayed in a short time without requiring much manpower. You can change the display. You can also get a stable image without the display collapsing. The in-vehicle advertisement may be configured to be capable of transmitting and receiving information wirelessly.

[0324] 29 shows an example of an electronic book 2700. For example, the electronic book 2700 includes: It consists of two housings, housing 2701 and housing 2703. The body 2703 is integrated with a shaft 2711, and the shaft 2711 is used as an axis for opening and closing. This configuration allows the device to operate like a paper book. This becomes:

[0325] The housing 2701 incorporates a display unit 2705, and the housing 2703 incorporates a display unit 2707. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display (display 2705 in FIG. 29) and An image can be displayed on the display unit (display unit 2707 in FIG. 29).

[0326] 29 shows an example in which an operation unit is provided on the housing 2701. 2701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The back of the housing may be provided with a keyboard, a pointing device, etc. or on the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. You may do so.

[0327] The electronic book 2700 may also be configured to be capable of transmitting and receiving information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. It is also possible.

[0328] (Embodiment 12) A semiconductor device according to one embodiment of the present invention can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television (also called television receivers), computer monitors, digital cameras and digital video Cameras such as cameras, digital photo frames, mobile phones (also known as mobile phones or mobile phone devices) (hereinafter referred to as "games"), portable game machines, personal digital assistants, sound reproduction devices, large game machines such as pachinko machines Examples include:

[0329] FIG. 30(A) shows an example of a television device 9600. The display unit 9603 is incorporated into the housing 9601 of the device 600. In addition, the stand 9605 is used to hold the case 960 This shows a configuration that supports 1.

[0330] The television device 9600 can be operated using an operation switch provided on the housing 9601 or a separate remote control. This can be done by using the remote control operation device 9610. The channel and volume can be controlled by the -9609, and the information displayed on the display 9603 In addition, the remote control operation device 9610 can operate the video. A display unit 9607 for displaying information output from the device 9610 may be provided.

[0331] The television device 9600 includes a receiver, a modem, and the like. It allows reception of general television broadcasts, and also provides wired or wireless reception via a modem. By connecting to a communication network, it can be one-way (sender to receiver) or two-way It is also possible to communicate information in both directions (between a sender and a receiver, or between receivers). .

[0332] FIG. 30(B) shows an example of a digital photo frame 9700. The digital photo frame 9700 has a display unit 9703 built into a housing 9701. The display unit 9703 is capable of displaying various images, for example, images taken with a digital camera. By displaying the image data, it can function like a regular photo frame. .

[0333] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, It is equipped with a terminal that can be connected to various cables such as USB cable, a recording medium insertion section, etc. These components may be incorporated on the same surface as the display unit, but they may also be incorporated on the side or back It is preferable to prepare for this because it improves the design. For example, Insert the memory that stores the image data taken with the digital camera into the media insertion section to create the image data. The image data can be captured and the captured image data can be displayed on the display portion 9703 .

[0334] The digital photo frame 9700 may also be configured to be able to send and receive information wirelessly. It is also possible to configure the device to wirelessly retrieve and display desired image data.

[0335] FIG. 31(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected by a connecting portion 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in FIG. 31(A) also includes a speaker unit 9884, a recording medium insertion unit 98 86, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature , chemicals, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, (including functions to measure vibration, odor or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and at least According to one embodiment of the present invention, an oxide semiconductor layer containing In, Ga, and Zn and a gold layer having n-type conductivity are It is sufficient if the device is configured to include a thin film transistor including a metal oxide layer, and other auxiliary equipment is appropriately provided. The portable gaming machine shown in FIG. The function of reading out the stored program or data and displaying it on the display unit, and the function of It has the function of sharing information by wireless communication with the portable game device shown in Figure 31(A). The functions of the machine are not limited to these, and the machine may have a variety of functions.

[0336] FIG. 31(B) shows an example of a slot machine 9900, which is a large gaming machine. The computer machine 9900 has a display unit 9903 built into a housing 9901. The Tomashin 9900 also has other operating means such as a start lever and stop switch, It is equipped with a slot slot, a speaker, etc. Of course, the configuration of the slot machine 9900 is as described above. The oxide containing at least In, Ga, and Zn according to one embodiment of the present invention is not limited to the above. A structure including a thin film transistor including a compound semiconductor layer and a metal oxide layer having n-type conductivity. Any other auxiliary equipment may be provided as appropriate.

[0337] FIG. 32 shows an example of a mobile phone 1000. The mobile phone 1000 has a housing 10 In addition to the display unit 1002 incorporated in the 01, there are operation buttons 1003 and an external connection port 1004. , a speaker 1005, a microphone 1006, etc.

[0338] The mobile phone 1000 shown in FIG. 32 displays information by touching the display unit 1002 with a finger or the like. In addition, operations such as making a phone call or sending an email can be performed using the display unit 10. This can be done by touching 02 with your finger or something.

[0339] The screen of the display unit 1002 has three main modes. The first is a mode that mainly displays images. The first mode is a display mode, and the second mode is an input mode that mainly inputs information such as characters. This is a display + input mode that combines the display mode and the input mode.

[0340] For example, when making a call or creating an email, the display unit 1002 is used for inputting characters. In this case, you can input characters displayed on the screen. In this case, it is possible to display a keyboard or number buttons on most of the screen of the display unit 1002. preferable.

[0341] The mobile phone 1000 also includes a sensor for detecting tilt, such as a gyro or acceleration sensor. By providing a detection device having the above, the orientation (portrait or landscape) of the mobile phone 1000 can be determined, The screen display on the display unit 1002 can be automatically switched.

[0342] The screen mode can be switched by touching the display unit 1002 or by operating the housing 1001. The type of image displayed on the display unit 1002 can be selected by operating the operation button 1003. For example, the image signal to be displayed on the display unit can be switched by If the data is text data, the mode switches to display mode, and if the data is text data, the mode switches to input mode.

[0343] In the input mode, the optical sensor of the display unit 1002 detects a signal and displays the If there is no input by touch operation on the display unit 1002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0344] The display unit 1002 can also function as an image sensor. By touching the palm or fingers to 002, palm prints, fingerprints, etc. can be captured and identity authentication can be performed. In addition, the display unit may be provided with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a light source for imaging, it is also possible to image finger veins, palm veins, etc. [Explanation of symbols]

[0345] 100 boards 101 gate electrode layer 102 Gate insulating layer 103 Semiconductor layer 104a Buffer layer 104b Buffer layer 105a Source electrode layer or drain electrode layer 105b Source electrode layer or drain electrode layer 105a1 Source electrode layer or drain electrode layer 105a2 Source electrode layer or drain electrode layer 105a3 Source electrode layer or drain electrode layer 105b1 Source electrode layer or drain electrode layer 105b2 Source electrode layer or drain electrode layer 105b3 Source electrode layer or drain electrode layer 106a Buffer layer 106b Buffer layer 111 Semiconductor film 113 Mask 114 Metal oxide film 115 Metal oxide film 116 Mask 117 Conductive film 118 Mask 121 Conductive film 122 Mask 131 Semiconductor Film 132 Metal oxide film 133 Conductive Film 135 Mask 137 Metal oxide films 138 Conductive Film 139 Mask 150 boards 151a gate electrode layer 152 Gate insulating layer 153 Semiconductor layer 153a Semiconductor layer 153b Semiconductor layer 154a Buffer layer 154b buffer layer 154c buffer layer 155a Source electrode layer or drain electrode layer 155b Source electrode layer or drain electrode layer 156 wiring layer 170a Thin-film transistor 170b thin film transistor 170c thin film transistor 170d thin film transistor 171a Thin-film transistor 171b Thin-film transistor 171c Thin-film transistor 173 Thin-film transistor 174 Thin-film transistor

Claims

[Claim 1] a gate electrode layer; a gate insulating layer on the gate electrode layer; a semiconductor layer on the gate insulating layer; a buffer layer having n-type conductivity on the semiconductor layer; a thin film transistor including a source electrode layer and a drain electrode layer on the buffer layer; the semiconductor layer is an oxide semiconductor layer containing indium, gallium, and zinc, the buffer layer is a metal oxide layer; The semiconductor device is configured such that the semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer via the buffer layer.

Images