Imaging apparatus

Abstract

To provide an imaging apparatus having an image processing function and capable of performing high-speed operation.SOLUTION: An imaging device with an additional function such as image processing can hold analog data obtained by imaging operation in a pixel and take out data obtained by multiplying the analog data by a given weight coefficient. In the imaging device, the data can be stored in a memory cell and pooling processing of the data stored in a plurality of memory cells can be performed. Since the pixel and at least one of the memory cell, the pooling processing circuit, and the reading circuit of the pixel are provided so as to overlap with each other, an increase in the area of the imaging device can be suppressed while an additional function is provided.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the invention disclosed herein more specifically relates to The technical field of one aspect of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, operation method thereof, or manufacturing method thereof This can be cited as an example.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] The technology of constructing transistors using oxide semiconductor thin films formed on substrates has been attracting attention. For example, a transistor having an oxide semiconductor and extremely low off-state current is used in a pixel circuit. An imaging device having such a configuration is disclosed in Patent Document 1.

[0005] Furthermore, Patent Document 2 discloses a technique for adding a calculation function to an imaging device. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-119711 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-123087 Summary of the Invention [Problem to be solved by the invention]

[0007] Imaging devices installed in mobile devices are generally equipped with a function that can capture high-resolution images. In the next generation, imaging devices will be required to have even more intelligent functions. It is being done.

[0008] The image data (analog data) acquired by the imaging device is converted into digital data and sent to an external device. After the image is extracted, image processing is performed as necessary. If possible, cooperation with external devices will be faster, and user convenience will be improved. The load and power consumption of peripheral devices can also be reduced. If complex data processing can be performed in a single step, the time required for data conversion can also be reduced.

[0009] In addition, when adding functions to the imaging device, elements such as additional circuits are stacked. For example, by providing a plurality of circuits so as to overlap the pixel circuit, it is possible to increase the area. This makes it possible to suppress the size of the image pickup device, thereby forming a compact, highly functional image pickup device.

[0010] Therefore, one aspect of the present invention is to provide an imaging device capable of image processing. Another object is to provide a high-performance, compact imaging device. Another object is to provide an imaging device that can operate at high speed. It is an object of the present invention to provide an imaging device with low power consumption and high reliability. One of the objects is to provide a novel imaging device. Another object of the present invention is to provide a method for driving the imaging device. Another object is to provide a novel semiconductor device or the like.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention relates to an imaging device that has an image processing function and is capable of high-speed operation.

[0013] One aspect of the present invention is a pixel block having a first circuit, Each of the memory cells has a plurality of pixels and a memory cell. The analog data calculated in accordance with the data generated by the first circuit is stored in the memory. The maximum value of the analog data stored in the memory cells of each block is read. It is an imaging device that has the function of detecting the image.

[0014] The memory cell preferably has an area overlapping with at least one of the pixel and the first circuit. Desirable.

[0015] Another aspect of the present invention is a pixel circuit including a plurality of pixel blocks, a first circuit, a second circuit, and a third circuit. Each of the plurality of pixel blocks has a plurality of pixels and a memory cell. Each of the plurality of pixels has a function of retaining first data according to a reset operation; Each of the plurality of pixels has a function of retaining second data according to a photoelectric conversion operation, Each of the pixels in the image is subjected to a weighting factor and a function of adding the first data to generate the third data. and each of the plurality of pixels adds a weighting coefficient and the second data to generate fourth data. The first circuit has a function of generating a sum of first data held in a plurality of pixels and a plurality of The fifth data is generated based on the difference between the sum of the third data generated by the pixel and the fifth data. The first circuit sums the second data held by the plurality of pixels and the second data generated by the plurality of pixels. The second circuit has a function of generating sixth data according to a difference between the sum of the fourth data and the sixth data. The seventh data is generated based on the difference between the fifth data and the sixth data. The memory cell stores seventh data, and the third circuit stores seventh data for each of the plurality of pixel blocks. The seventh data stored in the memory cell of the imaging device has a function of reading out the maximum value. It is an imaging device.

[0016] The pixel includes a photoelectric conversion device, a first transistor, a second transistor, and a third transistor. a first transistor, a fourth transistor, a fifth transistor, and a first capacitor; one electrode of the photoelectric conversion device is connected to the source or drain of the first transistor; The other of the source and drain of the first transistor is electrically connected to the second transistor. One of the source or drain of the transistor, one electrode of the first capacitor, and the third and a source or drain of a third transistor. One of the terminals of the first transistor is electrically connected to one of the source and drain of the fourth transistor. The other electrode of the first capacitor is electrically connected to one of the source and drain of the fifth transistor. can be electrically connected.

[0017] The memory cell includes a sixth transistor, a seventh transistor, and a second capacitor. One of the source and drain of the sixth transistor and one of the potentials of the second capacitor The pole and the gate of the seventh transistor may be electrically connected.

[0018] The sixth transistor and the seventh transistor each have a metal oxide in a channel formation region. The metal oxides are In, Zn, and M (M is Al, Ti, Ga, Ge, Sn, Y, Zr, and one or more of La, Ce, Nd or Hf).

[0019] The first circuit and the second circuit may be correlated double sampling circuits.

[0020] The third circuit may include a plurality of current mirror circuits.

[0021] The first to third circuits each include a transistor having silicon in a channel formation region. It is preferable that

[0022] It is preferable that at least one of the first to third circuits has an overlapping area with the pixel. In addition, any one or more of the first circuit to the third circuit and the pixel and the memory cell It may have overlapping regions. [Effects of the Invention]

[0023] By using one embodiment of the present invention, an imaging device capable of image processing can be provided. Alternatively, a highly functional and compact imaging device can be provided. Alternatively, it is possible to provide an imaging device that can perform the above-described imaging. Alternatively, a highly reliable imaging device can be provided. Alternatively, a driving method for the imaging device can be provided. Alternatively, a novel semiconductor device or the like can be provided. [Brief explanation of the drawings]

[0024] [Figure 1] FIG. 1 is a block diagram illustrating an imaging device. [Figure 2] FIG. 2 is a block diagram illustrating the imaging device. [Figure 3] FIG. 3 is a diagram illustrating a pixel selection operation. [Figure 4] FIG. 4 is a diagram illustrating a pixel selection operation. [Figure 5] FIG. 5 is a diagram illustrating a pixel selection operation. [Figure 6] 6A and 6B are diagrams illustrating pixels. [Figure 7] 7A and 7B are diagrams illustrating pixels. [Figure 8] FIG. 8 is a diagram for explaining the circuit 201 and the circuit 202. As shown in FIG. [Figure 9] 9A and 9B are timing charts illustrating the operation of the imaging device. [Figure 10] 10A and 10B are diagrams for explaining the arrangement of pixels and memory cells. [Figure 11] 11A and 11B are diagrams for explaining the arrangement of pixels and memory cells. [Figure 12] Fig. 12A is a diagram illustrating a memory circuit, and Fig. 12B and Fig. 12C are diagrams illustrating a memory cell. [Figure 13] FIG. 13 is a diagram illustrating the circuit 203. [Figure 14] 14A is a diagram illustrating the circuit 230a, and FIG. 14B is a diagram illustrating the circuit 240. [Figure 15] 15A and 15B are diagrams illustrating the circuit 204. FIG. [Figure 16] FIG. 16 is a diagram illustrating a memory cell. [Figure 17] 17A and 17B are diagrams showing examples of the configuration of a neural network. [Figure 18] 18A to 18D are diagrams illustrating the configuration of a pixel of an imaging device. [Figure 19] 19A to 19C are diagrams illustrating the configuration of a photoelectric conversion device. [Figure 20] FIG. 20 is a cross-sectional view illustrating a pixel. [Figure 21] 21A to 21C are diagrams illustrating a Si transistor. [Figure 22] FIG. 22 is a cross-sectional view illustrating a pixel. [Figure 23] FIG. 23 is a cross-sectional view illustrating a pixel. [Figure 24] FIG. 24 is a cross-sectional view illustrating a pixel. [Figure 25] 25A to 25D illustrate an OS transistor. [Figure 26] FIG. 26 is a cross-sectional view illustrating a pixel. [Figure 27] FIG. 27 is a cross-sectional view illustrating a pixel. [Figure 28] FIG. 28 is a cross-sectional view illustrating a pixel. [Figure 29] FIG. 29 is a cross-sectional view illustrating a pixel. [Figure 30] 30A to 30C are perspective views (cross-sectional views) illustrating pixels. [Figure 31] 31A1 to 31A3 and 31B1 to 31B3 are perspective views of a package and a module that house an imaging device. [Figure 32]32A to 32F are diagrams illustrating an electronic device. [Figure 33] FIG. 33 is a diagram illustrating an automobile. DETAILED DESCRIPTION OF THE INVENTION

[0025] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-described embodiments. In the drawings, the same parts or parts having similar functions are designated by the same reference numerals. The same elements in the drawings are used interchangeably, and repeated explanations may be omitted. In some cases, the timing may be omitted or changed as appropriate between different drawings.

[0026] In addition, even if a circuit diagram shows a single element, there may be functional problems. If there is no need for a single element, the element may be composed of multiple elements. For example, a transistor that operates as a switch may be used. In some cases, multiple resistors may be connected in series or in parallel. It may be divided and placed in multiple positions.

[0027] In addition, when one conductor has multiple functions such as wiring, electrode, and terminal, In this specification, the same element may be referred to by multiple names. Even if the circuit diagram shows direct connections between elements, The elements may be connected via one or more conductors, and This type of configuration is also included in the category of direct connection.

[0028] (Embodiment 1) In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0029] One aspect of the present invention is an imaging device having additional functions such as image processing. The analog data (image data) acquired during the imaging operation is stored in the pixels, and the analog data and an arbitrary weighting coefficient can be multiplied to obtain analog data.

[0030] The analog data is stored in memory cells, and the analog data stored in the memory cells is A pooling process can be performed to read the maximum value from the log data. The pixel overlaps with one or more of the pooling circuits and the pixel readout circuits. Therefore, it is possible to suppress the expansion of the area of ​​the imaging device while providing additional functions. This can be done.

[0031] By inputting the pooled data into a neural network, it is possible to perform image recognition and other similar tasks. In one aspect of the present invention, a large amount of image data can be converted into analog data. Since the pixel can be held in this state, processing can be performed efficiently.

[0032] <Imaging device> FIG. 1 is a block diagram illustrating an imaging device according to one embodiment of the present invention. Circuit 300, circuit 201, circuit 202, circuit 203, circuit 204, and circuit 301 , a circuit 302, a circuit 303, a circuit 304, and a circuit 305. Each of the circuits 201 to 204 and the circuits 301 to 305 is not limited to a single circuit configuration. , may be composed of a combination of multiple circuits. Or, any of the above multiple circuits In addition, circuits other than those described above may be connected.

[0033] The pixel array 300 has an imaging function and a calculation function. The circuits 301 to 304 have a calculation function or a data conversion function. The circuit 305 has a function of supplying a potential for product-sum calculation to the pixel. The circuit may be a shift register or a decoder. may be provided outside the imaging device.

[0034] The pixel array 300 includes a plurality of pixel blocks 200. The pixel blocks 200 are shown in FIG. As shown in FIG. 1, the image sensor has a plurality of pixels 100 arranged in a matrix, and each pixel 10 0 is electrically connected to the circuit 201 through a wiring 113. Note that the circuit 201 is It may also be provided within the lock 200.

[0035] Furthermore, the pixel block 200 has at least one memory cell 150. The memory cell 150 may be provided in an area overlapping the pixel 100. 0 is electrically connected to the circuit 202 through a wiring 141. , and is electrically connected to the circuit 203 through a wiring 142.

[0036] The circuit 301 and the circuit 302 have a selection function for operating the pixel 100. 4. The circuit 305 has a selection function for operating the memory cell 150. Although not shown, the pixel block 200 and the circuit 201, the pixel block 200 and the circuit 202 03, between circuit 201 and circuit 202, between circuit 203 and circuit 204, etc. A selection circuit or a sequence circuit for controlling the output may be provided as appropriate.

[0037] The pixel 100 acquires image data and generates data by adding the image data and a weighting factor. In FIG. 2, the pixel block 200 has, as an example, The number of prime numbers is 3x3, but it is not limited to this. For example, it can be 2x2, 4x4, etc. Alternatively, the number of pixels 100 in the horizontal direction may differ from the number of pixels 100 in the vertical direction. Also, some pixels 100 can be shared between adjacent pixel blocks.

[0038] For example, in the configuration shown in FIG. 3, the number of pixels 100 included in the pixel block 200 can be changed. FIG. 3 shows rows [n-1] to [n+1], columns [m-1] to [m+1]. ] (n and m are integers of 2 or more) are arranged in a row. 0, a selection switch is provided, and the selection switch is connected to the row wirings RL[n-1] to RL The selection signal supplied to [n+1] controls "ON" or "OFF". The switch is electrically connected to one of the column wirings CL[m-1] to CL[m+1]. In addition, at least one of the column wirings is electrically connected to the circuit 201[m-1]. will be done.

[0039] A conductive switch SW[m-1] is provided between the column wirings CL[m-1] and CL[m], A conductive switch SW[m] is provided between the column wirings CL[m] and CL[m+1]. The conductive switches are turned "ON" and "OFF" by selection signals supplied to signal lines G1 and G2. When the selection switch is turned “ON”, the adjacent column wiring is It can be made conductive.

[0040] For example, as shown in Figure 4, when the selection switches are set to "ON" for the row wiring RL[n-1] and RL[n], and a signal to turn on the conductive switch SW[m-1] is supplied to the signal line G1. When this is supplied, the 2×2 pixel 100 (pixel 100[n-1, m-1], pixel 100[n-1, m], pixel 100[n,m-1], pixel 100[n,m]) are selected. CL[m-1] and the column wiring CL[m] are electrically connected. and circuit 201[m-1] are electrically connected.

[0041] Furthermore, a signal to turn on the selection switch is supplied to the row wiring RL[n+1], and the signal line G2 When a signal to turn on the conductive switch SW[m] is sent to the ×3 pixels 100 are electrically connected to the circuit 201 .

[0042] In this configuration, the selected rows and columns can be changed arbitrarily, so the stride number can be changed. This makes it possible to perform operations that are simplified.

[0043] Also, as shown in FIG. 5, only one row of pixels 100 can be selected, and all When the conductive switch is turned "OFF", one column wiring and one pixel 100 are in a conductive state. Here, as shown in FIG. 5, a circuit 201 is electrically connected to each column wiring. If the pixel data is stored in the memory, the information of each pixel 100 can be read out. Image data and the like can be read out. Note that the number of circuits 201 is set to be less than the number of column wirings. Alternatively, the signal may be read out by selecting a wiring in the circuit 201.

[0044] The pixel block 200, the circuit 201, and the circuit 202 are operated as a multiply-and-accumulate circuit. The pixel block 200 is electrically connected to the circuit 201 via the wiring 113. The circuit 201 is electrically connected to the circuit 202 through a wiring 140 .

[0045] The data (analog data) of the sum-of-products operation is stored in the memory cell 150 via the wiring 141. The analog data stored in the memory cell 150 is transmitted to the circuit 203 via the wiring 142. In the circuit 203, the analog data stored in the plurality of memory cells 150 is read out. and output the maximum value. It can be made to function as such.

[0046] At least one of the circuit 201, the circuit 202, and the circuit 203 overlaps with the pixel 100. It is preferable that the circuit 201, the circuit 202, and the circuit 203 and at least one of the pixels have an area overlapping with the memory cell 150. By adopting this configuration, the area of ​​the entire imaging device can be reduced. This allows the formation of a compact, highly functional imaging device. Thus, the pixel 100, the memory cell 150, the circuit 201, the circuit 202, and the circuit 203 This allows for shorter wiring lengths for electrical connections, resulting in high speed and reduced power consumption. Operation becomes possible.

[0047] <Pixel circuit> As shown in FIG. 6A, the pixel 100 includes a photoelectric conversion device 101, a transistor 102, and , transistor 103, capacitor 104, transistor 105, and transistor 1 06 and a transistor 108.

[0048] One electrode of the photoelectric conversion device 101 is connected to the source or drain of the transistor 102. The other of the source and drain of the transistor 102 is electrically connected to the one of the source and drain of the transistor 103, one electrode of the capacitor 104, and The gate of the transistor 105 is electrically connected to the source of the transistor 105. One of the drains is electrically connected to one of the source and drain of the transistor 108. The other electrode of the capacitor 104 is connected to the source or drain of the transistor 106. One is electrically connected to the other.

[0049] The other electrode of the photoelectric conversion device 101 is electrically connected to the wiring 114. The gate of the transistor 102 is electrically connected to a wiring 116. The other of the drain and the gate of the transistor 103 is electrically connected to a wiring 115. The source or drain of the transistor 105 is electrically connected to the wiring 117. The source or drain of the transistor 108 is electrically connected to a GND wiring or the like. The other end of the transistor 106 is electrically connected to a wiring 113. The other terminal of the transistor 106 is electrically connected to a wiring 111. The gate of the transistor 108 is electrically connected to a wiring 122. To be continued.

[0050] Here, the other of the source or drain of the transistor 102 and the source of the transistor 103 One of the source or drain of the capacitor 104 and one of the electrodes of the transistor 105 The electrical connection point (wiring) with the gate is called node N.

[0051] The wirings 114 and 115 can function as power supply lines. The wiring 112 can function as a high-potential power supply line, and the wiring 115 can function as a low-potential power supply line. , 116, 117, and 122 function as signal lines that control the conduction of each transistor. The wiring 111 is used as a wiring for supplying a potential corresponding to a weighting coefficient to the pixel 100. The wiring 113 electrically connects the pixel 100 and the circuit 201. It can function as a wiring.

[0052] An amplifier circuit or a gain adjustment circuit may be electrically connected to the wiring 113. .

[0053] A photodiode can be used as the photoelectric conversion device 101. If it is desired to increase the light detection sensitivity, it is preferable to use an avalanche photodiode.

[0054] The transistor 102 can have a function of controlling the potential of the node N. The transistor 103 can have a function of initializing the potential of the node N. The node N5 has a function of controlling the current flowing from the circuit 201 in accordance with the potential of the node N. The transistor 108 can have a function of selecting a pixel. 106 can have a function of supplying a potential corresponding to a weighting coefficient to the node N.

[0055] As shown in FIG. 6B, the transistors 105 and 108 are transistors. One of the source or drain of transistor 105 and the source or drain of transistor 108 and the other of the source and drain of the transistor 105 is electrically connected to the wiring 11. 3, and the other of the source and drain of the transistor 108 is electrically connected to a GND wiring or the like. Alternatively, the two may be connected in a direct manner.

[0056] 6A and 6B, the direction of connection of a pair of electrodes of the photoelectric conversion device 101 is In this case, the wiring 114 is a low-potential power supply line, and the wiring 115 is a high-potential power supply line. It should function as such.

[0057] The transistors 102 and 103 are transistors using metal oxide in the channel formation region. It is preferable to use an OS transistor (OS transistor). By using OS transistors for the transistors 102 and 103, Therefore, the period during which the charge can be held at the node N can be made extremely long. The global system performs charge accumulation operations simultaneously in all pixels without complicating the system and operation method. In addition, while the node N holds the image data, It is also possible to perform multiple calculations using image data.

[0058] On the other hand, there are cases where it is desirable for the transistor 105 to have excellent amplification characteristics. The transistors 106 and 108 are made of high-mobility transistors that can operate at high speed. Therefore, the transistors 105, 106, and 108 may be A transistor (Si transistor) using a silicon nitride film in a channel forming region may be used.

[0059] The present invention is not limited to the above, and any combination of OS transistors and Si transistors may be used. Alternatively, all the transistors may be OS transistors. All the transistors may be Si transistors. Transistors with fast silicon, crystalline silicon (microcrystalline silicon, low-temperature polysilicon) Examples include transistors with silicon (single crystal silicon).

[0060] The potential of the node N in the pixel 100 is determined by the reset potential supplied from the wiring 115 and the photo potential. A potential obtained by adding a potential (image data) generated by photoelectric conversion by the electric conversion device 101 Alternatively, a potential corresponding to the weighting coefficient supplied from the wiring 111 is determined by the capacitance Therefore, the transistor 105 can apply an arbitrary weighting factor to the image data. A current corresponding to the data with the added number can be passed.

[0061] As shown in FIG. 7A, a back gate (second gate) is provided in the transistor 105. The back gate is electrically connected to one of the source and drain of the transistor 106. Also, a capacitor 109 may be provided, one of the electrodes of which is connected to the back gate. The capacitor 109 functions as a storage capacitor. It may also be composed.

[0062] As shown in FIG. 7B, a transistor having a back gate (second gate) may be provided. By electrically connecting the back gate to the front gate, In addition, by applying an appropriate constant potential to the back gate, By supplying a voltage to the transistor, the threshold voltage of the transistor can be controlled. The configuration of providing a back gate in the starter can also be applied to other circuits in this specification. In addition, transistors with and without back gates are mixed together to form a circuit. A path may be formed.

[0063] The above is an example of the circuit configuration of the pixel 100, and the photoelectric conversion operation can be performed using other circuit configurations. It can also be done in.

[0064] <Circuit 201, Circuit 202> As shown in FIG. 2, the pixels 100 in the pixel block 200 are electrically connected to each other by wiring 113. The circuit 201 uses the sum of the currents flowing through the transistors 105 of each pixel 100. Calculations can be performed using

[0065] The circuit 201 can have the configuration shown in Fig. 8. The circuit 201 includes a capacitor 222 and , transistor 223, transistor 224, transistor 225, and transistor 226 and a transistor 227 as a voltage conversion circuit. An appropriate analog potential (Bias) is applied to the port.

[0066] One electrode of the capacitor 222 is connected to one of the source and drain of the transistor 223. and electrically connected to the gate of the transistor 224. The source or drain of the transistor 225 is connected to the source or drain of the transistor 226. The capacitor 22 is electrically connected to either the source or the drain of the transistor 226. The other electrode of the transistor 227 is connected to the wiring 113 and one of the source and drain of the transistor 227. and electrically connected to each other.

[0067] Here, one electrode of the capacitor 222 and the source or drain of the transistor 223 The point (wiring) connecting the other side and the gate of the transistor 224 is referred to as node C.

[0068] The other of the source and the drain of the transistor 223 is electrically connected to the wiring 218. The other of the source and the drain of the transistor 224 is electrically connected to the wiring 219. The other of the source and drain of the transistor 225 is connected to a reference power supply line such as a GND line. The other of the source and the drain of the transistor 226 is electrically connected to the wiring 14. The other of the source and the drain of the transistor 227 is electrically connected to the wiring 2 The gate of the transistor 223 is electrically connected to the wiring 216. The gate of the transistor 225 is electrically connected to the wiring 215. The gate of the capacitor 226 is electrically connected to the wiring 213 .

[0069] The wirings 217, 218, and 219 can function as power supply lines. The line 218 functions as a wiring for supplying a reset potential (Vr) for reading. The wirings 217 and 219 can function as high-potential power supply lines. 213, 215, and 216 function as signal lines that control the conduction of each transistor. This can be done.

[0070] The transistor 223 has a function of resetting the potential of the node C to the potential of the wiring 218. The transistors 224 and 225 function as a source follower circuit. The transistor 226 can have the function of controlling the readout. The circuit 201 functions as a correlated double sampling circuit (CDS circuit), It is also possible to replace it with a circuit having another configuration that has the function.

[0071] In one aspect of the present invention, an offset component other than the product of the image data (X) and the weighting coefficient (W) is The target WX is extracted by removing the WX. WX is the exposure (image capture) acquired at the same pixel. Data without exposure (no image capture) and data when weights are applied to each of them. It can be calculated using

[0072] The current (I p ) is the sum of kΣ(XV th ) 2 , weight When a current (I p ) is the sum of kΣ(W+XV th ) 2 Tona In addition, the current (I ref ) is the sum of kΣ(0-V th ) 2 , the current (I ref ) is the sum of kΣ(W- V th ) 2 where k is a constant, V th is the threshold voltage of transistor 105 do.

[0073] First, calculate the difference (data A) between the data with exposure and the data with weighting. kΣ((XV th ) 2 -(W+XV th) 2 )=kΣ(-W 2 -2W·X+ 2W·V th )

[0074] Next, calculate the difference (data B) between the data without exposure and the data with the weight applied to the data. kΣ((0-V th ) 2 -(WV th ) 2 )=kΣ(-W 2 +2W·V th ) This becomes:

[0075] Then, take the difference between data A and data B. kΣ(-W 2 -2W·X+2W·V th - (-W 2 +2W·V th ))=kΣ(-2W·X). That is, image data (X) and the weighting coefficient (W).

[0076] The circuit 201 can generate data A and data B. The difference calculation with the circuit 202 can be performed by the circuit 202. As shown in FIG. The circuit 202 may have a configuration similar to that of the circuit 201. The operation of the circuit 202 may be replaced by a processing operation by software.

[0077] <Image capture operation> FIG. 9A shows the pixel block 200 and the circuit 201, which are used to compare data with exposure and data without exposure. The timing chart explains the operation of calculating the difference between the weighted data and the data (data A). For convenience, the timing at which each signal is converted is also shown. In practice, it is preferable to shift the time by taking into consideration the delay inside the circuit. High potential is represented by "H" and low potential is represented by "L".

[0078] First, in a period T1, the potential of the wiring 117 is set to "H" and the potential of the wiring 116 is set to "H". The potential of the node N at 0 is set to a reset potential. The potential of the wirings 112_1 to 112_3 (the wirings 112 in the first to third rows) is set to "H" and the weighting coefficient is set to 0. Sink into.

[0079] The potential of the wiring 116 is maintained at "H" until the period T2, and the potential of the wiring 117 is set to "L". A potential X (image data) is written to the node N by photoelectric conversion of the photoelectric conversion device 101. .

[0080] During the period T3, the potentials of the wirings 122_1, 122_2, and 122_3 are set to "H" to At this time, the transistor 105 of each pixel 100 is A current flows according to the potential X. In addition, by setting the potential of the wiring 216 to "H", The potential Vr of the wiring 218 is written to C. The operation in the periods T1 to T3 is to acquire data with exposure. This corresponds to the data being initialized to the potential Vr of the node C.

[0081] During the period T4, the potential of the wiring 111 is set to a weighting coefficient W11 (weighting added to the pixels in the first row). The potential of the wiring 112_1 is set to "H", and the potential of the wiring 112_2 is set to "H". A weighting factor W11 is added to the node N by the capacitive coupling of the capacitor 104.

[0082] During the period T5, the potential of the wiring 111 is set to a weighting coefficient W12 (weighting added to the pixels in the second row). The potential of the wiring 112_2 is set to "H" and the potential of the pixel 100 in the second row is set to "H". A weighting factor W12 is added to the node N by the capacitive coupling of the capacitor 104.

[0083] During the period T6, the potential of the wiring 111 is set to a weighting coefficient W13 (weighting added to the pixels in the third row). The potential of the wiring 112_3 is set to "H" and the potential of the pixel 100 in the third row is set to "H". A weighting coefficient W13 is added to the node N by the capacitive coupling of the capacitor 104. The operation of T6 corresponds to generating data by weighting the captured data.

[0084] During a period T7, the potentials of the wirings 122_1, 122_2, and 122_3 are set to "H" to At this time, the transistors 10 of the pixels 100 in the first row are selected. A current corresponding to the potential W11+X flows through the transistor 5 of the pixel 100 in the second row. A current corresponding to the potential W12+X flows through the transistor 105. A current corresponding to the potential W13+X flows through the transistor 105.

[0085] Here, the potential of the other electrode of the capacitor 222 changes according to the current flowing through the wiring 113. The change Y is added to the potential Vr of the node C by capacitive coupling. The potential of the node C is "Vr + Y". Here, if Vr = 0, Y is the difference itself. Thus, data A is calculated.

[0086] In addition, the potential of the wiring 213 is set to "H" and the potential of the wiring 215 is set to "V bias " etc. By setting the potential to a logarithmic potential, the circuit 201 operates as a source follower to drive the pixel block 2 in the first row. A signal potential corresponding to data A of 00 can be output.

[0087] FIG. 9B shows the pixel block 200 and the circuit 201, which are used to compare data without exposure and data with the The timing chart explains the operation of calculating the difference between the weighted data and the data (data B). The data B can be acquired as needed. For example, the weights to be input are If there is no change, the acquired data B is stored in memory and data B is read from the memory. It is also possible to store multiple pieces of data B corresponding to multiple weights in the memory. Also, it doesn't matter which of Data A and Data B is acquired first.

[0088] First, in the period from T1 to T2, the potential of the wiring 117 is set to "H" and the potential of the wiring 116 is set to "H". The node N of the pixel 100 is set to a reset potential (0). At the end of the period T2, the wiring 117 The potential of the wiring 116 is set to "L". The potential of node N is the reset potential regardless of the operation of the photoelectric conversion device 101.

[0089] In the period T1, the potential of the wiring 111 is set to "L" and the potential of the wirings 112_1, 112_2, and 112_3 is set to "L". _3 is set to "H" and a weighting coefficient of 0 is written. This operation is performed when the potential of node N is reset. This can be done during a certain period.

[0090] During the period T3, the potentials of the wirings 122_1, 122_2, and 122_3 are set to "H" to At this time, the transistor 105 of each pixel 100 is A current corresponding to the reset potential flows. The potential Vr of the wiring 218 is written to the node C. The operation in the periods T1 to T3 is performed for data without exposure. This corresponds to the acquisition of data, and the data is initialized to the potential Vr of the node C.

[0091] During the period T4, the potential of the wiring 111 is set to a weighting coefficient W11 (weighting added to the pixels in the first row). The potential of the wiring 112_1 is set to "H", and the potential of the wiring 112_2 is set to "H". A weighting factor W11 is added to the node N by the capacitive coupling of the capacitor 104.

[0092] During the period T5, the potential of the wiring 111 is set to a weighting coefficient W12 (weighting added to the pixels in the second row). The potential of the wiring 112_2 is set to "H" and the potential of the pixel 100 in the second row is set to "H". A weighting factor W12 is added to the node N by the capacitive coupling of the capacitor 104.

[0093] During the period T6, the potential of the wiring 111 is set to a weighting coefficient W13 (weighting added to the pixels in the third row). The potential of the wiring 112_3 is set to "H" and the potential of the pixel 100 in the third row is set to "H". A weighting factor W13 is added to the node N by the capacitive coupling of the capacitor 104. Period T4 Period T6 The operation of (2) corresponds to generating data by weighting data without imaging.

[0094] During a period T7, the potentials of the wirings 122_1, 122_2, and 122_3 are set to "H" to At this time, the transistors 10 of the pixels 100 in the first row are selected. A current corresponding to the potential W11+0 flows through the transistor 5 of the pixel 100 in the second row. A current corresponding to the potential W12+0 flows through the transistor 105. A current corresponding to the potential W13+0 flows through the transistor 105.

[0095] Here, the potential of the other electrode of the capacitor 222 changes according to the current flowing through the wiring 113. The change Y is added to the potential Vr of the node C. Therefore, the potential of the node C becomes " Vr+Z”. Here, if Vr=0, Z is the difference itself, and data B is It will have been calculated.

[0096] In addition, the potential of the wiring 213 is set to “H” and the potential of the wiring 215 is set to an appropriate analog potential (V bias ), the circuit 201 operates as a source follower to drive the pixel block 20 in the first row. A signal potential corresponding to data B of 0 can be output.

[0097] The data A and B output from the circuit 201 by the above operation are sent to the circuit 202 in order. Next, the circuit 202 performs the operation of finding the difference between data A and data B, similar to the circuit 201. The calculation is performed to remove unnecessary offsets other than the product of the image data (potential X) and the weighting coefficient (potential W). Components can be removed.

[0098] In the above operation, the potential of the node C of the circuit 201 is The data acquisition operation of data B is initialized to the same potential "Vr". So, "(Vr+Y)-(Vr+Z)" = "YZ", and the component of the potential "Vr" is removed. As mentioned above, other unnecessary offset components are also removed, so the image data The product of the data (potential X) and the weighting coefficient (potential W) can be extracted.

[0099] This operation corresponds to the initial operation of a neural network that performs inference, etc. Therefore, at least one calculation is performed within the imaging device before the large amount of image data is output to the outside. This reduces the load on external calculations and data input / output, speeds up processing, and Power consumption can be reduced.

[0100] In addition, as a different operation from the above, the acquisition operation of data A and the acquisition operation of data B are performed by circuit 2. The potential of node C of 01 may be initialized to a different potential. For example, when acquiring data A, When data B is acquired, it is initialized to a potential "Vr2". In this case, the difference calculation after that is "(Vr1+Y)-(Vr2+Z)" = "(Vr 1-Vr2)+(YZ)”. As in the previous operation, “YZ” is the image data (potential X) and a weighting coefficient (potential W), and then "Vr1-Vr2" is added. Here, "Vr1-Vr2" is the threshold adjustment in the calculation of the intermediate layer of the neural network. This corresponds to the bias used as an integral.

[0101] In addition, the weights are, for example, It acts as a filter for the Onal Neural Network, but amplifies the data. Alternatively, it may have the role of attenuating. For example, the weighting coefficient ( If W is the product of the filtering and amplification, the filtered data corrected to a bright image is Data B is data without imaging and is black level data. Therefore, the operation of taking the difference between data A and data B is This can be said to be an operation to promote the visualization of the captured image. Brightness correction using a workpiece becomes possible.

[0102] As described above, in one aspect of the present invention, a bias can be generated by the operation of an imaging device. In addition, functional weights can be added within the imaging device. This can reduce the load on the subject and can be used for various purposes. In addition to the theory, we also provide information on image data resolution correction, brightness correction, color image generation from monochrome images, Generation of 3D images from 2D images, restoration of missing information, generation of videos from still images, out-of-focus Some of the image correction and blurred image generation processes are performed within the imaging device. It is possible.

[0103] <Memory cell> As shown in FIG. 2, at least one memory cell 150 is provided in each pixel block 200. The memory cell 150 also stores the data acquired by the plurality of pixels 100 in the pixel block 200. The result of multiplying and accumulating data is stored.

[0104] As mentioned above, the pixels 100 included in the pixel block 200 are not fixed but can be arbitrarily selected. Therefore, the memory cell 150 is always one regardless of the stride number. The above is the configuration provided within the pixel block 200.

[0105] For example, if a pixel block 200 has 3×3 pixels 100, then the stride corresponding to 1 is To achieve this, the pixels 100 and memory cells 150 are arranged in the configuration shown in FIG. 10A. The configuration shown in FIG. 10A is a configuration in which the number of pixels 100 and memory cells 150 is approximately the same. is.

[0106] 10A is a schematic diagram, and the absolute positions of the pixel 100 and the memory cell 150 are not shown. For example, the combination of one pixel 100 and one memory cell 150 In this alignment, when viewed from above, the pixel 100 is positioned in any of the up, down, left, right, and diagonal directions. Alternatively, the pixel 100 and the memory cell 150 may be located in the same pixel. The filters 150 may be provided on different layers and may have overlapping areas.

[0107] FIG. 10A shows the result of a product-sum operation on 3×3 pixels 100 in a pixel block 200 surrounded by a dashed line. FIG. 10B shows the next operation in stride 1. 10A, a 3×3 pixel block 200 shifted by one pixel in the row direction is shown. The figure shows how the product-sum operation result of the pixel 100 is written to the central memory cell 150. The memory cells 150 into which the product-sum operation results are written are limited to the memory cells 150 located in the center. The memory cell 150 may be located at any other position.

[0108] The number of pixels 100 and the number of memory cells 150 are the same, and the stride is 1, forming a pixel block 200. When selecting this, the number of memory cells 150 is greater than the total number of pixel blocks 200. Therefore, some memory cells 150 are not written. The number may be appropriately reduced.

[0109] In addition, the pixel block 200 has 3×3 pixels 100, and in order to correspond to the stride 2, The configuration shown in FIG. 11A is preferably a matrix-shaped configuration. With the pixel 100 arranged in every other row and every other column as a reference, the pixel 100 arranged in every other row and every other column is The configuration is approximately equal in number to 150.

[0110] FIG. 11A shows the result of the product-sum operation of 3×3 pixels 100 in a pixel block 200 enclosed by a dashed line. FIG. 11B shows the next operation at stride 2. 11A, and the 3×3 pixels in the pixel block 200 shifted by two pixels in the row direction. 100 is written to memory cell 150.

[0111] In this way, when the stride number is fixed to 2 or more, the number of memory cells 150 is set to 1. As shown in Figs. 10A and 10B, When the number of elements 100 and the number of memory cells 150 are almost the same, any stride number will be compatible. We can respond to your requests.

[0112] FIG. 12A is a diagram showing the connection relationship between the memory cell 150, the circuit 304, and the circuit 305. The transistors constituting the memory cell 150 are preferably OS transistors. Here, a configuration including the memory cell 150, the circuit 304, and the circuit 305 is This is called the relay circuit 151.

[0113] The memory circuit 151 has m (m is an integer of 1 or more) memory cells in a column and n (n is an integer of 1 or more) memory cells in a row. The memory cells 150 are arranged in a matrix. are.

[0114] 12B and 12C show memory cell 150a and memory 1 is a diagram illustrating a cell 150b. In the following description, the bit lines are referred to as the 5 (column driver). The word lines can be connected to the circuit 304 (row The bit lines can be connected to both the circuit 202 and the circuit 203. Electrical connections are made but are not shown here.

[0115] The circuit 304 (row driver) and the circuit 305 (column driver) include, for example, a decoder. A row driver or a shift register can be used. A plurality of circuits 305 (column drivers) may be provided.

[0116] FIG. 12B shows a gain cell type ("2Tr1") having two transistors and one capacitor. 1 shows an example of the circuit configuration of a memory cell 150a of the "type C" type. The circuit includes a transistor 273 , a transistor 272 , and a capacitor 274 .

[0117] One of the source and drain of the transistor 273 is connected to one electrode of the capacitor 274. The other of the source and the drain of the transistor 273 is connected to the wiring WBL. The gate of the transistor 273 is connected to the wiring WL. The other electrode of the capacitor 274 is connected to the wiring RL. One of the source and drain of the transistor 273 is connected to the wiring RBL. The other of the source and the drain of the transistor 273 is connected to the wiring SL. The gate of the transistor 272 is connected to one electrode of the capacitor 274 .

[0118] The wiring WBL functions as a write bit line. The wiring RBL functions as a read bit line. The wiring WL functions as a word line. The wiring RL functions as the other end of the capacitor 274. It functions as a wiring for applying a predetermined potential to the electrode. During the holding period, it is preferable to apply a reference potential to the line RL.

[0119] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor 273. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor 273 The value voltage can be increased or decreased.

[0120] To write data, a high-level potential is applied to the wiring WL to turn on the transistor 273. The wiring WBL and one electrode of the capacitor 274 are electrically connected to each other. Specifically, when the transistor 273 is in a conductive state, the information to be recorded in the wiring WBL is A potential corresponding to Then, a low-level potential is applied to the wiring WL, and the transistor 2 By making 73 non-conductive, the potential of one electrode of the capacitor 274 and The potential of the gate of the transistor 272 is maintained.

[0121] Data is read by applying a predetermined potential to the wiring RL and the wiring SL. The current flowing between the source and drain of the transistor 272 and the current flowing between the source and drain of the transistor 273 The potential of either the source or the drain is connected to the potential of the gate of the transistor 272 and the potential of the transistor 273. The potential of the other of the source or drain of the transistor 273 is determined. The potential of the wiring RBL connected to one of the source or drain of 273 is read out. held on one electrode of the capacitor 274 (or the gate of the transistor 272) by That is, the potential stored in one electrode (or The potential held at the gate of transistor 272 is used to write the data to this memory cell. The information stored in this memory cell can be read out. You can find out whether or not there is a problem.

[0122] Also, as shown in FIG. 12C, the wiring WBL and the wiring RBL are integrated into one wiring BIL. The memory cell 150b shown in FIG. 12C has the same arrangement as the memory cell 150a. The line WBL and the line RBL are connected to one line BIL, and the source or drain of the transistor 273 is connected to the line WBL. The other of the drains and one of the source and drain of the transistor 273 are connected to the wiring BIL That is, the memory cell 150b is connected to the write bit line The read bit line and the read bit line are configured to operate as one wiring BIL.

[0123] In the memory cell 150a and the memory cell 150b, the transistor 273 It is preferable to use an OS transistor. In this case, 2Tr1C type memory cells such as memory cell 150a and memory cell 150b The memory device using NOSRAM (Non-volatile Oxide Semiconductor) The memory is called Conductor Random Access Memory. The cell can change the circuit configuration as needed.

[0124] <Circuit 203> The circuit 203 functions as a pooling circuit. A plurality of memory cells 150 in which analog data is written are electrically connected. 03 can read out the maximum value of the analog data.

[0125] The circuit 203 can have, for example, the configuration shown in FIG. 0a, circuit 230b, circuit 240, circuit 250 and a plurality of current mirror circuits. In this configuration, the magnitudes of two analog data input to the circuit 230a are compared. The larger of these is then taken as significant and compared with the analog data input to circuit 230b. Next, the larger of the two is taken as significant and compared with the analog data input to the circuit 240. The output of the circuit 240 is converted into a voltage by the circuit 250. and output to the outside (circuit 204, etc.). The maximum value can be read from the analog data. By doing so, the number of target memory cells 150 can be changed.

[0126] Here, the current mirror circuit has two p-channel transistors, Either the source or the drain is electrically connected to the power supply line (high potential power supply line). The gates of the two transistors are electrically connected, and the source or drain of one transistor is The other side of the transistor is electrically connected to the gate. The first transistor is called the output transistor, and the other transistor is called the output transistor.

[0127] The circuit 230a has terminals a1, a2, and a3. The circuit 230b has terminals b1, b2, and b 3. Circuit 240 has terminals c1, c2, and c3.

[0128] The terminal a1 of the circuit 230a is connected to the source of the output transistor of the current mirror circuit CM. The other of the drains is electrically connected to the input transistor of the current mirror circuit CM. The other of the source or drain of the memory cell 150 is connected to the select circuit 155. The source and drain of the transistor 272 are electrically connected to each other. Therefore, a current of the same value as the current flowing through the transistor 272 of the memory cell 150 flows through the terminal a1. is supplied.

[0129] A plurality of memory cells 150 are electrically connected to the selection circuit 155, and one of the selected memory cells 150 is The memory cells 150 can be electrically connected to the current mirror circuit CM. The selection circuit 155 may not be provided. It may be an element.

[0130] Terminal a2 of circuit 230a, terminal b2 of circuit 230b, and terminal c2 of circuit 240 are also selected. The memory cells 150 are connected to the respective memory cells 150 via the current mirror circuit CM and the current mirror circuit CM. are electrically connected.

[0131] The terminal a3 of the circuit 230a is connected to the source of the input transistor of the current mirror circuit CMa. The other of the drains is electrically connected, and the output transistor of the current mirror circuit CMa The other of the source and drain of the capacitor is electrically connected to terminal b1 of circuit 230b. The terminal a3 of the circuit 230a receives the larger of the currents input to the terminals a1 and a2. The terminal b1 of the circuit 230b is configured such that a current of the same value as that of the terminal a3 flows through the terminal b1. A current of flows.

[0132] The terminal b3 of the circuit 230b is connected to the source or drain of the input transistor of the current mirror circuit CMb. The other drain of the transistor is electrically connected to the output side of the current mirror circuit CMb. The other of the source and drain is electrically connected to the terminal c1 of the circuit 240. The terminal b3 of 30b is connected to the larger of the currents input to terminal b1 and terminal b2. The terminal c1 of the circuit 240 is configured to have a current of the same value flowing through it, and the terminal b3 is configured to have a current of the same value flowing through it. is playing.

[0133] The terminal c3 of the circuit 240 receives the larger of the currents input to the terminals c1 and c2. Therefore, the terminal c3 of the circuit 240 is configured such that the same current as that of the terminal The addresses stored in each memory cell 150 input to terminal a1, terminal a2, terminal b2, and terminal c2 are This is the terminal for reading the maximum value of analog data.

[0134] An example of the configuration of the circuit 230a is shown in Fig. 14A. Note that terminal a1 is connected to terminal b1, and terminal a2 is connected to terminal b 2. By replacing terminal a3 with terminal b3, the circuit 230b can also be configured in the same way. Cut.

[0135] The circuit 230a includes a current mirror circuit CM1 and a current mirror circuit CM2. The current mirror circuits CM1 and CM2 have three n-channel transistors, Either the source or drain of the The gates of the three transistors are electrically connected, and one transistor The other of the source and drain of the transistor is electrically connected to the gate. One transistor is the input transistor, and the other two transistors are the output transistors. It is called.

[0136] Terminal a1 is connected to the source or drain of the input transistor of the current mirror circuit CM1. On the other hand, the gates of the three transistors of the current mirror circuit CM1 and the The other of the source or drain of one output transistor of the circuit CM2 is electrically connected will be done.

[0137] Terminal a2 is connected to the source or drain of the input transistor of the current mirror circuit CM2. On the other hand, the gates of the three output transistors of the current mirror circuit CM2, - The other of the source or drain of one output transistor of the circuit CM1 is electrically connected will be done.

[0138] The terminal a3 is connected to the other output transistor of the current mirror circuit CM1 (transistor T r1) and the other output side of the current mirror circuit CM2 Either the source or the drain of the transistor (transistor Tr2) is electrically connected. The other of the source or drain of transistor Tr1 and the source of transistor Tr2 The other of the source and drain is electrically connected to the power supply line (low potential power supply line, reference potential line such as GND) are connected to the network.

[0139] In the above configuration, for example, at the beginning of the circuit operation, the current (I a1 ) is the current flowing into terminal a2 (I a2 ), one side of the current mirror circuit CM1 The resistance of the output transistor of the current mirror circuit CM1 is higher than the resistance of the input transistor of the current mirror circuit CM2. It becomes lower.

[0140] Here, the current input to terminal a2 flows through one output transistor of the current mirror circuit CM1. The potential of the gate of the transistor in the current mirror circuit CM2 is small. Therefore, the current (I a1 ) is the current (I a2 ) is sufficiently larger than When this happens, a current flows into the terminal a3 via the transistor Tr1. is the current (I a1 ) will flow. Conversely, the current flowing into terminal a2 will be (I a2 ) flows into terminal a1 (I a1 ), terminal a3 has a transformer The current (I a2 ) will flow a current of the same value.

[0141] An example of the configuration of the circuit 240 is shown in FIG. 14B. The circuit 240 includes a current mirror circuit CM3 and a The current mirror circuits CM3 and CM4 are two n-channel One of the source and drain of each transistor is electrically connected to the terminal c3. The gates of the two transistors are electrically connected, and one of the transistors The other of the source and drain of the transistor is electrically connected to the gate. The transistor is called the input transistor and the other transistor is called the output transistor.

[0142] Terminal c1 is connected to the source or drain of the input transistor of the current mirror circuit CM3. On the other hand, the gates of the two transistors of the current mirror circuit CM3 and the The other of the source or drain of the output transistor of the circuit CM4 is electrically connected .

[0143] Terminal c2 is connected to the source or drain of the input transistor of the current mirror circuit CM4. On the other hand, the gates of the two transistors of the current mirror circuit CM4 and the The other of the source or drain of the output transistor of the circuit CM3 is electrically connected .

[0144] In the above configuration, for example, at the beginning of the circuit operation, the current (I c1 ) is the current that flows into terminal c2 (I c2 ) is larger than the output of the current mirror circuit CM3. The resistance of the side transistor is lower than the resistance of the input side transistor of the current mirror circuit CM2. become.

[0145] Here, the current input to terminal c2 flows through the output transistor of the current mirror circuit CM3. The potential of the gate of the transistor in the current mirror circuit CM4 tends to decrease. Therefore, the current (I c1 ) is the current (I c2 ), the end The current (I c1 )but Conversely, the current flowing into terminal c2 (I c2 ) flows into terminal c1 (I c1 ), terminal c3 is connected to the input side transistor of the current mirror circuit CM4. and the current (I c2 ) will be played.

[0146] 14A. The circuit 240 is similar to the circuit in FIG. 14A except that the terminal a1 is replaced with the terminal c1, the terminal a2 is replaced with the terminal c2, and the terminal A configuration in which terminal a3 is replaced with terminal c3 may also be used.

[0147] The current output from the circuit 240 to the circuit 250 is converted into a voltage and, if necessary, binarized. The circuit 250 can output the signal to the outside (such as the circuit 204). The circuit may include a circuit for performing a function calculation. For example, the circuit may include a comparator circuit. The comparator circuit compares the input data with the set threshold value. The pixel block 200 and the circuit 20 output the comparison result as binary data. 1 to 203 can act as some elements of a neural network.

[0148] <Circuit 204> 15A is a diagram illustrating the circuit 204. The data output from the circuit 203 is The signals are sequentially input to the circuit 204. The circuit 204 may include, for example, a latch circuit and a shift register. This configuration allows parallel-to-serial conversion to be performed. The data input in parallel can be output to the wiring 311 as serial data. The connection destination of the wiring 311 is not limited. For example, it can be a neural network, a storage device, or the like. , and can be connected to communication devices, etc.

[0149] Also, as shown in FIG. 15B, the circuit 204 may include a neural network. The neural network has memory cells arranged in a matrix, and each memory The weighting coefficient is stored in the memory cell 3. 15B. The number of lines is an example and is not limited.

[0150] The neural network shown in FIG. 15B is composed of memory cells 320 arranged in a matrix. and reference memory cell 325, circuit 330, circuit 350, circuit 360, and circuit 37. 0.

[0151] FIG. 16 shows an example of a memory cell 320 and a reference memory cell 325. 25 are arranged in any one row. The memory cells 320 and the reference memory cells 325 are similarly arranged. The transistor 161, the transistor 162, and the capacitor 163 are Has.

[0152] The source or drain of the transistor 161 is connected to the gate of the transistor 162. The gate of the transistor 162 is electrically connected to one electrode of the capacitor 163. Here, either the source or the drain of the transistor 161 is electrically connected. The point where the gate of the transistor 162 and one electrode of the capacitor 163 are connected is called a node NM. do.

[0153] The gate of the transistor 161 is electrically connected to the wiring WL. The other electrode is electrically connected to the wiring RW. One of the terminals is electrically connected to a reference potential wiring such as a GND wiring.

[0154] In the memory cell 320, the other of the source and drain of the transistor 161 is connected to a wiring The other of the source and drain of the transistor 162 is electrically connected to the wiring WD. It is electrically connected to BL.

[0155] In the reference memory cell 325, the other of the source or drain of the transistor 161 is The source or drain of the transistor 162 is electrically connected to the wiring WDref. The other end is electrically connected to the wiring BLref.

[0156] The wiring WL is electrically connected to the circuit 330. The circuit 330 includes a decoder or a shift register. A resistor or the like can be used.

[0157] The wiring RW is electrically connected to the circuit 301. Each memory cell receives an output from the circuit 301. The binary data thus obtained is written. Note that a shift register is provided between the circuit 301 and each memory cell. It may also have a sequential circuit such as a register.

[0158] The wiring WD and the wiring WDref are electrically connected to the circuit 350. The circuit 350 includes: A decoder or a shift register can be used. The circuit 350 may include a converter or an SRAM. It is possible to output the weighting coefficients.

[0159] The wiring BL and the wiring BLref are electrically connected to the circuit 360. The circuit 360 can be configured in the same way as the circuit 201. A signal with the red component removed can be obtained.

[0160] The circuit 360 is electrically connected to the circuit 370. The circuit 370 can also be referred to as an activation function circuit. The activation function circuit converts the signal input from the circuit 360 into a predefined It has the function of performing calculations to convert according to activation functions. For example, activation functions are For example, sigmoid function, tanh function, softmax function, ReLU function, threshold function The signal converted by the activation function circuit is used as output data. and output to the outside.

[0161] As shown in Figure 17A, the neural network NN consists of an input layer IL, an output layer OL, and an intermediate layer OL. It can be composed of an input layer IL, an output layer OL, and an intermediate layer HL. Each layer has one or more neurons (units). The neural network may have two or more hidden layers HL. The network can also be called a DNN (Deep Neural Network). Learning using deep neural networks can also be called deep learning.

[0162] Input data is input to each neuron in the input layer IL. The output signal of the neurons in the previous or next layer is input to each neuron in the output layer OL. The output signal of the neuron in the previous layer is input to each neuron. It can be connected to all neurons (fully connected), or it can be connected to only some neurons ( Good too.

[0163] Figure 17B shows an example of a neuron operation. Here, we consider a neuron N and a neuron The figure shows two neurons in the previous layer that output signals to N. Neuron N has a The output of the neuron x1 and the output of the neuron x2 in the previous layer are input. In N, the multiplication result of output x1 and weight w1 (x1w1) and the multiplication result of output x2 and weight w2 After the sum of the results (x2w2) x1w1+x2w2 is calculated, a bias b is added if necessary. The value a is calculated by the activation function h. and the neuron N outputs an output signal y=ah.

[0164] In this way, the operation of a neuron involves adding the product of the output of the previous layer neuron and the weight. This multiplication and addition operation is called multiplication and addition (x1w1+x2w2 above). This may be done on software using a program, or on hardware. Good too.

[0165] In one embodiment of the present invention, a product-sum operation is performed using an analog circuit as hardware. When using analog circuits for the calculation circuit, it is necessary to reduce the circuit scale of the product-sum calculation circuit or to transfer the circuit to memory. This reduces the number of accesses, thereby improving processing speed and reducing power consumption.

[0166] The multiply-accumulate circuit preferably includes an OS transistor. Since the off-state current of the transistor is extremely small, it can be used as a transistor that constitutes the analog memory of the product-sum operation circuit. It is also possible to use both Si transistors and OS transistors for multiply-and-add operations. A calculation circuit may be configured.

[0167] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0168] (Embodiment 2) In this embodiment, a structural example of an imaging device according to one embodiment of the present invention will be described.

[0169] <Structure example> FIG. 18A is a diagram showing an example of the structure of a pixel of an imaging device, and shows the stack of layers 561 and 563. It may be a layered structure.

[0170] The layer 561 includes the photovoltaic device 101. The photovoltaic device 101 is shown in FIG. As shown, it may have layers 565a and 565b. It can also be called an area.

[0171] The photoelectric conversion device 101 shown in FIG. 19A is a pn junction photodiode, for example, The layer 565a may be made of a p-type semiconductor, and the layer 565b may be made of an n-type semiconductor. Alternatively, an n-type semiconductor may be used for the layer 65a and a p-type semiconductor for the layer 565b.

[0172] The pn junction photodiode is typically formed using single crystal silicon. Photodiodes that use single-crystal silicon as a photoelectric conversion layer can detect light ranging from ultraviolet to near-infrared. It has a relatively wide spectral sensitivity characteristic, and when combined with the optical conversion layer described later, it can It can detect long wavelength light.

[0173] In addition, a compound semiconductor may be used as the photoelectric conversion layer of a pn junction photodiode. Examples of the compound semiconductor include gallium-arsenic-phosphide (GaAsP), Gallium phosphide (GaP), indium gallium arsenide (InGaAs) , lead-sulfur compounds (PbS), lead-selenium compounds (PbSe), indium-arsenic compounds (InAs), indium-antimonide (InSb), mercury-cadmium-tellurium Compounds such as HgCdTe can be used.

[0174] Compound semiconductors include group 13 elements (aluminum, gallium, indium, etc.) and Compound semiconductors containing group 15 elements (nitrogen, phosphorus, arsenic, antimony, etc.) semiconductors), or group 12 elements (magnesium, zinc, cadmium, mercury, etc.) ) and compound semiconductors containing group 16 elements (oxygen, sulfur, selenium, tellurium, etc.) (2-6 It is preferable that the semiconductor is a group compound semiconductor.

[0175] Compound semiconductors have band gaps that vary depending on the combination of constituent elements and their atomic ratio. This allows for photosensitivity in a wide range of wavelengths from ultraviolet to infrared. A diode can be formed.

[0176] The wavelength of ultraviolet light is around 0.01 μm to around 0.38 μm, and the wavelength of visible light is around 0. The wavelength of near infrared light is from about 0.75 μm to about 2.5 μm. The wavelength of mid-infrared light is around 2.5 μm to 4 μm, and the wavelength of far-infrared light is 4 μm. It can be generally defined as a distance of approximately 1000 μm to approximately 1000 μm.

[0177] For example, to form a photodiode that is sensitive to light ranging from ultraviolet light to visible light, GaP can be used for the electric conversion layer. Also, it has high photosensitivity from ultraviolet light to near-infrared light. To form a photodiode having a photoelectric conversion layer, the above-mentioned silicon or GaAs In addition, a photosensitive material having a photosensitivity from visible light to mid-infrared light can be used. To form a photodiode, InGaAs or the like can be used for the photoelectric conversion layer. In addition, to form a photodiode that is sensitive to light from near infrared light to mid-infrared light, PbS or InAs can be used for the electric conversion layer. To form a photodiode that is sensitive to light, the photoelectric conversion layer is made of PbSe and I nSb or HgCdTe or the like can be used.

[0178] Photodiodes using the above compound semiconductors can be used with pin junctions as well as pn junctions. The pn junction and pin junction are not limited to a homojunction structure, but may be a heterojunction. It may be a composite structure.

[0179] For example, in a heterojunction, a first compound semiconductor is used in one layer of a pn junction structure, and the other The layer can be made of a second compound semiconductor different from the first compound semiconductor. The first compound semiconductor is used in one or two layers of the in-junction structure, and the other layers are A second compound semiconductor different from the first compound semiconductor can be used. Either the compound semiconductor or the second compound semiconductor may be a semiconductor of an element such as silicon. stomach.

[0180] The photoelectric conversion layer of the photodiode may be formed using different materials for each pixel. By using this configuration, it is possible to obtain a pixel that detects ultraviolet light, a pixel that detects visible light, and a pixel that detects infrared light. An imaging device having two or three types of pixels, such as a pixel that emits light, is formed. It is possible.

[0181] As shown in FIG. 19B, the photoelectric conversion device 101 included in the layer 561 is The layer 566b, the layer 566c, and the layer 566d may be stacked. The photoelectric conversion device 101 is an example of an avalanche photodiode, and includes a layer 566a, a layer 566b, and a layer 566c. 66d corresponds to an electrode, and layers 566b and 566c correspond to a photoelectric conversion portion.

[0182] The layer 566a is preferably a low resistance metal layer, such as aluminum or titanium. It is possible to use tungsten, tantalum, silver or a laminate thereof.

[0183] The layer 566d is preferably formed using a conductive layer that has high transparency to visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide oxide, indium-gallium-zinc oxide, or graphene can be used. The layer 566d may be omitted.

[0184] The layers 566b and 566c of the photoelectric conversion section are pn junctions in which a selenium-based material is used as the photoelectric conversion layer. The layer 566b is made of selenium, which is a p-type semiconductor. For the layer 566c, an n-type semiconductor such as gallium oxide can be used. preferable.

[0185] Photoelectric conversion devices using selenium-based materials have the characteristic of high external quantum efficiency for visible light. In this photoelectric conversion device, the incident light is multiplied by using avalanche multiplication. The electron amplification relative to the amount of light can be increased. In addition, selenium-based materials have a light absorption coefficient This has the advantage in terms of production, as it allows the photoelectric conversion layer to be made into a thin film. The thin film can be formed by vacuum deposition or sputtering.

[0186] Selenium-based materials include crystalline selenium (single crystal selenium, polycrystalline selenium) and amorphous selenium. These have photosensitivity from ultraviolet light to visible light. Indium and selenium compounds (CIS) or copper, indium, gallium, and selenium Compounds such as CIGS can be used. These emit light from ultraviolet to near-infrared. It has light sensitivity.

[0187] The n-type semiconductor is formed from a material that has a wide band gap and is transparent to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or These materials can be used for hole injection. It also functions as a blocking layer and can reduce dark current.

[0188] As shown in FIG. 19C, the photoelectric conversion device 101 included in the layer 561 is Alternatively, the layer 567b, the layer 567c, the layer 567d, and the layer 567e may be stacked. The photovoltaic device 101 shown in FIG. 19C is an example of an organic photoconductive film, and layer 567a is a bottom electrode. The layer 567e is a light-transmitting upper electrode, and the layers 567b, 567c, and 567d are light-transmitting layers. It corresponds to the electric conversion unit.

[0189] One of the layers 567b and 567d of the photoelectric conversion portion is a hole transport layer, and the other is an electron transport layer. The layer 567c can be a photoelectric conversion layer.

[0190] The hole transport layer may be made of, for example, molybdenum oxide. For example, C 60 , C 70 or derivatives thereof. It is possible.

[0191] The photoelectric conversion layer is a mixed layer of n-type organic semiconductor and p-type organic semiconductor (bulk heterojunction). There are various types of organic semiconductors, and they can be made photosensitive to the desired wavelength. A material having such a property may be selected for the photoelectric conversion layer.

[0192] The layer 563 shown in FIG. 18A may be, for example, a silicon substrate. The capacitor substrate has a silicon transistor and the like. The silicon transistor is used to form the pixel circuit. Other circuits include circuits that drive the pixel circuits, image signal readout circuits, image processing circuits, neural networks, etc. It can be used to form networks, communication circuits, etc. Random Access Memory (RDMA) and other memory circuits, Processing Unit), MCU (Micro Controller U) In this embodiment, the above circuits except for the pixel circuit are This is called a functional circuit.

[0193] For example, the pixel circuit (pixel 100) and the functional circuit (circuit 201, 202, 203, 204, 301, 302, 303, 304, 305, etc.) In the transistor, some or all of it may be provided in layer 563.

[0194] Alternatively, layer 563 may be a stack of multiple layers as shown in Figure 18B. Although three layers, 563a, 563b, and 563c, are shown as an example, two layers may be used. Alternatively, layer 563 may be a stack of four or more layers. These layers may be formed by, for example, a lamination process. By using such a configuration, pixel circuits and functional circuits can be stacked on multiple layers. The pixel circuits and functional circuits can be stacked on top of each other, making it possible to realize a compact, high-performance image capture device. An imaging device can be fabricated.

[0195] Also, the pixel has a stacked structure of layers 561, 562, and 563 as shown in FIG. 18C. It may be possible.

[0196] Layer 562 can include OS transistors. Alternatively, the layer 563 may be formed of a Si transistor and the layer 56 One or more functional circuits may be formed using the OS transistors included in the semiconductor device 2. The layer 563 is a support substrate such as a glass substrate, and the layer 562 has an OS transistor for forming a pixel circuit. The circuits may form functional circuits.

[0197] For example, a normally-off CPU (" It is possible to realize a NoffCPU (registered trademark). U is the normally conductive state (also called the off state) even when the gate voltage is 0V. An integrated circuit includes an off-state transistor.

[0198] The NoffCPU stops supplying power to circuits that are not required to operate, and The power supply is stopped and the circuit in standby mode is powered down. Therefore, the No-CPU can minimize power consumption. In addition, the NoffCPU can retain information necessary for operation, such as setting conditions, for a long period of time even if the power supply is stopped. To return from standby mode, simply restart the power supply to the circuit. It is possible to quickly return from standby mode without having to rewrite settings. In this way, NoffCPU can reduce power consumption without significantly reducing the operating speed. It can be reduced.

[0199] Layer 562 may also be a stack of multiple layers as shown in Figure 18D. Although two layers, 562a and 562b, are shown as an example, three or more layers may be laminated. These layers can be formed, for example, stacked on top of layer 563. Alternatively, a layer formed on the layer 561 may be bonded to a layer formed on the layer 3.

[0200] The semiconductor material used for the OS transistor has an energy gap of 2 eV or more. Metal oxides having a specific resistance of 2.5 eV or more, more preferably 3 eV or more, can be used. A typical example is an oxide semiconductor containing indium, for example, a CAAC -OS or CAC-OS can be used. CAAC-OS forms a crystal. The atoms are stable, making it suitable for transistors where reliability is important. Because it exhibits high mobility, it is suitable for use in transistors that operate at high speed.

[0201] Since the energy gap of the semiconductor layer of an OS transistor is large, the current is several yA / μm (channel The OS transistor exhibits extremely low off-state current characteristics (current value per 1 μm of transistor width). The stan- dard is free from impact ionization, avalanche breakdown, and short channel effects. These features differ from Si transistors, allowing for the creation of highly reliable circuits with high voltage resistance. In addition, the electrical characteristics caused by the non-uniformity of the crystallinity, which is a problem in Si transistors, can be improved. OS transistors are also less likely to experience variations in performance.

[0202] The semiconductor layer of the OS transistor is made of, for example, indium, zinc, and M (aluminum). , titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium In containing one or more metals selected from the group consisting of tin, neodymium, and hafnium The In-M-Zn oxide can be used as a film. Typically, it can be formed by sputtering. Alternatively, the insulating layer may be formed by a layer deposition method.

[0203] Sputtering tube used to form In-M-Zn oxide by sputtering method The atomic ratio of the metal elements in the get preferably satisfies In≧M and Zn≧M. The atomic ratio of the metal elements in the sputtering target is In:M:Zn=1:1:1. , In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4 :2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M: Zn=5:1:7, In:M:Zn=5:1:8, etc. are preferred. The atomic ratio of each layer is the atomic ratio of the metal elements contained in the sputtering target. This includes a variation of plus or minus 40% in the ratio.

[0204] The semiconductor layer is made of an oxide semiconductor with a low carrier density. Carrier density is 1×10 17 / cm 3 Less than 1 × 10 15 / cm 3 Further details are as follows: Preferably 1 x 10 13 / cm 3 Less than 1×10, more preferably 11 / cm 3 Below, further Preferably 1 x 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than career secrets Such an oxide semiconductor can be a highly pure intrinsic or This oxide semiconductor has a low density of defect states and is stable. It can be said that this oxide semiconductor has stable characteristics.

[0205] However, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the required properties (e.g., the mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of a transistor, the carrier density, impurity concentration, and defect density of the semiconductor layer must be controlled. It is preferable to appropriately set the density, atomic ratio of metal element to oxygen, interatomic distance, density, etc. stomach.

[0206] In the oxide semiconductor that constitutes the semiconductor layer, silicon or carbon, which is one of the group 14 elements, is If silicon is included, oxygen vacancies increase, causing the semiconductor layer to become n-type. The silicon or carbon concentration (obtained by secondary ion mass spectrometry) was 2 × 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0207] In addition, alkali metals and alkaline earth metals generate carriers when bonded with oxide semiconductors. This may result in an increase in the off-state current of the transistor. The concentration of alkali metals or alkaline earth metals in the conductor layer (measured by secondary ion mass spectrometry) The concentration obtained is 1 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 16 a toms / cm 3 Do the following:

[0208] In addition, if nitrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, electrons, which are carriers, This increases the carrier density and makes it easier to become n-type. Transistors using conductors tend to be normally-on. The nitrogen concentration (obtained by secondary ion mass spectrometry) was 5 x 10 18atoms / cm 3 It is preferable to do the following:

[0209] In addition, if hydrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, the oxide that bonds with the metal atoms Since the oxygen reacts with oxygen to form water, oxygen vacancies may be formed in the oxide semiconductor. If the channel formation region in the conductor contains oxygen vacancies, the transistor will be normally on. Furthermore, defects in which hydrogen has entered the oxygen vacancies act as donors, In addition, some of the hydrogen atoms bond with the metal atoms, resulting in the generation of carrier electrons. It may combine with hydrogen to generate electrons, which are carriers. A transistor including an oxide semiconductor having such a structure tends to be normally on.

[0210] A defect in which hydrogen is inserted into an oxygen vacancy can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate the defects. Therefore, in this specification, the acid As a parameter of the compound semiconductor, we assume a state in which no electric field is applied, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like is This can sometimes be rephrased as "donor concentration."

[0211] Therefore, it is preferable that the amount of hydrogen in the oxide semiconductor be reduced as much as possible. In oxide semiconductors, secondary ion mass spectrometry (SIMS) The hydrogen concentration obtained by mass spectrometry was calculated as 1×10 20 a toms / cm 3Less than 1 x 10 19 atoms / cm 3 Less than, more preferably is 5 x 10 18 atoms / cm 3 less than 1×10 18 atoms / c m 3 The oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used as the transistor chip. By using it in the channel forming region, stable electrical characteristics can be imparted.

[0212] The semiconductor layer may also have a non-single crystal structure, for example. The non-single crystal structure may have a c-axis orientation. CAAC-OS (C-Axis Aligned Crystalline ne Oxide Semiconductor), polycrystalline, microcrystalline, or non-crystalline Among non-single crystalline structures, the amorphous structure has the highest defect level density and CAA C-OS has the lowest density of defect states.

[0213] An amorphous oxide semiconductor film has, for example, a disordered atomic arrangement and does not contain crystalline components. Alternatively, the amorphous oxide film may have a completely amorphous structure and no crystalline portion. stomach.

[0214] The semiconductor layer may have an amorphous structure, a microcrystalline structure, a polycrystalline structure, or a CAAC structure. The film may be a mixed film having two or more of the -OS region and the single crystal structure region. The film may have a single layer structure including two or more of the above-mentioned regions, or a laminated structure. It may have a structure.

[0215] Hereinafter, we will discuss CAC (Cloud-Aligned C), which is one type of non-single-crystal semiconductor layer. This section explains the structure of the .NET composite OS.

[0216] CAC-OS is a type of oxide semiconductor in which the elements constituting the oxide semiconductor are 0.5 nm to 10 nm thick. Preferably, the material is unevenly distributed in a size range of 1 nm to 2 nm or in the vicinity thereof. In the following, it is assumed that one or more metal elements are present in the oxide semiconductor. The region containing the metal element is unevenly distributed and has a size of 0.5 nm to 10 nm, preferably 1 nm A mixed state of particles with sizes of 2 nm or less or close to that size is called a mosaic or patch state. It is also called.

[0217] Note that the oxide semiconductor preferably contains at least indium. In addition to these, aluminum, gallium, yttrium, and zinc are preferably contained. Thorium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, Contains one or more selected from tantalum, tungsten, magnesium, etc. It may be included.

[0218] For example, CAC-OS made of In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS) α-Zn oxide may be specifically referred to as CAC-IGZO. (Hereinafter, InO X1 (X1 is a real number greater than 0) or indium zinc oxide In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) . ), or gallium zinc oxide (GaX4 Zn Y4 O Z4 (X4, Y4, and Z4 is a real number greater than 0.) The material is separated into two parts, forming a mosaic pattern. Mosaic InO X1 , or In X2 Zn Y2 O Z2 is uniformly distributed in the film This is a cloud-like configuration (hereinafter also referred to as "cloud-like").

[0219] In other words, CAC-OS is X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 A composite oxide semiconductor having a structure in which a region in which In this specification, for example, the atomic ratio of In to the element M in the first region is is greater than the atomic ratio of In to the element M in the second region. Compared to region 2, the concentration of In is higher.

[0220] IGZO is a common name and refers to a compound of In, Ga, Zn, and O. A typical example is InGaO3(ZnO) m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of such crystalline compounds include:

[0221] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and are aligned in the ab plane. is a non-oriented connected crystal structure.

[0222] On the other hand, CAC-OS refers to the material structure of an oxide semiconductor. In a material composition containing Ga, Zn, and O, some nanoparticles with Ga as the main component were observed. The region where the In nanoparticles are observed is shown in part. This refers to a structure in which the pixels are randomly distributed in a mosaic pattern. The crystal structure is a secondary factor.

[0223] It should be noted that the CAC-OS does not include a laminated structure of two or more films with different compositions. For example, a structure consisting of two layers, one containing In as the main component and the other containing Ga as the main component, is not included. do not have.

[0224] In addition, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 but In some cases, a clear boundary between the main component region and the main component region cannot be observed.

[0225] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium can be used. , boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more selected elements such as sodium are included, CAC-OS will The nanoparticle-like regions are observed in the region where the metal element is the main component, and the region where In is the main component. The nanoparticle-like regions are randomly dispersed in a mosaic pattern. say.

[0226] CAC-OS is formed by sputtering without intentionally heating the substrate. In addition, when the CAC-OS is formed by a sputtering method, the deposition gas is The gas is selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. One or more of these may be used. The lower the flow rate ratio of the gas, the more preferable. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%. It is more preferable to set the content to 0% or more and 10% or less.

[0227] CAC-OS is a type of X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan by the out-of-plane method, In other words, from the X-ray diffraction measurement, It can be seen that the orientation of the regions in the ab plane direction and the c axis direction is not observed.

[0228] In addition, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron diffraction pattern obtained by irradiating the sample, a ring-shaped area of ​​high brightness (phosphor) is formed. The electron diffraction pattern is Therefore, the crystal structure of CAC-OS does not have orientation in the planar direction and the cross-sectional direction. It can be seen that it has a nano-crystal structure.

[0229] For example, in the CAC-OS of In-Ga-Zn oxide, energy dispersive X Energy Dispersive X-ray spectroscopy (EDX) EDX mapping obtained using scopy revealed that GaO X3 The region where is the principal component And, In X2 Zn Y2 O Z2 , or InO X1 The area where the main component is unevenly distributed and mixed It can be confirmed that the compound has a structure similar to that of the compound shown in FIG.

[0230] CAC-OS has a structure different from that of IGZO compounds, in which metal elements are uniformly distributed. CAC-OS has different properties from ZO compounds. X3 The main ingredients are In a certain area, X2 Zn Y2 O Z2 , or InO X1 The region where is the principal component and The phases are separated into two, and the regions containing each element as the main component are arranged in a mosaic pattern.

[0231] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X3 This region has higher conductivity than the region where In is the main component. X2 Zn Y 2O Z2 , or InO X1 The carriers flow through the region where the main component is oxidized. Therefore, the conductivity of In is expressed as a semiconductor. X2 Zn Y2 O Z2 , or In O X1 The region where the main component is distributed in a cloud-like shape in the oxide semiconductor allows for a high electric field. Effective mobility (μ) can be achieved.

[0232] On the other hand, GaO X3 The region where the main components are In X2 Zn Y2 O Z2 , or InOX It is a region with high insulation compared to the region where 1 is the main component. That is, GaO X3 and the like By the region where it is the main component being distributed in the oxide semiconductor, the leakage current is suppressed, and good etching operation can be realized.

[0233] Therefore, when CAC-OS is used for a semiconductor device, the insulation X3 caused by GaO and the conductivity caused by In X2 Zn Y2 O Z2 or InO X1 act complementarily, so that a high on-current (I on ) and a high field-effect mobility (μ) can be realized. And it can be achieved.

[0234] Also, the semiconductor device using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0235] <Stacked Structure 1> Next, the stacked structure of the imaging device will be described using a cross-sectional view. Note that the elements such as the insulating layer and the conductive layer shown below are examples, and other elements may be further included. Or, some of the elements shown below may be omitted. Also, the stacked structure shown below can be formed using a bonding process, a polishing process, etc. as necessary.

[0236] FIG. 20 is an example of a cross-sectional view of a laminate having layers 560, 561, and 563, and having a bonding surface between layer 563a and layer 5 which constitute layer 563.

[0237] [[ID=�8]]<Layer 563b> Layer 563b may include functional circuitry disposed on silicon substrate 611. As a part of the functional circuit, the transistor 227 and the transistor 222 included in the circuit 201 are 3, transistor 224, and capacitor 222 are shown.

[0238] The layer 563b includes a silicon substrate 611, insulating layers 612, 613, 614, 616, and 617. , 618 are provided. The insulating layer 612 functions as a protective film. The insulating layer 61 functions as an interlayer insulating film and a planarizing film. The conductive layer 619 functions as a bonding layer. It is electrically connected to the gate of the resistor 105 .

[0239] Examples of the protective film include a silicon nitride film, a silicon oxide film, and an aluminum oxide film. As the interlayer insulating film and the planarizing film, for example, a silicon oxide film can be used. Inorganic insulating films such as those made of acrylic resins and polyimide resins can be used. The dielectric layer of the capacitor may be a silicon nitride film, a silicon oxide film, or an aluminum oxide film. The bonding layer will be described later.

[0240] It can also be used as wiring, electrodes, and plugs for electrical connections between devices. Conductors that can be used include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, Titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Nesium, zirconium, beryllium, indium, ruthenium, iridium, strontium Metal elements selected from the group consisting of thium, lanthanum, etc., or alloys containing the above-mentioned metal elements Alternatively, an alloy or the like combining the above-mentioned metal elements may be appropriately selected and used. It is not limited to a single layer, but may be a plurality of layers made of different materials.

[0241] <Layer 563a> Layer 563a includes elements of pixel 100 and may also include elements of functional circuitry. Here, transistors 102 and 103 are included as part of the pixel 100. 8. In the cross-sectional view shown in FIG. 20, the electrical connection between them is not shown.

[0242] The layer 563a includes a silicon substrate 632, insulating layers 631, 633, 634, 635, and 637. , 638 are provided. Conductive layers 636, 639 are also provided.

[0243] The insulating layer 631 and the conductive layer 639 function as bonding layers. , 635, and 637 function as an interlayer insulating film and a planarizing film. The insulating layer 638 serves as a protective film. The insulating layer 638 has an insulating function. The insulating layer 638 can be formed of the same material as the other insulating layers. The insulating layer 638 may be formed using the same material as the insulating layer 631.

[0244] The conductive layer 639 is connected to the other of the source and drain of the transistor 105 and the conductive layer 619 The conductive layer 636 is electrically connected to the wiring 114 (see FIG. 6). will be done.

[0245] The Si transistor shown in FIG. 20 has a channel in a silicon substrate (silicon substrates 611 and 632). The cross section in the channel width direction (shown in layer 563a in FIG. 20) is a fin type having a hole forming region. The cross section of the Si transistor is shown in FIG. 21A. It may also be of a planar type.

[0246] Alternatively, as shown in FIG. 21C, a transistor having a semiconductor layer 545 of a silicon thin film may be used. The semiconductor layer 545 may be formed on an insulating layer 546 on a silicon substrate 611, for example. The silicon-on-insulator (SOI) It is possible.

[0247] <layer 561> The layer 561 includes the photoelectric conversion device 101. The photoelectric conversion device 101 includes the layer 563a. In FIG. 20, the photoelectric conversion device 101 can be formed on the substrate shown in FIG. 19C. The photoelectric conversion layer 567a is made of an organic photoconductive film. the cathode, and layer 567e the anode.

[0248] Layer 561 is provided with insulating layers 651, 652, 653, 654 and conductive layer 655. do.

[0249] The insulating layers 651, 653, and 654 function as an interlayer insulating film and a planarizing film. In addition, the insulating layer 654 is provided to cover the edge of the photoelectric conversion device 101, and the layer 567e and the layer 567f are The insulating layer 652 also functions as an element isolation layer. As the element isolation layer, it is preferable to use an organic insulating film or the like.

[0250] The layer 567a corresponding to the cathode of the photoelectric conversion device 101 is a transistor included in the layer 563a. The photoelectric conversion device 1 is electrically connected to either the source or the drain of the transistor 102. The layer 567e corresponding to the anode of O1 is connected to the conductive layer 655 via the conductive layer 655. The electrode layer 636 is electrically connected to the electrode layer 636 .

[0251] <layer 560> The layer 560 is formed on the layer 561. The layer 560 includes a light-shielding layer 671, an optical conversion layer 672, and and a microlens array 673.

[0252] The light-shielding layer 671 can prevent light from flowing into adjacent pixels. A metal layer such as aluminum or tungsten can be used. A dielectric film having a function as an anti-reflection film may be laminated.

[0253] When the photoelectric conversion device 101 is sensitive to visible light, a color filter is applied to the optical conversion layer 672. The color filters are red, green, blue, yellow, and C. A color image can be obtained by assigning colors such as C (cyan) and M (magenta) to each pixel. For example, as shown in the perspective view (including cross section) of FIG. 30A, Color filter 672R (red), color filter 672G (green), color filter 672B (blue) Each of these can be assigned to a different pixel.

[0254] In addition, in a suitable combination of the photoelectric conversion device 101 and the optical conversion layer 672, If a wavelength cut filter is used in the conversion layer 672, images in various wavelength regions can be obtained. It may be an imaging device.

[0255] For example, if an infrared filter that blocks light having wavelengths shorter than visible light is used for the optical conversion layer 672, The optical conversion layer 672 can be used as an infrared imaging device. If a filter that blocks infrared rays is used, it can be used as a far-infrared imaging device. If an ultraviolet filter that blocks light with wavelengths longer than visible light is used in 72, it can be used as an ultraviolet imaging device. It is possible.

[0256] It is also possible to arrange a plurality of different optical conversion layers in one imaging device. For example, in FIG. As shown, color filter 672R (red), color filter 672G (green), The blue filter 672B and the infrared filter 672IR can be assigned to different pixels. In this configuration, visible light images and infrared light images can be acquired simultaneously. .

[0257] Alternatively, as shown in FIG. 30C, a color filter 672R (red), a color filter 672 G (green), color filter 672B (blue), ultraviolet filter 672UV In this configuration, visible light images and ultraviolet light images can be captured simultaneously. You can gain.

[0258] In addition, if a scintillator is used for the optical conversion layer 672, the radiation used in an X-ray imaging device, etc. It can be used as an imaging device to obtain an image that visualizes the intensity of radiation such as X-rays that has passed through the subject. When radiation strikes the scintillator, it emits visible or ultraviolet light due to the photoluminescence phenomenon. The light is converted into light (fluorescence) such as external light. The light is then detected by the photoelectric conversion device 101. Image data is acquired by installing an imaging device having this configuration in a radiation detector or the like. It may be used.

[0259] When exposed to radiation such as X-rays or gamma rays, the scintillator absorbs the energy. It includes materials that absorb and emit visible or ultraviolet light. For example, Gd2O2S:Tb, Gd2O 2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, Ba F2, CeF3, LiF, LiI, ZnO, etc. dispersed in resin or ceramics can be used.

[0260] By taking images using infrared or ultraviolet light, it is possible to perform inspection, security, and sensor functions. For example, by taking an image using infrared light, Non-destructive testing of objects, sorting of agricultural products (such as sugar content meter functions), vein authentication, medical testing, etc. In addition, by taking an image using ultraviolet light, it is possible to detect the ultraviolet light emitted from the light source or flame. This allows for the management of light sources, heat sources, production equipment, etc.

[0261] A microlens array 673 is provided on the optical conversion layer 672. The light passing through each lens of the lens 673 passes through the optical conversion layer 672 directly below, and By providing the microlens array 673, Since the collected light can be incident on the photoelectric conversion device 101, photoelectric conversion can be performed efficiently. The microlens array 673 has high transparency to light of a target wavelength. It is preferable to form the substrate from a thin resin or glass.

[0262] <Laminating> Next, the bonding of the layer 563b and the layer 563a will be described.

[0263] The layer 563b is provided with an insulating layer 618 and a conductive layer 619. The conductive layer 619 is an insulating The insulating layer 618 and the conductive layer 619 have a buried region. They are flattened to match the height.

[0264] The layer 563a includes an insulating layer 631 and a conductive layer 639. The conductive layer 639 is an insulating The insulating layer 631 and the conductive layer 639 have a buried region. They are flattened to match the height.

[0265] Here, the conductive layer 619 and the conductive layer 639 preferably contain the same metal element as the main component. In addition, it is preferable that the insulating layer 618 and the insulating layer 631 are made of the same component. Desirable.

[0266] For example, the conductive layers 619 and 639 may be made of Cu, Al, Sn, Zn, W, Ag, Pt, or A. In view of ease of bonding, Cu, Al, W, or The insulating layers 618 and 631 are made of silicon oxide, silicon oxynitride, or nitride. Silicon oxide, silicon nitride, titanium nitride, etc. can be used.

[0267] That is, the conductive layer 619 and the conductive layer 639 are made of the same metal material as described above. In addition, it is preferable that the insulating layer 618 and the insulating layer 631 are made of the above-described material. It is preferable to use the same insulating material. The bonding can be performed with the boundary of a as the joining position.

[0268] The conductive layer 619 and the conductive layer 639 may have a multilayer structure. The insulating layer 618 and the insulating layer 619 may be made of the same metal material as long as the surface layers (bonding surfaces) are made of the same metal material. 31 may also be a multi-layer structure with multiple layers, in which case the surface layers (joint surfaces) are made of the same insulating material. It's fine as long as it's free.

[0269] By this bonding, electrical connection between the conductive layer 619 and the conductive layer 639 can be obtained. Furthermore, it is possible to obtain a connection having mechanical strength between the insulating layer 618 and the insulating layer 631. can be done.

[0270] To bond metal layers together, the oxide film on the surface and the adsorption layer of impurities are removed by sputtering or other methods. The surface activated bonding method is used to bond the cleaned and activated surfaces together. Alternatively, a diffusion bonding method can be used, which uses a combination of temperature and pressure to bond surfaces together. Both of these bond at the atomic level, so they can be used not only electrically but also mechanically. Mechanically excellent bonding can also be obtained.

[0271] In addition, to bond the insulating layers together, after obtaining high flatness by polishing, etc., oxygen plasma etc. The hydrophilic treated surfaces are brought into contact with each other to temporarily bond them together, and then the final bonding is performed by dehydrating them through heat treatment. Aqueous bonding methods can be used. Hydrophilic bonding also occurs at the atomic level, so , and mechanically excellent bonding can be obtained.

[0272] When the layer 563b and the layer 563a are bonded together, an insulating layer and a metal layer are mixed on each bonding surface. Therefore, for example, the surface activated bonding method and the hydrophilic bonding method may be combined.

[0273] For example, after polishing, the surface is cleaned, and the surface of the metal layer is subjected to an anti-oxidation treatment and then to a hydrophilic treatment. Alternatively, the surface of the metal layer may be treated with a hard metal such as Au. It is also possible to use an oxidized metal and then subject it to hydrophilic treatment. That's fine.

[0274] By the above-mentioned bonding, the circuit of the layer 563b and the pixel 100 of the layer 563a are The elements can be electrically connected.

[0275] <Modification of laminate structure 1> FIG. 22 shows a modification of the laminated structure shown in FIG. 20, in which the layer 561 has a photoelectric conversion device 1 The structure of layer 561 and the structure of part of layer 563a are different, and there is also a layer 561 and a layer 563a between them. It has a mating surface.

[0276] The layer 561 includes the photovoltaic device 101, insulating layers 661, 662, 664, 665 and conductive layers. The conductive layers 685 and 686 are provided.

[0277] The photoelectric conversion device 101 is a pn junction photodiode, and the layer corresponding to the p-type region 565b and a layer 565a corresponding to an n-type region. This shows an example in which a photodiode is formed on a silicon substrate. It is a built-in photodiode, and is provided on the surface side (current extraction side) of the layer 565a. The thin p-type region (part of the layer 565b) can suppress dark current and reduce noise. Cut.

[0278] The insulating layer 661 and the conductive layers 685 and 686 function as bonding layers. The insulating layer 664 functions as an interlayer insulating film and a planarizing film. It has the function as.

[0279] The silicon substrate has grooves for separating pixels, and an insulating layer 665 is formed on the top surface of the silicon substrate and The insulating layer 665 is provided in the groove. This can prevent carriers generated in the insulating layer from flowing to adjacent pixels. The insulating layer 665 also has the function of suppressing the intrusion of stray light. In addition, an anti-reflection film is formed between the upper surface of the silicon substrate and the insulating layer 665. may be provided.

[0280] The insulating layer 664 is formed by LOCOS (LOCal Oxidation of Silicon) Alternatively, the STI (Shallow Trench Ionization) method can be used. The insulating layer 665 may be formed by, for example, an acid isolation method. Inorganic insulating films such as silicon dioxide and silicon nitride, and organic insulating films such as polyimide resin and acrylic resin An insulating film can be used. The insulating layer 665 may have a multi-layer structure. A space may be provided in a portion of the edge layer 665. The space may be filled with a gas such as air or an inert gas. The space may be in a reduced pressure state.

[0281] The layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101 is connected to the conductive layer 685. The layer 565b (p-type region, corresponding to the anode) is electrically connected to the conductive layer 686. The conductive layers 685 and 686 have regions buried in the insulating layer 661. In addition, the surfaces of the insulating layer 661 and the conductive layers 685 and 686 are aligned to the same height. It is flattened.

[0282] In the layer 563a, an insulating layer 638 is formed on the insulating layer 637. a conductive layer 683 electrically connected to one of the source and drain of the transistor 102; A conductive layer 684 is formed that is electrically connected to the conductive layer 636 .

[0283] The insulating layer 638 and the conductive layers 683 and 684 function as bonding layers. 83, 684 have regions buried in the insulating layer 638. Also, the insulating layer 638 and the conductive The surfaces of the conductive layers 683 and 684 are flattened so that they are at the same height.

[0284] Here, the conductive layers 683, 684, 685, and 686 are the same as the conductive layers 619 and 639 described above. The insulating layers 638 and 661 are the same as the insulating layers 618 and 631. It is the same lamination layer as

[0285] Therefore, by bonding the conductive layer 683 and the conductive layer 685 together, the photoelectric conversion device 10 The first layer 565a (n-type region, corresponding to the cathode) and the source or drain of the transistor 102 In addition, the conductive layer 684 and the conductive layer 686 can be attached to each other. By combining them, the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device 101 is formed. The wiring 114 (see FIG. 6) can be electrically connected. By bonding 661, the layer 561 and the layer 563a are electrically and mechanically bonded. This can be done.

[0286] FIG. 23 shows a modified example different from the above, in which the transistor 102 is provided on the layer 561. In this configuration, one of the source and drain of the transistor 102 is The other of the source and drain is directly connected to the electric conversion device 101 and acts as a node N. In this configuration, the charge accumulated in the photoelectric conversion device 101 can be completely transferred. This makes it possible to provide an imaging device with less noise.

[0287] Here, the other of the source and the drain of the transistor 102 included in the layer 561 is a conductive layer 692. The gate of the transistor 105 in the layer 563 is electrically connected to The conductive layers 691 and 692 are electrically connected to the conductive layer 619 and the conductive layer 692. It is the same lamination layer as 639.

[0288] <Laminated structure 2> FIG. 24 shows a laminate having layers 560, 561, 562, and 563 and no bonding surface. 5 is an example of a cross-sectional view. Layer 563 is provided with a Si transistor. Layer 562 is provided with an O The layers 563, 561, and 560 are configured as shown in FIG. 0, so the explanation will be omitted here.

[0289] <layer 562> Layer 562 is formed on layer 563. Layer 562 includes an OS transistor. shows transistor 102 and transistor 108. In the cross-sectional view shown in FIG. The electrical connection between them is not shown.

[0290] The layer 562 is provided with insulating layers 621, 622, 623, 624, 625, 626, and 628. In addition, a conductive layer 627 is provided. The conductive layer 627 is connected to the wiring 114 (see FIG. 6). Electrical connection can be made.

[0291] The insulating layer 621 functions as a blocking layer. , 626, and 628 function as an interlayer insulating film and a planarizing film. , and has a function as a protective film.

[0292] As the blocking layer, it is preferable to use a film having a function of preventing the diffusion of hydrogen. In Si devices, hydrogen is needed to terminate dangling bonds, Hydrogen near the OS transistor is one of the factors that generate carriers in the oxide semiconductor layer. Therefore, the layer where the Si device is formed and the OS transistor It is preferable that a hydrogen blocking film is provided between the layer on which the transistor is formed and the layer on which the transistor is formed.

[0293] The blocking film may be made of, for example, aluminum oxide, aluminum oxynitride, or oxide. Gallium, gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide Examples of usable materials include hafnium oxide nitride, yttria stabilized zirconia (YSZ), etc. do.

[0294] The other of the source or drain of transistor 108 is connected to transistor 10 through a plug. The conductive layer 627 is electrically connected to the gate of the gate electrode 5. The conductive layer 627 is also electrically connected to the wiring 114 (see FIG. 3A). are electrically connected.

[0295] One of the source and drain of the transistor 102 is a photoelectric conversion device included in the layer 561. The conductive layer 627 is electrically connected to the cathode of the photoelectric conversion layer 561. It is electrically connected to the anode of the device 101 .

[0296] FIG. 25A shows the details of an OS transistor. The OS transistor shown in FIG. An insulating layer is provided over a stack of a semiconductor layer and a conductive layer, and an opening reaching the oxide semiconductor layer is provided. A self-aligned structure in which a source electrode 705 and a drain electrode 706 are formed by It is completed.

[0297] The OS transistor has a channel formation region 708 and a source region 709 formed in the oxide semiconductor layer. 703 and drain region 704, as well as a gate electrode 701 and a gate insulating film 702. In the opening, at least the gate insulating film 702 and the gate An electrode 701 is provided. An oxide semiconductor layer 707 is further provided in the opening. That's fine.

[0298] As shown in FIG. 25B, the OS transistor is formed by forming a semiconductor layer 701 using the gate electrode 701 as a mask. As a self-aligned structure in which a source region 703 and a drain region 704 are formed in Good too.

[0299] Alternatively, as shown in FIG. 25C, the source electrode 705 or the drain electrode 706 and the gate electrode A non-self-aligned top-gate transistor having an area overlapping with the electrode 701. It's okay to have one.

[0300] The OS transistor has a structure having a back gate 735. The back gate 735 may be a transistor channel as shown in FIG. As shown in the cross section in the panel width direction, the front gate and the electric 25D is an example of a cross section of the transistor shown in FIG. 25A taken along line B1-B2. However, the same applies to transistors with other structures. 35 may be configured to be supplied with a fixed potential different from that of the front gate.

[0301] <Modification of laminate structure 2> FIG. 26 shows a modified example of the laminated structure shown in FIG. 25, in which the layer 561 has a photoelectric conversion device 1 The structure of layer 561 and the structure of part of layer 562 are different, and the layer 561 and the layer 562 are bonded together. It has a surface.

[0302] The photoelectric conversion device 101 included in the layer 561 is a pn junction photodiode. The configuration is the same as that shown in 22.

[0303] In layer 562, insulating layer 648 is formed on insulating layer 628. a conductive layer 688 electrically connected to one of the source and drain of the capacitor 102; A conductive layer 689 is formed that is electrically connected to layer 627 .

[0304] The insulating layer 648 and the conductive layers 688 and 689 function as bonding layers. 88, 689 have regions buried in the insulating layer 648. Also, the insulating layer 648 and the conductive The surfaces of the conductive layers 683 and 684 are flattened so that they are at the same height.

[0305] Here, the conductive layers 688 and 689 are the same laminating layers as the conductive layers 619 and 639 described above. The insulating layer 648 is a laminated layer similar to the insulating layers 618 and 631 described above. .

[0306] Therefore, by bonding the conductive layer 688 and the conductive layer 685 together, the layer of the photoelectric conversion device 565a (n-type region, corresponding to the cathode) and the source or drain of the transistor 102 One of the conductive layers 689 and 686 can be electrically connected. By this, the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device and the wiring 114 ( 6) can be electrically connected. By joining the layers 561 and 562 together, electrical and mechanical bonding can be achieved. Cut.

[0307] When multiple Si devices are stacked, the polishing and bonding processes are required multiple times. Therefore, there are issues such as the large number of processes, the need for dedicated equipment, and low yields, which increases manufacturing costs. The OS transistor is formed by stacking it on a semiconductor substrate on which other devices are formed. This allows the bonding process to be reduced.

[0308] Note that the structure in which the transistor 102 is provided in the layer 561 shown in FIG. 23 is applied to this structure. Good too.

[0309] As shown in FIG. 27, a reflective layer is provided between the photoelectric conversion device 101 and the OS transistor. 629 may be provided. However, some of the light with longer wavelengths is absorbed by the semiconductor layer of the photoelectric conversion device. The light may pass through the electric conversion device 101 and reach the device below.

[0310] Irradiation of light onto the OS transistor causes noise such as an increase in off-state current. By providing the reflective layer 629 with the potential G By fixing it to a neutral potential, it can act as an electromagnetic shield, and further reduce noise. can be reduced.

[0311] Furthermore, the light reflected by the reflective layer 629 returns to the semiconductor layer of the photoelectric conversion device 101, and Therefore, the sensitivity of the photoelectric conversion device 101 can be improved. 629 is a metal similar to the conductor that can be used as the wiring, electrode and plug described above. It can be formed from a metal material.

[0312] The surface of the reflective layer 629 can efficiently reflect light incident on the photoelectric conversion device 101. As such a configuration, it is preferable to provide unevenness on the surface of the reflective layer 629, The implementer can select the most suitable structure as appropriate, such as making the surface of 29 mirror-finished.

[0313] Also, the memory cell 150 can be provided in, for example, layer 562. Functional circuitry 203 may be provided, for example, in layer 563 .

[0314] FIG. 28 shows the transistors 102, 108, etc., which are elements of the pixel circuit, and the memory cell 150. The transistor 272 and other components are provided on the same surface of the layer 562. 563 is a transistor 271 (the input of the current mirror circuit CM) which is an element of the circuit 203. The transistor 272 is connected to the transistor It is electrically connected to the transistor 271 .

[0315] FIG. 29 also shows that in layer 562, transistors 102 and 105, which are elements of the pixel circuit, are , 108, etc., and transistors 272, 273, etc., which are elements of the memory cell 150, overlap. This structure is stacked to have a region. By using this structure, the circuit area can be reduced. This allows for the formation of a highly functional and compact imaging device. This allows for shorter wiring distances to be electrically connected, enabling high-speed, low-power operation. It becomes possible to create

[0316] 28 and 29 show an example in which memory cell 150 is formed of an OS transistor. When the memory cell 150 is formed of a Si transistor, the memory cell 150 is formed of a Si transistor as shown in FIGS. The transistors constituting the memory cell 150 can be provided in the layer 563a shown in FIG.

[0317] 28 and 29, the transistor 102 is provided in the layer 561 shown in FIG. Alternatively, the configuration of the photoelectric conversion device 101 shown in FIG. Good too.

[0318] <Package, Module> FIG. 31A1 is a perspective view showing the appearance of the upper surface side of a package containing an image sensor chip. The package is a package that fixes the image sensor chip 450 (see FIG. 31A3). The substrate 410, the cover glass 420, and the adhesive 430 that bonds the two together are included.

[0319] 31A2 is a perspective view of the bottom surface of the package. It has a BGA (Ball grid array) with rice balls as bumps 440. Not just BGA, but also LGA (Land grid array) or PGA (Pin The ion implantation device may have a grid array or the like.

[0320] FIG. 31A3 shows the package with the cover glass 420 and adhesive 430 partially removed. Electrode pads 460 are formed on a package substrate 410. The electrode pad 460 and the bump 440 are electrically connected via a through hole. The electrode 460 is electrically connected to the image sensor chip 450 by a wire 470. do.

[0321] FIG. 31B1 shows a camera in which an image sensor chip is housed in a lens-integrated package. This is a perspective view of the top surface of the module. The package substrate 411, the lens cover 421, and the lens 451 (FIG. 31B3) are fixed to the package substrate 411. The package substrate 411 and the image sensor chip 451 are also included. Between them is an IC chip 490 ( Figure 31B3 is also provided, and SiP (System in package) It has the following structure.

[0322] 31B2 is a perspective view of the appearance of the lower surface side of the camera module. The bottom and side surfaces of the package 1 are provided with lands 441 for mounting. The structure is an example only. QFP (Quad flat package) or the BGA mentioned above is provided. Good too.

[0323] FIG. 31B3 shows the module with the lens cover 421 and part of the lens 435 omitted. The land 441 is electrically connected to the electrode pad 461, and the electrode pad 4 61 is electrically connected to the image sensor chip 451 or IC chip 490 by wires 471 are actively connected.

[0324] By housing the image sensor chip in the package of the above type, it is possible to This makes it easier to mount image sensor chips on various semiconductor devices and electronic equipment. It is possible.

[0325] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0326] (Embodiment 3) Examples of electronic devices that can use the imaging device according to one embodiment of the present invention include display devices, personal computers, and the like. a personal computer, an image storage device or image reproduction device equipped with a recording medium, a mobile phone, a mobile phone Game consoles, including those with a camcorder, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras such as cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copying machines, fax machines, printers, printer-combined machines, automated teller machines (ATMs), Examples of such electronic devices include vending machines, etc. Specific examples of these electronic devices are shown in Figures 32A to 32F.

[0327] FIG. 32A shows an example of a mobile phone, which includes a housing 981, a display unit 982, an operation button 983, an external The mobile phone has a connection port 984, a speaker 985, a microphone 986, a camera 987, etc. The mobile phone has a touch sensor on the display unit 982. All operations, such as touching the display 982 with a finger or a stylus, can be performed. The imaging device and the operation method thereof according to one embodiment of the present invention are applied to the mobile phone. It is possible.

[0328] FIG. 32B shows a portable data terminal, which includes a housing 911, a display unit 912, a speaker 913, a camera The display unit 912 has a touch panel function for inputting and outputting information. In addition, characters and the like can be recognized from an image acquired by the camera 919 and output through the speaker 913. The character can be output as voice. and its operating method can be applied.

[0329] FIG. 32C shows a surveillance camera, which includes a support base 951, a camera unit 952, and a protective cover 953. The camera unit 952 is provided with a rotation mechanism and is installed on the ceiling. The present invention relates to the elements for image acquisition in the camera unit. The imaging device and the operation method thereof according to the above embodiment can be applied to a surveillance camera. This is a common name and does not limit its use. For example, it can be used as a surveillance camera. The device is also called a camera or video camera.

[0330] FIG. 32D shows a video camera, which includes a first housing 971, a second housing 972, a display unit 973, and an operation unit. It has a key 974, a lens 975, a connection part 976, a speaker 977, a microphone 978, etc. The operation keys 974 and the lens 975 are provided on the first housing 971, and the display unit 973 is The video camera is provided in a second housing 972. The video camera is provided with an imaging device according to one embodiment of the present invention and The method of operation can be applied.

[0331] FIG. 32E shows a digital camera, which includes a housing 961, a shutter button 962, and a microphone 963. , a light emitting unit 967, a lens 965, etc. The digital camera is The device and its method of operation can be applied.

[0332] FIG. 32F shows a wristwatch-type information terminal, which includes a display unit 932, a housing / wristband 933, a camera, The display unit 932 has a touch panel for operating the information terminal. The display unit 932 and the housing / wristband 933 are flexible and have excellent wearability on the body. The imaging device and the operation method thereof according to one embodiment of the present invention are applied to the information terminal. can be done.

[0333] FIG. 33 shows an external view of an automobile as an example of a moving object. The automobile 890 has a plurality of It has a camera 891 and can acquire information on the front, back, left, right and above of the car 890. The imaging device and its operation method according to one embodiment of the present invention can be applied to the camera 891. In addition, automobiles 890 are equipped with infrared radar, millimeter wave radar, laser radar, etc. The car 890 is equipped with various sensors (not shown) such as The image captured by the camera 891 is analyzed to determine the surrounding area, such as the presence or absence of guardrails or pedestrians. The camera 891 can also detect the surrounding traffic conditions and perform automatic driving. It can be used in systems that perform risk prediction, etc.

[0334] In the imaging device according to one aspect of the present invention, the obtained image data is subjected to a computation such as a neural network. By performing computational processing, for example, it is possible to increase the resolution of images, reduce image noise, and perform facial recognition (for crime prevention purposes). etc.), object recognition (for the purpose of autonomous driving, etc.), image compression, image correction (wide dynamic range image restoration, positioning, character recognition, and reflection reduction for lensless image sensors. Which processing can be performed?

[0335] In the above description, an automobile is used as an example of a moving body. The vehicle may be any of a vehicle with a fuel cell, an electric vehicle, a hydrogen vehicle, etc. For example, the mobile object is not limited to a car. Other examples include helicopters, unmanned aerial vehicles (drones), airplanes, and rockets. By applying the computer of one aspect of the present invention to these moving bodies, a system using artificial intelligence can be realized. can be granted. [Explanation of symbols]

[0336] a1: terminal, a2: terminal, a3: terminal, b1: terminal, b2: terminal, b3: terminal, c1: terminal child, c2: terminal, c3: terminal, CM: current mirror circuit, CMa: current mirror circuit , CMb: current mirror circuit, CM1: current mirror circuit, CM2: current mirror circuit, CM3: current mirror circuit, CM4: current mirror circuit, G1: signal line, G2 : signal line, Tr1: transistor, Tr2: transistor, 100: pixel, 101: photoelectric Conversion device, 102: transistor, 103: transistor, 104: capacitor, 1 05:Transistor, 106:Transistor, 108:Transistor, 109:Capacitor ta, 111: wiring, 112: wiring, 112_1: wiring, 112_2: wiring, 112_3: Wiring, 113: Wiring, 114: Wiring, 115: Wiring, 116: Wiring, 117: Wiring, 12 2: Wiring, 122_1: Wiring, 122_2: Wiring, 122_3: Wiring, 140: Wiring, 1 41: wiring, 142: wiring, 150: memory cell, 150a: memory cell, 150b: memory cell, 151: memory circuit, 155: selection circuit, 161: transistor, 162: Transistor, 163: capacitor, 200: pixel block, 201: circuit, 202: circuit ,203: Circuit, 204: Circuit, 212: Wiring, 213: Wiring, 215: Wiring, 216: Wiring, 217: Wiring, 218: Wiring, 219: Wiring, 222: Capacitor, 223: Transistor Transistor, 224: transistor, 225: transistor, 226: transistor, 22 7: transistor, 230: circuit, 230a: circuit, 230b: circuit, 240: circuit, 2 50: Circuit, 271: Transistor, 272: Transistor, 273: Transistor, 2 74: capacitor, 300: pixel array, 301: circuit, 302: circuit, 303: circuit, 304: Circuit, 305: Circuit, 311: Wiring, 320: Memory cell, 325: Reference memory Cell, 330: circuit, 350: circuit, 360: circuit, 370: circuit, 410: package Substrate, 411: package substrate, 420: cover glass, 421: lens cover, 430 : Adhesive, 435: Lens, 440: Bump, 441: Land, 450: Image sensor Chip, 451: image sensor chip, 460: electrode pad, 461: electrode pad, 4 70: Wire, 471: Wire, 490: IC chip, 545: Semiconductor layer, 546: Insulation layer, 560: layer, 561: layer, 562: layer, 562a: layer, 563: layer, 563a: layer, 563b: layer, 563c: layer, 565a: layer, 565b: layer, 566a: layer, 566b: layer, 566c: layer, 566d: layer, 567a: layer, 567b: layer, 567c: layer, 567 d: layer, 567e: layer, 611: silicon substrate, 612: insulating layer, 613: insulating layer, 61 4: insulating layer, 616: insulating layer, 617: insulating layer, 618: insulating layer, 619: conductive layer, 62 1: insulating layer, 622: insulating layer, 623: insulating layer, 624: insulating layer, 625: insulating layer, 62 6: insulating layer, 627: conductive layer, 628: insulating layer, 629: reflective layer, 631: insulating layer, 63 2: silicon substrate, 633: insulating layer, 634: insulating layer, 635: insulating layer, 636: conductive layer , 637: insulating layer, 638: insulating layer, 639: conductive layer, 648: insulating layer, 651: insulating layer , 652: insulating layer, 653: insulating layer, 654: insulating layer, 655: conductive layer, 661: insulating layer 662: insulating layer, 664: insulating layer, 665: insulating layer, 671: light-shielding layer, 672: optical variable 672B: Color filter, 672G: Color filter, 672IR: Infrared filter 672R: Color filter, 672UV: Ultraviolet filter, 673: Microlens Array, 683: Conductive layer, 684: Conductive layer, 685: Conductive layer, 686: Conductive layer, 688 : Conductive layer, 689: Conductive layer, 691: Conductive layer, 692: Conductive layer, 701: Gate electrode, 7 02: Gate insulating film, 703: Source region, 704: Drain region, 705: Source electrode 706: drain electrode; 707: oxide semiconductor layer; 708: channel formation region; 735 : back gate, 890: automobile, 891: camera, 892: imaging direction, 911: housing, 912: Display unit, 913: Speaker, 919: Camera, 932: Display unit, 933: Housing and Wristband, 939: camera, 951: support stand, 952: camera unit, 953: holder Protective cover, 961: Housing, 962: Shutter button, 963: Microphone, 965: Lens 967: light emitting unit, 971: housing, 972: housing, 973: display unit, 974: operation keys, 975: Lens, 976: Connection part, 977: Speaker, 978: Microphone, 981: Housing, 982: Display unit, 983: Operation buttons, 984: External connection port, 985: Speaker, 9 86: Microphone, 987: Camera

Claims

[Claim 1] a plurality of pixel blocks and a first circuit; each of the plurality of pixel blocks includes a plurality of pixels and a memory cell; the memory cells store analog data calculated in accordance with data generated by the plurality of pixels; The first circuit has a function of reading out a maximum value of the analog data stored in the memory cells of each of the plurality of pixel blocks.

Images