Image pickup device

Abstract

To suppress an influence of an IR drop caused by a difference in wiring length for each pixel, and to suppress unevenness caused in a captured image.SOLUTION: One aspect of the present invention is an image sensor. The imaging element includes a signal line connected to a plurality of pixels provided side by side along a first direction and a second direction intersecting the first direction, the signal line including a first signal line disposed at a center of a region where the plurality of pixels are provided when viewed from a third direction orthogonal to the first direction and the second direction, and a second signal line disposed so as to surround the first signal line in the region when viewed from the third direction, the second signal line branching from the first signal line and connected to each of the plurality of pixels. The imaging element includes a first current source that is connected to the first signal line and supplies a current to the signal line. The image sensor includes a second current source connected to the second signal line and configured to supply a current to the signal line.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to an imaging device. [Background technology]

[0002] For example, there is a technology described in Patent Document 1 below as an imaging element, but it is desired to suppress the influence of IR drop caused by differences in wiring length for each pixel and to suppress unevenness that occurs in captured images. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-151692 Summary of the Invention

[0004] One aspect of the present invention is an image sensor. The image sensor includes signal lines connected to a plurality of pixels arranged side by side along a first direction and a second direction intersecting the first direction, the signal lines including a first signal line disposed at the center of an area in which the plurality of pixels are arranged when viewed from a third direction orthogonal to the first and second directions, and second signal lines disposed in the area so as to surround the first signal line when viewed from the third direction, branching from the first signal line and connected to each of the plurality of pixels. The image sensor includes a first current source connected to the first signal line for supplying a current to the signal line. The image sensor includes a second current source connected to the second signal line for supplying a current to the signal line. [Brief explanation of the drawings]

[0005] [Figure 1] 1 is a schematic diagram showing the overall configuration of an image sensor according to an embodiment. [Figure 2] FIG. 2 is a diagram showing a circuit configuration of a pixel of an image sensor according to an embodiment. [Figure 3] 2 is a cross-sectional view of a chip that constitutes the imaging element according to the first embodiment. FIG. [Figure 4]1 is a perspective view showing a schematic configuration of a pixel block and a circuit unit in an imaging element according to a first embodiment. [Figure 5] 1 is a circuit configuration diagram showing a schematic configuration of a pixel block and a circuit unit according to a first embodiment. [Figure 6] FIG. 10 is a circuit configuration diagram showing a schematic configuration of a pixel block and a circuit unit in an image sensor according to a second embodiment. [Figure 7] FIG. 10 is a circuit configuration diagram showing a schematic configuration of a pixel block and a circuit unit in an image sensor according to a third embodiment. [Figure 8] FIG. 11 is a perspective view showing a second current source arranged between a plurality of pixel blocks in an image sensor according to a third embodiment. [Figure 9] FIG. 11 is a diagram showing the configuration of a switching section of a second current source arranged between four pixel blocks in an image sensor according to a third embodiment. [Figure 10] FIG. 10 is a cross-sectional view of a chip that constitutes an imaging element according to a third embodiment. [Figure 11] FIG. 10 is a circuit configuration diagram showing a second current source arranged between a plurality of pixel blocks in an image sensor according to a fourth embodiment. [Figure 12] FIG. 10 is a circuit configuration diagram showing a schematic configuration of a pixel block and a circuit unit in an image sensor according to a fifth embodiment. [Figure 13] FIG. 11 is a perspective view showing a second current source and a second processing unit arranged between a plurality of pixel blocks in an image sensor according to a fifth embodiment. [Figure 14] FIG. 13 is a diagram showing the configuration of a second current source disposed between four pixel blocks and a switching section of a second processing section in an image sensor according to a fifth embodiment. [Figure 15] FIG. 10 is a cross-sectional view of a chip that constitutes an imaging element according to a fifth embodiment. [Figure 16] FIG. 13 is a circuit configuration diagram showing a schematic configuration of a pixel block and a circuit unit in an image sensor according to a sixth embodiment. [Figure 17] FIG. 13 is a circuit configuration diagram showing a schematic configuration of a pixel block and a circuit unit in an image sensor according to a seventh embodiment. [Figure 18] FIG. 13 is a circuit configuration diagram showing a schematic configuration of a pixel block and a circuit unit in an image sensor according to an eighth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0006] Hereinafter, embodiments will be described with reference to the drawings. In the drawings, in order to explain the embodiments, some parts are enlarged or emphasized, and the scale is appropriately changed, and the shape and dimensions may differ from those of the actual product. The drawings include diagrams that explain directions in the drawings using an XYZ coordinate system. In this XYZ coordinate system, a plane parallel to the chip that constitutes the imaging element is defined as the XY plane. One direction in this XY plane is referred to as the X direction (first direction), and the direction perpendicular to the X direction is referred to as the Y direction (second direction). The direction perpendicular to the XY plane is referred to as the Z direction (third direction).

[0007] [First embodiment] A first embodiment will be described. FIG. 1 is a schematic diagram showing the overall configuration of an image sensor 1A. As shown in FIG. 1, the image sensor 1A is, for example, a CMOS image sensor in which a plurality of pixels are two-dimensionally arranged. The image sensor 1A is provided in, for example, an imaging section of a digital camera, a digital video camera, or a portable information terminal with an imaging function (e.g., a smartphone, a tablet, or a mobile phone with a camera). The image sensor 1A captures an image formed by an imaging optical system provided in the imaging section. The imaging result of the image sensor 1A includes, for example, information on the gradation value for each color of each pixel (e.g., RGB data). The image sensor 1A outputs the imaging result in, for example, a full-color image data format.

[0008] The imaging element 1A includes a pixel section 2 and a circuit section 4A. When viewed from the Z direction, the imaging element 1A is configured from a chip 11 that is, for example, a rectangular plate. The chip 11 is formed along the XY plane. The chip 11 has a pad arrangement region 12 and a pixel region 13. The pad arrangement region 12 is arranged along the four sides of the chip 11 on the periphery of the chip 11. The pixel region 13 is arranged inside the pad arrangement region 12. The pixel region 13 is arranged and surrounded on its periphery by the pad arrangement region 12.

[0009] The pixel section 2 is arranged in a pixel region 13 located in the center of the chip 11. The pixel section 2 has a plurality of pixels 20. The plurality of pixels 20 are arranged along an XY plane. The plurality of pixels 20 are arranged in a matrix along the X and Y directions. Specifically, the plurality of pixels 20 are arranged in a plurality of columns, with or without gaps in the X direction. In each column, the plurality of pixels 20 are arranged in a plurality of rows, with or without gaps in the Y direction.

[0010] 2 is a diagram showing the circuit configuration of a pixel 20 of the image sensor 1A. As shown in FIG. 2, each pixel 20 functionally comprises a photoelectric conversion unit 21, a transfer unit 22, a reset unit 23, and an output unit 24. The photoelectric conversion unit 21 is composed of, for example, a photodiode 21d. The photoelectric conversion unit 21 photoelectrically converts received light to generate electric charges. The photoelectric conversion unit 21 outputs the generated electric charges to the transfer unit 22.

[0011] The transfer unit 22, the reset unit 23, and the output unit 24 constitute a readout circuit that reads out the charge (signal) generated by the photoelectric conversion unit 21. The transfer unit 22 is composed of, for example, a transfer transistor 22t. The charge output from the photoelectric conversion unit 21 is accumulated by a capacitance (so-called floating diffusion) of a wiring unit 25 that connects the transfer unit 22 and the output unit 24. The transfer unit 22 outputs the charge output from the photoelectric conversion unit 21 and accumulated in the wiring unit 25 to the output unit 24. The transfer unit 22 is controlled to output the charge to the output unit 24 by a command signal from the circuit unit 4A. When the command signal is input, the transfer unit 22 outputs the charge accumulated in the wiring unit 25 to the output unit 24. The reset unit 23 is composed of, for example, a reset transistor 23t. The reset unit 23 discharges the charge accumulated in the wiring unit 25 to the power supply circuit 50. The reset unit 23 resets the pixels 20 by discharging the electric charges accumulated in the wiring unit 25 every time an image is captured.

[0012] The output unit 24 outputs the charges output by the transfer unit 22 to a processing unit 60A, which will be described later. The output unit 24 includes a current-voltage conversion unit 26 and a selection unit 27. The current-voltage conversion unit 26 is composed of a gate transistor 26t that forms a common-drain circuit (source follower circuit). The current-voltage conversion unit 26 generates a voltage signal according to the charges accumulated in the wiring unit 25. The selection unit 27 is composed of a selection transistor 27t. When a selection signal is turned ON by currents supplied from a first current source 61 and a second current source 62A, which will be described later and are provided in the circuit unit 4A, the selection unit 27 outputs the voltage signal generated by the current-voltage conversion unit 26 to a signal line 41.

[0013] Here, the pixel 20 in this embodiment includes one photoelectric conversion unit 21 (PD) and four transistors (a transfer transistor 22t, a reset transistor 23t, a gate transistor 26t, and a selection transistor 27t), but is not limited to this. The number of photodiodes constituting the photoelectric conversion unit 21 and the numbers of transistors constituting the transfer unit 22, reset unit 23, and output unit 24 of the pixel 20 can be changed as appropriate.

[0014] The pixel 20 described above sequentially performs the following operations under the control of an image sensor controller (not shown). First, before capturing an image, the charge in the photodiode 21d of the photoelectric conversion unit 21 is reset. To do this, the reset transistor 23t and the transfer transistor 22t are turned on, and the photodiode 21d is electrically connected to the power supply circuit 50 (described later). With this configuration, the charge accumulated in the photodiode 21d is discharged to the power supply circuit 50 and reset.

[0015] Next, the reset transistor 23t and the transfer transistor 22t are switched OFF. With this configuration, exposure begins at the photodiode 21d. The photodiode 21d converts irradiated light into electric charges and accumulates them. After a predetermined exposure time has elapsed, the transfer transistor 22t is switched ON. As a result, the electric charges accumulated in the photodiode 21d are transferred to the wiring unit 25. The image sensor controller (not shown) sequentially reads out voltage signals from the multiple pixels 20 in a predetermined readout order. When the selection signal of the selection transistor 27t of the pixel 20 is turned ON, the gate transistor 26t of the current-voltage conversion unit 26 generates a voltage signal corresponding to the electric charges accumulated in the wiring unit 25. The generated voltage signal is output to a signal line 41 (described later) via the selection transistor 27t of the selection unit 27.

[0016] FIG. 3 is a cross-sectional view of a chip 11 constituting the image sensor 1A. The chip 11 of the image sensor 1A having the circuit configuration described above has a laminated structure. The chip 11 of the image sensor 1A has a first layer 110 and a second layer 120 laminated on the first layer 110. The first layer 110 and the second layer 120 are each arranged along the XY plane. The first layer 110 and the second layer 120 are laminated in the Z direction. The first layer 110 and the second layer 120 are manufactured separately. The first layer 110 and the second layer 120 are bonded to each other by bonding pads 15.

[0017] The pixel unit 2 is formed on the first layer 110. The first layer 110 has a substrate layer 101a and a wiring layer 101b. The substrate layer 101a has a substrate main body 111, a light-shielding metal 114, a color filter 112, and a lens 113. The substrate main body 111 is disposed along the XY plane and has a predetermined thickness in the Z direction. The substrate main body 111 is mainly made of a silicon material. Photodiodes 21d made of a semiconductor and constituting the photoelectric conversion unit 21 are embedded in the substrate main body 111. The photodiodes 21d are arranged at intervals in the X direction and the Y direction. The silicon material that forms the substrate main body 111 is interposed between photodiodes 21d adjacent to each other in the X direction and the Y direction.

[0018] The light-shielding metal 114 is disposed so as to cover a surface 111f on one side in the Z direction of the substrate main body 111. The light-shielding metal 114 has openings 114a at positions facing in the Z direction relative to the photodiodes 21d of the pixels 20 adjacent to each other in the XY plane. The light-shielding metal 114 has a grid 114c that closes the gap between the openings 114a of the pixels 20 adjacent to each other in the XY direction.

[0019] The color filter 112 is stacked and arranged on one side in the Z direction with respect to the light-shielding metal 114. The color filter 112 has R filters that transmit red light, G filters that transmit green light, and B filters that transmit blue light arranged in a predetermined array. Each of the R filters, G filters, and B filters is arranged on one side in the Z direction with respect to the light-shielding metal 114 so as to cover the opening 114a of the light-shielding metal 114. The lens 113 is arranged on one side in the Z direction with respect to the color filter 112 so as to cover each of the R filters, G filters, and B filters.

[0020] In the wiring layer 101b, wiring and elements constituting a digital circuit are embedded in an insulator 117 formed to a predetermined thickness in the Z direction. Examples of the wiring and elements embedded in the insulator 117 include the transfer transistor 22t, the wiring section 25, the reset transistor 23t, the gate transistor 26t, the selection transistor 27t, and the power supply circuit 50. In the second layer 120, wiring and elements constituting an analog circuit are embedded. Examples of the wiring and elements embedded in the second layer 120 include a signal line 41, an ADC (analog-digital converter) serving as a processing section (first processing section) 60A, a first current source (current source) 61, and a second current source (current source) 62A, which will be described later.

[0021] FIG. 4 is a perspective view showing a schematic configuration of a pixel block 200 and a circuit section 4A. FIG. 5 is a circuit configuration diagram showing a schematic configuration of the pixel block 200 and the circuit section 4A. The pixel section 2 including the pixels 20 described above has a plurality of pixel blocks 200. As shown in FIGS. 4 and 5, each pixel block 200 is composed of a plurality of pixels 20 arranged in the X direction and the Y direction. For example, in this embodiment, one pixel block 200 is composed of three pixels 20 in the X direction and three pixels 20 in the Y direction, for a total of nine pixels 20. Each pixel 20 in each pixel block 200 is supplied with power (voltage) from a pixel power supply arranged outside the image sensor 1A by a power supply circuit 50 (see FIG. 2).

[0022] The circuit section 4A mainly includes a signal line 41, a first current source 61, and a second current source 62A. The signal line 41 transmits a voltage signal output from each pixel 20 to the processing section 60A. One set of signal lines 41 is arranged for each pixel block 200. The signal line 41 connects the selection transistor 27t (see FIG. 2) of each pixel 20 arranged on the first layer 110 to the processing section 60A arranged on the second layer 120. The signal line 41 includes a first signal line 411 and a second signal line 412. The signal line 41 is arranged across the first layer 110 and the second layer 120.

[0023] 2, 4, and 5, the first signal line 411 extends in the Z direction. The first signal line 411 is disposed in the center of the pixel block 200 in the XY plane. That is, the first signal line 411 is disposed in the center of the region in which the plurality of pixels 20 are disposed, as viewed from the Z direction orthogonal to the X and Y directions. One end of the first signal line 411 is connected to the processing unit 60A disposed in the second layer 120. The other end of the first signal line 411 is connected to the second signal line 412 in the first layer 110. The first signal line 411 is disposed in a position closest to the first pixel 201A disposed in the center of the pixel block 200.

[0024] The second signal lines 412 are arranged in the second layer 120. The second signal lines 412 are arranged in a grid pattern along the XY plane. The second signal lines 412 are formed in a grid pattern when viewed from the Z direction. The second signal lines 412 have X-direction wiring portions 412x extending in the X direction and Y-direction wiring portions 412y extending in the Y direction. Three X-direction wiring portions 412x are arranged at intervals in the Y direction. Three Y-direction wiring portions 412y are arranged at intervals in the X direction. The second signal lines 412 are connected to the output units 24 (selection units 27) of each pixel 20 near the intersections of the X-direction wiring portions 412x and the Y-direction wiring portions 412y. When viewed from the Z direction, the second signal lines 412 are arranged to surround the first signal lines 411 in a region where a plurality of pixels 20 constituting the pixel block 200 are arranged. The second signal line 412 branches off from the first signal line 411 and is connected to each of the plurality of pixels 20 .

[0025] The processing unit 60A reads out signals from each pixel 20 that is connected to the signal lines 41 (first signal line 411, second signal line 412) and that constitutes the pixel block 200. When reading out signals from each pixel 20, a current is supplied to the selection unit 27 of each pixel 20 from a first current source 61 and a second current source 62A provided in the circuit unit 4A.

[0026] One or both of the first current source 61 and the second current source 62A are provided on the second layer 120. In this embodiment, the first current source 61 and the second current source 62A are arranged on the second layer 120. Furthermore, in this embodiment, the first current source 61 and the second current source 62A are provided for each of a plurality of pixel blocks 200. The first current source 61 supplies a current to the first signal line 411. The first current source 61 is connected to the first signal line 411 via a current supply line 611. The current supply line 611 has a connection portion 611j for the first signal line 411. The connection portion 611j is arranged on the first signal line 411 between the processing unit 60A and the second signal line 412.

[0027] A plurality of second current sources 62A are provided for each pixel block 200. Each second current source 62A is connected to the second signal line 412 via a current supply line 621A. The current supply line 621A has a connection portion 621Aj for the second signal line 412. The connection portion 621Aj is connected to the second signal line 412 between the plurality of pixels 20 and the first current source 61. With this configuration, each second current source 62A has a connection portion 621Aj for the second signal line 412 (signal line 41) between the plurality of pixels 20 and the first current source 61. In this embodiment, the second current source 62A and the current supply line 621A having the connection portion 621Aj are arranged between the first current source 61 and second pixels 202A to 202D at the four corners of the pixel block 200, which have the longest path lengths to the first current source 61 and the processing unit 60A among the plurality of pixels 20 constituting the pixel block 200.

[0028] Each current supply line 621A extends in the Z direction. One end of the current supply line 621A is connected to the second signal line 412 in the first layer 110. The other end of the current supply line 621A is connected to the second current source 62A on the second layer 120. The second current source 62A is grounded to a ground (GND) provided on the second layer 120. The second current source 62A supplies a current to the second signal line 412 via a connection portion 621Aj.

[0029] In this embodiment, the first signal line 411 is disposed in the center of the pixel block 200 in the XY plane. That is, the first pixel 201A is disposed closer to the processing unit 60A than the second pixels 202A to 202D located at the four corners of the pixel block 200. For this reason, the path lengths of the signal lines 41 connected to each pixel 20 in the pixel block 200 are different. The wiring length from the selection unit 27 of the first pixel 201A to the processing unit 60A via the signal line 41 and first current source 61 is different from the path length from the selection unit 27 of the second pixels 202A to 202D to the processing unit 60A via the signal line 41 and first current source 61.

[0030] In contrast, the second current source 62A and the connection portion 621Aj are disposed between the first current source 61 and second pixels 202A to 202D, which are the other pixels 20, excluding the first pixel 201A, which is the pixel 20 having the shortest path length to the first current source 61, among the multiple pixels 20 connected to the second signal line 412. In this embodiment, the second current source 62A and the connection portion 621Aj are disposed between the first current source 61 and second pixels 202A to 202D at the four corners of the pixel block 200, which have the longest path lengths to the first current source 61 and the processing unit 60A among the multiple pixels 20 constituting the pixel block 200.

[0031] With this configuration, the first current source 61 and the plurality of second current sources 62A vary the amount of current supplied to the signal line 41 depending on the path length of the signal line 41 connecting the processing unit 60A and each pixel 20 of the pixel block 200 whose signal is read out by the processing unit 60A. The second pixels 202A to 202D, which have a long path length from the processing unit 60A, are supplied with current from the second current source 62A in addition to the first current source 61. As a result, it is possible to reduce the amount of voltage drop from the second pixels 202A to 202D located at the four corners of each pixel block 200 to the processing unit 60A.

[0032] Thus, according to this embodiment, by connecting the first current source 61 and the second current source 62A to the signal line 41 within the pixel block 200, it is possible to suppress the influence of IR drop that occurs due to differences in the wiring length to the processing unit 60A between multiple pixels 20 in the pixel block 200, and to suppress unevenness that occurs in the captured image at the image sensor 1A.

[0033] [Second embodiment] A second embodiment will now be described. FIG. 6 is a circuit diagram showing the schematic configuration of a pixel block 200 and a circuit section 4C. In this embodiment, components similar to those in the above-described embodiments are given the same reference numerals, and their description will be omitted or simplified. As shown in FIG. 6, an image sensor 1B includes a pixel section 2 and a circuit section 4B. In this embodiment, the circuit section 4B mainly includes a signal line 41, a first current source 61, and a second current source 62B.

[0034] In this embodiment, the second current source 62B and the current supply line 621B having the connection portion 621Bj are arranged in the pixel block 200 between the first current source 61 and all of the second pixels 202A to 202H except for the first pixel 201A that is closest to the processing unit 60A. The second current source 62B is connected to the second signal line 412 via the current supply line 621B. The current supply line 621B has a connection portion 621Bj to the second signal line 412. The connection portion 621Bj is connected to the second signal line 412 between the plurality of pixels 20 and the first current source 61. With this configuration, each second current source 62B has a connection portion 621Bj to the second signal line 412 (signal line 41) between the plurality of pixels 20 and the first current source 61.

[0035] The first current source 61 and the plurality of second current sources 62B vary the amount of current supplied to the signal line 41 depending on the path length of the signal line 41 connecting the processing unit 60A and each pixel 20 in the pixel block 200 whose signal is read out by the processing unit 60A. Current is supplied from the second current source 62B in addition to the first current source 61 to the second pixels 202A-202H, which have a long path length from the processing unit 60A. As a result, it is possible to suppress the amount of voltage drop from the second pixels 202A-202H in each pixel block 200 to the processing unit 60A. The amount of current supplied by the second current source 62B may be varied depending on the wiring length of the second pixels 202A-202H to the processing unit 60A.

[0036] Thus, according to this embodiment, by connecting the first current source 61 and the second current source 62B to the signal line 41 within the pixel block 200, it is possible to suppress the influence of IR drop that occurs due to differences in the wiring length to the processing unit 60A between multiple pixels 20 in the pixel block 200, and to suppress unevenness that occurs in the captured image at the image sensor 1B.

[0037] [Third embodiment] A third embodiment will now be described. FIG. 7 is a circuit diagram showing the schematic configuration of a pixel block 200 and a circuit section 4C. In this embodiment, the same components as those in the above-described embodiments are denoted by the same reference numerals, and their description will be omitted or simplified. As shown in FIG. 7, an image sensor 1C includes a pixel section 2 and a circuit section 4C. The circuit section 4C mainly includes a signal line 41, a first current source 61, and a second current source 62C. The signal line 41 includes a first signal line 411 and a second signal line 412.

[0038] The second current source 62C is provided so as to be shared by multiple pixel blocks 200. In this embodiment, the second current source 62C is arranged between four pixel blocks 200 adjacent to each other in the X direction and the Y direction. With this configuration, when viewed from each pixel block 200, four second current sources 62C are arranged at the four corners of the pixel block 200.

[0039] Fig. 8 is a perspective view showing a second current source 62C arranged between four pixel blocks 200. As shown in Figs. 7 and 8, the second current source 62C is connected to the second signal lines 412 of the four pixel blocks 200A to 200D via four current supply lines 621C. Each current supply line 621C has a connection portion 621Cj between the first current source 61 and the second pixel 202A to 202D at the corner of the pixel block 200A to 200D that has the longest path length to the first current source 61.

[0040] FIG. 9 is a diagram showing the configuration of a switching unit 66C of a second current source 62C arranged between four pixel blocks 200. FIG. 10 is a cross-sectional view of an image sensor 1C. As shown in FIGS. 9 and 10, the current supply line 621C extends in the Z direction. The other ends of the current supply lines 621C located at the corners of four pixel blocks 200A to 200D adjacent to each other in the X and Y directions are connected to the second current source 62C via a first selection unit 65C. The first selection unit 65C selectively connects one of the four current supply lines 621C connected to the second signal lines 412 of the four pixel blocks 200A to 200D to the second current source 62C.

[0041] The first selection unit 65C includes a switching unit 66C provided on each current supply line 621C. Each switching unit 66C is configured to be able to switch the second current source 62C between connection and disconnection with respect to the second signal line 412. The switching unit 66C includes a switch transistor 66Ct and a switch control line 66Cs. Each switch transistor 66Ct is disposed between the second current source 62C and the current supply line 621C connected to the second signal line 412. The switch control line 66Cs is individually connected to each switch transistor 66Ct. The first selection unit 65C selects one of the four switch control lines 66Cs and supplies power to it. As a result, the switch transistor 66Ct connected to the supplied switch control line 66Cs is turned on, and power is supplied from the second current source 62C to the current supply line 621C via the switch transistor 66Ct.

[0042] In this way, the second current source 62C is selectively connected to different second signal lines 412 arranged in the four pixel blocks 200A to 200D by the first selection unit 65C. With this configuration, current is supplied from the second current source 62C to the second pixels 202A to 202D at the corner of one pixel block 200 of the four pixel blocks 200A to 200D. The switching unit 66C is provided in a current supply line 621C connected to the second signal line 412 near the first pixel 201A located at the corner of each pixel block 200, and switches between connection and non-connection depending on the length of the signal line 41.

[0043] In the plurality of pixel blocks 200, the order of reading out signals from the plurality of pixels 20 constituting each pixel block 200 is unified. When reading out signals from each pixel 20 in the plurality of pixel blocks 200, the switching operation of the first selection unit 65C provided in each second current source is synchronized in accordance with the order of reading out signals from the plurality of pixels 20.

[0044] Thus, according to this embodiment, similarly to the first embodiment, by connecting the first current source 61 and the second current source 62C to the signal line 41 within the pixel block 200, it is possible to suppress the influence of IR drop caused by differences in the wiring length to the processing unit 60A among the multiple pixels 20 of the pixel block 200, and to suppress unevenness occurring in the captured image at the image sensor 1A. Furthermore, by sharing the second current source 62C among multiple pixel blocks 200, it is possible to reduce the number of second current sources 62C and reduce the area of ​​the readout circuit.

[0045] [Fourth embodiment] A fourth embodiment will now be described. FIG. 11 is a circuit diagram showing a second current source 62D arranged between a plurality of pixel blocks 200. In this embodiment, components similar to those in the above-described embodiments are given the same reference numerals, and their description will be omitted or simplified. As shown in FIG. 11, an image sensor 1D includes a pixel section 2 and a circuit section 4D. The circuit section 4D mainly includes a signal line 41, a first current source 61, and a second current source 62D.

[0046] The second current source 62D is provided so as to be shared by multiple pixel blocks 200. In this embodiment, the second current source 62D is disposed between two pixel blocks 200E and 200F adjacent to each other in the X direction (or Y direction). Each second current source 62D is connected to the second signal lines 412 of the two pixel blocks 200E and 200F via two current supply lines 621D. Each current supply line 621D has a connection portion 621Dj between the first current source 61 and the second pixel 202A-202D at the corner of each pixel block 200, which has the longest path length to the first current source 61. The other end of each current supply line 621D is connected to the second current source 62D via a first selection unit 65C. The first selection section 65C selectively connects one of the two current supply lines 621D connected to the second signal lines 412 of the two pixel blocks 200E and 200F to the second current source 62D.

[0047] As described above, according to this embodiment, similarly to the third embodiment, by connecting the first current source 61 and the second current source 62D to the signal line 41 within the pixel block 200, it is possible to suppress the influence of IR drop caused by differences in the wiring length to the processing unit 60B among the multiple pixels 20 of the pixel block 200, and to suppress unevenness that occurs in the captured image at the image sensor 1A. Furthermore, by sharing the second current source 62D among multiple pixel blocks 200, the number of second current sources 62D can be reduced, and the area of ​​the readout circuit can be reduced.

[0048] [Fifth embodiment] A fifth embodiment will now be described. FIG. 12 is a circuit diagram showing the schematic configuration of a pixel block 200 and a circuit unit 4E. FIG. 13 is a perspective view showing a second current source 62E and a second processing unit 70E arranged between four pixel blocks 200. In this embodiment, components similar to those in the above-described embodiments are denoted by the same reference numerals, and their description will be omitted or simplified. As shown in FIGS. 12 and 13, an image sensor 1E includes a pixel unit 2 and a circuit unit 4E. The circuit unit 4E mainly includes a signal line 41, a first current source 61E, a second current source 62E, a first processing unit 60E, and a second processing unit 70E. The signal line 41 includes a first signal line 411 and a second signal line 412. One end of the first signal line 411 is connected to the first processing unit 60E. The other end of the first signal line 411 is connected to the second signal line 412.

[0049] A third selection unit 78 is provided on the first signal line 411. The third selection unit 78 connects and disconnects the first processing unit 60E and the pixel block 200. A first current source 61E is provided for each of the plurality of pixel blocks 200. The first current source 61E supplies a current to the first signal line 411. The first current source 61 has a connection portion 61j for the first signal line 411. The connection portion 61j is arranged on the first signal line 411 between the first processing unit 60E and the second signal line 412.

[0050] The second current source 62E and the second processing unit 70E are provided so as to be shared by multiple pixel blocks 200. In this embodiment, the second current source 62E and the second processing unit 70E are arranged between four pixel blocks 200A to 200D that are adjacent in the X and Y directions. Each second current source 62E and second processing unit 70E is connected to the second signal lines 412 of the four pixel blocks 200A to 200D via four third signal lines 413. Each third signal line 413 has a connection portion 413j between the first current source 61E and the second pixel 202A to 202D at the corner of each pixel block 200 that has the longest wiring length to the first current source 61E.

[0051] FIG. 14 is a diagram showing the configuration of a second current source 62E arranged between four pixel blocks 200 and a second selection unit 76E of a second processing unit 70E. FIG. 15 is a cross-sectional view of an image sensor 1D. As shown in FIGS. 13 to 15, a third signal line 413 extends in the Z direction. One end of the third signal line 413 is connected to the second signal line 412 in the first layer 110. The other end of the third signal line 413 is arranged in the second layer 120.

[0052] The other ends of the third signal lines 413 located at the corners of four pixel blocks 200A-200D adjacent to each other in the X and Y directions are connected to a second current source 62E via a second selection unit (third selection unit) 76E. The second selection unit 76E selectively connects one of the four third signal lines 413 connected to the second signal lines 412 of the four pixel blocks 200A-200D to the second current source 62E.

[0053] The second selection unit 76E includes a switching unit 77E provided on each third signal line 413. Each switching unit 77E is configured to be able to switch the connection of the second current source 62E and the second processing unit 70E to or from the second signal line 412. The switching unit 77E includes a switch transistor 66Et and a switch control line 66Es. Each switch transistor 66Et is disposed between the second current source 62E and the third signal line 413 connected to the second signal line 412. The switch control line 66Es is connected to each switch transistor 66Et. The second selection unit 76E selects one of the four switch control lines 66Es and supplies power to it. As a result, the switch transistor 66Et connected to the supplied switch control line 66Es is turned on, and power is supplied from the second current source 62E to the third signal line 413 via the switch transistor 66Et. In this way, the second current source 62E and the second processing unit 70E are selectively connected to the different second signal lines 412 arranged in the four pixel blocks 200A to 200D by the second selection unit 76E.

[0054] With this configuration, current is supplied from the second current source 62E to the second pixels 202A-202D at the corner of one pixel block 200 of the four pixel blocks 200A-200D. The switching unit 77E is provided on the third signal line 413 connected to the second signal line 412 near the first pixel 201A located at the corner of each pixel block 200, and switches between connection and non-connection depending on the length of the signal line 412.

[0055] The first processing unit 60E and the second processing unit 70E read out signals from each pixel 20 that constitutes the pixel block 200 and that are connected to the signal line 41 (first signal line 411, second signal line 412). When reading out a signal from the first pixel 201A that is located in the center of the pixel block 200, the third selection unit 78 connects the first processing unit 60E and the first current source 61E to the signal line 41 (first signal line 411). In this case, the switching unit 77E of the second selection unit 76E provided on the third signal line 413 keeps the second current source 62E and the second processing unit 70E disconnected from the second signal line 412. Switch between.

[0056] Furthermore, when signals are read out from the second pixels 202A to 202D arranged at the four corners of the pixel block 200, the switching unit 77E of the second selection unit 76E provided on the third signal lines 413 corresponding to the second pixels 202A to 202D connects the second current source 62E and the second processing unit 70E to the second signal line 412. In this case, the third selection unit 78 disconnects the first processing unit 60E and the first current source 61E from the first signal line 411. Furthermore, when signals are read out from pixels 20 other than the first pixel 201A and the second pixels 202A to 202D in the pixel block 200, the third selection unit 78 and the switching unit 77E of the second selection unit 76E may be switched so as to read out signals from either the first processing unit 60E or the second processing unit 70E, whichever has the shorter wiring length from each pixel 20.

[0057] As described above, according to the present embodiment, each pixel block 200 is provided with a first processing unit 60E and a second processing unit 70E, and either one of the first processing unit 60E or the second processing unit 70E is selectively connected to the signal line 41 by the third selection unit 78 and the second selection unit 76E depending on the position (wiring length) of the pixel 20 within the pixel block 200. With this configuration, it is possible to suppress the influence of IR drop caused by differences in wiring length between the multiple pixels 20 of the pixel block 200, and to suppress unevenness that occurs in the captured image at the image sensor 1A.

[0058] Also, similar to the third and fourth embodiments, by connecting the first current source 61E and the second current source 62E to the signal line 41 within the pixel block 200, it is possible to suppress the influence of IR drop caused by differences in the wiring length to the first processing unit 60E among the multiple pixels 20 of the pixel block 200, and to suppress unevenness in the captured image at the image sensor 1A. Furthermore, by sharing the second current source 62E among multiple pixel blocks 200, the number of second current sources 62E can be reduced, and the area of ​​the readout circuit can be reduced.

[0059] In the fifth embodiment, the second processing unit 70E and the second current source 62E are arranged between four pixel blocks 200A to 200D adjacent to each other in the X and Y directions, but this is not limiting. As in the fourth embodiment, the second processing unit 70E and the second current source 62E may be shared by two pixel blocks 200 adjacent to each other in the X or Y direction.

[0060] [Sixth embodiment] A sixth embodiment will now be described. FIG. 16 is a circuit diagram showing the schematic configuration of a pixel block 200 and a circuit section 4F. In this embodiment, components similar to those in the above-described embodiments are assigned the same reference numerals, and their description will be omitted or simplified. As shown in FIG. 16, an image sensor 1F includes a pixel section 2 and a circuit section 4F. The circuit section 4F mainly includes a signal line 41, a first current source 61F, a second current source 62F, a first processing section 60E, and a second processing section 70F. The signal line 41 includes a first signal line 411 and a second signal line 412. A central third selection section (third selection section) 79F is provided on the first signal line 411. The central third selection section 79F connects and disconnects the first processing section 60E and the pixel section 2. The first current source 61F supplies current to the first signal line 411.

[0061] The second current source 62F and the second processing unit 70F are arranged at the four corners of each pixel block 200. Each second processing unit 70F is connected to the second signal line 412 via a third signal line 413. The third signal line 413 has a connection portion 413j for the second signal line 412 between the second pixel 202A-202D at the corner where the wiring length to the first current source 61F is longest and the first current source 61F (first signal line 411). The other end of the third signal line 413 is connected to the second current source 62F via a peripheral third selection unit (third selection unit) 80F. The peripheral third selection unit 80F connects and disconnects the third signal line 413 from the second current source 62F and the second processing unit 70F.

[0062] The first processing unit 60E and the second processing unit 70F read out signals from each pixel 20 that constitutes the pixel block 200 and that are connected to the signal line 41 (first signal line 411, second signal line 412). When reading out a signal from the first pixel 201A that is arranged in the center of the pixel block 200, the central third selection unit 79F connects the first processing unit 60E and the first current source 61F to the signal line 41. In this case, the switching unit 77E of the peripheral third selection unit 80F that is provided on the third signal line 413 keeps the second current source 62F and the second processing unit 70F disconnected from the second signal line 412.

[0063] Furthermore, when reading out signals from the second pixels 202A to 202D arranged at the four corners of the pixel block 200, the switching units 77E of the outer peripheral third selection units 80F provided on the third signal lines 413 corresponding to the second pixels 202A to 202D respectively connect the second current source 62F and the second processing unit 70F to the second signal line 412. In this case, the first processing unit 60E and the first current source 61F are disconnected from the signal line 41 by the central third selection unit 79F.

[0064] Furthermore, in the pixel block 200, when reading out signals from pixels 20 other than the first pixel 201A and the second pixels 202A to 202D, the switching units 77E of the central third selection unit 79F and the peripheral third selection unit 80F may be switched so that the signals are read out from either the first processing unit 60E or the second processing unit 70, whichever has the shorter wiring length from the pixel 20.

[0065] As described above, according to the present embodiment, each pixel block 200 is provided with a first processing unit 60E and a second processing unit 70F, and either one of the first processing unit 60E or the second processing unit 70F is selectively connected to the signal line 41 by the central third selection unit 79F and the peripheral third selection unit 80F depending on the position (wiring length) of the pixel 20 within the pixel block 200. With this configuration, it is possible to suppress the influence of IR drop caused by differences in wiring length between the multiple pixels 20 of the pixel block 200, and to suppress unevenness that occurs in the captured image at the image sensor 1A.

[0066] Furthermore, by connecting the first current source 61F and the second current source 62F to the signal line 41 within the pixel block 200, it is possible to suppress the influence of IR drop caused by differences in the wiring length to the first processing unit 60E between the multiple pixels 20 in the pixel block 200, and to suppress unevenness that occurs in the captured image at the image sensor 1A.

[0067] [Seventh embodiment] A seventh embodiment will be described. Fig. 17 is a circuit configuration diagram showing the schematic configuration of a pixel block 200 and a circuit section 4G. As shown in Fig. 17, an image sensor 1G includes a pixel section 2 and a circuit section 4G. The circuit section 4G mainly includes a signal line 41G and a current source 90. The signal line 41G transmits a voltage signal output from each pixel 20 to a processing section 60G. One set of signal lines 41G is arranged for each pixel block 200. The signal line 41G connects each pixel 20 arranged in the first layer 110 to the processing section 60G.

[0068] The signal lines 41G include a first signal line 411, a second signal line 412, and a fourth signal line 415. The first signal line 411 is arranged in the center of the pixel block 200 in the XY plane. One end of the first signal line 411 is connected to the processing unit 60G via a current source 90. The second signal lines 412 form a lattice pattern when viewed from the Z direction, and are connected to each of the multiple pixels 20 that make up the pixel block 200. Each pixel 20 is connected to the second signal line 412 via a pixel connection line 417 that extends in the Z direction.

[0069] The fourth signal line 415 connects the first signal line 411 to other pixels 20 (for example, second pixels 202A to 202D at the four corners) in the pixel block 200 that have a longer wiring length to the first signal line 411 and the processing unit 60G than the first pixel 201G arranged in the center of the pixel block 200. One end of the fourth signal line 415 is connected to the second signal line 412 at a connection portion 417j of the pixel connection line 417 that connects the pixel connection line 417 to the second signal line 412. The fourth signal line 415 is provided independently from the second signal line 412. The other end of the fourth signal line 415 is connected to the first signal line 411 between the second signal line 412 and the current source 90.

[0070] The current source 90 supplies a current to the first signal line 411. The current source 90 is connected to the first signal line 411 via a current supply line 911c. The current supply line 911c has a connection portion 911j for the first signal line 411. The connection portion 911j is arranged on the first signal line 411 between the processing unit 60G and the second signal line 412.

[0071] In this embodiment, the path lengths of the signal lines 41G connected to each pixel 20 in the pixel block 200 are different. The wiring length from the first pixel 201A to the processing unit 60G is different from the path length from the second pixels 202A to 202D to the processing unit 60G. In contrast, the second signal line 412 and the fourth signal line 415 are provided in parallel between the second pixels 202A to 202D and the processing unit 60G. With this configuration, the cross-sectional area of ​​the second signal line 412 and the fourth signal line 415, which are arranged between the second pixels 202A to 202D and the processing unit 60G, is larger than the cross-sectional area of ​​the first signal line 411, which is arranged between the first pixel 201A and the processing unit 60G.

[0072] That is, the second signal line 412 and the fourth signal line 415 arranged between the second pixels 202A-202D and the processing unit 60G have a smaller resistance value than the first signal line 411 arranged between the first pixel 201 and the processing unit 60G. This makes it possible to reduce the amount of voltage drop from the second pixels 202A-202D located at the four corners of the pixel block 200 to the processing unit 60G. This makes it possible to reduce the influence of IR drop caused by differences in wiring length to the processing unit 60G among the multiple pixels 20 in the pixel block 200, and to reduce unevenness in the captured image at the image sensor 1G.

[0073] [Eighth embodiment] An eighth embodiment will be described. Fig. 18 is a circuit configuration diagram showing the schematic configuration of a pixel block 200 and a circuit section 4G. As shown in Fig. 8, an image sensor 1H includes a pixel section 2 and a circuit section 4H. The circuit section 4H mainly includes a signal line 41H, a processing section 60H, and a current source 90. The signal line 41H transmits a voltage signal output from each pixel 20 to the processing section 60F. One set of the signal line 41H is arranged for each pixel block 200. The signal line 41H connects each pixel 20 arranged in the first layer 110 to the processing section 60F.

[0074] The signal line 41H includes a first signal line 411 and a second signal line 412. The first signal line 411 is disposed in the center of the pixel block 200 in the XY plane. One end of the first signal line 411 is connected to the processing unit 60F via a current source 90. The second signal lines 412 form a lattice pattern when viewed from the Z direction, and are connected to the plurality of pixels 20 that constitute the pixel block 200. Each pixel 20 is connected to the second signal line 412 via a pixel connection line 418 that extends in the Z direction.

[0075] In this embodiment, the pixel connecting line 418 includes a first pixel connecting line 418A and a second pixel connecting line 418B. The first pixel connecting line 418A is connected to a first pixel 201F arranged in the center of the pixel block 200. The second pixel connecting line 418B is connected to other pixels 20 (for example, second pixels 202A to 202D at the four corners) that have a longer wiring length to the first signal line 411 and the processing unit 60F than the first pixel connecting line 418A. The cross-sectional area of ​​the second pixel connecting line 418B is larger than the cross-sectional area of ​​the first pixel connecting line 418A.

[0076] This configuration can reduce the amount of voltage drop from the second pixels 202A to 202D located at the four corners of the pixel block 200 to the processing unit 60F. Therefore, it is possible to reduce the influence of IR drop caused by differences in wiring length to the processing unit 60F among the multiple pixels 20 in the pixel block 200, and to reduce unevenness in the captured image at the image sensor 1H.

[0077] Although the embodiments have been described above, the technical scope of the present invention is not limited to the aspects described in the above embodiments. One or more of the requirements described in the above embodiments may be omitted. Furthermore, the requirements described in the above embodiments may be combined as appropriate. Furthermore, to the extent permitted by law, the disclosures of all documents cited in this specification are incorporated by reference and are included as part of the description of this text. [Explanation of symbols]

[0078] 1A to 1H: Image sensor, 20: Pixel, 27: Selection unit, 41, 41G, 41H: Signal line, 60A, 60B, 60F, 60G, 60H: Processing unit, 60E: First processing unit, 60E: Second processing unit, 61, 61E, 61F: First current source, 61j: Connection unit, 62A to 62F: Second current source, 65C: First selection unit, 66C: Switching unit, 70, 70E, 70F: Second processing unit, 76E: Second selection unit selection section, 77E... switching section, 78... third selection section, 79F... central third selection section (third selection section), 80F... peripheral third selection section (third selection section), 90... current source, 110... first layer, 120... second layer, 200, 200A to 200F... pixel block, 411... first signal line, 412... second signal line, 413j, 417j, 611j, 621Aj, 621Bj, 621Cj, 621Dj, 911j... connection section

Claims

[Claim 1] signal lines connected to a plurality of pixels arranged side by side along a first direction and a second direction intersecting the first direction, the signal lines including: a first signal line arranged in the center of a region in which the plurality of pixels are arranged when viewed from a third direction orthogonal to the first and second directions; and second signal lines arranged so as to surround the first signal line in the region when viewed from the third direction, the second signal lines branching from the first signal line and connected to each of the plurality of pixels; a first current source connected to the first signal line for supplying a current to the signal line; a second current source connected to the second signal line for supplying a current to the signal line; An imaging element comprising:

Images