Photoelectric conversion device and driving method thereof

Abstract

To provide a technique for achieving a circuit configuration for acquiring an image of a high dynamic range at low cost.SOLUTION: The photoelectric conversion apparatus includes a photoelectric conversion unit configured to generate charges in accordance with incidence of light, a first charge holding unit, a second charge holding unit, a transfer unit configured to transfer the charges of the photoelectric conversion unit to the first charge holding unit in accordance with a control signal to a control node, a switch configured to control connection between the first charge holding unit and the second charge holding unit, and a capacitor configured by electrostatic coupling between a first wiring connected to the control node and a second wiring arranged side by side with the first wiring and connected to the second charge holding unit. And an output unit configured to output a signal corresponding to a potential of the first charge holding unit.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and a driving method thereof. [Background technology]

[0002] Patent Document 1 describes an imaging device that is provided with a capacitive coupling wiring that capacitively couples with a floating diffusion region, and is configured to adjust the charge retention capacitance of the floating diffusion region by the voltage of a signal applied to the capacitive coupling wiring.The imaging device described in Patent Document 1 can acquire images with a high dynamic range by switching the conversion efficiency of pixels depending on the charge retention capacitance of the floating diffusion region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-104203 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the imaging device described in Patent Document 1 requires a control circuit for adjusting the signal applied to the capacitive coupling wiring, which, combined with the increased wiring density due to the addition of the capacitive coupling wiring, raises concerns that the circuit density will further increase. As a result, particularly in imaging devices with small pixel sizes, there is a possibility that the yield of wiring and circuits will decrease, and ultimately manufacturing costs will increase.

[0005] An object of the present invention is to provide a technique for realizing, at low cost, a circuit configuration for acquiring an image with a high dynamic range in a photoelectric conversion device. [Means for solving the problem]

[0006] According to one disclosure of the present specification, there is provided a photoelectric conversion device having a photoelectric conversion unit that generates charge in response to incident light, a first charge holding unit, a second charge holding unit, a transfer unit that transfers charge from the photoelectric conversion unit to the first charge holding unit in response to a control signal to a control node, a switch that controls the connection between the first charge holding unit and the second charge holding unit, a capacitance formed by electrostatic coupling between a first wiring connected to the control node and a second wiring arranged alongside the first wiring and connected to the second charge holding unit, and an output unit that outputs a signal in response to the potential of the first charge holding unit.

[0007] Furthermore, according to another disclosure of this specification, there is provided a photoelectric conversion device having a photoelectric conversion unit that generates charges in response to incident light, a first charge holding unit, a second charge holding unit, a transfer unit that transfers charges from the photoelectric conversion unit to the first charge holding unit in response to a control signal to a control node, a switch that controls the connection between the first charge holding unit and the second charge holding unit, an MIM or MOM type capacitor connected between the control node and the second charge holding unit, and an output unit that outputs a signal in response to the potential of the first charge holding unit.

[0008] Furthermore, according to yet another disclosure of the present specification, a semiconductor device includes first and second photoelectric conversion units that generate charges in response to incidence of light, first and second charge holding units, a first transfer unit that transfers charges from the first photoelectric conversion unit to the first charge holding unit in response to a control signal to a control node, a second transfer unit that transfers charges from the second photoelectric conversion unit to the first charge holding unit in response to a control signal to a control node, a switch that controls connection between the first charge holding unit and the second charge holding unit, a first capacitance formed by electrostatic coupling between a first wiring connected to the control node of the first transfer unit and a second wiring arranged alongside the first wiring and connected to the second charge holding unit, a second capacitance formed by electrostatic coupling between the second wiring and a third wiring arranged alongside the second wiring and connected to the control node of the second transfer unit, and a second capacitance formed by electrostatic coupling between the first charge holding unit and a third wiring arranged alongside the second wiring and connected to the control node of the second transfer unit. and an output unit that outputs a signal corresponding to the potential of a charge holding unit, wherein the first transfer unit is driven when the switch is on, thereby changing the potential of the first charge holding unit through capacitive coupling by the first capacitance, and transferring the charges held by the first photoelectric conversion unit to the first charge holding unit, and outputting a signal corresponding to the potential of the first charge holding unit from the output unit; and the first transfer unit and the second transfer unit are driven when the switch is on, thereby changing the potential of the first charge holding unit through capacitive coupling by the first capacitance and the second capacitance, and transferring the charges held by the first photoelectric conversion unit and the second photoelectric conversion unit to the first charge holding unit, and outputting a signal corresponding to the potential of the first charge holding unit from the output unit. [Effects of the Invention]

[0009] According to the present invention, a circuit configuration for acquiring an image with a high dynamic range can be realized at low cost in a photoelectric conversion device. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a first embodiment. [Figure 2]1 is an equivalent circuit diagram showing an example of the configuration of a pixel of a photoelectric conversion device according to a first embodiment. [Figure 3] FIG. 3 is a timing chart showing the operation of a pixel of the photoelectric conversion device according to the first embodiment. [Figure 4] FIG. 10 is an equivalent circuit diagram showing an example of the configuration of a pixel of a photoelectric conversion device according to a second embodiment. [Figure 5] FIG. 10 is a timing chart showing the operation of a pixel of the photoelectric conversion device according to the second embodiment. [Figure 6] FIG. 10 is an equivalent circuit diagram showing an example of the configuration of a pixel of a photoelectric conversion device according to a third embodiment. [Figure 7] 10A and 10B are a plan view and a cross-sectional view showing an example of the arrangement of photoelectric conversion units in a pixel of a photoelectric conversion device according to a third embodiment. [Figure 8] FIG. 10 is a timing chart showing the operation of a pixel of the photoelectric conversion device according to the third embodiment. [Figure 9] FIG. 10 is a plan view (part 1) showing an example of the layout of pixels in a photoelectric conversion device according to a third embodiment. [Figure 10] FIG. 11 is a plan view (part 2) showing an example of the layout of pixels in a photoelectric conversion device according to a third embodiment. [Figure 11] FIG. 10 is an equivalent circuit diagram showing an example of the configuration of a pixel of a photoelectric conversion device according to a fourth embodiment. [Figure 12] FIG. 10 is a plan view showing an example of the layout of pixels in a photoelectric conversion device according to a fourth embodiment. [Figure 13] FIG. 10 is a block diagram showing a schematic configuration of an imaging system according to a fifth embodiment. [Figure 14] FIG. 13 is a diagram illustrating an example of the configuration of an imaging system and a moving object according to a sixth embodiment. [Figure 15] FIG. 13 is a block diagram showing a schematic configuration of a device according to a seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the following embodiments, an apparatus for image capture will be mainly described as an example of a photoelectric conversion device. However, each embodiment is not limited to this apparatus for image capture, and can also be applied to other examples of photoelectric conversion devices. For example, there are distance measurement devices (devices for measuring distance using focus detection or TOF (Time Of Flight)), photometry devices (devices for measuring the amount of incident light, etc.), etc.

[0012] In the following embodiments, the connection between elements of a circuit may be described. In this case, even if another element is interposed between the elements of interest, the elements of interest are treated as being connected to each other unless otherwise specified. For example, assume that element A is connected to one node of a capacitive element C having multiple nodes, and element B is connected to the other node. Even in such a case, element A and element B are treated as being connected to each other unless otherwise specified.

[0013] [First embodiment] A schematic configuration of a photoelectric conversion device according to a first embodiment of the present invention will be described with reference to Fig. 1. Fig. 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to this embodiment.

[0014] 1, the photoelectric conversion device 100 according to this embodiment includes a pixel unit 10, a vertical scanning circuit 20, a readout circuit 30, a horizontal scanning circuit 40, an output circuit 50, and a control circuit 60. The pixel unit 10 is connected to the vertical scanning circuit 20 and the readout circuit 30. The readout circuit 30 is connected to the horizontal scanning circuit 40 and the output circuit 50. The control circuit 60 is connected to the vertical scanning circuit 20, the readout circuit 30, the horizontal scanning circuit 40, and the output circuit 50.

[0015] The pixel section 10 has a plurality of pixels 12 arranged in a matrix having a plurality of rows and a plurality of columns. Each pixel 12 includes a photoelectric conversion unit formed of a photoelectric conversion element such as a photodiode, and outputs a pixel signal corresponding to the amount of incident light. The number of rows and columns of the pixel array arranged in the pixel section 10 is not particularly limited. In addition to effective pixels that output pixel signals corresponding to the amount of incident light, the pixel section 10 may also include optical black pixels whose photoelectric conversion units are shielded from light, dummy pixels that do not output signals, and the like.

[0016] Control lines 14 are arranged in each row of the pixel section 10, extending in a first direction (the horizontal direction in FIG. 1). Each of the control lines 14 is connected to the pixels 12 aligned in the first direction, and serves as a signal line common to these pixels 12. Each of the control lines 14 may include multiple signal lines. The control lines 14 are connected to a vertical scanning circuit 20. The first direction in which the control lines 14 extend may also be referred to as the row direction or the horizontal direction.

[0017] In each column of the pixel section 10, an output line 16 is arranged, extending in a second direction (the vertical direction in FIG. 1 ) intersecting the first direction. Each output line 16 is connected to the pixels 12 aligned in the second direction, and serves as a signal line common to these pixels 12. Each output line 16 may include multiple signal lines. The output line 16 is connected to a readout circuit 30. The second direction in which the output lines 16 extend may be referred to as the column direction or the vertical direction.

[0018] The vertical scanning circuit 20 has a function of generating control signals for driving the pixels 12 in response to control signals from the control circuit 60. The vertical scanning circuit 20 drives the pixels 12 arranged in the pixel section 10 row by row by supplying the generated control signals via the control lines 14 of each row of the pixel section 10. The vertical scanning circuit 20 may be configured using a shift register and an address decoder. Signals read out from the pixels 12 row by row are input to the readout circuit 30 via the output lines 16 of each column.

[0019] The readout circuit 30 has a role of holding pixel signals read out from the pixel unit 10 and may also have a function of performing predetermined signal processing on the pixel signals. Examples of signal processing on pixel signals include amplification, correction using CDS (correlated double sampling), addition, and A / D (analog-to-digital) conversion. The readout circuit 30 may include a column amplifier, a CDS circuit, an addition circuit, an A / D conversion circuit, etc. The readout circuit 30 also has a signal holding unit for holding the pixel signals of each column received from the pixel unit 10 and the pixel signals of each column after signal processing.

[0020] The horizontal scanning circuit 40 has a function of generating control signals for transferring pixel signals held by the readout circuit 30 to the output circuit 50 in response to control signals from the control circuit 60. The horizontal scanning circuit 40 sequentially supplies the generated control signals to the signal holding units of each column of the readout circuit 30. As a result, the readout circuit 30 sequentially transfers the pixel signals held in the signal holding units of each column to the output circuit 50. The horizontal scanning circuit 40 can be configured using a shift register and an address decoder.

[0021] The output circuit 50 may be configured to include a signal processing circuit that performs predetermined signal processing on pixel signals sequentially transferred from the readout circuit 30, and an external interface circuit that outputs the processed pixel signals to the outside of the photoelectric conversion device 100. Examples of signal processing circuits that the output circuit 50 may include a buffer amplifier and a differential amplifier. Examples of signal processing performed by the output circuit 50 include correction processing using CDS, amplification processing, and HDR compositing processing. The external interface circuit that the output circuit 50 may include is not particularly limited. Examples of the external interface circuit that may be used include a SerDes (SERializer / DESerializer) transmission circuit such as an LVDS (Low Voltage Differential Signaling) circuit or an SLVS (Scalable Low Voltage Signaling) circuit.

[0022] The control circuit 60 has a function of supplying control signals for controlling the operation and timing of each functional block, such as the vertical scanning circuit 20, the readout circuit 30, the horizontal scanning circuit 40, and the output circuit 50. Some or all of the control signals supplied to each functional block may be supplied from outside the photoelectric conversion device 100.

[0023] Next, a configuration example of the pixel 12 in the photoelectric conversion device according to this embodiment will be described with reference to Fig. 2. Fig. 2 is an equivalent circuit diagram showing a configuration example of a pixel in the photoelectric conversion device according to this embodiment.

[0024] As shown in FIG. 2, each of the pixels 12 constituting the pixel unit 10 may include a photoelectric conversion unit PD, a transfer transistor M1, an amplification transistor M2, a selection transistor M3, and reset transistors M4 and M5. The photoelectric conversion unit PD may be configured with a photoelectric conversion element, such as a photodiode. The transfer transistor M1, the amplification transistor M2, the selection transistor M3, and the reset transistors M4 and M5 may be configured with MOS transistors. The pixel 12 may further include a microlens and a color filter arranged on the optical path of incident light leading to the photoelectric conversion unit PD. The microlens focuses the incident light onto the photoelectric conversion unit PD. The color filter selectively transmits light of a predetermined color.

[0025] The photoelectric conversion unit PD has an anode connected to the ground node and a cathode connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the gate of the amplification transistor M2 and the source of the reset transistor M4. The connection node between the drain of the transfer transistor M1, the gate of the amplification transistor M2, and the source of the reset transistor M4 is a so-called floating diffusion unit FD. The floating diffusion unit FD includes a capacitance component (floating diffusion capacitance) and functions as a charge storage unit. In FIG. 2, this capacitance component is represented by capacitance C1. Note that, although one electrode of capacitance C1 is connected to the ground node in FIG. 2, the capacitance component associated with the floating diffusion unit FD may also include a capacitance component formed between the floating diffusion unit FD and components other than the ground node.

[0026] The drain of the reset transistor M4 is connected to the source of the reset transistor M5. The connection node between the drain of the reset transistor M4 and the source of the reset transistor M5 is a floating diffusion region FD2. The floating diffusion region FD2 includes a capacitance component (floating diffusion capacitance) and functions as a charge storage region. In FIG. 2, this capacitance component is represented by capacitances C2 and C3. A wiring having the same potential as the floating diffusion region FD2 is connected to the floating diffusion region FD2. The capacitance component formed by electrostatic coupling between at least a portion of this wiring and a wiring connected to the gate of the transfer transistor M1 is the capacitance C2. The wiring connected to the floating diffusion region FD2 and the wiring connected to the gate of the transfer transistor M1 may be arranged in parallel. The capacitance C2 may be formed, for example, by a MOM (Metal-Oxide-Metal) capacitor, a MIM (Metal-Insulator-Metal) capacitor, a POM (Polysilicon-Oxide-Metal) capacitor, or a combination of these. The capacitance C2 is set to have a capacitance value sufficient to change the potential of the floating diffusion FD due to capacitive coupling with the floating diffusion FD when the transfer transistor M1 is driven. Note that the wiring connected to the floating diffusion FD2 and the wiring connected to the gate of the transfer transistor M1 do not necessarily need to be strictly parallel, as long as they are arranged side by side so that capacitive coupling is formed between them.

[0027] The capacitance C3 is a capacitance component formed between the floating diffusion region FD2 and a component other than the wiring connected to the gate of the transfer transistor M1. Although one electrode of the capacitance C3 is connected to the ground node in FIG. 2, the capacitance C3 may also include a capacitance component formed between the component other than the wiring connected to the gate of the transfer transistor M1 and the ground node. The capacitance C3 may also include a capacitance component of the channel portion under the gate that is added when the reset transistor M4 is turned on.

[0028] The drain of the reset transistor M5 and the drain of the amplifying transistor M2 are connected to a power supply voltage node (voltage: VDD). The source of the amplifying transistor M2 is connected to the drain of the selection transistor M3. The source of the selection transistor M3 is connected to the output line 16. The voltage supplied to the drain of the reset transistor M5 and the voltage supplied to the drain of the amplifying transistor M2 may be the same or different.

[0029] Each of the control lines 14 includes four signal lines connected to the gates of the transfer transistor M1, the selection transistor M3, the reset transistor M5, and the reset transistor M4. A control signal P_TX is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M1. A control signal P_SEL is output from the vertical scanning circuit 20 to the signal line connected to the gate of the selection transistor M3. A control signal P_RES is output from the vertical scanning circuit 20 to the signal line connected to the gate of the reset transistor M5. A control signal P_RES1 is output from the vertical scanning circuit 20 to the signal line connected to the gate of the reset transistor M4. When each transistor is an N-type transistor, a high-level control signal supplied from the vertical scanning circuit 20 turns the corresponding transistor on, and a low-level control signal supplied from the vertical scanning circuit 20 turns the corresponding transistor off.

[0030] In this embodiment, the description will be made assuming that electrons, among electron-hole pairs generated in the photoelectric conversion unit PD by incident light, are used as signal charges. When electrons are used as signal charges, each transistor constituting the pixel 12 may be configured as an N-type MOS transistor. However, the signal charges are not limited to electrons; holes may also be used as signal charges. When holes are used as signal charges, the conductivity type of each transistor will be the opposite conductivity type to that described in this embodiment. In this specification, when the first conductivity type is N-type, the second conductivity type is P-type, and when the first conductivity type is P-type, the second conductivity type is N-type. Furthermore, when the charge of the first polarity is a negative charge (electron), the charge of the second polarity is a positive charge (hole), and when the charge of the first polarity is a positive charge (hole), the charge of the second polarity is a negative charge (electron).

[0031] Furthermore, the names of the source and drain of a MOS transistor may differ depending on the conductivity type of the transistor and the function of interest. Some or all of the names of the source and drain used in this embodiment may be called by the reversed names. Note that in this specification, the source and drain terminals of a MOS transistor may be called the main node, and the gate may be called the control node.

[0032] The photoelectric conversion unit PD converts incident light into an electric charge in an amount corresponding to the amount of light (photoelectric conversion) and accumulates the generated electric charge. When the transfer transistor M1 is turned on, it functions as a transfer unit that transfers the electric charge held by the photoelectric conversion unit PD to the floating diffusion unit FD. The floating diffusion unit FD holds the electric charge transferred from the photoelectric conversion unit PD and sets the voltage of the input node of the amplifier unit (the gate of the amplifier transistor M2) to a voltage corresponding to its capacitance (floating diffusion capacitance) and the amount of transferred electric charge.

[0033] The reset transistor M4 functions as a switch that electrically connects the floating diffusion region FD and the floating diffusion region FD2 when it is turned on. The reset transistor M4 also switches the capacitance of the floating diffusion region FD depending on its connection state. That is, when the reset transistor M4 is turned on, it adds capacitances C2 and C3 to the capacitance C1 of the floating diffusion region FD, and when it is turned off, it separates capacitances C2 and C3 from the capacitance C1 of the floating diffusion region FD.

[0034] The reset transistor M5 functions as a reset unit that resets the floating diffusion units FD and FD2 to a voltage corresponding to the voltage VDD by turning on together with the reset transistor M4. At this time, it is also possible to reset the photoelectric conversion unit PD to a voltage corresponding to the voltage VDD by also turning on the transfer transistor M1.

[0035] The amplifier transistor M2 has a drain supplied with a voltage VDD and a source supplied with a bias current from a current source (not shown) via the selection transistor M3, forming an amplifier section (source follower circuit) with its gate as an input node. This allows the amplifier transistor M2 to generate a signal corresponding to the voltage of the floating diffusion region FD and output it to the output line 16 via the selection transistor M3. In other words, the amplifier transistor M2 and the selection transistor M3 function as an output section that outputs a signal corresponding to the potential of the floating diffusion region FD.

[0036] The selection transistor M3 selects whether or not to output a signal corresponding to the source voltage of the amplification transistor M2 as a pixel signal to the output line 16. That is, when the selection transistor M3 is turned on, the signal of the pixel 12 is set in a state (selected state) in which it can be output to the output line 16.

[0037] Next, a more specific example of the operation of the pixel 12 will be described with reference to Fig. 3. Fig. 3 is a timing chart showing the operation of a pixel in the photoelectric conversion device according to this embodiment. Fig. 3 shows the time variations of control signals P_TX, P_SEL, P_RES, and P_RES1 supplied from the vertical scanning circuit 20 to the pixel 12. When each control signal is at a high level, the corresponding transistor is active (on state).

[0038] During a frame period, which is a unit time for acquiring one image, a readout operation of pixel signals based on signal charges accumulated in the floating diffusion regions FD of the pixels 12 in each row during a predetermined exposure period is performed sequentially for each row. Of the control signals supplied during the Nth frame, Figure 3 shows the control signals supplied to the pixels 12 in the nth row and the control signals supplied to the pixels 12 in the (n+1)th row. The control signals supplied to the pixels 12 in the nth row are denoted by (n) and the control signals supplied to the pixels 12 in the (n+1)th row are denoted by (n+1). The readout operation for the nth row starts at time t01, and ends at time t06.

[0039] The photoelectric conversion device according to this embodiment can operate in multiple operating modes, including a high gain mode (hereinafter referred to as HG mode) and a low gain mode (hereinafter referred to as LG mode). In HG mode, the reset transistor M4 is turned off during signal readout to reduce the capacitance of the floating diffusion layer FD. This increases the output signal amplitude for a small signal input, thereby minimizing noise in low-light imaging scenes. In LG mode, the reset transistor M4 is turned on to increase the capacitance added to the floating diffusion layer FD. This allows large signals generated in high-light imaging scenes to be read out. The drive pulses of the control signals P_RES and P_RES1 differ between the HG mode and the LG mode. Note that while FIG. 3 shows both the control signals P_RES and P_RES1 in LG mode and the control signals P_RES and P_RES1 in HG mode, only one of these is supplied depending on the operating mode.

[0040] Just before time t01, the control signals P_TX(n), P_SEL(n), P_TX(n+1), and P_SEL(n+1) are at low level, and the control signals P_RES(n), P_RES1(n), P_RES(n+1), and P_RES1(n+1) are at high level.

[0041] At time t01, the vertical scanning circuit 20 changes the control signal P_SEL(n) from low to high. This turns on the selection transistor M3 of the pixel 12 in the nth row, and the amplification transistor M2 of the pixel 12 in each column in the nth row is connected to the output line 16 of the corresponding column via the selection transistor M3, resulting in a selected state in which pixel signals can be read out. At this time, the reset transistors M5 and M4 are turned on in response to the high-level control signals P_RES(n) and P_RES1(n), and the floating diffusions FD and FD2 are reset to a potential corresponding to the voltage VDD. As a result, a signal corresponding to the reset potential of the floating diffusion FD is output to the output line 16.

[0042] In the HG mode, at the next time t02, the vertical scanning circuit 20 changes the control signal P_RES1(n) from high to low. This turns off the reset transistor M4 of the pixel 12 in the nth row, releasing the reset state of the floating diffusion FD. The voltage of the output line 16 that stabilizes after turning off the reset transistor M4 is the reset level voltage VRES of the pixel 12. In this way, the reset level voltage VRES of the pixel 12 is read out to the output line 16. Thereafter, the capacitance associated with the floating diffusion FD becomes capacitance C1, and a signal is read out with a high gain.

[0043] On the other hand, in the LG mode, at time t02, the vertical scanning circuit 20 changes the control signal P_RES(n) from high to low. This turns off the reset transistor M5 of the pixel 12 in the nth row, and the reset state of the floating diffusions FD and FD2 is released. The voltage of the output line 16 that stabilizes after turning off the reset transistor M5 is the reset level voltage VRES of the pixel 12. In this way, the reset level voltage VRES of the pixel 12 is read out to the output line 16. Thereafter, the capacitance associated with the floating diffusion FD becomes the combined capacitance of the capacitances C1, C2, and C3, and signal readout is performed with a low gain.

[0044] During the subsequent period from time t03 to time t04, the vertical scanning circuit 20 changes the control signal P_TX(n) from low to high. This turns on the transfer transistor M1 of the pixel 12 in the nth row, and the signal charge held in the photoelectric conversion unit PD is transferred to the floating diffusion unit FD. At this time, the floating diffusion unit FD has a potential corresponding to the amount of signal charge transferred from the photoelectric conversion unit PD, and a voltage corresponding to the potential of the floating diffusion unit FD is output to the output line 16.

[0045] In this case, in the LG mode, the voltage of the floating diffusion FD increases with the change in the control signal P_TX due to the capacitive coupling of the capacitance C2 between the signal line transmitting the control signal P_TX and the floating diffusion FD2. Here, if the voltage increase of the floating diffusion FD is dV and the voltage difference between the on voltage and off voltage of the control signal P_TX is dVtx, the voltage increase dV can be expressed as the following equation (1). dV=dVtx×C2 / (C1+C2+C3) …(1)

[0046] By boosting the floating diffusion region FD, it becomes possible to store more charge in the floating diffusion region FD, thereby expanding the dynamic range of the output signal. Furthermore, by boosting the floating diffusion region FD, the potential difference between the floating diffusion region FD and the photoelectric conversion region PD becomes larger, so that the charge transferred from the photoelectric conversion region PD to the floating diffusion region FD is less likely to remain in the photoelectric conversion region PD. This makes it easier to achieve complete charge transfer from the photoelectric conversion region PD to the floating diffusion region FD.

[0047] This effect can be further enhanced when capacitance C2 is large, for example, in a circuit in which the capacitance value of capacitance C2 is larger than the capacitance value of capacitance C3. For example, in a pixel circuit in which capacitance C1 is 1 fF, capacitance C2 is 2 fF, capacitance C3 is 1 fF, and the voltage difference dVtx of the control signal P_TX is 4 V, a voltage increase amount dV of 2 V can be obtained.

[0048] When capacitance C2 is small, for example, in a circuit in which the capacitance of capacitance C3 is larger than that of capacitance C2, the influence of the control signal P_TX on the voltage settling of the floating diffusion region FD can be reduced. In this case, even when the control signal P_TX settles slowly, the proportion of capacitance C2 in the total capacitance of the floating diffusion region FD is small, so the voltage settling of the floating diffusion region FD is less affected by the settling of the control signal P_TX. This leads to improved frame rates and reduced readout noise. For example, in a pixel circuit with capacitances C1 and C3 of 1 fF, C2 and C3 of 2 fF, and a voltage difference dVtx of the control signal P_TX of 4 V, the proportion of capacitance C2 in the total capacitance of the floating diffusion region FD can be kept to 25% while achieving a voltage increase dV of 1 V.

[0049] The voltage of the output line 16 that settles after the transfer transistor M1 is turned off at time t04 is the signal level voltage VSIG of the pixel 12. In this way, the signal level voltage VSIG of the pixel 12 based on the signal charge held in the photoelectric conversion unit PD is read out to the output line 16. The difference between the reset level voltage VRES and the signal level voltage VSIG obtained in this way, i.e., |VSIG-VRES|, is a physical quantity corresponding to the amount of signal charge held in the photoelectric conversion unit PD.

[0050] At the next time t05, the vertical scanning circuit 20 changes the control signal PRES1(n) in the HG mode or the control signal P_RES(n) in the LG mode from low to high. This turns on the reset transistors M5 and M4 of the pixels 12 in the nth row, resetting the floating diffusions FD and FD2 to a potential corresponding to the voltage VDD. A signal corresponding to the reset potential of the floating diffusion FD is output to the output line 16.

[0051] Also at time t05, the vertical scanning circuit 20 changes the control signal P_SEL(n) from high to low, thereby turning off the selection transistors M3 of the pixels 12 in the nth row and deselecting the nth row.

[0052] During the period from time t05 to time t06, signals based on the signal charges accumulated in the photoelectric conversion units PD are read out from the pixels 12 in the (n+1)th row in the same manner as during the period from time t01 to time t05. The readout operation for the pixels 12 in the other rows is also similar.

[0053] Although it is conceivable to use a coupling capacitance between a fixed potential wiring and the floating diffusion as the capacitance to be added to the floating diffusion, in this case, it is necessary to add wiring and circuits to adjust the capacitance of the floating diffusion, which may increase the number of wirings, wiring density, number of circuits, and circuit density. Therefore, particularly in imaging devices with small pixel sizes, there is a possibility that the yield of wiring and circuits will deteriorate and ultimately manufacturing costs will increase.

[0054] In this regard, in the photoelectric conversion device of this embodiment, the capacitance of the floating diffusion is controlled by utilizing the capacitance formed by the electrostatic coupling between the wiring connected to the transfer wiring and the wiring connected to the floating diffusion, eliminating the need for a dedicated circuit for adjusting the capacitance of the floating diffusion. This makes it possible to achieve a circuit configuration for acquiring images with a high dynamic range while suppressing increases in manufacturing costs due to circuit complexity.

[0055] As described above, according to this embodiment, a circuit configuration for acquiring an image with a high dynamic range can be realized at low cost in a photoelectric conversion device.

[0056] [Second embodiment] A photoelectric conversion device and a driving method thereof according to a second embodiment of the present invention will be described with reference to Figs. 4 and 5. Components similar to those in the photoelectric conversion device according to the first embodiment are given the same reference numerals, and their description will be omitted or simplified. Fig. 4 is an equivalent circuit diagram showing an example of the configuration of a pixel in the photoelectric conversion device according to this embodiment. Fig. 5 is a timing chart showing the operation of a pixel in the photoelectric conversion device according to this embodiment.

[0057] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion device according to the first embodiment except for the configuration of the pixel 12. In this embodiment, differences from the photoelectric conversion device of the first embodiment will be mainly described, and descriptions of parts that are similar to the photoelectric conversion device of the first embodiment will be omitted as appropriate.

[0058] Pixel 12 of the photoelectric conversion device according to this embodiment differs from pixel 12 of the photoelectric conversion device according to the first embodiment in that the source of reset transistor M5 is connected to the floating diffusion region FD rather than the floating diffusion region FD2, as shown in FIG.

[0059] In the pixel 12 of this embodiment, the connection node between the drain of the transfer transistor M1, the source of the reset transistor M4, the source of the reset transistor M5, and the gate of the amplification transistor M2 is the floating diffusion region FD. The floating diffusion region FD includes a capacitance C1 (floating diffusion capacitance) and functions as a charge storage region. Note that, although one electrode of the capacitance C1 is connected to the ground node in FIG. 4, the capacitance component connected to the floating diffusion region FD may also include a capacitance component formed between the capacitance C1 and a member other than the ground node.

[0060] Furthermore, in the pixel 12 of this embodiment, the drain of the reset transistor M4 is the floating diffusion region FD2. The floating diffusion region FD2 includes capacitance components (capacitances C2 and C3) and functions as a charge storage region. A wiring having the same potential as the floating diffusion region FD2 is connected to the floating diffusion region FD2. The capacitance component formed between at least a portion of this wiring and the wiring connected to the gate of the transfer transistor M1 is the capacitance C2. The capacitance C3 is a capacitance component formed between the floating diffusion region FD2 and a component other than the wiring connected to the gate of the transfer transistor M1. Note that, although one electrode of the capacitance C3 is connected to the ground node in FIG. 4, the capacitance C3 may also include capacitance components formed between the wiring connected to the gate of the transfer transistor M1 and components other than the ground node.

[0061] As in the first embodiment, the reset transistor M4 connects the floating diffusion region FD and the floating diffusion region FD2 when it is turned on. The reset transistor M4 also switches the capacitance of the floating diffusion region FD depending on its operating state. That is, when the reset transistor M4 is turned on, it adds capacitances C2 and C3 to the capacitance C1 of the floating diffusion region FD, and when it is turned off, it disconnects capacitances C2 and C3 from the floating diffusion region FD. When the reset transistor M5 is turned on, it resets the floating diffusion region FD to a voltage corresponding to the voltage VDD. At this time, it is also possible to reset the photoelectric conversion unit PD to a voltage corresponding to the voltage VDD by also turning on the transfer transistor M1.

[0062] The photoelectric conversion device according to this embodiment can also operate in a plurality of operation modes, including the HG mode and the LG mode, similarly to the photoelectric conversion device according to the first embodiment. For example, the driving method of the photoelectric conversion device according to this embodiment can be the same as the driving method of the photoelectric conversion device according to the first embodiment shown in Fig. 3, except for the control signal P_RES in the HG mode. In the HG mode, for example, as shown in Fig. 5, the control signal P_RES may be controlled to a low level during the pixel signal readout period (the period from time t02 to time t05 in the nth row).

[0063] In the photoelectric conversion device of this embodiment, the connection relationship between the source of the reset transistor M5 and the floating diffusion regions FD, FD2 is different from that of the photoelectric conversion device of the first embodiment, but like the first embodiment, the dynamic range of the output signal can be expanded without adding drive wiring or circuits. An appropriate configuration can be selected for the connection between the source of the reset transistor M5 and the floating diffusion regions FD, FD2 depending on the design constraints of the layout of the pixel 12, etc.

[0064] As described above, according to this embodiment, a circuit configuration for acquiring an image with a high dynamic range can be realized at low cost in a photoelectric conversion device.

[0065] [Third embodiment] A photoelectric conversion device and a driving method thereof according to a third embodiment of the present invention will be described with reference to Figures 6 to 10. Components similar to those of the photoelectric conversion device according to the first or second embodiment are given the same reference numerals, and descriptions thereof will be omitted or simplified.

[0066] First, a configuration example of a photoelectric conversion device according to this embodiment will be described with reference to Fig. 6 and Fig. 7. Fig. 6 is an equivalent circuit diagram showing a configuration example of a pixel of the photoelectric conversion device according to this embodiment. Fig. 7 is a plan view and a cross-sectional view of a pixel of the photoelectric conversion device according to this embodiment.

[0067] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion device according to the first or second embodiment, except for the configuration of the pixel 12. In this embodiment, differences from the photoelectric conversion device according to the first or second embodiment will be mainly described, and descriptions of parts that are similar to the photoelectric conversion device according to the first or second embodiment will be omitted as appropriate.

[0068] 6, a pixel 12 of the photoelectric conversion device according to this embodiment may include photoelectric conversion units PDA and PDB, transfer transistors M1A and M1B, an amplification transistor M2, a selection transistor M3, and reset transistors M4 and M5. The photoelectric conversion units PDA and PDB may be formed of photoelectric conversion elements, such as photodiodes. The transfer transistors M1A and M1B, the amplification transistor M2, the selection transistor M3, and the reset transistors M4 and M5 may be formed of MOS transistors.

[0069] The photoelectric conversion unit PDA has an anode connected to the ground node and a cathode connected to the source of the transfer transistor M1A. The photoelectric conversion unit PDB has an anode connected to the ground node and a cathode connected to the source of the transfer transistor M1B. The drains of the transfer transistors M1A and M1B are connected to the gate of the amplifier transistor M2 and the source of the reset transistor M4. The connection node between the drain of the transfer transistor M1A, the drain of the transfer transistor M1B, the gate of the amplifier transistor M2, and the source of the reset transistor M4 is the floating diffusion unit FD. The floating diffusion unit FD includes a capacitance C1 (floating diffusion capacitance) and functions as a charge storage unit. Note that, although one electrode of the capacitance C1 is connected to the ground node in FIG. 6, the capacitance component connected to the floating diffusion unit FD may also include capacitance components formed between the floating diffusion unit FD and components other than the ground node.

[0070] The drain of the reset transistor M4 is connected to the source of the reset transistor M5. The connection node between the drain of the reset transistor M4 and the source of the reset transistor M5 is the floating diffusion region FD2. The floating diffusion region FD2 includes capacitance components (capacitances C2A, C2B, and C3) and functions as a charge storage region. A wiring having the same potential as the floating diffusion region FD2 is connected to the floating diffusion region FD2. The capacitance component formed between at least a portion of this wiring and a wiring connected to the gate of the transfer transistor M1A is the capacitance C2A. Furthermore, the capacitance component formed between at least a portion of this wiring and a wiring connected to the gate of the transfer transistor M1B is the capacitance C2B. The capacitance C3 is a capacitance component formed between the floating diffusion region FD2 and a component other than the wiring connected to the gate of the transfer transistor M1A and the wiring connected to the gate of the transfer transistor M1B. 6, one electrode of the capacitor C3 is connected to the ground node, but the capacitor C3 may also include capacitance components formed between the wiring connected to the gates of the transfer transistors M1A and M1B and components other than the ground node. The capacitor C3 may also include a capacitance component of the channel portion under the gate that is added when the reset transistor M4 is turned on.

[0071] Each of the control lines 14 includes five signal lines connected to the gates of the transfer transistor M1A, the transfer transistor M1B, the selection transistor M3, the reset transistor M5, and the reset transistor M4. A control signal P_TXA is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M1A. A control signal P_TXB is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M1B. A control signal P_SEL is output from the vertical scanning circuit 20 to the signal line connected to the gate of the selection transistor M3. A control signal P_RES is output from the vertical scanning circuit 20 to the signal line connected to the gate of the reset transistor M5. A control signal P_RES1 is output from the vertical scanning circuit 20 to the signal line connected to the gate of the reset transistor M4. When each transistor is an N-type transistor, a high-level control signal supplied from the vertical scanning circuit 20 turns the corresponding transistor on, and a low-level control signal supplied from the vertical scanning circuit 20 turns the corresponding transistor off.

[0072] FIG. 7 is a schematic diagram showing an example of the arrangement of the photoelectric conversion unit PDA and the photoelectric conversion unit PDB that constitute one pixel 12. FIG. 7(a) is a top view, and FIG. 7(b) is a cross-sectional view taken along line AA′ in FIG. 7(a). The photoelectric conversion unit PDA and the photoelectric conversion unit PDB are provided in a semiconductor layer 110 together with each transistor (not shown) that constitutes the pixel 12. A microlens ML is disposed above the semiconductor layer 110 via a color filter layer CF or the like. As shown in FIGS. 7(a) and 7(b), the photoelectric conversion unit PDA and the photoelectric conversion unit PDB that constitute one pixel 12 share one microlens ML. In other words, the photoelectric conversion unit PDA and the photoelectric conversion unit PDB are configured to receive light that has passed through different pupil regions of light that has entered the imaging optical system. That is, the microlens ML focuses light that passes through a first pupil region of the exit pupil of the imaging lens onto the photoelectric conversion unit PDA, and focuses light that passes through a second pupil region different from the first pupil region onto the photoelectric conversion unit PDB. With this configuration, a signal (image A signal) based on the charges generated by the photoelectric conversion unit PDA and a signal (image B signal) based on the charges generated by the photoelectric conversion unit PDB can be used as a phase difference detection signal for distance measurement. Furthermore, a signal (image A+B signal) based on the total charges generated by the photoelectric conversion units PDA and PDB can be used as a signal for generating an image.

[0073] Next, a more specific example of the operation of the pixel 12 will be described with reference to Fig. 8. Fig. 8 is a timing chart showing the operation of a pixel in the photoelectric conversion device according to this embodiment. Fig. 8 shows the time variations of control signals P_TXA, P_TXB, P_SEL, P_RES, and P_RES1 supplied from the vertical scanning circuit 20 to the pixel 12. When each control signal is at a high level, the corresponding transistor is active (on state).

[0074] During a frame period, which is a unit period for acquiring one image, a readout operation of pixel signals based on signal charges accumulated in the floating diffusion regions FD of the pixels 12 in each row during a predetermined exposure period is performed sequentially for each row. Figure 8 shows, among the control signals supplied during the Nth frame, the control signals supplied to the pixels 12 in the nth row and the control signals supplied to the pixels 12 in the (n+1)th row. The control signals supplied to the pixels 12 in the nth row are denoted by (n) and the control signals supplied to the pixels 12 in the (n+1)th row are denoted by (n+1). The readout operation for the nth row starts at time t11, and ends at time t18.

[0075] As described above, the photoelectric conversion device according to this embodiment can also operate in multiple operating modes, including the HG mode and the LG mode. In the HG mode, the reset transistor M4 is turned off during signal readout to reduce the capacitance of the floating diffusion layer FD. This increases the output signal amplitude for a small signal input, thereby minimizing noise in low-light imaging scenes. In the LG mode, the reset transistor M4 is turned on to increase the capacitance added to the floating diffusion layer FD. This allows large signals generated in high-light imaging scenes to be read out. The drive pulses of the control signals P_RES and P_RES1 differ between the HG mode and the LG mode. Note that while FIG. 8 shows both the control signals P_RES and P_RES1 in the LG mode and the control signals P_RES and P_RES1 in the HG mode, only one of these is supplied depending on the operating mode.

[0076] Just before time t11, the control signals P_TXA(n), P_TXB(n), and P_SEL(n) are low, and the control signals P_RES(n) and P_RES1(n) are high. Also, the control signals P_TXA(n+1), P_TXB(n+1), and P_SEL(n+1) are low, and the control signals P_RES(n+1) and P_RES1(n+1) are high.

[0077] At time t11, the vertical scanning circuit 20 changes the control signal P_SEL(n) from low to high. This turns on the selection transistor M3 of the pixel 12 in the nth row, and the amplification transistor M2 of the pixel 12 in each column in the nth row is connected to the output line 16 of the corresponding column via the selection transistor M3, resulting in a selected state in which pixel signals can be read out. At this time, the reset transistors M5 and M4 are turned on in response to the high-level control signals P_RES(n) and P_RES1(n), and the floating diffusions FD and FD2 are reset to a potential corresponding to the voltage VDD. As a result, a signal corresponding to the reset potential of the floating diffusion FD is output to the output line 16.

[0078] In the HG mode, the vertical scanning circuit 20 subsequently changes the control signal P_RES1(n) from high to low at time t12. This turns off the reset transistor M4 of the pixel 12 in the nth row, releasing the reset state of the floating diffusion FD. The voltage of the output line 16 that stabilizes after turning off the reset transistor M4 is the reset level voltage VRES of the pixel 12. In this way, the reset level voltage VRES of the pixel 12 is read out to the output line 16. Thereafter, the capacitance associated with the floating diffusion FD becomes capacitance C1, and a signal is read out with a high gain.

[0079] On the other hand, in the LG mode, the vertical scanning circuit 20 changes the control signal P_RES(n) from high to low at time t12. This turns off the reset transistor M5 of the pixel 12 in the nth row, releasing the reset state of the floating diffusions FD and FD2. The voltage of the output line 16 that settles after turning off the reset transistor M5 is the reset level voltage VRES of the pixel 12. In this way, the reset level voltage VRES of the pixel 12 is read out to the output line 16. Thereafter, the capacitance associated with the floating diffusion FD is the combined capacitance of the capacitances C1, C2, and C3, and signal readout is performed with a low gain.

[0080] During the subsequent period from time t13 to time t14, the vertical scanning circuit 20 changes the control signal P_TXA(n) from low to high. This turns on the transfer transistor M1A of the pixel 12 in the nth row, and the signal charge held in the photoelectric conversion unit PDA is transferred to the floating diffusion unit FD. At this time, the floating diffusion unit FD has a potential corresponding to the amount of signal charge transferred from the photoelectric conversion unit PDA, and a voltage corresponding to the potential of the floating diffusion unit FD is output to the output line 16.

[0081] In this case, in the LG mode, the voltage of the floating diffusion FD increases with the change in the control signal P_TXA due to the capacitive coupling of the capacitance C2A between the signal line transmitting the control signal P_TXA and the floating diffusion FD2. Here, if the voltage increase amount of the floating diffusion FD is dV and the voltage difference between the on voltage and off voltage of the control signal P_TXA is dVtx, the voltage increase amount dV can be expressed as the following equation (2). dV=dVtx×C2A / (C1+C2A+C2B+C3) …(2)

[0082] By boosting the floating diffusion region FD, it becomes possible to store more charge in the floating diffusion region FD, thereby expanding the dynamic range of the output signal. Furthermore, by boosting the floating diffusion region FD, the potential difference between the floating diffusion region FD and the photoelectric conversion region PDA becomes larger, so the charge transferred from the photoelectric conversion region PDA to the floating diffusion region FD is less likely to remain in the photoelectric conversion region PDA. This makes it easier to achieve complete charge transfer from the photoelectric conversion region PDA to the floating diffusion region FD.

[0083] The capacitance associated with the signal line that transmits the control signal P_TXA when reading out the image signal A is smaller than the capacitance associated with the signal lines that transmit the control signals P_TXA and P_TXB when reading out the image signal A. Therefore, it is also possible to shorten the period (from time t13 to time t14) during which the transfer transistor M1A is turned on, thereby improving the frame rate.

[0084] The voltage of the output line 16 that settles after the transfer transistor M1A is turned off at time t14 is the signal level voltage VSIGA of the pixel 12. In this way, the signal level voltage VSIGA of the pixel 12 based on the signal charge held in the photoelectric conversion unit PDA is read out to the output line 16. The difference between the reset level voltage VRES and the signal level voltage VSIGA obtained in this way, i.e., |VSIGA-VRES|, is a physical quantity corresponding to the amount of signal charge held in the photoelectric conversion unit PDA.

[0085] During the subsequent period from time t15 to time t16, the vertical scanning circuit 20 changes the control signals P_TXA(n) and P_TXB(n) from low to high. This turns on the transfer transistors M1A and M1B of the pixels 12 in the nth row, and the signal charges held in the photoelectric conversion units PDA and PDB are transferred to the floating diffusion units FD. At this time, the floating diffusion units FD have a potential corresponding to the amount of signal charges transferred from the photoelectric conversion units PDA and PDB, and a voltage corresponding to the potential of the floating diffusion units FD is output to the output line 16.

[0086] In this case, in the LG mode, the voltage of the floating diffusion FD increases with changes in the control signals P_TXA and P_TXB due to capacitive coupling by capacitances C2A and C2B between the signal lines transmitting the control signals P_TXA and P_TXB and the floating diffusion FD2. Here, if the voltage increase amount of the floating diffusion FD is dV, the voltage difference between the on voltage and off voltage of the control signal P_TXA is dVtxA, and the voltage difference between the on voltage and off voltage of the control signal P_TXB is dVtxB, the voltage increase amount dV can be expressed as follows: dV=(dVtxA×C2A+dVtxB×C2B) / (C1+C2A+C2B+C3) …(3)

[0087] Boosting the floating diffusion region FD allows it to store more charge, expanding the dynamic range of the output signal. Boosting the floating diffusion region FD also increases the potential difference between the floating diffusion region FD and the photoelectric conversion regions PDA and PDB, making it less likely that charge transferred from the photoelectric conversion regions PDA and PDB to the floating diffusion region FD will remain in the photoelectric conversion regions PDA and PDB. This makes it easier to achieve complete charge transfer from the photoelectric conversion regions PDA and PDB to the floating diffusion region FD.

[0088] This effect can be further enhanced when capacitance C2A and capacitance C2B are large, for example in a circuit in which the sum of the capacitance values ​​of capacitances C2A and C2B is larger than the capacitance value of capacitance C3. For example, in a pixel circuit in which capacitance C1 is 1 fF, capacitance C2A is 1 fF, capacitance C2B is 1 fF, and capacitance C3 is 1 fF, the voltage difference dVtxA of the control signal P_TXA is 4 V, and the voltage difference dVtxB of the control signal P_TXB is 4 V, a voltage increase dV of 2 V can be obtained.

[0089] When the capacitances C2A and C2B are small, for example, in a circuit where the sum of the capacitances of C2A and C2B is smaller than the capacitance of C3, the influence of the control signals P_TXA and P_TXB on the voltage settling of the floating diffusion region FD can be reduced. In this case, even when the control signals P_TXA and P_TXB settle slowly, the proportion of capacitances C2A and C2B in the total capacitance of the floating diffusion region FD is small, so the voltage settling of the floating diffusion region FD is less affected by the settling of the control signals P_TXA and P_TXB. This leads to improved frame rates and reduced readout noise. For example, consider a pixel circuit with capacitance C1 of 1 fF, capacitance C2A of 1 fF, capacitance C2B of 1 fF, and capacitance C3 of 5 fF. The voltage difference dVtxA of the control signal P_TXA is 4 V, and the voltage difference dVtxB of the control signal P_TXB is 4 V. In this case, while obtaining a voltage increase dV of 1 V, the proportion of capacitance C2A to the total capacitance of the floating diffusion region FD can be reduced to approximately 13%, and the proportion of capacitance C2B to the total capacitance of the floating diffusion region FD can be reduced to approximately 13%.

[0090] The voltage of the output line 16 that settles after the transfer transistors M1A and M1B are turned off at time t16 is the signal level voltage VSIGAB of the pixel 12. In this way, the signal level voltage VSIGAB of the pixel 12, which is based on the signal charge held in the photoelectric conversion units PDA and PDB, is read out to the output line 16. The difference between the reset level voltage VRES and the signal level voltage VSIGAB obtained in this way, i.e., |VSIGAB-VRES|, is a physical quantity corresponding to the amount of signal charge held in the photoelectric conversion units PDA and PDB.

[0091] At the next time t17, the vertical scanning circuit 20 changes the control signal PRES1(n) in the HG mode or the control signal P_RES(n) in the LG mode from low to high. This turns on the reset transistors M5 and M4 of the pixels 12 in the nth row, resetting the floating diffusions FD and FD2 to a potential corresponding to the voltage VDD. A signal corresponding to the reset potential of the floating diffusion FD is output to the output line 16.

[0092] Also at time t17, the vertical scanning circuit 20 changes the control signal P_SEL(n) from high to low, thereby turning off the selection transistors M3 of the pixels 12 in the nth row and deselecting the nth row.

[0093] During the period from time t17 to time t18, signals based on the signal charges accumulated in the photoelectric conversion units PD are read out from the pixels 12 in the (n+1)th row in the same manner as during the period from time t11 to time t17. The readout operation for the pixels 12 in the other rows is also similar.

[0094] 9 and 10 are plan views showing an example of the layout of pixels 12 in the photoelectric conversion device of this embodiment. FIGS. 9 and 10 show four pixels 12 arranged translationally symmetrically with respect to the horizontal (X) and vertical (Y) directions. To simplify the drawings, FIGS. 9 and 10 only show the active regions 112 and 114 provided in the semiconductor substrate (semiconductor layer 110), the polysilicon layer constituting the gate electrodes of each transistor, and the patterns of the first and second wiring layers. The active regions 112 and 114 are represented by white regions surrounded by solid lines, and the cathodes of the photoelectric conversion units PDA and PDB arranged in the active region 112 are represented by coarsely dotted regions surrounded by dashed lines. The polysilicon layer is represented by a finely dotted region surrounded by solid lines, and the gate electrodes of each transistor are assigned a symbol representing that transistor. The first wiring layer is represented by a diagonally shaded region surrounded by solid lines. The second wiring layer is represented by the white area surrounded by a dashed line. The rectangular areas marked with an x ​​represent contact holes and via holes between layers for connecting conductive members. The first and second wiring layers can be made of metal materials such as aluminum or copper.

[0095] The active region 112 includes an active region 112a in which the photoelectric conversion units PDA, PDB and the transfer transistors M1A, M1B are arranged, and an active region 112b in which the reset transistors M4, M5 are arranged. The active region 112a extends in the horizontal direction and forms a single region common to multiple pixels 12 aligned in the horizontal direction. The active region 112b is provided for each pixel 12 so as to branch off from the active region 112a. The active region 114 is a region in which the amplification transistor M2 and the selection transistor M3 are arranged, and is provided for each pixel 12, spaced apart from the active region 112.

[0096] The first wiring layer is disposed above the semiconductor layer 110 and the gate layer via an interlayer insulating film (not shown), and includes wirings 120, 122, and 124. The wiring 120 is electrically connected to the gate of the transfer transistor M1A via a via hole provided in the interlayer insulating film. The wiring 122 is electrically connected to the gate of the transfer transistor M1B via a via hole provided in the interlayer insulating film. The wiring 124 is electrically connected to the floating diffusion region FD2 via a contact hole provided in the interlayer insulating film. The second wiring layer is disposed above the wirings 120, 122, and 124 via an interlayer insulating film (not shown), and includes wiring 130. The wiring 130 is electrically connected to the gate of the transfer transistor M1B via a via hole provided in the interlayer insulating film and the wiring 122. The layouts of the wirings constituting the first wiring layer and the second wiring layer differ between FIGS. 9 and 10.

[0097] A control signal P_TXA from the vertical scanning circuit 20 is supplied to each pixel 12 via a wiring (not shown) and is supplied to the gate of the transfer transistor M1A via a wiring 120. A control signal P_TXB from the vertical scanning circuit 20 is supplied to each pixel 12 via a wiring (not shown) and is supplied to the gate of the transfer transistor M1B via a wiring 130 and a wiring 122.

[0098] In the layout example of FIG. 9, the wiring 124 extends to the region between the photoelectric conversion units PDA and PDB. The wirings 120 and 122 are arranged parallel to the wiring 124. By configuring the first wiring layer and the second wiring layer in this manner, an MIM-type capacitance constituting the capacitance C2A is formed between the wiring 124 and the wiring 120. Furthermore, an MIM-type capacitance constituting the capacitance C2B is formed between the wiring 124 and the wiring 122 and the wiring 130. The length of the portion where the wiring 120 and the wiring 124 extend in parallel and the length of the portion where the wiring 122 and the wiring 124 extend in parallel can be set appropriately depending on the capacitance values ​​required for the capacitances C2A and C2B. The magnitudes of the capacitances C2A and C2B may be the same or different.

[0099] When the capacitance value of capacitor C2A is larger than the capacitance value of capacitor C2B, the voltage increase dV of the floating diffusion FD between time t13 and time t14 when the control signal P_TXA turns on can be made larger than when the capacitance value of capacitor C2B is larger than the capacitance value of capacitor C2A. Since the voltage of the floating diffusion FD is boosted, the potential difference between the floating diffusion FD and the photoelectric conversion unit PDA becomes larger, which makes it easier to achieve complete transfer of charge from the photoelectric conversion unit PDA to the floating diffusion FD, and may make the voltage VSIGA based on the signal charge held in the photoelectric conversion unit PDA more accurate.

[0100] On the other hand, if the capacitance value of capacitor C2B is larger than the capacitance value of capacitor C2A, the capacitance associated with the signal line that transmits the control signal P_TXA when reading out the image A signal becomes smaller. Therefore, it is possible to shorten the period (from time t13 to time t14) during which the transfer transistor M1A is turned on, thereby achieving a configuration that prioritizes improving the frame rate.

[0101] In the layout example of FIG. 9, the wiring 130 is provided on the wiring 120, so that the wiring 120 and the wiring 130 are capacitively coupled. In other words, the wiring 120 and the wiring 122 are electrostatically coupled via capacitance. Therefore, the capacitance associated with the gate of the transfer transistor M1A and the capacitance associated with the gate of the transfer transistor M1B can be made equal. However, other wiring that is not connected to these wirings may be arranged between the wiring 120 and the wiring 122. In this case, the capacitance associated with the gate of the transfer transistor M1A and the capacitance associated with the gate of the transfer transistor M1B will not be equal, with one capacitance being larger and the other capacitance being smaller.

[0102] When the capacitances C2A and C2B are present, the potential of the floating diffusion portion FD increases during the charge transfer period from the photoelectric conversion portion PDA to the floating diffusion portion FD from time t13 to time t14, and during the charge transfer period from the photoelectric conversion portions PDA and PDB to the floating diffusion portion FD from time t15 to time t16. Because the potential of the floating diffusion portion FD is boosted during both charge transfer timings, charge transfer from the photoelectric conversion portions PDA and PDB to the floating diffusion portion FD can be facilitated.

[0103] In the layout example of FIG. 10, the wiring 124 extends to a region overlapping with the photoelectric conversion unit PDB. The wiring 122 is arranged in parallel to the wiring 124. By configuring the first wiring layer and the second wiring layer in this manner, an MIM-type capacitance that constitutes the capacitance C2B is formed between the wiring 124 and the wiring 122 and the wiring 130. In the layout example of FIG. 10, unlike the layout example of FIG. 9, the capacitance C2A is not formed. The length of the portion where the wiring 122 and the wiring 124 extend in parallel can be set appropriately depending on the capacitance value required for the capacitance C2B.

[0104] 10, the capacitance C2A is not formed, so the settling time of the control signal P_TXA during the charge transfer period from the photoelectric conversion unit PDA to the floating diffusion unit FD from time t13 to time t14 is shorter than in the layout example of FIG. 9. This makes it possible to shorten the time required to read out the signal. Meanwhile, during the charge transfer period from the photoelectric conversion units PDA, PDB to the floating diffusion unit FD from time t15 to time t16, the presence of capacitance C2B increases the potential of the floating diffusion unit FD, thereby achieving the same effect as in the layout example of FIG. 9.

[0105] As described above, according to this embodiment, a circuit configuration for acquiring an image with a high dynamic range can be realized at low cost in a photoelectric conversion device.

[0106] [Fourth embodiment] A photoelectric conversion device and a driving method thereof according to a fourth embodiment of the present invention will be described with reference to Figs. 11 and 12. Components similar to those in the photoelectric conversion devices according to the first to third embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 11 is an equivalent circuit diagram showing an example of the configuration of a pixel in the photoelectric conversion device according to this embodiment. Fig. 12 is a plan view showing an example of the layout of a pixel in the photoelectric conversion device according to this embodiment.

[0107] The photoelectric conversion device according to this embodiment differs from the photoelectric conversion devices according to the first to third embodiments in that a readout circuit unit within the pixel is shared by multiple pixels 12 and that a reset transistor M6 is further included. In this embodiment, the differences from the photoelectric conversion device of the first embodiment will be mainly described, and descriptions of parts that are similar to those of the photoelectric conversion device of the first embodiment will be omitted as appropriate.

[0108] As shown in FIG. 11 , the photoelectric conversion device according to this embodiment includes a pixel block 12B including a pixel element including a photoelectric conversion unit PD_0 and a transfer transistor M1_0, and a pixel element including a photoelectric conversion unit PD_1 and a transfer transistor M1_1. The pixel element including the photoelectric conversion unit PD_0 and the transfer transistor M1_0 and the pixel element including the photoelectric conversion unit PD_1 and the transfer transistor M1_1 are arranged in adjacent rows. For example, the pixel element including the photoelectric conversion unit PD_0 and the transfer transistor M1_0 is arranged in the (2n-1)th row, and the pixel element including the photoelectric conversion unit PD_1 and the transfer transistor M1_1 is arranged in the 2nth row, where n is an integer greater than or equal to 1. The pixel element including the photoelectric conversion unit PD_0 and the transfer transistor M1_0 and the pixel element including the photoelectric conversion unit PD_1 and the transfer transistor M1_0 are typically arranged in the same column, but they do not necessarily have to be arranged in the same column and may be arranged in adjacent columns. These two pixel elements share the amplifier transistor M2, the select transistor M3, the reset transistors M4, M5, and M6, and the floating diffusion regions FD, FD2, and FD3. Note that one pixel block 12B corresponds to two pixels 12 adjacent to each other in the column direction in the pixel array of FIG.

[0109] The photoelectric conversion unit PD_0 has an anode connected to the ground node and a cathode connected to the source of the transfer transistor M1_0. The photoelectric conversion unit PD_1 has an anode connected to the ground node and a cathode connected to the source of the transfer transistor M1_1. The drains of the transfer transistors M1_0 and M1_1 are connected to the gate of the amplifier transistor M2 and the source of the reset transistor M4. The connection node between the drain of the transfer transistor M1_0, the drain of the transfer transistor M1_1, the gate of the amplifier transistor M2, and the source of the reset transistor M4 is the floating diffusion unit FD. The floating diffusion unit FD includes a capacitance component (floating diffusion capacitance) and functions as a charge storage unit. In FIG. 11, this capacitance component is represented by capacitance C1. Note that, although one electrode of capacitance C1 is connected to the ground node in FIG. 11, the capacitance component associated with the floating diffusion unit FD may also include a capacitance component formed between the floating diffusion unit FD and components other than the ground node.

[0110] The drain of the reset transistor M4 is connected to the source of the reset transistor M6. The connection node between the drain of the reset transistor M4 and the source of the reset transistor M6 is the floating diffusion region FD2. The floating diffusion region FD2 includes a capacitance component (floating diffusion capacitance) and functions as a charge storage region. In FIG. 11, this capacitance component is represented by capacitances C2_0, C2_1, and C3. A wiring having the same potential as the floating diffusion region FD2 is connected to the floating diffusion region FD2. A capacitance component formed between at least a portion of this wiring and a wiring connected to the gate of the transfer transistor M1_0 is capacitance C2_0. Furthermore, a capacitance component formed between at least a portion of this wiring and a wiring connected to the gate of the transfer transistor M1_1 is capacitance C2_1. The wiring connected to the floating diffusion region FD2 and the wiring connected to the gates of the transfer transistors M1_0 and M1_1 may be arranged in parallel. The capacitance C3 is a capacitance component formed between the floating diffusion region FD2 and a member other than the wiring connected to the gate of the transfer transistor M1_0 and the wiring connected to the gate of the transfer transistor M1_1. While one electrode of the capacitance C3 is connected to the ground node in FIG. 11 , the capacitance C3 may also include a capacitance component formed between the wiring connected to the gates of the transfer transistors M1_0 and M1_1 and a member other than the ground node. The capacitance C3 may also include a capacitance component of the channel portion under the gate that is added when the reset transistor M4 is turned on.

[0111] The drain of the reset transistor M6 is connected to the source of the reset transistor M5. The connection node between the drain of the reset transistor M6 and the source of the reset transistor M5 is the floating diffusion region FD3. The floating diffusion region FD3 includes a capacitance component (capacitance C4) and functions as a charge storage region. Note that, although one electrode of the capacitance C4 is connected to the ground node in FIG. 11, the capacitance C4 may also include a capacitance component formed between the capacitance C4 and a member other than the ground node. The capacitance C4 may also include a capacitance component of the channel region under the gate that is added when the reset transistor M6 is turned on.

[0112] The control lines 14 include six signal lines connected to the gates of transfer transistor M1_0, transfer transistor M1_1, selection transistor M3, reset transistor M5, reset transistor M6, and reset transistor M4 for every two adjacent rows. A control signal P_TX_0 is output from the vertical scanning circuit 20 to the signal line connected to the gate of transfer transistor M1_0. A control signal P_TX_1 is output from the vertical scanning circuit 20 to the signal line connected to the gate of transfer transistor M1_1. A control signal P_SEL is output from the vertical scanning circuit 20 to the signal line connected to the gate of selection transistor M3. A control signal P_RES is output from the vertical scanning circuit 20 to the signal line connected to the gate of reset transistor M5. A control signal P_RES2 is output from the vertical scanning circuit 20 to the signal line connected to the gate of reset transistor M6. A control signal P_RES1 is output from the vertical scanning circuit 20 to the signal line connected to the gate of reset transistor M4. When each transistor is an N-type transistor, when a high-level control signal is supplied from the vertical scanning circuit 20, the corresponding transistor turns on, and when a low-level control signal is supplied from the vertical scanning circuit 20, the corresponding transistor turns off.

[0113] The photoelectric conversion device according to this embodiment can operate in multiple operating modes, including HG mode, medium gain mode (hereinafter referred to as MG mode), and LG mode. In HG mode, the reset transistor M4 is turned off during signal readout to reduce the capacitance of the floating diffusion FD. This increases the output signal amplitude for a small signal input, thereby minimizing noise in low-light imaging scenes. In LG mode, the reset transistors M4 and M6 are turned on to further add capacitances C2_0, C2_1, C3, and C4 to the capacitance C1 of the floating diffusion FD, thereby increasing the capacitance of the floating diffusion FD. This allows for the reading of large signals generated in high-light imaging scenes. In MG mode, the reset transistor M4 is turned on and the reset transistor M6 is turned off to add capacitances C2_0 and C2_1 to the capacitance C1 of the floating diffusion FD, thereby increasing the capacitance of the floating diffusion FD. This allows for the reading of signals generated in imaging scenes with an intermediate level of light between HG mode and LG mode. In MG mode, the capacitance of the floating diffusion FD is smaller than in LG mode, so scenes with an amount of light that would cause saturation in HG mode can be captured with less noise than in LG mode.By providing multiple reset transistors M4, M5, and M6 in pixel block 12B, it is possible to select a more appropriate capacitance of the floating diffusion FD depending on the scene being captured.

[0114] In the photoelectric conversion device according to this embodiment, the wiring connected to the gate of the transfer transistor M1_0 and the floating diffusion region FD2 are capacitively coupled by a capacitance C2_0. Furthermore, the wiring connected to the gate of the transfer transistor M1_1 and the floating diffusion region FD2 are capacitively coupled by a capacitance C2_1. In the LG mode and the MG mode, the reset transistor M4 is turned on, and these capacitances C2_0 and C2_1 are added to the capacitance C1 of the floating diffusion region FD. Therefore, the floating diffusion region FD can be boosted during charge transfer, thereby expanding the dynamic range of the output signal.

[0115] 11, a capacitor may be added to capacitively couple the floating diffusion FD3 to the wiring connected to the gate of the transfer transistor M1_0, or a capacitor may be added to capacitively couple the floating diffusion FD3 to the wiring connected to the gate of the transfer transistor M1_1. This configuration can further enhance the effect of boosting the floating diffusion FD in the LG mode.

[0116] Furthermore, although the equivalent circuit diagram of FIG. 11 shows three reset transistors M5, M6, and M4 connected in series between the power supply line and the floating diffusion region FD, the number of reset transistors connected between the power supply line and the floating diffusion region FD may be four or more. This configuration allows for a larger capacitance setting value associated with the floating diffusion region FD, further increasing the number of operating modes. In this embodiment, the readout circuit unit within the pixel is shared by multiple pixels 12, so the impact of adding transistors on the circuit area is smaller than when a readout circuit unit is provided for each pixel. The number of reset transistors connected between the power supply line and the floating diffusion region FD may be two, as in the first to third embodiments.

[0117] FIG. 12 is a plan view showing an example layout of a pixel 12 in a photoelectric conversion device according to this embodiment. FIG. 12 shows two pixel blocks 12B arranged translationally symmetrically with respect to the horizontal direction (X direction). Each pixel block 12B includes two pixels arranged in the vertical direction (Y direction). To simplify the drawing, FIG. 12 only shows the active regions 112, 114, and 116 provided on the semiconductor substrate (semiconductor layer 110), the polysilicon layer constituting the gate electrodes and capacitor electrodes of the transistors, and the patterns of the first and second wiring layers. The active regions 112, 114, and 116 are represented by white regions surrounded by solid lines, and the cathodes of the photoelectric conversion units PD_0 and PD_1 arranged in the active region 112 are represented by coarsely dotted regions surrounded by dashed lines. The polysilicon layer is represented by a finely dotted region surrounded by solid lines, and the gate electrodes and capacitor electrodes are assigned symbols indicating their transistors and capacitances. The first wiring layer is represented by the diagonally shaded area surrounded by a solid line. The second wiring layer is represented by the white area surrounded by a dashed line. The rectangular areas marked with an x ​​represent contact holes and via holes between layers for connecting conductive members.

[0118] The active region 112 includes an active region 112a in which the photoelectric conversion units PD_0 and PD_1 and the transfer transistors M1_0 and M1_1 are arranged, and an active region 112b in which the reset transistor M4 is arranged. The active region 112a extends in the vertical direction and forms a single region common to multiple pixel blocks 12B aligned in the vertical direction. The active region 112b is provided for each pixel block 12B so as to branch off from the active region 112a. The active region 114 is a region in which the amplification transistor M2 and the selection transistor M3 are arranged, and is provided for each pixel block 12B, spaced apart from the active region 112. The active region 116 is a region in which the reset transistors M5 and M6 and the capacitor C4 are arranged, and is provided for each pixel block 12B, spaced apart from the active regions 112 and 114.

[0119] The first wiring layer is disposed above the semiconductor layer 110 and the gate layer via an interlayer insulating film (not shown), and includes wirings 120, 122, and 124. The wiring 120 is electrically connected to the gate of the transfer transistor M1_0 via a via hole provided in the interlayer insulating film. The wiring 122 is electrically connected to the gate of the transfer transistor M1_1 via a via hole provided in the interlayer insulating film. The wiring 124 is electrically connected to the floating diffusion region FD2 via a contact hole provided in the interlayer insulating film. The second wiring layer is disposed above the wirings 120, 122, and 124 via an interlayer insulating film (not shown), and includes wirings 132 and 134. The wiring 132 is electrically connected to the gate of the transfer transistor M1_0 via a via hole provided in the interlayer insulating film and the wiring 120. The wiring 134 is electrically connected to the gate of the transfer transistor M1_1 via a via hole provided in the interlayer insulating film and the wiring 122.

[0120] A control signal P_TX_0 from the vertical scanning circuit 20 is supplied to each pixel block 12B via wiring (not shown), and is supplied to the gate of the transfer transistor M1_0 via wiring 132 and wiring 120. A control signal P_TX_1 from the vertical scanning circuit 20 is supplied to each pixel block 12B via wiring (not shown), and is supplied to the gate of the transfer transistor M1_1 via wiring 134 and wiring 122.

[0121] The wiring 124 extends to a region where the photoelectric conversion unit PD_0 is disposed and a region where the photoelectric conversion unit PD_1 is disposed. The wiring 120 is disposed parallel to the wiring 124 in the region where the photoelectric conversion unit PD_0 is disposed. The wiring 132 is provided so as to cover the wirings 120 and 132 via an interlayer insulating film (not shown) and is electrically connected to the wiring 120. The wiring 122 is also disposed parallel to the wiring 124 in the region where the photoelectric conversion unit PD_1 is disposed. The wiring 134 is provided so as to cover the wirings 122 and 134 via an interlayer insulating film (not shown) and is electrically connected to the wiring 124. By configuring the first wiring layer and the second wiring layer in this manner, an MIM-type capacitance constituting the capacitance C2_0 is formed between the wiring 124 and the wiring 120 and wiring 132. An MIM-type capacitance constituting the capacitance C2_1 is also formed between the wiring 124 and the wiring 122 and wiring 134. The capacitor C4 can be configured to include a MOS capacitor formed between a capacitor electrode made of a gate layer and a semiconductor layer, as shown in FIG.

[0122] 12, the portion of the wiring 124 facing the wiring 120 and the portion of the wiring 124 facing the wiring 122 are arranged symmetrically with respect to a line connecting the floating diffusions FD in the horizontal direction. The portion of the wiring 124 facing the wiring 132 and the portion of the wiring 124 facing the wiring 134 are arranged symmetrically with respect to a boundary between adjacent pixels in the column direction, i.e., a line connecting the floating diffusions FD in the horizontal direction. This makes the capacitance values ​​of the capacitors C2_0 and C2_1 the same, thereby making it possible to match the boost amounts and pixel characteristics of the floating diffusions FD of the pixels 12 in the (2n-1)th row and the pixels 12 in the 2nth row.

[0123] As described above, according to this embodiment, a circuit configuration for acquiring an image with a high dynamic range can be realized at low cost in a photoelectric conversion device.

[0124] [Fifth embodiment] A photoelectric conversion system according to a fifth embodiment of the present invention will be described with reference to Fig. 13. Fig. 13 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

[0125] The photoelectric conversion device 100 described in the first to fourth embodiments can be applied to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in the photoelectric conversion system. Fig. 13 illustrates a block diagram of a digital still camera as an example of such systems.

[0126] 13 includes an imaging device 201, a lens 202 that forms an optical image of a subject on the imaging device 201, an aperture 204 that adjusts the amount of light passing through the lens 202, and a barrier 206 that protects the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light on the imaging device 201. The imaging device 201 is the photoelectric conversion device 100 described in any one of the first to fourth embodiments, and converts the optical image formed by the lens 202 into image data.

[0127] The photoelectric conversion system 200 also includes a signal processing unit 208 that processes an output signal output from the imaging device 201. The signal processing unit 208 generates image data from a digital signal output by the imaging device 201. The signal processing unit 208 also performs various corrections and compressions as necessary and outputs the image data. The imaging device 201 may include an AD conversion unit that generates a digital signal to be processed by the signal processing unit 208. The AD conversion unit may be formed in a semiconductor layer (semiconductor substrate) on which the photoelectric conversion unit of the imaging device 201 is formed, or may be formed in a semiconductor layer different from the semiconductor layer on which the photoelectric conversion unit of the imaging device 201 is formed. The signal processing unit 208 may also be formed in the same semiconductor layer as the imaging device 201.

[0128] The photoelectric conversion system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. The photoelectric conversion system 200 further includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading out imaging data from the recording medium 214. The recording medium 214 may be built into the photoelectric conversion system 200 or may be detachable.

[0129] Furthermore, the photoelectric conversion system 200 has an overall control / calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the image capture device 201 and the signal processing unit 208. Here, timing signals and the like may be input from outside, and the photoelectric conversion system 200 only needs to have at least the image capture device 201 and the signal processing unit 208 that processes the output signal output from the image capture device 201.

[0130] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0131] As described above, according to this embodiment, a photoelectric conversion system can be realized to which the photoelectric conversion device 100 according to the first to fourth embodiments is applied.

[0132] [Sixth embodiment] A photoelectric conversion system and a moving object according to a sixth embodiment of the present invention will be described with reference to Fig. 14. Fig. 14 is a diagram showing the configuration of the photoelectric conversion system and a moving object according to this embodiment.

[0133] FIG. 14(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 300 includes an imaging device 310. The imaging device 310 is the photoelectric conversion device 100 described in any one of the first to fourth embodiments. The photoelectric conversion system 300 includes an image processing unit 312 that performs image processing on multiple pieces of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 300. The photoelectric conversion system 300 also includes a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to the object. In other words, the distance information is information related to the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 318 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0134] The photoelectric conversion system 300 is connected to a vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 318. The photoelectric conversion system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the determination result of the collision determination unit 318. For example, if the determination result of the collision determination unit 318 indicates a high possibility of a collision, the control ECU 330 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0135] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 300. Fig. 14(b) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the photoelectric conversion system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0136] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, and control of automatic driving to prevent deviation from a lane. Furthermore, the photoelectric conversion system is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0137] [Seventh embodiment] A device according to a seventh embodiment of the present invention will be described with reference to Fig. 15. Fig. 15 is a block diagram showing a schematic configuration of the device according to this embodiment.

[0138] FIG. 15 is a schematic diagram showing equipment EQP including a photoelectric conversion device APR. The photoelectric conversion device APR has the functions of the photoelectric conversion device 100 of any one of the first to fourth embodiments. All or part of the photoelectric conversion device APR is a semiconductor device IC. The photoelectric conversion device APR of this example can be used, for example, as an image sensor, an AF (Auto Focus) sensor, a photometry sensor, or a distance measurement sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC, each including a photoelectric conversion unit, are arranged in a matrix. The semiconductor device IC can have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0139] The photoelectric conversion device APR may have a structure (chip stacking structure) in which a first semiconductor chip provided with a plurality of photoelectric conversion units and a second semiconductor chip provided with peripheral circuits are stacked. The peripheral circuits in the second semiconductor chip may be column circuits corresponding to the pixel columns of the first semiconductor chip. The peripheral circuits in the second semiconductor chip may also be matrix circuits corresponding to the pixels or pixel blocks of the first semiconductor chip. The first and second semiconductor chips may be connected by through-silicon vias (TSVs), inter-chip wiring formed by direct bonding of a conductor such as copper, connection by microbumps between chips, connection by wire bonding, or the like.

[0140] The photoelectric conversion device APR may include, in addition to the semiconductor device IC, a package PKG that houses the semiconductor device IC. The package PKG may include a base to which the semiconductor device IC is fixed, a cover such as glass that faces the semiconductor device IC, and connecting members such as bonding wires or bumps that connect terminals provided on the base to terminals provided on the semiconductor device IC.

[0141] The equipment EQP may further include at least one of an optical device OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric conversion device APR as a photoelectric conversion device, and is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the photoelectric conversion device APR and is, for example, a semiconductor device such as an ASIC. The processing device PRCS processes signals output from the photoelectric conversion device APR and constitutes an AFE (analog front end) or a DFE (digital front end). The processing device PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application-specific integrated circuit). The display device DSPL is an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving part or a propulsion part such as a motor or an engine. The device EQP displays the signal output from the photoelectric conversion device APR on a display device DSPL and transmits the signal to the outside using a communication device (not shown) provided in the device EQP. For this purpose, the device EQP preferably further includes a memory device MMRY and a processing device PRCS in addition to the memory circuit unit and arithmetic circuit unit provided in the photoelectric conversion device APR.

[0142] The device EQP shown in FIG. 15 can be an electronic device such as an information terminal with a photographing function (e.g., a smartphone or a wearable device) or a camera (e.g., an interchangeable lens camera, a compact camera, a video camera, or a surveillance camera). The mechanical device MCHN in the camera can drive components of the optical device OPT for zooming, focusing, and shutter operation. The device EQP can also be transportation equipment (mobile object) such as a vehicle, a ship, or an aircraft. The device EQP can also be medical equipment such as an endoscope or a CT scanner.

[0143] The mechanical device MCHN in the transportation equipment can be used as a moving device. The device EQP as a transportation equipment is suitable for transporting the photoelectric conversion device APR and for assisting and / or automating driving (piloting) using a photographing function. The processing device PRCS for assisting and / or automating driving (piloting) can perform processing to operate the mechanical device MCHN as a moving device based on information obtained by the photoelectric conversion device APR.

[0144] The photoelectric conversion device APR according to this embodiment can provide high value to its designer, manufacturer, seller, purchaser, and / or user. Therefore, if the photoelectric conversion device APR is installed in a device EQP, the value of the device EQP can also be increased. Therefore, when manufacturing and selling the device EQP, deciding to install the photoelectric conversion device APR according to this embodiment in the device EQP is advantageous in increasing the value of the device EQP.

[0145] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible. For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also an embodiment of the present invention.

[0146] 2, 4, 6, and 11 are merely examples and may be modified as appropriate. For example, in FIGS. 2 and 6, one reset transistor is inserted between the reset transistor M5 and the floating diffusion region FD, but two or more reset transistors may be inserted between the reset transistor M5 and the floating diffusion region FD, as in FIG. 11. In addition, in FIG. 6, two photoelectric conversion units PD are provided to share a microlens, but three or more photoelectric conversion units PD may share one microlens. In addition, in FIG. 11, two pixels share a readout circuit unit, but three or more pixels may share a readout circuit unit.

[0147] In the above embodiment, the capacitors C2, C2A, C2B, C2_0, and C2_1 are configured using first-layer and second-layer metal wiring, but the wiring layers that configure these capacitors can be changed as appropriate. Furthermore, the capacitors C2, C2A, C2B, C2_0, and C2_1 do not necessarily need to be configured using two wiring layers, and may be configured using one wiring layer or three or more wiring layers.

[0148] Furthermore, the imaging systems shown in the fifth and sixth embodiments above are examples of imaging systems to which the photoelectric conversion device of the present invention can be applied, and imaging systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 13 and 14.

[0149] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program.The present invention can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0150] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features.

[0151] The disclosure of the above embodiment includes the following configurations and methods. (Configuration 1) a photoelectric conversion unit that generates charges in response to incident light; a first charge holding unit; a second charge holding unit; a transfer unit that transfers the charge of the photoelectric conversion unit to the first charge holding unit in response to a control signal to a control node; a switch that controls a connection between the first charge holding unit and the second charge holding unit; a capacitance formed by electrostatic coupling between a first wiring connected to the control node and a second wiring arranged alongside the first wiring and connected to the second charge holding unit; an output section that outputs a signal according to the potential of the first charge holding section; A photoelectric conversion device comprising: (Configuration 2) a photoelectric conversion unit that generates charges in response to incident light; a first charge holding unit; a second charge holding unit; a transfer unit that transfers the charge of the photoelectric conversion unit to the first charge holding unit in response to a control signal to a control node; a switch that controls a connection between the first charge holding unit and the second charge holding unit; a MIM or MOM type capacitor connected between the control node and the second charge storage unit; an output section that outputs a signal according to the potential of the first charge holding section; A photoelectric conversion device comprising: (Configuration 3) The capacitance is formed by electrostatic coupling between a first wiring connected to the control node and a second wiring connected to the second charge storage unit. 3. The photoelectric conversion device according to configuration 2. (Configuration 4) a second photoelectric conversion unit that generates charges in response to incident light; a second transfer unit that transfers the charges of the second photoelectric conversion unit to the first charge storage unit. 4. The photoelectric conversion device according to any one of configurations 1 to 3. (Configuration 5) a second capacitance connected between a control node of the second transfer unit and the second charge holding unit; 5. The photoelectric conversion device according to configuration 4. (Configuration 6) The second capacitance is formed by electrostatic coupling between a second wiring connected to the second charge holding unit and a third wiring arranged alongside the second wiring and connected to the control node of the second transfer unit. 6. The photoelectric conversion device according to configuration 5. (Configuration 7) The control circuit further includes a third capacitance formed by electrostatic coupling between a first wiring connected to the control node and the third wiring. 7. The photoelectric conversion device according to configuration 6, (Configuration 8) The second capacitance is a MIM or MOM type capacitance connected between the control node of the second transfer unit and the second charge storage unit. 8. The photoelectric conversion device according to any one of configurations 5 to 7. (Configuration 9) The photoelectric conversion unit and the second photoelectric conversion unit share a microlens. 9. The photoelectric conversion device according to any one of configurations 4 to 8. (Configuration 10) a first pixel including the photoelectric conversion unit and the transfer unit; a second pixel including the second photoelectric conversion unit and the second transfer unit; 9. The photoelectric conversion device according to any one of configurations 5 to 8. (Configuration 11) The capacitor and the second capacitor are arranged symmetrically with respect to the boundary between the first pixel and the second pixel. 11. The photoelectric conversion device according to configuration 10. (Configuration 12) The first pixel and the second pixel share the first charge holding unit, the second charge holding unit, the switch, and the output unit. 12. The photoelectric conversion device according to configuration 10 or 11. (Configuration 13) a third charge holding unit; a second switch that controls a connection between the second charge holding unit and the third charge holding unit. 13. The photoelectric conversion device according to any one of configurations 1 to 12. (Configuration 14) Further, a reset unit is provided for resetting the first charge holding unit to a predetermined potential. 14. The photoelectric conversion device according to any one of configurations 1 to 13. (Configuration 15) The reset unit is connected between a power supply voltage node and the second charge holding unit. 15. The photoelectric conversion device according to configuration 14. (Configuration 16) The reset unit is connected between a power supply voltage node and the first charge holding unit. 15. The photoelectric conversion device according to configuration 14. (Configuration 17) The capacitance value of the capacitor is set so that the potential of the first charge holding unit changes when the transfer unit is driven due to capacitive coupling with the first charge holding unit. 17. The photoelectric conversion device according to any one of configurations 1 to 16. (Configuration 18) The photoelectric conversion device according to any one of configurations 1 to 17, a signal processing device that processes a signal output from the photoelectric conversion device; A photoelectric conversion system comprising: (Configuration 19) A mobile object, The photoelectric conversion device according to any one of configurations 1 to 17, a distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object characterized by having: (Configuration 20) The photoelectric conversion device according to any one of configurations 1 to 17, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on the information obtained by the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; and a storage device that stores information obtained by the photoelectric conversion device; An apparatus characterized by comprising: (Method 1) a first transfer unit that transfers charges from the first photoelectric conversion unit to the first charge holding unit in response to a control signal to a control node; a second transfer unit that transfers charges from the second photoelectric conversion unit to the first charge holding unit in response to a control signal to a control node; a switch that controls connection between the first charge holding unit and the second charge holding unit; a first capacitance formed by electrostatic coupling between a first wiring connected to the control node of the first transfer unit and a second wiring arranged alongside the first wiring and connected to the second charge holding unit; a second capacitance formed by electrostatic coupling between the second wiring and a third wiring arranged alongside the second wiring and connected to the control node of the second transfer unit; and an output unit that outputs a signal according to a potential of the first charge holding unit, By driving the first transfer unit while the switch is in an on state, the potential of the first charge holding unit is changed by capacitive coupling due to the first capacitance, and the charge held by the first photoelectric conversion unit is transferred to the first charge holding unit, and a signal according to the potential of the first charge holding unit is output from the output unit; By driving the first transfer unit and the second transfer unit while the switch is in an on state, the potential of the first charge holding unit is changed by capacitive coupling between the first capacitance and the second capacitance, and the charges held by the first photoelectric conversion unit and the second photoelectric conversion unit are transferred to the first charge holding unit, and a signal according to the potential of the first charge holding unit is output from the output unit. A method for driving a photoelectric conversion device. (Method 2) The length of the period in which the first transfer unit is driven is shorter than the length of the period in which the first transfer unit and the second transfer unit are driven. The method for driving a photoelectric conversion device according to Method 1, [Explanation of symbols]

[0152] C1,C2,C2A,C2B,C2_0,C2_1,C3,C4…Capacity M1, M1A, M1B, M1_0, M1_1...transfer transistors M2: Amplification transistor M3: Select transistor M4, M5, M6...Reset transistors FD, FD2, FD3...Floating diffusion section PD, PDA, PDB, PD_0, PD_1... Photoelectric conversion section 10...Pixel section 12...pixels 12B...pixel block 120, 122, 124, 130, 132, 134... wiring

Claims

1. a photoelectric conversion unit that generates charges in response to incident light; a first charge holding unit; a second charge holding unit; a transfer unit that transfers the charges of the photoelectric conversion unit to the first charge holding unit in response to a control signal to a control node; a switch that controls a connection between the first charge holding unit and the second charge holding unit; a capacitance formed by electrostatic coupling between a first wiring connected to the control node and a second wiring arranged alongside the first wiring and connected to the second charge holding unit; an output section that outputs a signal corresponding to the potential of the first charge holding section; A photoelectric conversion device comprising:

2. a photoelectric conversion unit that generates charges in response to incident light; a first charge holding unit; a second charge holding unit; a transfer unit that transfers the charges of the photoelectric conversion unit to the first charge holding unit in response to a control signal to a control node; a switch that controls a connection between the first charge holding unit and the second charge holding unit; a MIM or MOM type capacitor connected between the control node and the second charge storage unit; an output section that outputs a signal corresponding to the potential of the first charge holding section; A photoelectric conversion device comprising:

3. The capacitance is formed by electrostatic coupling between a first wiring connected to the control node and a second wiring connected to the second charge holding unit.

3. The photoelectric conversion device according to claim 2.

4. a second photoelectric conversion unit that generates charges in response to incident light; a second transfer unit that transfers the charges of the second photoelectric conversion unit to the first charge storage unit.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

5. a second capacitance connected between a control node of the second transfer unit and the second charge holding unit; 5. The photoelectric conversion device according to claim 4.

6. The second capacitance is formed by electrostatic coupling between a second wiring connected to the second charge holding unit and a third wiring arranged alongside the second wiring and connected to the control node of the second transfer unit.

6. The photoelectric conversion device according to claim 5.

7. a third capacitance formed by electrostatic coupling between a first wiring connected to the control node and the third wiring; 7. The photoelectric conversion device according to claim 6.

8. The second capacitance is an MIM or MOM type capacitance connected between the control node of the second transfer unit and the second charge holding unit.

6. The photoelectric conversion device according to claim 5.

9. The photoelectric conversion unit and the second photoelectric conversion unit share a microlens.

5. The photoelectric conversion device according to claim 4.

10. a first pixel including the photoelectric conversion unit and the transfer unit; a second pixel including the second photoelectric conversion unit and the second transfer unit; 6. The photoelectric conversion device according to claim 5.

11. The capacitor and the second capacitor are arranged symmetrically with respect to the boundary between the first pixel and the second pixel.

11. The photoelectric conversion device according to claim 10.

12. The first pixel and the second pixel share the first charge holding unit, the second charge holding unit, the switch, and the output unit.

11. The photoelectric conversion device according to claim 10.

13. a third charge holding portion; a second switch that controls a connection between the second charge holding unit and the third charge holding unit.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

14. Further, a reset unit is provided for resetting the first charge holding unit to a predetermined potential.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

15. The reset unit is connected between a power supply voltage node and the second charge holding unit.

15. The photoelectric conversion device according to claim 14.

16. The reset unit is connected between a power supply voltage node and the first charge holding unit.

15. The photoelectric conversion device according to claim 14.

17. The capacitance value of the capacitor is set so that the potential of the first charge holding unit changes when the transfer unit is driven due to capacitive coupling with the first charge holding unit.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

18. The photoelectric conversion device according to any one of claims 1 to 3, a signal processing device that processes a signal output from the photoelectric conversion device; A photoelectric conversion system comprising:

19. A mobile object, The photoelectric conversion device according to any one of claims 1 to 3, a distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object characterized by having:

20. The photoelectric conversion device according to any one of claims 1 to 3, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on the information obtained by the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; and a storage device that stores information obtained by the photoelectric conversion device; An apparatus characterized by comprising:

21. a first transfer unit that transfers charges from the first photoelectric conversion unit to the first charge holding unit in response to a control signal to a control node; a second transfer unit that transfers charges from the second photoelectric conversion unit to the first charge holding unit in response to a control signal to a control node; a switch that controls connection between the first charge holding unit and the second charge holding unit; a first capacitance formed by electrostatic coupling between a first wiring connected to the control node of the first transfer unit and a second wiring arranged alongside the first wiring and connected to the second charge holding unit; a second capacitance formed by electrostatic coupling between the second wiring and a third wiring arranged alongside the second wiring and connected to the control node of the second transfer unit; and an output unit that outputs a signal according to a potential of the first charge holding unit, By driving the first transfer unit while the switch is in an on state, the potential of the first charge holding unit is changed by capacitive coupling due to the first capacitance, and the charge held by the first photoelectric conversion unit is transferred to the first charge holding unit, and a signal according to the potential of the first charge holding unit is output from the output unit; By driving the first transfer unit and the second transfer unit while the switch is in an on state, the potential of the first charge holding unit is changed by capacitive coupling between the first capacitance and the second capacitance, and the charges held by the first photoelectric conversion unit and the second photoelectric conversion unit are transferred to the first charge holding unit, and a signal according to the potential of the first charge holding unit is output from the output unit. A method for driving a photoelectric conversion device.

22. The length of the period in which the first transfer unit is driven is shorter than the length of the period in which the first transfer unit and the second transfer unit are driven.

22. The method for driving a photoelectric conversion device according to claim 21.

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