Doping activation and ohmic contact formation in sic electronic devices and sic electronic devices

Abstract

To provide a method of manufacturing an SiC-based electronic device (50).SOLUTION: The method comprising the steps of implanting a P-type dopant species in a front side (52a) of a solid body (52) of SiC having N-type conductivity to form an implanted region (59 ') starting from the front side (52a) and having a depth extending into the solid body and a top surface coplanar with the front side (52a), and forming one or more carbon-rich layers, such as graphene and / or graphite layers, in the implanted region (59 '); Simultaneously generating a laser beam (82) directed towards the implantation zone (59 ') so as to cause heating of the implantation zone (59 ') to a temperature of between 1500 °C. and 2600 °C. in order to activate the dopant species of P type.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a SiC electronic device and a SiC electronic device so manufactured. In particular, the present invention relates to a method for activating doping in SiC electronic devices. and simultaneously forming an ohmic contact. [Background technology]

[0002] As is known, wide band gaps, especially band gaps higher than 1.1 eV, Energy value Eg and low on-state resistance (R ON ), high values ​​of thermal conductivity, and high operating frequencies Semiconductor materials exhibiting high saturation of charge carriers and high saturation of charge carriers are particularly useful in diodes for power applications. These properties make it ideal for the manufacture of electronic components such as silicon dioxide and transistors. Materials that are manufactured using silicon dioxide and are designed for use in the manufacture of electronic components are In particular, silicon carbide is available in its different polytypes (e.g. For example, 3C-SiC, 4H-SiC, and 6H-SiC, the above-mentioned properties are , and is more preferable than silicon.

[0003] Electronic devices built on silicon carbide substrates are similar to those built on silicon substrates. Compared to conventional devices, it has low output resistance in conduction, low leakage current, high operating temperature, and high dynamic range. In particular, SiC Schottky diodes offer many advantages, such as higher operating frequencies. The SiC electronics devices exhibit excellent switching performance, which makes them suitable for high-frequency applications. In the current application, it is particularly suitable for electrical properties and long-term reliability of the device. It imposes conditions on gender.

[0004] Figure 1 shows a cross section in the X, Y, and Z (three-axis) Cartesian coordinate system of a known type 1 shows a combined PIN Schottky (MPS) device 1.

[0005] The MPS device 1 has a surface 3a opposite to a surface 3b and has a thickness of about 350 μm. a substrate 3 of N-type SiC having a thickness and a first doping concentration; C having a second doping concentration lower than the first doping concentration; The drill extends over the surface 3a of the substrate 3 and has a thickness between 5 and 15 μm. a soft layer 2 (grown epitaxially) and a thin film extending over the surface 3b of the substrate 3; ohmic contact region 6 (made of, for example, nickel silicide) and A cathode metallization 16 extending over the contact region 6 and the drift anode metallization 8 extending over the upper surface 2a of the drift layer 2; 2 and each of which is connected to a respective implanted region 9' of P type and an ohmic contact of metal material. Multi-junction barrier (JB) elements 9 in the drift layer 2, including back contacts 9 and an end termination region or protection region, which is a P-type implant region, which surrounds the JB element 9 in a discontinuous manner. It includes a protection ring 10 (this is optional) and

[0006] The Schottky diode 12 is located between the drift layer 2 and the anode metallization 8. In particular, the Schottky junction (between the semiconductor and the metal) is formed at the interface between the anode and the by portions of the drift layer 2 in direct electrical contact with respective portions of the talization 8. It is formed by

[0007] The area of ​​MPS1 that includes JB element 9 and Schottky diode 12 (i.e., the protection link The area enclosed within ring 10 is the active area 4 of the MPS device 1.

[0008] The steps for fabricating the MPS device 1 of FIG. 1 include implantation region 9′ and edge termination region 10. A dopant species (e.g., boron or aluminum) having a second conductivity type (P) is added to form a The method includes the step of masked implantation of dopants (aluminum). A thermal annealing step is performed to allow diffusion and activation of the oxidizing species. Annealing can be performed at temperatures higher than 1600°C (e.g., 1700°C and 1900°C). The reaction is carried out at a temperature between 100°C and 150°C, and in some cases even higher. After treatment, implanted region 9' has a size of about 1×10 17 〜1×10 20 atoms / cm 3 Consists of between It has a concentration of a dopant species.

[0009] Then steps are carried out to perform the formation of ohmic contacts 9 ″, In particular, a silicon oxide mask is used to cover the surface area of ​​the drift layer 2 other than the implantation region 9′. The deposition of nickel is carried out exclusively in the implanted region 9' using a high temperature (1 at temperatures between 900°C and 1000°C for a time period of 10 minutes to 120 minutes. Subsequent thermal annealing leads to a chemical reaction between the deposited nickel and the silicon of the drift layer 2. This allows the formation of nickel silicide ohmic contacts 9″. The deposited nickel reacts with the surface material of the drift layer 2 to form Ni2Si (i.e., ohmic contact). The nickel in contact with the oxide of the mask does not react. A step is then performed to remove the unreacted metal and the mask.

[0010] The steps described above are first for doping activation and then for ohmic contact. It requires several thermal annealing steps for ohmic contact formation. The metal deposition step, which reacts with the drift layer 2 to form the tact 9″, is performed in the implanted region 9 It is critical that an optimum match be achieved between the ' and the deposited metal. In fact, the contact and the shielding with metals useful for forming ohmic contacts 9" are Possible mismatch with the area of ​​the Schottky diode 12 can cause device malfunction. In fact, ohmic contacts formed on SiC epitaxy have low resistance and It is no longer a diode, or else a shot with an extremely low barrier height. In either case, the resulting key contact The resulting device becomes unusable due to high leakage in reverse bias. Summary of the Invention [Problem to be solved by the invention]

[0011] The object of the present invention is to provide an electronic device that can eliminate the drawbacks of the above-mentioned prior art. The present invention provides a method for manufacturing a SiC electronic device and a corresponding SiC electronic device. [Means for solving the problem]

[0012] According to the invention, a method for manufacturing an electronic device and a corresponding SiC electronic device are provided as claimed in the claims. For a better understanding of the present invention, reference is made to the accompanying drawings, in which: A preferred embodiment thereof will now be described, purely by way of non-limiting example, in accordance with the present invention. be. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a schematic cross-sectional view of an MPS device according to one known embodiment. [Figure 2] 1 is a schematic cross-sectional view of an MPS device according to one embodiment of the present invention. [Figure 3] 3A-3C are schematic cross-sectional views illustrating certain steps in fabricating the device of FIG. 2 in accordance with one embodiment of the present invention. [Figure 4] 3A-3C are schematic cross-sectional views illustrating certain steps in fabricating the device of FIG. 2 in accordance with one embodiment of the present invention. [Figure 5] 3A-3C are schematic cross-sectional views illustrating certain steps in fabricating the device of FIG. 2 in accordance with one embodiment of the present invention. [Figure 6] 3A-3C are schematic cross-sectional views illustrating certain steps in fabricating the device of FIG. 2 in accordance with one embodiment of the present invention. [Figure 7] 4 is a graph illustrating the voltage-current curve of a device made in accordance with the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0014] The present invention will be described with particular reference to a merged PIN Schottky (MPS) device, but the following As will be apparent from the description, the present invention generally applies to any SiC-based device, such as a MOSFET. It is applicable to electronic devices.

[0015] FIG. 2 illustrates an MPS device 50 according to one aspect of the present invention, which is mounted on an X, Y, and Z (three-axis) curvilinear axis. The cross section is shown in a cyan coordinate system.

[0016] The MPS device 50 has a first doping concentration and a surface 53b opposite the surface 53. a is provided and is between 50 μm and 350 μm, more particularly between 160 μm and 200 μm, for example, made of N-type SiC having a thickness of 180 μm. a substrate 53; and a substrate having a second doping concentration lower than the first doping concentration. It extends over the surface 53a of the plate 53 and has a thickness of, for example, between 5 μm and 15 μm. The drift layer 52 (epitaxially formed) is made of N-type SiC. ohmic contact regions extending onto the surface 53b of the substrate 53; The layer 56 (for example, made of nickel silicide) and the ohmic contact The Ti / NiV / Ag or Ti / NiV / Au alloy extends over the Ti / NiV / Ag alloy region 56. a cathode metallization 57 formed on the upper surface 52a of the drift layer 52; It is made of, for example, Ti / AlSiCu or Ni / AlSiCu. Anode metallization 58 and an anode for protecting the anode metallization 58 a passivation layer 69 on the metallization 58; and an upper surface 55 of the drift layer 52. 2a and each have a respective P-type implanted region 59' and ohmic contact 59" and a multi-junction barrier (JB) element 59 in the drift layer 52 including: An end termination region or guard ring 6, which is a P-type implanted region completely surrounding element 89. 0 (optional) is included.

[0017] Laterally with respect to the implantation region 59', the drift layer 52 and the anode metallization 58 At the interface between the two, one or more Schottky diodes 62 are formed. , a Schottky junction (semiconductor-metal type) is formed on the anode metallization 58 and the drift layer 52 in direct electrical contact with the respective portions of the It has been done.

[0018] The region of the MPS device 50 that includes the JB element 59 and the Schottky diode 62 (i.e. , the area contained within the guard ring 60) is the active area 54 of the MPS device 50. .

[0019] According to one aspect of the invention, each ohmic contact 59" is made of, for example, graphite. One or more carbon-rich layers including graphene layers or graphene multilayers More specifically, each ohmic contact 59″ is formed by a layer including a In the SiC substrate, silicon atoms are separated based on the phase separation between silicon atoms and carbon atoms. The number of carbon atoms is predominant (e.g., at least two times higher, especially two to The SiC amorphous layer has a resistance of 100 times higher than that of the ohmic contacts. The contact 59″ is a carbon cluster ( For example, a layer containing a graphite layer may be provided. The formation of 59" is due to the thermal decomposition of silicon carbide as a result of the manufacturing process exemplified below. This is due to the solution.

[0020] According to a further aspect of the invention, the ohmic contact 59" is , self-aligned with implanted region 59' (i.e., in plan view in plane XY, ohmic Contact 59" has the same shape and extent as implanted region 59'. , the electrical contact between the anode metallization 58 and the implanted region 59' is exclusively ohmic. It occurs through contact 59”.

[0021] Furthermore, in accordance with a further aspect of the present invention, ohmic contact 59" extends beyond surface 52a. ohmic contact 59" does not extend along the Z axis, i.e., ohmic contact 59" does not extend along surface 52a. having an upper surface 52a that is coplanar (i.e., aligned along axis X); and it is between 1 nanometer and tens of nanometers measured starting from the surface 52a. within the ohmic contact 59' over a depth (e.g., between 1 nm and 20 nm). Extends in depth (along Z).

[0022] The step of forming ohmic contacts 59″ is particularly relevant to the steps of manufacturing MPS device 50. This will be explained below with reference to the accompanying drawings (FIGS. 3 to 6).

[0023] Referring to FIG. 3, a SiC substrate 53 (particularly, 4H—SiC, however, there are limitations to these) Other polycrystalline silicon such as, but not limited to, 2H-SiC, 3C-SiC, and 6H-SiC A wafer 100 including a silicon wafer (a silicon wafer type can also be used) is prepared.

[0024] The substrate 53 has a first conductivity type (in this example, N-type doping) and a surface The substrate 53 has a side surface 53a and a back surface 53b, which are opposite to each other along the Z axis. The substrate 53 is 1×10 19 and 1×10 22 atoms / cm 3 Doping between It has a high concentration.

[0025] The front side of the wafer 100 corresponds to the front surface 53a, and the back side of the wafer 100 corresponds to the back surface 53b. The resistivity of the substrate 30 is, for example, 2 mΩ·cm and 40 mΩ·cm. Between cm.

[0026] For example, silicon carbide is grown on the front surface 53a of the substrate 53 by epitaxial growth. A drift layer 52 of the semiconductor layer is formed, and the drift layer 52 has a first conductivity type (N). and has a lower doping concentration than that of the substrate 53, e.g., 1×10 14 ~5×1 0 16 atoms / cm 3 The drift layer 52 is made of SiC, particularly 4H—SiC, or It is composed of 2H, 6H, 3C, or 15R polytypes. It is also possible.

[0027] Drift layer 52 has a thickness defined between top side 52a and bottom side 52b. (The bottom side 52b is in direct contact with the front surface 53a of the substrate 53).

[0028] Then (FIG. 4), a hard mask 70 is deposited on the upper side 52a of the drift layer 52, e.g. Deposit photoresist, or TEOS, or another material designed for that purpose. The hard mask 70 is formed by depositing a thin film of SiO 2 to a thickness of between 0.5 μm and 2 μm. In any case, the thickness is such that it shields the implant, as will be described later with reference again to FIG. The hard mask 70 will be used to form the active layers of the MPS device 50 in a later step. ) area 54 extends into the area of ​​wafer 100 in which it is to be formed.

[0029] In a top plan view in plane XY, the hard mask 70 is 6. The upper side 52a of the drift layer 52 is covered with the upper side 52a of the drift layer 52, which forms the gate 62. The upper side 52 of the drift layer 52 that will form the implanted region 59' identified by reference The area a is left exposed.

[0030] Next, the hard mask 70 is used to form a second conductivity type (here, P-type conductivity). An implantation step of a dopant species (e.g., boron or aluminum) is carried out (the implantation During the step of FIG. 4, the guard ring 60 is also , if present, is formed.

[0031] In one embodiment given by way of example, the implantation step of FIG. 18 atom Number / cm 3 To form implanted region 59' having a higher doping concentration than 1×10 12 atoms / cm 3 〜1×10 15 atoms / cm 3 Between doses and 30k one of the dopant species having the second conductivity type at an implantation energy between 400 eV and 400 keV, or Therefore, the implanted area is measured from surface 52a to surface 52b. It is formed to a depth of between 0.4 μm and 1 μm.

[0032] 5, the mask 70 is removed, and in FIG. 6, one or more of the above-mentioned The implantation of further carbon-rich layers (e.g., graphene and / or graphite layers) A heat treatment is generated at surface 52a that makes it suitable for generation in region 59'. .

[0033] For that purpose, the surface 52a (particularly the implanted area) is heated to a temperature of about 1500°C to 2600°C. a laser source configured to generate a beam 82 that locally heats a region 59' The source 80 is used. Given the maximum depth of the implanted region 59', This ensures that the temperature is within the above range even at the maximum depth (e.g., 1 μm) reached by the A temperature of about 2000° C. at the level of the surface 52 a is sufficient for this purpose.

[0034] This temperature is maintained exclusively in implanted region 59', and not at surface 52a where implanted region 59' is absent. In this case, the formation of a carbon-rich ohmic contact compound is favorable. This effect is of a known type and is described, for example, in Maxim e G. Lemitre, "Semiconductors via Ion Implantation and Pulsed Laser Annealing" Low-temperature, site-selective graphitization of SiC e selective graphitization of SiC via io n implantation and pulsed laser annealin g), APPLIED PHYSICS LETT ERS) 100, 193105 (2012).

[0035] In one embodiment, the conversion of a portion of implanted region 59' to an ohmic contact 59" is performed by: This is generated by moving the laser 80 appropriately to heat the entire wafer 100 .

[0036] In a further embodiment, an ohmic contact 59" on the surface portion of implanted region 59' The conversion occurs by heating the useful surface of the wafer 100. The "surface" includes, for example, implanted region 59' outwardly bounded by end termination region 10. The surface portion of the drift layer 52 is referred to as the useful surface, which is the surface of the wafer 100. may not correspond to the whole (for example, in that they do not participate in the transfer of charge). During use of the MPS device 50, the lateral wafer with respect to the active area 54 of no interest is (Excluding a certain portion of the 100 possibilities).

[0037] According to a further embodiment, the area transparent to the beam 82 (i.e., the beam 82 passes through) areas) and areas that are opaque to the beam 82 (i.e., the beam 82 does not pass through or is below The radiation is transmitted in an attenuated manner so as not to cause significant heating of the portion of the wafer 100 that is present therein. A mask having a region through which the mask passes is placed above (in contact with) the surface 52a. The transparent area of ​​the mask can be The implanted regions 59' are aligned to allow for the formation of respective ohmic contacts 59''.

[0038] Regardless of the embodiment employed, implanted region 59' (particularly, about 1×10 17 atoms / cm 3 〜1×10 20 atoms / cm 3 The doping is performed to obtain a concentration of the dopant species between Activation) and ohmic contacts 59" to each implanted region are simultaneously formed. Furthermore, the ohmic contacts are formed exclusively in implanted region 59', even in the absence of a mask. Since the implanted regions 59' are formed in parallel, there is no self-contained contact between the implanted regions 59' and the respective ohmic contacts 59''. There is a match.

[0039] In the implanted region 59', a localized surface increase in temperature This results in the formation of implanted regions 59', while laterally with respect to implanted regions 59', this effect is not significant. The conversion of p-type SiC to graphene occurs between 1200°C and 2600°C, and more detailed In particular, it occurs at temperatures above 1600° C. According to the invention, these temperatures are This is achieved in the surface area of ​​59' (a few nanometers, e.g., 1 to 20 nm). At greater depths, the temperature converts silicon carbide into carbon-rich layers (graphene and and / or graphite layers) no longer occurs. The formation of the ohmic contact 59" is self-limiting. The contacts 59" do not extend through the thickness of each implanted region, but only on its surface. It is at the level.

[0040] The laser 80 is, for example, a UV excimer laser. Other types of lasers may also be used. It is also possible to use lasers with wavelengths in the visible light region.

[0041] Optimized for the purposes of the present invention, i.e., the graph in the injection region 59' The shape and activation parameters of the laser 80 that allow the formation of ohmic contacts The data is as follows:

[0042] The wavelength is between 290 and 370 nm, in particular 310 nm.

[0043] The pulse duration is between 100 ns and 300 ns, in particular 160 ns.

[0044] The number of pulses is between 1 and 10, in particular 4.

[0045] Energy density is (2) 1.6 to 4 J / cm 3 Especially (3) 2.6 J / cm 3 in (considered at the level of surface 52a).

[0046] The temperature is between 1400° C. and 2600° C., in particular 1800° C. (at the level of the surface 52a) (Discussed in).

[0047] The spot area of ​​the beam 82 at the level of the surface 52a is, for example, 0.7 to 1.5 cm 2 It is between.

[0048] To cover the entire wafer 100 or a sub-area of ​​the wafer 100 to be heated, the planes XY One or more scans of the laser 80 are performed (e.g., relative to each other and axially) multiple scans parallel to the X and / or Y axis).

[0049] However, as has been discovered by the present invention, with the above parameters, M The desired electrical behavior of the MPS device 50 is achieved. FIG. 7 illustrates in this regard the MPS device 50 Experimental data on the change in conduction current as a function of the voltage applied between the anode and cathode of Curve S1 shows the electrical measurements of the PiN diode before laser treatment. while curve S2 is for the ohmic contact after laser treatment. These curves S1 and S2 relate to electrical measurements of the PiN diode. The S2 profile confirms that the expected behavior is achieved.

[0050] In view of the characteristics of the present invention obtained based on this disclosure, the advantages achieved by the present invention are: It's obvious.

[0051] Although specific embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments. The present invention should not be limited to the examples, and various modifications may be made without departing from the technical scope of the present invention. Of course, various modifications and alterations are possible. In particular, as already mentioned above, The invention is not limited to forming ohmic contacts in MPS devices, but Tokey diodes, JBS diodes, MOSFETs, IGBTs, JFETs, DMOSs, etc. This also extends to ohmic contact formation in typical vertical conduction electron devices.

Claims

1. A method for manufacturing a SiC-based electronic device (50), comprising: The implanted region (59') has an N-type conductivity type and a P-type dopant species. a front side (52a) of a solid body (52) of SiC, the implanted region being located on the front side of the solid body; Starting from the side portion (52a), it extends to a certain depth into the solid body and The front side portion (52a) has an upper surface that is flush with the front side portion (52a). Injection is then performed. In the implanted region (59') one or more carbon-rich layers, in particular graphene and / or graphite layer, and simultaneously activate the P-type dopant species. heating the implanted region (59') to a temperature between 1500°C and 2600°C to induce a laser beam (82) directed toward the implanted region (59') to generate To live, A way of embracing that.

2. The laser beam (82) wavelengths between 290 nm and 370 nm, in particular 310 nm, a pulse duration between 100 and 300 ns, in particular 160 ns, Between 1 and 10 pulses, in particular 4 pulses, 1.6 to 4 J / cm ２ Between ２ The energy density of 2. The method of claim 1, wherein the parameter is generated under the following conditions:

3. Heating the implanted area (59') causes the implanted area (59') to expand in thickness along the direction (Z).

3. The method according to claim 1, wherein the method is carried out over the entire length of the substrate.

4. Forming the ohmic contact region (59") is performed by: Initiating the formation of the one or more carbon-rich layers within the implanted region (59').

4. The method of any one of claims 1 to 3, comprising:

5. The ohmic contact region (59") coincides with the upper surface of the implanted region (59').

5. The method of claim 4, wherein the substrate has an upper surface.

6. The ohmic contact region (59") has a thickness between 1 nm and 20 nm.

6. The method according to any one of claims 1 to 5, wherein

7. The material of the solid body is selected from the group consisting of 4H-SiC, 6H-SiC, 3C-SiC, and 15R-SiC.

7. The method according to claim 1, wherein the method is one of the following:

8. The electronic device (50) is a combined PiN Schottky diode, a Schottky diode one of a diode, a JBS diode, a MOSFET, an IGBT, a JFET, and a DMOS 8. The method according to any one of claims 1 to 7, wherein

9. The electronic device (50) is a combined PiN Schottky (MPS) diode, The law, An N-type SiC substrate having its own front side and its own back side opposite each other. A substrate is prepared, and an N-type SiC drift layer (52) is epitaxially grown on the front side of the substrate. forming the solid body by selectively growing the solid body; A junction barrier (JB) diode is formed with the injection region (59') and the drift layer (5 2) and the ohmic contact region (59") to form a Schottky diode. and electrically contacts the implantation region (59') via a first electrical terminal (58) that is in direct electrical contact with the drift layer (52) in the lateral direction; ) forming a forming a second electrical terminal (57) on the back side of the substrate; 9. The method of claim 8, comprising:

10. In a SiC-based electronic device (50), a solid body (52) of SiC having N-type conductivity; an implanted region (59') in the front side (52a) of the solid body (52), starting from the front side (52a) into the solid body, a top surface coplanar with the obverse side (52a) of the solid body; the injection region (59'), an ohmic contact region (59") extending into said implanted region (59'), one or more carbon-rich layers, in particular graphene and / or graphite layers, the ohmic contact region (59") containing the An electronic device having:

11. The ohmic contact region (59") extends from the front side (52a) of the solid body. the one or more carbon-rich layers extending exclusively within the implanted region beginning at 11. The electronic device according to claim 10.

12. The ohmic contact region (59") coincides with the upper surface of the implanted region (59').

12. The electronic device of claim 11, having a top surface thereof.

13. The ohmic contact region (59") has a thickness between 1 nm and 20 nm.

13. The electronic device according to claim 10, wherein:

14. The material of the solid body is selected from the group consisting of 4H-SiC, 6H-SiC, 3C-SiC, and 15R-SiC.

14. The electronic device according to claim 10, wherein the electronic device is one of the above.

15. Combined PiN Schottky diode, Schottky diode, JBS diode, Selected from MOSFET, IGBT, JFET, and DMOS.

15. An electronic device according to any one of claims 10 to 14.

16. A type of integrated PiN Schottky (MPS) diode, the solid body of which is an N-type SiC substrate having its own front and back sides opposite each other; a drift layer (52) of N-type SiC on the front side of the substrate, and further comprising: A junction barrier (JB) diode is formed with the injection region (59') and the drift layer (5 2) and the ohmic contact region (59") to form a Schottky diode. and electrically contacts the implantation region (59') through the implantation region (59'). a first electrical contact directly with the drift layer (52) laterally with respect to the first electrical contact; a target terminal (58), and a second electrical terminal (57) on the back side of the substrate; 15. An electronic device according to any one of claims 10 to 14, comprising:

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