Wide bandgap semiconductor device with sensor element

Abstract

To achieve accurate measurement of one or a plurality of operation parameters by a compact solution.SOLUTION: Shielding techniques are used to provide embedded sensor elements, such as temperature sensing elements, on wide bandgap power semiconductor devices. The semiconductor device may include a drift layer and an embedded sensor element. The drift layer may be a wide bandgap semiconductor material. A shielding structure is provided in the drift layer below the embedded sensor element. The embedded sensor element may be provided between contacts that are in electrical contact with the shielding well. The distance between the contacts can be minimized. Noise reduction wells can be provided between the contacts to further isolate the embedded sensor elements from parasitic signals.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] This application claims priority to U.S. Patent Application No. 17 / 201,468, filed March 15, 2021.

[0002] The present disclosure relates to semiconductor devices, and more particularly to wide bandgap semiconductor devices, including sensor elements. [Background technology]

[0003] Wide-bandgap semiconductor devices are often used in power applications where the semiconductor device handles high voltages and / or currents. It is often desirable to monitor one or more operating conditions of these wide-bandgap power semiconductor devices, such as their temperature or current, in order to adjust one or more control signals sent to them. For example, if the device's temperature rises above a threshold, it may be desirable to adjust the device's switching speed or power it down to avoid damaging the device. While embedded sensor elements integrated into the device die are preferred, incorporating sensor elements into wide-bandgap power semiconductor devices presents several technical challenges that must be overcome. Therefore, current solutions rely on separate sensor elements placed in close proximity to the semiconductor die they are measuring. This results in both reduced accuracy and increased area. Therefore, there is a need for wide-bandgap power semiconductor devices with one or more embedded sensor elements. Summary of the Invention [Means for solving the problem]

[0004] In one embodiment, a semiconductor device includes a drift layer and a buried sensor element. The drift layer includes a wide bandgap semiconductor material. By including a buried sensor element on the wide bandgap semiconductor device, accurate measurement of one or more operating parameters can be achieved in a compact solution.

[0005] In one embodiment, the buried sensor element is a temperature-sensing element such as a diode. The semiconductor device may further include an insulating layer between the buried sensor element and the drift layer. To provide further shielding, a shielding well having a doping type opposite that of the drift layer may be provided in the drift layer below the buried sensor element. The shielding well may further isolate the buried sensor element from parasitic signals. The buried sensor element may further be provided between a first contact and a second contact, both of which are in electrical contact with the shielding well and coupled to a fixed potential, such as ground. Coupling the shielding well to the fixed potential may further isolate the buried sensor element from parasitic signals. The first contact and the second contact may be electrically coupled to the shielding well via a first contact well and a second contact well, respectively, which have the same doping type as the shielding well and a higher doping concentration than the shielding well. The shielding well may further include a noise-reduction well. The noise-reduction well may have a doping type opposite that of the shielding well. The noise reduction well reduces resistance at the surface of the drift layer below the embedded sensor element, thereby further isolating the embedded sensor element from parasitic signals. The first contact and the second contact may be in electrical contact with the noise reduction well. In yet another embodiment, a functional layer and an additional insulating layer are provided between the embedded sensor element and the drift layer. The functional layer and the additional insulating layer may further isolate the embedded sensor element from parasitic signals. To further improve isolation of the embedded sensor element from parasitic signals, the distance between the first contact well and the second contact well may be minimized. In various embodiments, the distance between the first contact well and the second contact well is less than 200 μm, less than 100 μm, less than 50 μm, and less than 25 μm.

[0006] In one embodiment, a method for fabricating a semiconductor device includes providing a drift layer and providing an embedded sensor element. The drift layer may include a wide bandgap semiconductor material. By including an embedded sensor element on the wide bandgap semiconductor device, accurate measurement of one or more operating parameters can be achieved in a compact solution.

[0007] In one embodiment, the buried sensor element is a temperature-sensing element such as a diode. The method may further include providing an insulating layer between the buried sensor element and the drift layer. For further shielding, a shielding well having a doping type opposite that of the drift layer may be provided in the drift layer below the buried sensor element. The shielding well can further isolate the buried sensor element from parasitic signals. Furthermore, the buried sensor element may be provided between a first contact and a second contact, both of which are in electrical contact with the shielding well and coupled to a fixed potential, such as ground. Coupling the shielding well to the fixed potential can further isolate the buried sensor element from parasitic signals. The first contact and the second contact may be electrically coupled to the shielding well via a first contact well and a second contact well, respectively, which have the same doping type as the shielding well and a higher doping concentration than the shielding well. A noise-reduction well may further be provided in the shielding well. The noise-reduction well may have a doping type opposite that of the shielding well. The noise reduction well reduces resistance at the surface of the drift layer below the embedded sensor element, thereby further isolating the embedded sensor element from parasitic signals. The first contact and the second contact may be in electrical contact with the noise reduction well. In yet another embodiment, a functional layer and an additional insulating layer are provided between the embedded sensor element and the drift layer. The functional layer and the additional insulating layer may further isolate the embedded sensor element from parasitic signals. To further improve isolation of the embedded sensor element from parasitic signals, the distance between the first contact well and the second contact well may be minimized. In various embodiments, the distance between the first contact well and the second contact well is less than 200 μm, less than 100 μm, less than 50 μm, and less than 25 μm.

[0008] In other aspects, any of the aforementioned aspects individually or together, and / or various separate aspects and features described herein may be combined to further advantage. Any of the various features and elements as disclosed herein may be combined with one or more other disclosed features and elements, unless otherwise indicated herein.

[0009] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings.

[0010] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view of a semiconductor die according to one embodiment of the present disclosure. [Figure 2] 1 is a cross-sectional view of a semiconductor die according to one embodiment of the present disclosure. [Figure 3] 1 is a cross-sectional view of a semiconductor die according to one embodiment of the present disclosure. [Figure 4] 1 is a cross-sectional view of a semiconductor die according to one embodiment of the present disclosure. [Figure 5] 1 is a cross-sectional view of a semiconductor die according to one embodiment of the present disclosure. [Figure 6] FIG. 1 is a top-down view of an embedded sensor element according to one embodiment of the present disclosure. [Figure 7] FIG. 1 is a top-down view of an embedded sensor element according to one embodiment of the present disclosure. [Figure 8] FIG. 1 is a top-down view of an embedded sensor element according to one embodiment of the present disclosure. [Figure 9] FIG. 2 is a top-down view of a portion of a shielding structure for an embedded sensor element according to one embodiment of the present disclosure. [Figure 10]FIG. 2 is a top-down view of a portion of a shielding structure for an embedded sensor element according to one embodiment of the present disclosure. [Figure 11A] 1 is a cross-sectional view of a functional component according to one embodiment of the present disclosure. [Figure 11B] FIG. 1 is a top-down view of functional components according to one embodiment of the present disclosure. [Figure 12] FIG. 1 is a flow diagram illustrating a method for manufacturing a semiconductor die according to one embodiment of the present disclosure. [Figure 13] 1 is a cross-sectional view of an embedded sensor element according to one embodiment of the present disclosure. [Figure 14] FIG. 1 is a top-down view of a transistor semiconductor die according to one embodiment of the present disclosure. [Figure 15] FIG. 1 is a top-down view of a transistor semiconductor die according to one embodiment of the present disclosure. [Figure 16] FIG. 1 is a top-down view of a transistor semiconductor die according to one embodiment of the present disclosure. [Figure 17] FIG. 1 is a top-down view of a transistor semiconductor die according to one embodiment of the present disclosure. [Figure 18] 1 is a cross-sectional view of a transistor semiconductor die according to one embodiment of the present disclosure. [Figure 19] 1 is a cross-sectional view of a transistor semiconductor die according to one embodiment of the present disclosure. [Figure 20A] 1 is a graph illustrating the performance of a transistor semiconductor die according to various embodiments of the present disclosure. [Figure 20B] 1 is a graph illustrating the performance of a transistor semiconductor die according to various embodiments of the present disclosure. [Figure 20C] 1 is a graph illustrating the performance of a transistor semiconductor die according to various embodiments of the present disclosure. [Figure 21] FIG. 1 is a top-down view of a transistor semiconductor die according to one embodiment of the present disclosure. [Figure 22] FIG. 1 is a top-down view of a transistor semiconductor die according to one embodiment of the present disclosure. [Figure 23] FIG. 1 is a top-down view of a transistor semiconductor die according to one embodiment of the present disclosure. [Figure 24] FIG. 1 is a top-down view of a transistor semiconductor die according to one embodiment of the present disclosure. [Figure 25] FIG. 1 is a top-down view of a transistor semiconductor die according to one embodiment of the present disclosure. [Figure 26] 1 is a cross-sectional view of a transistor semiconductor die according to one embodiment of the present disclosure. [Figure 27] 1 is a cross-sectional view of a transistor semiconductor die according to one embodiment of the present disclosure. [Figure 28] 1 is a cross-sectional view of a transistor semiconductor die according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012] The examples described below represent the information necessary to enable one skilled in the art to practice the examples and illustrate the best modes of practicing the examples. Upon reading the following description in light of the accompanying drawings, one skilled in the art will understand the concepts of the present disclosure and will recognize applications of these concepts not specifically addressed herein. It is understood that these concepts and applications are within the scope of this disclosure and the appended claims.

[0013] Terms such as "first," "second," etc. are used herein to describe various elements, but it is understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0014] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "upon" another element, it is understood that it can be directly on or extending directly onto the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Similarly, when an element, such as a layer, region, or substrate, is referred to as being "on" or extending "upon" another element, it is understood that it can be directly on or extending directly onto the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it is also understood that it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0015] Relative terms such as "lower" or "upper" or "top" or "below" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It is understood that these terms, and the terms discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0016] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It is further understood that as used herein, the terms "comprises," "comprising," "includes," and / or "comprising" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0017] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms used herein should be interpreted to have a meaning consistent with their meaning in the context of the present specification and related art, and are not to be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0018] Examples are described herein with reference to schematic diagrams of embodiments of the present disclosure. As such, actual dimensions of layers and elements may vary, and variations from the illustrated shapes are expected, for example, as a result of manufacturing techniques and / or tolerances. For example, regions illustrated or described as square or rectangular may have rounded or curved features, and regions shown as straight may have some irregularities. As such, regions illustrated in the figures are schematic, and their shapes are not intended to illustrate the precise shape of a region of a device, nor are they intended to limit the scope of the disclosure. Additionally, the size of a structure or region may be exaggerated relative to other structures or regions for illustrative purposes, and are provided to illustrate the overall structure of the present subject matter, and may or may not be drawn to scale. Common elements between figures may be indicated herein with common element numbers and may not be subsequently re-described.

[0019] 1 illustrates a cross-sectional view of a semiconductor die 10 according to one embodiment of the present disclosure. Semiconductor die 10 includes a substrate 12, a drift layer 14 on substrate 12, and an insulating layer 16 on drift layer 14. Semiconductor die 10 includes an active area 18 in which one or more implanted regions are provided to form a functional semiconductor device, and an edge termination region 20 surrounding active area 18. Somewhere within edge termination region 20 is provided an embedded sensor element 22. In some embodiments, embedded sensor element 22 is on insulating layer 16 such that insulating layer 16 is between embedded sensor element 22 and drift layer 14.

[0020] As discussed above, one or more implanted regions are provided in the active area 18 to form a functional semiconductor device. In one embodiment, the functional semiconductor device is a switching power semiconductor device. For example, the functional semiconductor device may be a metal-oxide-semiconductor field-effect transistor (MOSFET), particularly a vertical MOSFET, a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), a junction field-effect transistor (JFET), a gate-controlled thyristor (GTO), or the like. Furthermore, the functional semiconductor device may be of any suitable topology, such as planar, vertical, and trench devices. Accordingly, the substrate 12 and / or the drift layer 14 may include wide-bandgap materials, such as silicon carbide, gallium nitride, gallium oxide, and zinc oxide, which can be beneficial in devices intended to handle high voltages and / or currents. As discussed above, sensor elements integrated into wide-bandgap power semiconductor devices present several technical challenges. In particular, wide-bandgap materials have significantly higher sheet resistance than their narrow-bandgap counterparts. This high resistance, combined with the high voltages and currents handled by the power device, results in large parasitic signals that interfere with the operation of the embedded sensor element. For narrow-bandgap semiconductor devices such as silicon devices, sensor elements are often integrated directly into the drift layer, which otherwise provides minimal shielding from parasitic signals, but these same devices are non-functional when embedded in wide-bandgap power semiconductor devices.

[0021] Another obstacle to implementing embedded sensor elements in wide-bandgap power semiconductor devices is cost. While narrow-bandgap power semiconductor devices, such as silicon devices, are inexpensive to fabricate and extra process steps add little extra cost, each extra processing step in wide-bandgap power semiconductor devices adds significant cost. Therefore, it is desirable to implement embedded sensor elements using as few extra manufacturing steps as possible.

[0022] As defined herein, a power semiconductor device is a semiconductor device with an avalanche breakdown voltage of 50 V or greater. As discussed above, the high voltages and currents handled by these devices can create parasitic signals that present challenges to the implementation of embedded sensor elements. The relatively high sheet resistance of wide bandgap semiconductor materials further complicates the implementation of embedded sensor elements.

[0023] One way to isolate the embedded sensor element 22 is to provide an insulating layer 16 between the embedded sensor element 22 and the drift layer 14. In one embodiment, the insulating layer 14 is an oxide layer, such as a field oxide layer. For example, the insulating layer 14 may include one or more layers of Al2O3 and SiO2, separately or alternating, and / or one or more layers of Si3N4 and SiO2, separately or alternating. Thus, the insulating layer 14 may already be present on the semiconductor die 10. For example, the insulating layer 14 may form a gate oxide in some areas of the semiconductor die 10 and a field oxide in other areas of the semiconductor die 10. Thus, the insulating layer 14 is already available without additional manufacturing steps. Additionally, the embedded sensor element 22 may be provided on an already-existing polysilicon layer to create a functional semiconductor device on the semiconductor die 10. For example, the polysilicon layer may form a gate electrode and / or a gate contact in some portions of the semiconductor die 10. Thus, the layers used to provide the embedded sensor element 22 are already available without additional manufacturing steps, except for reworking the masks used to deposit the layers. To create the functionality of the embedded sensor element 22, one or more implants (e.g., to create diodes, lumped resistors, etc.) may be required in the portion of the polysilicon layer that forms the embedded sensor element 22, as discussed in more detail below. These extra manufacturing steps are the minimum number required to provide the embedded sensor element 22, thereby minimizing the cost of the embedded sensor element 22.

[0024] The polysilicon layer used to provide the gate electrodes and / or contacts and the sensor element 22 may be a doped polysilicon layer provided via any suitable process. In some embodiments, the polysilicon layer is provided via an epitaxial growth process in which dopants are provided in the atmosphere to create a desired doping profile. In other embodiments, the polysilicon layer may be deposited and then doped as desired via an implantation process. As discussed above, ion implantation may be a preferred approach when providing the sensor element 22 because providing a diode or other sensing device requires a separately doped area. Ion implantation can also provide other benefits, such as improving the sheet resistance uniformity of the polysilicon layer by 5-10% in some embodiments and 10-20% in other embodiments. This is due to the use of heavy dopant ions, such as boron difluoride (BF), which can break down the crystalline structure of the polysilicon layer into smaller crystal sizes.

[0025] While the insulating layer 16 provides some isolation for the embedded sensor element 22, in some scenarios, more isolation may be desirable. Accordingly, FIG. 2 illustrates a cross-sectional view of the semiconductor die 10 showing additional details of the embedded sensor element 22. For illustrative purposes, a MOSFET cell 24 is shown adjacent the embedded sensor element 22. However, as discussed above, this is merely an example, and any number of functional semiconductor devices, such as BJTs, IGBTs, and thyristors, may be provided in place of or in addition to the MOSFET cell 24.

[0026] MOSFET cell 24 includes a pair of junction implants 26 separated by a junction field effect transistor (JFET) region 28. Each one of the junction implants 26 includes a deep well region 30, a source region 32, and a body region 34. A gate oxide 36, which is part of insulating layer 16, is located on drift layer 14 over a portion of each one of the junction implants 26 and JFET regions 28, as shown. A source contact 38 is also located on drift layer 14 over a portion of each one of the junction implants 26, as shown. A gate contact 40 is located on gate oxide 36. A drain contact 42 is located on substrate 12 opposite drift layer 14. As shown, MOSFET cell 24 is an n-type device, where substrate 12, drift layer 14, deep well region 30, source region 32, body region 34, and JFET region 28 are labeled with their doping types and relative doping concentrations ("+" indicates a higher doping level relative to other regions). However, the principles of this disclosure apply equally to p-type devices in which all of the doping types shown are reversed. Those skilled in the art will recognize MOSFET cell 24 as a vertical MOSFET, specifically a double-diffused MOSFET (DMOS). Furthermore, those skilled in the art will understand that MOSFET cell 24 is only one of many cells disposed across active area 18 and interconnected to provide the MOSFET with certain desired characteristics, such as a desired on-state resistance and a desired blocking voltage. While the examples described throughout this application show MOSFET cell 24 with details of embedded sensor element 22, embedded sensor element 22 can also be disposed alongside BJT cells, IGBT cells, JFET cells, GTO cells, etc. Furthermore, embedded sensor element 22 can also be disposed alongside planar or trench devices, rather than the vertical devices shown.

[0027] Turning to the details of the embedded sensor element 22, the embedded sensor element 22 may include one or more layers over the field oxide 44, which is part of the insulating layer 16 on the drift layer 14. In particular, the embedded sensor element 22 may include a functional sensor layer 52 and a sensor contact layer 54. Note that the functional sensor layer 52 is part of the polysilicon layer also used to provide the gate contact 40. In other words, the gate contact 40 and the functional sensor layer 52 are formed from the same layer (e.g., patterned using a mask). As discussed above, this reduces manufacturing steps, thus enabling the implementation of the embedded sensor element 22 with minimal additional cost. As shown in FIG. 2 , the field oxide 44 is much thicker than the gate oxide 36 because of their different functions. While the gate oxide 36 acts as a dielectric that provides gate capacitance, the field oxide 44 is used to provide electrical isolation and shielding for various portions of the semiconductor die 10.

[0028] A shielding well 46 is provided in the drift layer 14 below the embedded sensor element 22. The drift layer 14 is an n-type layer, while the shielding well 46 is a p-type region. More generally, the shielding well 46 has a doping type that is opposite to that of the drift layer 14. The shielding well 46 may be an implanted region in the drift layer 14 in some embodiments, but generally may be provided by any suitable means. The shielding well 46 forms a PN junction with the drift layer 14 such that the shielding well blocks DC voltage at the surface of the drift layer 14 below the embedded sensor element 22. A first contact well 48A and a second contact well 48B are provided in the shielding well 46. The first contact well 48A and the second contact well 48B are p-type regions with a higher doping concentration than the shielding well 46. The first and second contact wells 48A and 48B may be implanted regions in the drift layer 14, but may be provided by any suitable means. The contact wells 48 provide ohmic connections to the shield well 46 for the first and second contacts 50A and 50B, such that the first and second contacts 50A and 50B are electrically coupled to the shield well 46 via the first and second contact wells 48A and 48B, respectively. To further shield the embedded sensor element 22 from parasitic voltages and currents, the first and second contacts 50A and 50B are coupled to a fixed potential, such as ground. In other embodiments, the first and second contacts 50A and 50B may be coupled to the source contacts 38 of the MOSFET cells 24 or may otherwise be connected to specific portions of a functional semiconductor device on the semiconductor die 10. By coupling the first contact 50A and the second contact 50B to a fixed potential or to a specific portion of a functional semiconductor device on the semiconductor die 10, parasitic currents in the shield well 46 due to transient signals (e.g., AC signals) in the drift layer 14 can be reduced. This is important because the shield well 46 has a finite resistance, and therefore any parasitic currents in the shield well 46 will generate voltages on the surface of the drift layer 14 below the embedded sensor element 22. These voltages may be capacitively coupled into the embedded sensor element 22 through the field oxide 44, which will interfere with its operation.In various embodiments, the first and second contacts 50A and 50B, as well as the source and drain contacts 38 and 42, may comprise any suitable ohmic metal, such as aluminum, titanium, and titanium nitride. Although not shown, a metal contact layer may be coupled to the gate contact 40 to form a gate contact pad. This additional metal contact layer may also comprise any suitable ohmic metal, such as aluminum, titanium, and titanium nitride.

[0029] Those skilled in the art will appreciate that wide-bandgap semiconductor materials have significantly higher resistivity than their narrow-bandgap counterparts. While this is generally beneficial for power devices, as they can support higher voltages without breakdown, it presents unique technical challenges for implementing embedded sensors due to their tendency to generate large parasitic signals that interfere with their operation. As shown in FIG. 2 , there is a distance D between the first contact well 48A and the second contact well 48B. The embedded sensor element 22 is located within this distance D between the first contact well 48A and the second contact well 48B. It is desirable to minimize the distance D between the first contact well 48A and the second contact well 48B to minimize resistance across the area of ​​the shield well 46 and, as discussed above, to reduce parasitic currents that may otherwise induce voltages that interfere with the operation of the embedded sensor element 22. The resistance of the shielding well 46 at the midpoint between the first contact well 48A and the second contact well 48B is proportional to the distance D between the first contact well 48A and the second contact well 48B. By minimizing the distance D, the resistance can be minimized. In one embodiment, the distance D between the first contact well 48A and the second contact well 48B is less than 200 μm. In other embodiments, the distance D between the first contact well 48A and the second contact well 48B is less than 100 μm, less than 50 μm, less than 25 μm, and a minimum of 5 μm. The smaller the distance between the first contact well 48A and the second contact well 48B, the lower the resistance through the shielding well 46. This results in less interference in the embedded sensor element 22 due to reduced parasitic voltage in the shielding well 46.

[0030] Minimizing the distance D between the first contact well 48A and the second contact well 48B means that the embedded sensor element 22 is generally provided as a long, narrow strip extending into and / or out of the page, as shown in FIG. 2 . The embedded sensor element 22 may be any type of sensing element, such as a diode, resistor, or the like, capable of providing a voltage and / or current proportional to a measurement of interest. For example, the diode may be provided by implanting n-type and / or p-type regions in the functional sensor layer 52, which is the same polysilicon layer used for the gate contact 40, as discussed above. In some embodiments, the polysilicon layer may already be doped in some manner (e.g., as a p-type layer), and therefore only one implant is required (e.g., an implant to form an n-type region). The diode may exhibit a forward voltage drop proportional to temperature, allowing an external sensing circuit to measure the temperature of the semiconductor die 10. Exemplary details of the embedded sensor element 22 are described below.

[0031] To further reduce parasitic signals coupled into the embedded sensor element 22, a noise-reduction well 56 may be provided in the shielding well 46, as shown in FIG. 3 . The noise-reduction well 56 has a doping type opposite to that of the shielding well 46 and is in electrical contact with the first contact 50A and the second contact 50B via the first contact well 48A and the second contact well 48B, respectively. In the example shown in FIG. 3 , the noise-reduction well 56 is an n-type region. The noise-reduction well 56 may be an implanted region in the drift layer 14, but may be provided by any suitable means. Those skilled in the art will appreciate that n-type wide-bandgap semiconductor materials often have up to three orders of magnitude lower resistance than their p-type counterparts. By providing the noise-reduction well 56, the resistance at the surface of the drift layer 14 below the embedded sensor element 22 can be further reduced, which in turn can reduce parasitic signals coupled into the embedded sensor element 22.

[0032] As discussed above, the functional sensor layer 52 is part of the polysilicon layer that also forms the gate contact 40. While this can reduce manufacturing steps, it can also prevent the layer from being metallized or silicided because the functional sensor layer 52 cannot comprise the sensing element, since the metallization or silicide is a blanket process that affects the entire polysilicon layer as a whole. Metallization or silicide of the polysilicon layer that forms the gate contact may be desirable because it can reduce resistance and therefore improve the distribution of the gate signal across the semiconductor die 10, improving switching speed and other performance characteristics. Furthermore, even with the use of the shielding well 46 and noise reduction well 56, further isolation between the embedded sensor element 22 and the drift layer 14 may be desirable. Accordingly, FIG. 4 illustrates an embedded sensor element 22 with further isolation, according to one embodiment of the present disclosure. The semiconductor die 10 shown in FIG. 4 is substantially the same as that shown in FIG. 2, except for the presence of an additional insulating layer 58 and an additional functional layer 60 between the embedded sensor element 22 and the drift layer 14. In this embodiment, the functional sensor layer 52 is not part of the same layer used to form the gate contact 40, but is a “second level” polysilicon layer added to that used to form the gate contact 40. The additional functional layer 60, as shown in FIG. 4 , is part of the same layer used to form the gate contact 40, which may be a polysilicon layer in various embodiments as discussed above. Two additional layers, the additional insulating layer 58 and the functional sensor layer 52, are provided on the additional functional layer 60 to configure the embedded sensor element 22, such that the insulating layer 16, the additional functional layer 60, and the additional insulating layer 58 are between the embedded sensor element 22 and the drift layer 14. The additional two layers further shield the embedded sensor element 22, adding only two additional necessary layers. The additional insulating layer 58 may comprise any suitable insulating material, such as SiO2. The functional sensor layer 52 may be a second level polysilicon layer, which is provided in the same manner as the first polysilicon layer that forms the gate contact 40 and the additional functional layer 60, as described above.While the second level polysilicon layer adds an additional manufacturing step to creating semiconductor die 10, it provides advantages such as allowing the first polysilicon layer to be metallized or silicided, which can improve the performance of semiconductor die 10, as described above.

[0033] To provide even more shielding, a noise-reduction well 56 may be added to the semiconductor die 10 shown in FIG. 4 . Such an embodiment is shown in FIG. 5 . As discussed above, the noise-reduction well 56 can further reduce parasitic voltage at the surface of the drift layer 14 below the embedded sensor element 22 by reducing the resistance in this area, thus further reducing interference with the embedded sensor element 22. Although not shown in FIGS. 4 or 5 , in embodiments in which the additional functional layer 60 is partially or fully metallized and / or silicided, the contact 50 may be electrically coupled to the additional functional layer 60, thereby further isolating the embedded sensor element 22.

[0034] In the embodiment described above, the substrate 12 has a thickness between 0.2 μm and 10.0 μm and a surface area of ​​1×10 17 cm -3 From 5 x 10 21 cm -3 The drift layer 14 may be an n-type layer having a thickness between 1.0 μm and 20.0 μm and a doping concentration between 1×10 15 cm -3 From 1×10 17 cm -3 The shielding well 46 may be an n-type layer having a thickness between 0.1 μm and 3.0 μm and a doping concentration between 1×10 17 cm -3 From 5 x 10 21 cm -3In various embodiments, the thickness of the shielding well 46 may be any subrange between 0.1 μm and 3.0 μm, or any discrete point within the range. For example, the thickness of the shielding well 46 may be between 0.1 μm and 2.5 μm, between 0.1 μm and 2.0 μm, between 0.1 μm and 1.5 μm, between 0.1 μm and 1.0 μm, between 0.1 and 0.5 μm, between 0.5 and 3.0 μm, between 1.0 μm and 3.0 μm, between 1.5 μm and 3.0 μm, between 2.0 μm and 3.0 μm, between 2.5 μm and 3.0 μm, between 0.5 μm and 2.5 μm, between 1.0 μm and 2.0 μm, between 1.5 μm and 2.0 μm, etc. Additionally, the doping concentration of the shielding well 46 may be between 1×10 and 1×10. 17 cm -3 From 5 x 10 21 cm -3 For example, the doping concentration of the shielding well 46 may be 5×10 17 cm -3 From 5 x 10 21 cm -3 Between 1×10 18 cm -3 From 5 x 10 21 cm -3 Between 5 x 10 18 cm -3 From 5 x 10 21 cm -3 Between 1×10 19 cm -3 From 5 x 10 21 cm -3 Between 5 x 10 19 cm -3 From 5 x 10 21 cm -3 Between 1×10 20 cm -3 From 5 x 10 21 cm -3 Between 5 x 10 20 cm -3 From 5 x 10 21 cm -3 Between 1×10 21 cm -3 From 5 x 10 21 cm -3Between 1×10 17 cm -3 From 1×10 21 cm -3 Between 1×10 17 cm -3 From 5 x 10 20 cm -3 Between 1×10 17 cm -3 From 1×10 20 cm -3 Between 1×10 17 cm -3 From 5 x 10 19 cm -3 Between 1×10 17 cm -3 From 1×10 19 cm -3 Between 1×10 17 cm -3 From 5 x 10 18 cm -3 Between 1×10 17 cm -3 From 1×10 18 cm -3 Between 1×10 17 cm -3 From 5 x 10 17 cm -3 Between 5 x 10 17 cm -3 From 1×10 21 cm -3 Between 1×10 18 cm -3 From 5 x 10 20 cm -3 Between 5 x 10 18 cm -3 From 1×10 20 cm -3 Between 1×10 and 1×10 19 cm -3 From 5 x 10 19 cm -3 Each one of the contact wells 48 may have a thickness between 0.1 μm and 2.5 μm and a thickness of 1×10 17 cm -3 From 5 x 10 21 cm -3In various embodiments, the thickness of the contact well 48 may be within any subrange between 0.1 μm and 2.5 μm, or at any discrete point within the range. For example, the thickness of the contact well 48 may be between 0.5 μm and 2.5 μm, between 1.0 μm and 2.5 μm, between 1.5 μm and 2.5 μm, between 2.0 μm and 2.5 μm, between 0.1 μm and 2.0 μm, between 0.1 μm and 1.5 μm, between 0.1 μm and 1.0 μm, between 0.1 μm and 0.5 μm, between 0.5 μm and 2.0 μm, and between 1.0 μm and 1.5 μm. Furthermore, the doping concentration of the contact well 48 may be between 1×10 17 cm -3 From 5 x 10 21 cm -3 For example, the doping concentration of the contact well 48 may be 5×10 17 cm -3 From 5 x 10 21 cm -3 Between 1×10 18 cm -3 From 5 x 10 21 cm -3 Between 5 x 10 18 cm -3 From 5 x 10 21 cm -3 Between 1×10 19 cm -3 From 5 x 10 21 cm -3 Between 5 x 10 19 cm -3 From 5 x 10 21 cm -3 , 1×10 20 cm -3 From 5 x 10 21 cm -3 Between 5 x 10 20 cm -3 From 5 x 10 21 cm -3 Between 1×10 21 cm -3 From 5 x 10 21 cm -3 Between 1×10 17 cm -3 From 1×1021 cm -3 Between 1×10 17 cm -3 From 5 x 10 20 cm -3 Between 1×10 17 cm -3 From 1×10 20 cm -3 Between 1×10 17 cm -3 From 5 x 10 19 cm -3 Between 1×10 17 cm -3 From 1×10 19 cm -3 Between 1×10 17 cm -3 From 5 x 10 18 cm -3 Between 1×10 17 cm -3 From 1×10 18 cm -3 Between 1×10 17 cm -3 From 5 x 10 17 cm -3 Between 5 x 10 17 cm -3 From 1×10 21 cm -3 Between 1×10 18 cm -3 From 5 x 10 20 cm -3 Between 5 x 10 18 cm -3 From 1×10 20 cm -3 Between 1×10 and 1×10 19 cm -3 From 5 x 10 19 cm -3 The noise reduction well 56 may be between 0.1 μm and 2.5 μm thick and between 1×10 17 cm -3 From 5 x 10 21 cm -3In various embodiments, the noise reduction well 56 may have a thickness within any subrange between 0.1 μm and 2.5 μm, or at any discrete point within the range. For example, the noise reduction well 56 may have a thickness between 0.5 μm and 2.5 μm, between 1.0 μm and 2.5 μm, between 1.5 μm and 2.5 μm, between 2.0 μm and 2.5 μm, between 0.1 μm and 2.0 μm, between 0.1 μm and 1.5 μm, between 0.1 μm and 1.0 μm, between 0.1 μm and 0.5 μm, between 0.5 μm and 2.0 μm, and between 1.0 μm and 1.5 μm. Additionally, the noise reduction well 56 may have a doping concentration of 1×10 17 cm -3 From 5 x 10 21 cm -3 For example, the doping concentration of the noise reduction well 56 may be 5×10 17 cm -3 From 5 x 10 21 cm -3 Between 1×10 18 cm -3 From 5 x 10 21 cm -3 Between 5 x 10 18 cm -3 From 5 x 10 21 cm -3 Between 1×10 19 cm -3 From 5 x 10 21 cm -3 Between 5 x 10 19 cm -3 From 5 x 10 21 cm -3 Between 1×10 20 cm -3 From 5 x 10 21 cm -3 Between 5 x 10 20 cm -3 From 5 x 10 21 cm -3 Between 1×10 21 cm -3 From 5 x 10 21 cm -3 Between 1×10 17 cm-3 From 1×10 21 cm -3 Between 1×10 17 cm -3 From 5 x 10 20 cm -3 Between 1×10 17 cm -3 From 1×10 20 cm -3 Between 1×10 17 cm -3 From 5 x 10 19 cm -3 Between 1×10 17 cm -3 From 1×10 19 cm -3 Between 1×10 17 cm -3 From 5 x 10 18 cm -3 Between 1×10 17 cm -3 From 1×10 18 cm -3 Between 1×10 17 cm -3 From 5 x 10 17 cm -3 Between 5 x 10 17 cm -3 From 1×10 21 cm -3 Between 1×10 18 cm -3 From 5 x 10 20 cm -3 Between 5 x 10 18 cm -3 From 1×10 20 cm -3 Between 1×10 and 1×10 19 cm -3 From 5 x 10 19 cm -3 It may be between.

[0035] The improvements discussed above, i.e., separating the embedded sensor element 22 from the drift layer 14 with the insulating layer 16, providing the shielding well 46, minimizing the distance between the contact wells 48, providing the noise-reducing well 56, providing the additional insulating layer 58, and providing the additional functional layer 60, either alone or in combination, can significantly improve the isolation of the embedded sensor element 22 from the drift layer 14. In particular, the improvements discussed herein can provide greater than 50 V of DC isolation from the high-power portions of the semiconductor die 10, such as its source and drain. In various embodiments, the improvements discussed herein can provide greater than 75 V and greater than 100 V of DC isolation. In general, the improvements discussed herein enable the inclusion of embedded sensor elements on wide-bandgap power semiconductor dies that, without these isolation measures, would be subject to interference that would destroy their functionality.

[0036] As discussed above, the embedded sensor element 22 can be any suitable sensing element. In one embodiment, the embedded sensor element 22 is a temperature sensing element. In particular, the embedded sensor element 22 can be a diode that experiences a forward voltage drop proportional to temperature. Accordingly, FIG. 6 illustrates a top-down view of the embedded sensor element 22 according to one embodiment of the present disclosure. Illustratively, first and second contacts 50A, 50B are also shown. The embedded sensor element 22 includes an anode contact 62 and a cathode contact 64. The anode contact 62 is in electrical contact with a p-type region 66 in the functional sensor layer 52. The cathode contact 64 is in electrical contact with an n-type region 68 in the functional sensor layer 52. The p-type region 66 and / or the n-type region 68 may be provided via implantation of the functional sensor layer 52 according to well-known processes. As illustrated, the p-type region 66 and the n-type region 68 may be separated by regions of material. This region of material may be intrinsic (undoped) or may be doped differently than p-type region 66 and n-type region 68 .

[0037] In some scenarios, it may be desirable to provide several diodes in series to tailor the forward voltage to a particular sensing circuit. Accordingly, FIG. 7 illustrates a top-down view of an embedded sensor element 22 according to an additional embodiment of the present disclosure. The embedded sensor element 22 illustrated in FIG. 7 is substantially the same as that illustrated in FIG. 6, except that it includes two diodes instead of one. The functional sensor layer 52 is separated into two separate portions, each used to form a discrete diode. These diodes are coupled via a metal layer as illustrated. While only two diodes are shown, those skilled in the art will understand that the embedded sensor element 22 may include any number of discrete elements, including diodes, without departing from the principles of the present disclosure.

[0038] 8 shows a top-down view of an embedded sensor element 22 in accordance with an additional embodiment of the present disclosure. The embedded sensor element 22 shown in FIG. 8 is substantially similar to that shown in FIG. 7, except that the p-type region 66 and n-type region 68 are nested, thereby reducing the area required for each diode. Those skilled in the art will appreciate that diodes can be formed using any number of layout techniques, all of which are contemplated herein.

[0039] In some embodiments, the noise reduction wells 56 are blanket regions below the entire embedded sensor element 22. However, this can provide a parasitic NPN transistor, which can be problematic in some circumstances. Therefore, in some embodiments, the noise reduction wells 56 may be patterned, as shown in FIGS. 9 and 10. FIGS. 9 and 10 show a top-down view of the noise reduction wells 56 and do not show the embedded sensor element 22 or insulating layer 16 to avoid obscuring the drawing. In FIG. 9, the noise reduction wells 56 are provided in a first broad grid pattern, while in FIG. 10, the noise reduction wells 56 are provided in a tight grid pattern. Note that these are merely exemplary patterns, and one of ordinary skill in the art will readily recognize that any suitable pattern can be used for the noise reduction wells 56 without departing from the principles of the present disclosure.

[0040] Returning to the embodiment discussed above with respect to FIGS. 4 and 5 , providing the embedded sensor element 22 on a second-level polysilicon layer can enable the implementation of other functional components in addition to the embedded sensor element 22. For example, a lumped resistor, which can be used as a gate resistor for a MOSFET, can be implemented in the second polysilicon layer along with the embedded sensor element 22. FIG. 11A therefore illustrates a cross-sectional view of a lumped resistor 70 according to one embodiment of the present disclosure. The lumped resistor 70 is provided in the functional layer 52, which is the same layer as the functional sensor layer 52 discussed above. Specifically, the lumped resistor 70 is provided via a doped portion of polysilicon having a first ohmic contact 72A and a second ohmic contact 72B, as shown in the top-down view of the lumped resistor in FIG. 11B. The lumped resistor 70 may be coupled to the gate contact 40 of the MOSFET cell 24 to provide an on-chip gate resistor. In some embodiments, one of the ohmic contacts 72 may provide a gate contact pad. In such cases, only one of the resistive contacts 72 may be provided, with the lumped resistor 70 internally bonded to the gate contact. However, in other embodiments, one of the resistive contacts 72 may be a gate contact pad, and the other may be exposed so that the resistance of the lumped resistor 70 can be measured during fabrication to ensure the desired resistance is achieved. As discussed above, the functional sensor layer 52 may be a polysilicon layer that is doped during growth (in-situ) or later doped via an implantation process, such as ion implantation, to achieve the desired resistance. Although the lumped resistor 70 is shown in FIGS. 11A and 11B as a simple rectangle, the lumped resistor 70 may be provided in any number of shapes. For example, the portion of the functional sensor layer 52 that forms the lumped resistor 70 may be provided in a circular shape, a polygonal shape, or any other shape. Providing the lumped resistor 70 in this manner can improve performance when the lumped resistor 70 is used as a gate resistor by improving current distribution and / or reducing parasitic signals. Those skilled in the art will appreciate that in addition to resistors, other functional components may also be implemented in the second level polysilicon layer.

[0041] Although not shown in the figures above, the various metal contacts, such as source contact 38, drain contact 42, contact 50, and ohmic contact 72, may not be directly located in the areas to which they are electrically coupled. Rather, any number of passivation or encapsulation layers may separate these contacts from the areas of semiconductor die 10 that they contact, and the connections between them may comprise vias through these layers.

[0042] FIG. 12 is a flow diagram illustrating a method for fabricating a semiconductor die including an embedded sensor element according to one embodiment of the present disclosure. First, a drift layer is provided on a substrate (Step 100). The drift layer includes a wide-bandgap semiconductor material. Providing the drift layer may include growing the drift layer by any suitable semiconductor growth process. One or more implants are provided in the drift layer (Step 102) to provide a functional semiconductor device, such as a MOSFET, BJT, IGBT, or thyristor, as well as a shielding structure for the embedded sensor element. The shielding structure for the embedded sensor element may include one or more of the shielding wells, contact wells, and noise reduction wells discussed above. The implanted regions may be provided by any suitable implantation process. An insulating layer is provided on the drift layer (Step 104). The insulating layer may have different thicknesses in different portions of the semiconductor die, and may therefore include gate oxide and field oxide layers. A gate contact and a functional sensor layer are provided on the insulating layer (Step 106). The gate contact and functional sensor layer may be a polysilicon layer provided by any suitable deposition process. The polysilicon layer may be deposited and patterned to create the gate contact and functional sensor layer. In some embodiments, the gate contact and functional sensor layer are not provided simultaneously. Instead, the gate contact and additional polysilicon layer are provided together, an additional insulating layer is provided on the additional polysilicon layer, and the functional sensor layer is provided on the additional insulating layer. The results of this approach are shown in Figures 4 and 5 above. One or more implanted regions are then provided in the functional sensor layer to provide the embedded sensor element (step 108). For example, p-type and / or n-type regions may be provided to form a diode and used as a temperature sensor. Finally, a metal layer is provided, at least a portion of which is used to provide electrical contact to the shielding structure and the embedded sensor element (step 110). In some embodiments, multiple metal layers may be provided, with passivation or intermetal dielectric layers provided between them.

[0043] FIG. 13 illustrates a cross-sectional view of an embedded sensor element 22 according to one embodiment of the present disclosure. The embedded sensor element 22 is substantially similar to that shown in FIG. 2, except that the cross-sectional view is perpendicular to that shown in FIG. 2 (i.e., across the embedded sensor element 22 and into the page, with reference to FIG. 2), and a pair of sensor contact pads 74 are shown. Those skilled in the art will understand that contact pads having certain minimum dimensions must be provided to make electrical connection with a portion of a semiconductor die. The minimum dimensions may be based on the minimum size that a desired electrical connection, such as one or more wire bonds, can achieve within certain process limitations. Because the sensor contact layer 54 shown in FIG. 2 may be coplanar with one or more other metal features (e.g., source contact 38, contact 50, gate metal layer, etc.), the area available for contact pads within this layer may be limited so that the contact pads do not overlap and therefore not electrically contact these features. 13 shows contacts 50 mounted on a first metal layer 76A and sensor contact pads 74 mounted on one or more additional metal layers 76B. An inter-metal dielectric layer 78 is disposed over the first metal layer 76A, providing a surface upon which the sensor contact pads 74 can be mounted. Note that when the sensor contact pads 74 are disposed on the inter-metal dielectric layer 78, there is more room for the contact pads because the contact pads can overlap with the contacts 50 in the underlying first metal layer 76B. By moving the sensor contact pads 74 onto the additional metal layers, the area available for the sensor contact pads 74 is increased, which can provide more reliable contact with the embedded sensor elements 22 and therefore improved performance in some embodiments.

[0044] To further illustrate aspects of the present disclosure in which one or more additional metal layers are used to provide space for contact pads, FIG. 14 shows a top view of a transistor semiconductor die 210 according to one embodiment of the present disclosure. For purposes of illustration, the transistor semiconductor die 210 is a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) device including a passivation layer 212 with openings for a gate contact pad 214 and several source contact pads 216. The transistor semiconductor die 210 is a vertical power device with a drain contact pad (not shown) located on the backside of the device. The gate contact pad 214 and the source contact pads 216 may be provided as surfaces for coupling the transistor semiconductor die 210 to an external circuit. Therefore, the gate contact pad 214 and the source contact pads 216 may have a minimum size to ensure they can be reliably connected. In one embodiment, the minimum size of each of the gate contact pads 214 and the source contact pads 216 is 0.4 mm. 2 In various embodiments, the minimum size of each one of the gate contact pads 214 and the source contact pads 216 is 0.5 mm. 2 , 0.6mm 2 , 0.7mm 2 , 0.8mm 2 , 0.9mm 2 , and up to 1.0 mm 2 may be.

[0045] FIG. 15 illustrates a top view of the transistor semiconductor die 210 with the passivation layer 212 removed. Beneath the passivation layer 212 are a gate metal layer 218, a gate via bar 220 coupled to the gate metal layer 218, and a source metal layer 222. As discussed in more detail below, the gate metal layer 218, the gate via bar 220, and the source metal layer 222 are provided by the same metallization layer; therefore, the source metal layer 222 must include an opening 224 to accommodate the entire area of ​​the gate metal layer 218 and the gate via bar 220, as shown. FIG. 15 also illustrates a device region 226 and an edge termination region 228 of the transistor semiconductor die 210. As discussed above, the device region 226 is a region of the transistor semiconductor die 210 that includes one or more implants electrically coupled to one or more electrodes to provide selective current conduction and voltage blocking capabilities of the device. Edge termination region 228 is provided to reduce electric field crowding at the edges of transistor semiconductor die 210, thus preventing breakdown at low reverse voltages.

[0046] FIG. 16 shows a top-down view of a transistor semiconductor die 210 with the gate metal layer 218, gate via bars 220, source metal layer 222, and several other layers (discussed below) removed. Beneath these layers are several source regions 230 separated by several gate regions 232. The source regions 230 may be provided as regions having a doping type and / or doping concentration different from that of the drift layer in which they are located (e.g., via a separate epitaxy process from the drift layer or by implantation in the drift layer), while the gate regions 232 may be provided as regions in which the doping type and / or doping concentration of the drift layer is relatively unchanged or changed by a different amount. As shown in FIG. 16, the gate regions 232 are provided as stripes, but the gate regions 232 may similarly be provided as a grid, as illustrated in FIG. 17. To provide primary functionality for transistor semiconductor die 210 , gate contact pad 214 must make electrical contact with gate region 232 , while source contact pad 216 must make electrical contact with source region 230 .

[0047] 18 illustrates a cross-sectional view of a portion of a transistor semiconductor die 210 according to one embodiment of the present disclosure. The transistor semiconductor die 210 includes a substrate 234 and a drift layer 236 on the substrate 234. Several implants 238 in the surface of the drift layer 236 provide source regions 230, while several non-implanted regions between the implants 238 provide gate regions 232. Several gate electrodes 240 are provided on the gate regions 232, such that each one of the gate electrodes 240 passes between the implants 238 on either side of the gate region 232 on which it is provided. Each one of the gate electrodes 240 is separated from the surface of the drift layer 236 by an oxide layer 242. Several source electrodes 244 are provided on the source regions 230, such that each one of the source electrodes 244 contacts a different one of the implants 238. 18 , a gate metal layer 218 is provided on the surface of the drift layer 236 such that the gate metal layer 218 is separated from the surface of the drift layer 236 by an oxide layer 242 and is coupled to a respective one of the gate electrodes 240 on a plane not shown in FIG. 18 . A dielectric layer 246 is provided over the gate electrodes 240 to electrically isolate the gate electrodes 240 from the source electrodes 244. The source electrodes 244 are exposed at the surface of the dielectric layer 246. A source metal layer 222 is provided on the dielectric layer 246 so as to contact the source electrodes 244. A drain metal layer 248 is provided on the substrate 234 opposite the drift layer 236.

[0048] 15 and 18, the source metal layer 222 and the gate metal layer 218 are provided in a single metallization step (i.e., as a single, appropriately patterned metal layer) within the device region 226 of the transistor semiconductor die 210. This means that the source metal layer 222 and the gate metal layer 218 are provided on the same surface / plane of the transistor semiconductor die 210. Therefore, the source metal layer 222 cannot overlap the gate metal layer 218 and must instead include an opening for the gate metal layer 218. Due to constraints on the size of the gate metal layer 218 (e.g., the size of a minimum contact pad for wire bonding), the coverage of the source metal layer 222 is therefore limited within the device region 226 of the transistor semiconductor die 210. As shown in FIG. 18, the area below the source metal layer 222 is the active area that conducts current from the source metal layer 222 to the drain metal layer 248 via the drift layer 236. The area below the gate metal layer 218 is an inactive area because current cannot be carried by the drift layer 236 below the gate metal layer 218. Therefore, the total active area of ​​the device region 226, and therefore the total current-carrying capacity of the transistor semiconductor die 210, may be limited for a given size of the die.

[0049] 19 illustrates a cross-sectional view of a transistor semiconductor die 210 according to an additional embodiment of the present disclosure. The transistor semiconductor die 210 illustrated in FIG. 19 is substantially similar to that illustrated in FIG. 18 , but further includes an additional dielectric layer 250 on the dielectric layer 246. Specifically, the gate electrode 240 and the source electrode 244 are disposed on the surface of the drift layer 236, the dielectric layer 246 is disposed on the gate electrode 240 and the source electrode 244 such that the gate electrode 240 is electrically isolated from the source electrode 244 and the source electrode 244 is exposed at the surface of the dielectric layer 246, the source metal layer 222 is disposed on the dielectric layer 246, the additional dielectric layer 250 is disposed on the dielectric layer 246 and the source metal layer 222, and the gate metal layer 218 is disposed on the additional dielectric layer 250. The gate metal layer 218 is electrically coupled to the gate electrode 240 by one or more vias 252 that pass through the dielectric layer 246 and the additional dielectric layer 250 (which are connected on a plane not shown in FIG. 19 ). As illustrated, providing the additional dielectric layer 250 allows at least a portion of the gate metal layer 218 to overlap the source metal layer 222. The one or more vias 252 are very small compared to the total area of ​​the gate metal layer 218. Therefore, only a very small opening in the source metal layer 222 is required, thereby increasing the total area covered by the source metal layer 222. As discussed above, because the area below the source metal layer 222 is the active area of ​​the transistor semiconductor die 210, this effectively increases the total active area of ​​the transistor semiconductor die, and therefore the current-carrying capacity. In fact, the total inactive area of ​​the device region 226 of the transistor semiconductor die 210 is less than the total area of ​​the gate metal layer 218, and in some embodiments, less than the total area of ​​the gate contact pad 214, which was previously unachievable.

[0050] Increasing the active area of ​​transistor semiconductor die 210 allows for an increase in current-carrying capacity for a given size. Alternatively, increasing the active area of ​​transistor semiconductor die 210 allows for a decrease in die size without sacrificing current-carrying capacity. This allows additional chips to be added to a given wafer when subsequently fabricating transistor semiconductor die 210. While the examples discussed herein primarily relate to transistor semiconductor die 210 comprising MOSFET devices, the principles described herein apply equally to transistor semiconductor die 210 comprising field-effect transistor (FET) devices, bipolar junction transistor (BJT) devices, insulated-gate bipolar transistor (IGBT) devices, or any other type of vertical transistor device having two or more top-level contacts. With this in mind, the gate contact pads 214 may be collectively referred to as first contact pads, the source contact pads 216 may be collectively referred to as second contact pads, the source metal layer 222 may be collectively referred to as a first metallization layer, the gate metal layer 218 may be collectively referred to as a second metallization layer, the source regions 230 may be collectively referred to as a first set of regions, and the gate regions may be collectively referred to as a second set of regions.

[0051] In one embodiment, substrate 234 and drift layer 236 are silicon carbide. Using silicon carbide for substrate 234 and drift layer 236 can significantly increase the performance of transistor semiconductor die 210 compared to using conventional material systems such as silicon. Although not shown, implant 238 may include several different implant regions therein as needed to provide selective current conduction and voltage blocking capabilities of transistor semiconductor die 210. Dielectric layer 246 and additional dielectric layer 250 may include one or more layers of Al2O3 and SiO2, for example, alternating. In other embodiments, dielectric layer 246 and additional dielectric layer 250 may include one or more layers of Si3N4 and SiO2, for example, alternating. In general, dielectric layer 246 and additional dielectric layer 250 may include any suitable dielectric material (e.g., one having a wide bandgap (>~5 eV) and a relatively low dielectric constant). Dielectric layer 246 and additional dielectric layer 250 may include the same or different materials. An additional passivation layer comprising Si3N4, Al2O3, AlN, SiO2, or any other suitable material may be alternated with dielectric layer 246 and additional dielectric layer 250 as needed to avoid interactions between the materials. Passivation layer 212 may comprise Si3N4, Al2O3, AlN, SiO2, or any other suitable material in various embodiments.

[0052] 20A is a graph illustrating an improvement in current-carrying capacity to transistor semiconductor die 210 by moving gate metal layer 218 above source metal layer 222. The solid line illustrates the relationship between current-carrying capacity and size of transistor semiconductor die 210 without the contact pad layout improvement, as shown in FIG. 18. The dashed line illustrates the same relationship between current-carrying capacity and size of transistor semiconductor die 210 with the improvement discussed above with respect to FIG. 19. This graph assumes a constant rated blocking voltage (e.g., 1200V). As shown, an improvement in the current-carrying capacity of transistor semiconductor die 210 is realized regardless of the size of the die. As discussed above, this is due to the increase in the active area of ​​device region 226.

[0053] FIG. 20B is a graph further illustrating the improvement in current-carrying capacity to the transistor semiconductor die 210 due to the movement of the gate metal layer 218 above the source metal layer 222. The graph illustrates the relationship between the percentage increase in current-carrying capacity (compared to a transistor semiconductor die without the improvements as illustrated in FIG. 18 ) and the current rating of the transistor semiconductor die 210. As illustrated, the percentage increase in current-carrying capacity of the transistor semiconductor die 210 has an inverse relationship to the current rating of the transistor semiconductor die 210. This is because as the current rating of the transistor semiconductor die 210 increases, its overall size also increases. Therefore, the active area recovered as a result of the movement of the gate metal layer 218 above the source metal layer 222 accounts for a smaller percentage of the total active area of ​​the device, thereby reducing the percentage increase in current-carrying capacity seen with the use of these improvements. FIG. 20B illustrates that the greatest improvement in device performance due to the improvements discussed herein is seen at lower current ratings.

[0054] 20C is a graph further illustrating the improvement in current-carrying capacity to the transistor semiconductor die 210 due to the movement of the gate metal layer 218 above the source metal layer 222. The graph shows the relationship between the percentage increase in current-carrying capacity (compared to a transistor semiconductor die without the improvements as illustrated in FIG. 18 ) and the voltage rating of the transistor semiconductor die 210. As illustrated, the percentage increase in current-carrying capacity of the transistor semiconductor die 210 has a positive relationship with the voltage rating of the transistor semiconductor die 210. The graph shown assumes a constant size of the transistor semiconductor die 210. The relationship between the percentage increase in current-carrying capacity and the voltage rating is due to the fact that as the voltage rating of the transistor semiconductor die 210 increases, the size of the edge termination region 228 also increases. Thus, the size of the device region 226 decreases such that the active area recovered as a result of the movement of the gate metal layer 218 above the source metal layer 222 accounts for a larger percentage of the total active area of ​​the device, thereby further increasing the percentage increase in current-carrying capacity seen with the use of these improvements. FIG. 20C illustrates that the greatest improvement in device performance for a given chip size is seen at higher voltage ratings.

[0055] FIG. 21 illustrates a top-down view of a transistor semiconductor die 210 according to one embodiment of the present disclosure. Specifically, FIG. 21 illustrates the transistor semiconductor die 210 with the gate metal layer 218 and the additional dielectric layer 250 removed. Beneath the additional dielectric layer 250, the source metal layer 222 is exposed. The gate via bar 220 is still present in the embodiment illustrated in FIG. 21 . A first dashed box 254 illustrates an area over which the gate metal layer 218 is disposed. This area may correspond to the boundary of the gate contact pad 214 or may extend beyond the boundary of the gate contact pad 214. In other words, the entire gate metal layer 218 may be exposed through the passivation layer 212, such as the gate contact pad 214, or a portion of the gate metal layer 218 may be covered by the passivation layer 212, such that only a portion of the gate metal layer 218 constitutes the gate contact pad 214. As shown, a portion of the gate metal layer 218 covers the gate via bar 220, so that the gate contact pad 214 can contact the gate electrode 240 that is coupled to the gate via bar 220. A second dashed box 256A and a third dashed box 256B illustrate the area of ​​the source contact pad 216. The gate via bar 220 is still located on the surface of the drift layer 236, so the source metal layer 222 is still required to have an opening 258 sized to accommodate the gate via bar 220. However, the overall size of the gate via bar 220 is much smaller than that of a conventional gate contact pad. Therefore, the size of the active area within the device region 226 of the transistor semiconductor die 210 can be significantly increased.

[0056] FIG. 22 illustrates a top-down view of a transistor semiconductor die 210 according to an additional embodiment of the present disclosure. Specifically, FIG. 22 illustrates the transistor semiconductor die 210 with the gate metal layer 218 and additional dielectric layer 250 removed. Beneath the additional dielectric layer 250, the source metal layer 222 is exposed. The gate via bars 220 are removed in the embodiment illustrated in FIG. 22 and replaced with several gate contact vias 260 that extend through the dielectric layer 246 and additional dielectric layer 250 to contact one or more underlying gate electrodes 240, which are then coupled to each other (e.g., in a lattice configuration as shown above) on the surface of the drift layer 236. A first dashed box 254 illustrates an area over which the gate metal layer 218 is disposed. As shown, a portion of the gate metal layer 218 covers the gate contact vias 260, thereby connecting the gate contact pad 214 to the gate electrode 240. Second dashed box 256A and third dashed box 256B illustrate the area of ​​source contact pad 216. Gate contact via 260 may have an even smaller area than gate via bar 220. Thus, the total size of opening 258 in source metal layer 222 that accommodates the connection from gate contact pad 214 to gate electrode 240 can be even smaller, thereby allowing for even larger active area within device region 226 of transistor semiconductor die 210.

[0057] As the size of the connection between the gate contact pad 214 and the underlying gate electrode 240 decreases, the gate resistance of the transistor semiconductor die 210 may increase. Therefore, the size and shape of the gate contact pad 214, the gate metal layer 218, and the number and placement of the gate contact vias 260 can be arranged to minimize the gate resistance of the transistor semiconductor die 210 while simultaneously maximizing the active portion of the device area 226, as illustrated in FIGS. 23 and 24 . In FIGS. 23 and 24 , a first dashed box 254 represents the placement of the gate metal layer 218 over the gate contact vias 260. The gate contact pad 214 may correspond to all or a subset of the gate metal layer 218, as discussed above. The second dashed box 256A and the third dashed box 256B again represent the area of ​​the source contact pad 216. In FIG. 23 , a fourth dashed box 256C and a fifth dashed box 256D represent additional areas of the source contact pad 216 that may be provided.

[0058] In addition to maximizing the active portion of the device region 226 of the transistor semiconductor die 210, the additional dielectric layer 250 may also be used to provide additional features. Accordingly, FIG. 25 illustrates a top-down view of the transistor semiconductor die 210 in accordance with one embodiment of the present disclosure. Specifically, FIG. 25 illustrates the transistor semiconductor die 210 with the passivation layer 212 removed. Beneath the passivation layer 212 is the additional dielectric layer 250 through which the gate contact pad 214 and the source contact pad 216 are exposed. In addition to these contact pads, several sensor contact pads 262 are provided on the additional dielectric layer 250. The sensor contact pads 262 are coupled to sensors 264, such as the embedded sensor elements 22 described above. The sensors 264 may be any type of sensor (e.g., a temperature sensor, a strain sensor, or a current sensor). The sensor 264 may also be located on the surface of the additional dielectric layer 250, or may be located further down in the layer stack, such as on the dielectric layer 246, on the drift layer 236, or within the drift layer 236. If the sensor 264 is located in the drift layer 236, it may detract from the total active area of ​​the device region 226. However, the sensor 264 is generally very small compared to the size of the device region 226, and therefore having the sensor in the drift layer 236 may result in only a slight reduction in the active area of ​​the device region 226. Overall, the sensor contact pad 262 is much larger than the sensor 264 itself, and because the sensor contact pad 262 can be located above the source metal layer 222, the active area of ​​the device region 226 is minimally affected by the introduction of one or more sensors into the transistor semiconductor die 210. The sensor contact pad 262, in some embodiments, may be formed by the same metallization layer (i.e., in the same metallization step) as the gate metal layer 218.

[0059] Figure 26 illustrates a cross-sectional view of a transistor semiconductor die 210 according to one embodiment of the present disclosure. The transistor semiconductor die 210 illustrated in Figure 26 is substantially similar to that illustrated in Figure 19, except that a sensor contact pad 262 is illustrated on the surface of the additional dielectric layer 250. Although the sensor 264 is not illustrated in Figure 26, the sensor 264 may be located behind the sensor contact pad 262 on the additional dielectric layer 250.

[0060] FIG. 27 illustrates a cross-sectional view of a transistor semiconductor die 210 according to an additional embodiment of the present disclosure. The transistor semiconductor die 210 illustrated in FIG. 27 is substantially similar to that illustrated in FIG. 26 , except that a sensor contact pad 262 is coupled to a sensor 264 located in the drift layer 236 by a sensor contact via 266. The sensor 264 may include one or more implanted regions in the drift layer 236, such that the sensor 264 can be any type of semiconductor device. The sensor 264 may be used to measure temperature, strain, current, voltage, or any other desired parameter. As discussed above, the sensor contact pad 262 generally requires a larger area to implement than the sensor 264 and the sensor contact via 266. Providing the sensor contact pad 262 on the additional dielectric layer 250 so that the sensor contact pad 262 at least partially overlaps the source metal layer 222 reduces the impact of providing the sensor 264 on the transistor semiconductor die 210 on the active area of ​​the device region 226. Although sensor 264 is shown on drift layer 236, sensor 264 may be located anywhere above or below drift layer 236 and coupled using any number of vias and intervening metal layers without departing from the principles of the present disclosure.

[0061] FIG. 28 illustrates a cross-sectional view of a transistor semiconductor die 210 according to an additional embodiment of the present disclosure. The transistor semiconductor die 210 is substantially similar to that illustrated in FIG. 19 , except that the transistor semiconductor die 210 further includes a first intervening layer 268A between the dielectric layer 246 and the additional dielectric layer 250, and a second intervening layer 268B between the additional dielectric layer 250 and the gate metal layer 218. The first intervening layer 268A and the second intervening layer 268B can reduce chemical interaction between the dielectric layer 246, the additional dielectric layer 250, the gate metal layer 218, and the source metal layer 222. This is important because the additional dielectric layer 250 may require a densification anneal for good dielectric properties. The first intervening layer 268A and the second intervening layer 268B may include various layers of SiN, AlO, AlN, SiO, the same, or any other suitable material. As discussed above, the dielectric layer 246 and the additional dielectric layer 250 may comprise SiO2 or any other suitable material. As shown, the second intervening layer 268B may be provided after openings for the one or more vias 252 are created. Thus, the second intervening layer 268B may be provided along the edges of the one or more vias 252 such that the second intervening layer 268B reduces chemical interaction between the metals of the one or more vias 252, the dielectric layer 246, and the additional dielectric layer 250. The one or more vias 252 may comprise a single conductive metal, the same or different from the gate metal layer 218, or may comprise a stack of different metals as needed to form a chemical or diffusion barrier layer along the walls of the one or more vias 252.

[0062] 28 also shows a passivation layer 212 over the gate metal layer 218. The passivation layer 212 can protect the transistor semiconductor die 210 from the surrounding environment. The passivation layer 212 may include alternating layers of SiN, AlO, SiO, the same, or any other suitable material.

[0063] Transistor semiconductor die 210 may be a power semiconductor die configured to conduct at least 0.5 A in a forward conduction mode of operation and block at least 100 V in a blocking mode of operation. In various embodiments, transistor semiconductor die 210 may be configured to conduct at least 1.0 A, at least 2.0 A, at least 3.0 A, at least 4.0 A, at least 5.0 A, at least 6.0 A, at least 7.0 A, at least 8.0 A, at least 9.0 A, and at least 10.0 A in a forward conduction mode of operation. Transistor semiconductor die 210 may be configured to block at least 250 V, at least 500 V, at least 750 V, at least 1 kV, at least 1.5 kV, and at least 2.0 kV in a blocking mode of operation. The same parameters apply to semiconductor die 10 discussed above.

[0064] It is contemplated that any of the foregoing aspects, and / or various separate aspects and features as described herein, may be combined to further advantage. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments, unless indicated to the contrary herein.

[0065] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure, and all such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

1. a drift layer comprising a wide bandgap semiconductor material; and A semiconductor device with an embedded sensor element.

2. The semiconductor device of claim 1 , wherein the embedded sensor element is a temperature sensing element.

3. The semiconductor device of claim 2 , further comprising an insulating layer between the drift layer and the embedded sensor element.

4. 4. The semiconductor device of claim 3, further comprising a shielding well between the drift layer and the buried sensor element, the shielding well having a doping type that is opposite to a doping type of the drift layer.

5. The semiconductor device of claim 4 , wherein the shielding well is an implanted region in the drift layer.

6. a first contact in electrical contact with the shielding well; and 6. The semiconductor device of claim 5, further comprising a second contact in electrical contact with said shielding well, said embedded sensor element being between said first contact and said second contact.

7. a first contact well, the first contact well is an implanted region in the shielding well; the first contact well has the same doping type as the shielding well and a doping concentration greater than the doping concentration of the shielding well; the first contact is in electrical contact with the shielding well through the first contact well; and a second contact well, the second contact well is an implanted region in the shielding well; the second contact well has the same doping type as the shielding well and a doping concentration greater than the doping concentration of the shielding well; 7. The semiconductor device of claim 6, further comprising: a second contact well, the second contact being in electrical contact with the shielding well through the second contact well.

8. 7. The semiconductor device of claim 6, wherein the first contact and the second contact are electrically coupled to a fixed potential.

9. 7. The semiconductor device of claim 6, wherein the distance between the first contact and the second contact is 200 [mu]m or less.

10. 10. The semiconductor device of claim 9, wherein the distance between the first contact and the second contact is 100 [mu]m or less.

11. 11. The semiconductor device of claim 10, wherein the distance between the first contact and the second contact is 50 [mu]m or less.

12. 12. The semiconductor device of claim 11, wherein the distance between the first contact and the second contact is at least 5 μm.

13. Further provided with a noise reduction well; the noise reduction well has a doping type that is opposite to the doping type of the shielding well; the noise reduction well is separated from the drift layer by at least a portion of the noise reduction well; The semiconductor device of claim 6 , wherein the first contact and the second contact are in electrical contact with the noise reduction well.

14. 5. The semiconductor device of claim 4, further comprising an additional functional layer and an additional insulating layer between the drift layer and the embedded sensor element, the insulating layer being on the drift layer, the additional functional layer being on the insulating layer, the additional insulating layer being on the additional functional layer, and the embedded sensor element being on the additional insulating layer.

15. The semiconductor device of claim 14 , wherein the additional functional layer comprises polysilicon.

16. 15. The semiconductor device of claim 14, wherein the additional functional layer comprises polysilicon that is either at least partially metallized and at least partially silicided.

17. The semiconductor device of claim 14 further comprising a lumped resistive element on the additional insulating layer.

18. the semiconductor device includes an active area; the active area includes one or more implanted regions configured to provide a metal oxide semiconductor field effect transistor (MOSFET); 20. The semiconductor device of claim 17, wherein the lumped resistive element is coupled to a gate of the MOSFET.

19. Further provided with a noise reduction well; the noise reduction well has a doping type that is opposite to the doping type of the shielding well; the noise reduction well is separated from the drift layer by at least a portion of the noise reduction well; 15. The semiconductor device of claim 14, wherein the first contact and the second contact are in electrical contact with the noise reduction well.

20. 4. The semiconductor device of claim 3, further comprising an active area, said active area including one or more implanted regions configured to provide a switching power semiconductor device.

21. 21. The semiconductor device of claim 20, wherein the switching power semiconductor device is a metal oxide semiconductor field effect transistor (MOSFET).

22. 22. The semiconductor device of claim 21, wherein the MOSFET is a vertical MOSFET.

23. 21. The semiconductor device of claim 20, wherein the switching power semiconductor device is one of a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), and a thyristor.

24. 21. The semiconductor device of claim 20, wherein the wide bandgap semiconductor material comprises silicon carbide.

25. 21. The semiconductor device of claim 20, wherein the wide bandgap semiconductor material comprises one of gallium nitride, gallium oxide, and zinc oxide.

26. an intermetal dielectric layer; a sensor contact pad on the inter-metal dielectric layer such that the sensor contact pad at least partially overlaps one of the first contact and the second contact, the sensor contact pad being electrically separated from the first contact and the second contact by a portion of the inter-metal dielectric layer; and 8. The semiconductor device of claim 7, further comprising a via passing through the intermetal dielectric layer such that the via electrically couples the sensor contact pad to the embedded sensor element.

27. The semiconductor device of claim 3 , wherein the embedded sensor element is a diode.

28. providing a drift layer, the drift layer comprising a wide bandgap semiconductor material; A method of manufacturing a semiconductor device comprising providing an embedded sensor element.

29. 30. The method of claim 28, wherein the embedded sensor element is a temperature sensing element.

30. 30. The method of claim 29, further comprising providing an insulating layer between the drift layer and the embedded sensor element.

31. 30. The method of claim 29, further comprising providing a shielding well between the drift layer and the buried sensor element, the shielding well having a doping type that is opposite to a doping type of the drift layer.

32. 32. The method of claim 31 , wherein providing the shielding well comprises implanting the shielding well into the drift layer.

33. providing a first contact in electrical contact with the shielding well; 33. The method of claim 32, further comprising providing a second contact in electrical contact with the shielding well such that the embedded temperature sensing element is between the first contact and the second contact.

34. a first contact well, the first contact well is an implanted region in the shielding well; the first contact well has the same doping type as the shielding well and a doping concentration greater than the doping concentration of the shielding well; providing a first contact well, the first contact being in electrical contact with the shielding well through the first contact well; a second contact well, the second contact well is an implanted region in the shielding well; the second contact well has the same doping concentration as the shielding well and a doping concentration greater than the doping concentration of the shielding well; 34. The method of claim 33, further comprising providing a second contact well, the second contact being in electrical contact with the shielding well through the second contact well.

35. 34. The method of claim 33, wherein the first contact and the second contact are electrically coupled to a fixed potential.

36. 34. The method of claim 33, wherein the first contact and the second contact are provided such that the distance between the first contact and the second contact is less than 200 μm.

37. 37. The method of claim 36, wherein the first contact and the second contact are provided such that the distance between the first contact and the second contact is less than 100 μm.

38. 38. The method of claim 37, wherein the first contact and the second contact are provided such that the distance between the first contact and the second contact is less than 50 μm.

39. 39. The method of claim 38, wherein the first contact and the second contact are provided such that the distance between the first contact and the second contact is at least 5 μm.

40. providing a noise reduction well; the noise reduction well has a doping type that is opposite to the doping type of the shielding well; the noise reduction well is separated from the drift layer by at least a portion of the noise reduction well; 34. The method of claim 33, wherein the first contact and the second contact are in electrical contact with the noise reduction well.

41. 41. The method of claim 40, further comprising providing an additional functional layer and an additional insulating layer between the drift layer and the embedded sensor element, the insulating layer being on the drift layer, the additional functional layer being on the insulating layer, the additional insulating layer being on the additional functional layer, and the embedded sensor element being on the additional insulating layer.

42. 42. The method of claim 41, wherein the additional functional layer comprises polysilicon.

43. 42. The method of claim 41, wherein the additional functional layer comprises polysilicon that is either at least partially metallized and at least partially silicided.

44. 42. The method of claim 41, further comprising providing a lumped resistive element on the additional insulating layer.

45. 45. The method of claim 44, further comprising providing one or more implanted regions in the active area such that the one or more implanted regions provide a metal oxide semiconductor field effect transistor (MOSFET), the lumped resistive element being coupled to a gate of the MOSFET.

46. providing a noise reduction well; the noise reduction well has a doping type that is opposite to the doping type of the shielding well; the noise reduction well is separated from the drift layer by at least a portion of the noise reduction well; 42. The method of claim 41, wherein the first contact and the second contact are in electrical contact with the noise reduction well.

47. 30. The method of claim 29, further comprising providing one or more implanted regions in an active area of ​​the drift layer, the one or more implanted regions configured to provide a switching power semiconductor device.

48. 48. The method of claim 47, wherein the switching power semiconductor device is a metal oxide semiconductor field effect transistor (MOSFET).

49. 49. The method of claim 48, wherein the MOSFET is a vertical MOSFET.

50. 48. The method of claim 47, wherein the switching power semiconductor device is one of a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), and a thyristor.

51. 48. The method of claim 47, wherein the wide bandgap semiconductor material comprises silicon carbide.

52. 48. The method of claim 47, wherein the wide bandgap semiconductor material comprises one of gallium nitride, gallium oxide, and zinc oxide.

53. 30. The method of claim 29, wherein the embedded sensor element is a diode.

54. substrate, a drift layer on the substrate; an insulating layer on the drift layer; a first functional layer on the insulating layer; an additional insulating layer on the first functional layer; and A semiconductor device comprising a lumped resistive element on said additional insulating layer.

55. 55. The semiconductor device of claim 54, wherein the first functional layer comprises polysilicon.

56. 56. The semiconductor device of claim 55, wherein the first functional layer comprises polysilicon that has been either partially metallized and partially silicided.

57. 57. The semiconductor device of claim 56, wherein the semiconductor device comprises an active area including one or more implanted regions in the drift layer, the one or more implanted regions configured to provide a metal-oxide-semiconductor field-effect transistor (MOSFET), and the lumped resistive element is coupled to a gate of the MOSFET.

58. 58. The semiconductor device of claim 57, wherein the first functional layer provides a gate electrode of the MOSFET.

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