Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device in which bonding reliability of wire bonding is improved.SOLUTION: A semiconductor device includes a semiconductor chip, a die pad, an inner lead, and a bonding wire. The semiconductor chip has a first lower surface and a bonding pad provided on a first upper surface. The bonding pad has a second upper surface. The die pad has a third upper surface. The inner lead has a fourth upper surface. The semiconductor chip is disposed on the die pad such that the first lower surface faces the third upper surface. The bonding wire electrically connects the bonding pad and the inner lead to each other. In a cross-sectional view, the second upper surface of the bonding pad to which the bonding wire is connected is located at the same height as the fourth upper surface of the inner lead to which the bonding wire is connected.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] The semiconductor device described in JP 2017-135230 A (Patent Document 1) has a lead frame having leads and a die pad, a semiconductor chip, and bonding wires. The semiconductor chip is disposed on the die pad. The semiconductor chip has bonding pads on its upper surface. The bonding wires connect the upper surfaces of the bonding pads to the upper surfaces of the leads. The semiconductor device described in JP 2018-107296 A (Patent Document 2) has a similar configuration to the semiconductor device described in Patent Document 1. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-135230 [Patent Document 2] Japanese Patent Application Publication No. 2018-107296 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device described in Patent Document 1 and the semiconductor device described in Patent Document 2, the upper surface of the bonding pad connected to the bonding wire is located at a different height from the upper surface of the lead connected to the bonding wire. Therefore, in the semiconductor device described in Patent Document 1 and the semiconductor device described in Patent Document 2, connection failures may occur during wire bonding. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0005] The semiconductor device of the present disclosure includes a semiconductor chip, a die pad, leads, and bonding wires. The semiconductor chip has a first lower surface and a first upper surface opposite the first lower surface. The semiconductor chip has bonding pads provided on the first upper surface. The bonding pads have a second upper surface. The die pad has a third upper surface. The leads have outer leads and inner leads. The inner leads have a fourth upper surface. The inner leads are connected to the outer leads. The semiconductor chip is disposed on the die pad so that the first lower surface faces the third upper surface. The bonding wire electrically connects the bonding pads to the inner leads. In a cross-sectional view, the second upper surface of the bonding pad to which the bonding wire is connected is located at the same height as the fourth upper surface of the inner lead to which the bonding wire is connected. [Effects of the Invention]

[0006] According to the semiconductor device of the present disclosure, the bonding reliability of wire bonding is improved. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a cross-sectional view of the semiconductor device DEV1. [Figure 2] 10A to 10C are manufacturing process diagrams of the semiconductor device DEV1. [Figure 3] FIG. 10 is a cross-sectional view illustrating a semiconductor chip mounting step S3. [Figure 4] FIG. 2 is a schematic diagram of a bonding apparatus BAP. [Figure 5] FIG. 10 is a first cross-sectional view illustrating a wire bonding step S4. [Figure 6] FIG. 2 is a second explanatory diagram illustrating the wire bonding step S4. [Figure 7] FIG. 10 is a third cross-sectional view illustrating the wire bonding step S4. [Figure 8] FIG. 4 is a fourth explanatory diagram illustrating the wire bonding step S4. [Figure 9] FIG. 2 is a cross-sectional view of the semiconductor device DEV2. [Figure 10] FIG. 10 is a first cross-sectional view illustrating a wire bonding step S4 in the manufacturing method of the semiconductor device DEV2. [Figure 11] FIG. 10 is a second cross-sectional view illustrating a wire bonding step S4 in the manufacturing method of the semiconductor device DEV2. [Figure 12] FIG. 10 is a cross-sectional view of a semiconductor device DEV3 according to a modified example. [Figure 13] FIG. 10 is a cross-sectional view of the semiconductor device DEV4. DETAILED DESCRIPTION OF THE INVENTION

[0008] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0009] (First embodiment) The semiconductor device DEV1 according to the first embodiment will be described.

[0010] <Configuration of semiconductor device DEV1> The configuration of the semiconductor device DEV1 will be described below.

[0011] As shown in FIG. 1, the semiconductor device DEV1 includes a semiconductor chip SC, a lead frame LF, a bonding material JM, bonding wires BW, and a sealing body EB.

[0012] The semiconductor chip SC has a top surface US1 and a bottom surface BS1 located on the opposite side of the top surface US1. The semiconductor chip SC has bonding pads BP provided on the top surface US1. The bonding pads BP have a top surface US2. The bonding pads BP are made of, for example, aluminum or an aluminum alloy.

[0013] The lead frame LF has a die pad DP and a plurality of leads LD. The die pad DP has an upper surface US3. The leads LD have outer leads OL and inner leads IL. The inner leads IL have an upper surface US4. The inner leads IL are connected to the outer leads OL. The lead frame LF is made of, for example, a copper alloy. A plating film PL may be formed on the upper surface US3.

[0014] The semiconductor chip SC is disposed on the die pad DP so that the bottom surface BS1 faces the top surface US3. A bonding material JM is interposed between the semiconductor chip SC (bottom surface BS1) and the die pad DP (top surface US3). The bonding material JM is formed of, for example, an adhesive.

[0015] The bonding wire BW has an end BWa and an end BWb located opposite the end BWa. The bonding wire BW electrically connects the top surface US2 and the top surface US4 to each other. More specifically, the bonding wire BW is connected to the top surface US2 at the end BWa and to the top surface US4 at the end BWb. The bonding wire BW is made of, for example, copper or a copper alloy. The bonding wire BW may also be made of gold, a gold alloy, silver, or a silver alloy.

[0016] The sealing body EB has a front surface FS, a back surface RS located opposite the front surface FS, and a side surface SS located between the front surface FS and the back surface RS. The sealing body EB also covers the semiconductor chip SC, the die pad DP, the inner leads IL, and the bonding wires BW. However, the outer leads OL protrude from the side surface SS of the sealing body EB. The sealing body EB is formed of, for example, epoxy resin. The outer leads OL have, for example, a gull-wing shape. The outer leads OL may also have a J-shape. The semiconductor device DEV1 is, for example, a QFP (Quad Flat Package), a PLCC (Plastic Leaded Chip Carrier), a SOP (Small Outline Package), or a SOJ (Small Outline J-leaded) type package.

[0017] 1, the upper surface US2 of the bonding pad BP to which the bonding wire BW (end BWa) is connected is located at the same height as the upper surface US4 of the inner lead IL to which the bonding wire BW (end BWb) is connected. Note that if the difference in height between the upper surface US2 to which the bonding wire BW is connected and the upper surface US4 to which the bonding wire BW is connected is 90 μm or less in cross-sectional view, the upper surface US2 of the bonding pad BP to which the bonding wire BW is connected is considered to be located at the same height as the upper surface US4 of the inner lead IL to which the bonding wire BW is connected.

[0018] <Method of Manufacturing Semiconductor Device DEV1> A method for manufacturing the semiconductor device DEV1 will be described below.

[0019] As shown in FIG. 2, the method for manufacturing the semiconductor device DEV1 includes a preparation step S1, a preparation step S2, a semiconductor chip mounting step S3, a wire bonding step S4, and a sealing step S5.

[0020] In the preparation step S1, a semiconductor chip SC is prepared. In the preparation step S2, a lead frame LF is prepared. However, at this stage, the gull-wing shape of the outer leads OL has not yet been formed. After the preparation steps S1 and S2, a semiconductor chip mounting step S3 is performed.

[0021] As shown in FIG. 3, in the semiconductor chip mounting process S3, the semiconductor chip SC is mounted on the die pad DP. In the semiconductor chip mounting process S3, first, a bonding material JM is applied to the upper surface US3. Second, the semiconductor chip SC is placed on the die pad DP so that the lower surface BS1 faces the upper surface US3 with the bonding material JM interposed therebetween. Third, heating is performed, thereby bonding the semiconductor chip SC and the die pad DP with the bonding material JM. This mechanically connects the semiconductor chip SC to the die pad DP. After the semiconductor chip mounting process S3, a wire bonding process S4 is performed.

[0022] In the wire bonding step S4, the top surface US2 and the top surface US4 are electrically connected to each other via a bonding wire BW.

[0023] The thickness of the semiconductor chip SC is defined as thickness T1, and the thickness of the bonding material JM is defined as thickness T2 (see FIG. 1). The difference in height between the upper surface US4 of the inner lead IL to which the bonding wire BW (end BWb) is connected and the upper surface US3 of the die pad DP is defined as distance DIS (see FIG. 1). In the preparation step S1, the semiconductor chip SC is selected so that the sum of thicknesses T1 and T2 is equal to distance DIS. Thickness T1 is adjusted, for example, by the amount of polishing when polishing the lower surface BS1 side. Thickness T2 is adjusted, for example, by the amount of bonding material JM applied to the upper surface US3. In the preparation step S2, the lead frame LF is selected so that the distance DIS is equal to the sum of thicknesses T1 and T2. The distance DIS is adjusted, for example, by the amount of press processing when forming the die pad DP, in other words, the amount of bending (offset amount) of the suspension leads (not shown) that support the die pad DP. This allows the upper surface US2 to which the bonding wires BW are connected to be positioned at the same height as the upper surface US4 to which the bonding wires BW are connected.

[0024] More specifically, the wire bonding step S4 is performed using a bonding apparatus BAP. As shown in FIG. 4, the bonding apparatus BAP has a stage STG, a bonding head BH, a transducer TD, and a capillary CP. The bonding head BH is disposed on the stage STG. The stage STG is an XY stage. The stage STG moves the bonding head BH within a horizontal plane. However, the stage STG cannot move the bonding head BH in a direction perpendicular to the horizontal plane. Note that in FIGS. 5 to 8, the stage STG and the bonding head BH of the bonding apparatus BAP are not shown.

[0025] The transducer TD has ends TDa and TDb. The end TDb is located opposite the end TDa. The transducer TD is connected to the bonding head BH at the end TDa. The bonding head BH can move the end TDb in an arc. The capillary CP has ends CPa and CPb. The end CPb is located opposite the end CPa. The capillary CP is attached to the end of the transducer TD on the TDb side at the end CPa. The capillary CP holds the bonding wire BW at the end CPb.

[0026] In the wire bonding step S4, first, as shown in FIG. 5, the lead frame LF, on which the semiconductor chip SC is mounted on the die pad DP, is attached to a holding jig JIG. The holding jig JIG has a heater block HB and a frame holder FP. The lead frame LF is placed on the heater block HB and then pressed against the heater block HB by the frame holder FP. This attaches the lead frame LF to the holding jig JIG. The heater block HB heats the semiconductor chip SC and the lead frame LF while bonding is being performed with the bonding wires BW.

[0027] Second, as shown in FIG. 6, the end BWa is connected to the top surface US2. The connection of the end BWa to the top surface US2 is achieved by applying ultrasonic waves to the bonding interface between the end BWa and the top surface US2 while the end BWa is in contact with the top surface US2. This ultrasonic wave is generated by applying a voltage to a piezoelectric element built into the transducer TD to vibrate the transducer TD, and is applied to the bonding interface through the capillary CP. When ultrasonic waves are applied to the bonding interface between the end BWa and the top surface US2, alloying occurs at the bonding interface, resulting in bonding. At this time, the extension direction of the capillary CP is parallel to the normal direction (direction D2 in FIG. 4) of the horizontal plane (direction D1 in FIG. 4) along which the bonding head BH moves. In other words, the capillary contact angle between the extension direction of the capillary CP and the top surface US2 is 90°. Furthermore, if the angle between the direction in which the capillary CP extends and the direction of the normal to the horizontal surface on which the bonding head BH moves is within the range of 90°±0.5°, the direction in which the capillary CP extends and the direction of the normal to the horizontal surface on which the bonding head BH moves are considered to be parallel (the capillary contact angle is 90°).

[0028] 7, the stage STG moves the bonding head BH until the end BWb held by the capillary CP is positioned above the upper surface US4. At this time, the bonding head BH moves the end TDb in an arc, tilting the extension direction of the capillary CP relative to the normal to the horizontal plane on which the bonding head BH moves, thereby raising the position of the end BWb and forming a loop of the bonding wire BW. When the end BWb has moved above the upper surface US4, the bonding head BH returns the extension direction of the capillary CP to a state parallel to the normal to the horizontal plane on which the bonding head BH moves.

[0029] Fourth, as shown in FIG. 8, ultrasonic waves are applied to the bonding interface between the end BWb and the upper surface US4 while the end BWa is in contact with the upper surface US2. At this time, the extending direction of the capillary CP is parallel to the normal to the horizontal plane along which the bonding head BH moves. That is, at this time, the capillary contact angle between the extending direction of the capillary CP and the upper surface US4 is 90°. After the wire bonding step S4, an encapsulation step S5 is performed. In the encapsulation step S5, a encapsulant EB is formed by, for example, a transfer molding method to cover the semiconductor chip SC, die pad DP, inner leads IL, and bonding wires BW. After the encapsulation step S5, the outer leads OL are bent to form the outer leads OL into a gull-wing shape. In this manner, the structure of the semiconductor device DEV1 shown in FIG. 1 is formed.

[0030] <Effects of semiconductor device DEV1> The effects of the semiconductor device DEV1 will be described below in comparison with a semiconductor device DEV2 according to a comparative example investigated by the present inventors.

[0031] 9, the semiconductor device DEV2 includes a lead frame LF, a semiconductor chip SC, bonding wires BW, and a sealing body EB. In this respect, the configuration of the semiconductor device DEV2 is common to the configuration of the semiconductor device DEV1.

[0032] 9, in the semiconductor device DEV2, the top surface US2 to which the bonding wire BW is connected is not located at the same height as the top surface US4 to which the bonding wire BW is connected. More specifically, in the semiconductor device DEV2, the top surface US2 to which the bonding wire BW is connected is located lower than the top surface US4 to which the bonding wire BW is connected. In this respect, the configuration of the semiconductor device DEV2 differs from the configuration of the semiconductor device DEV1.

[0033] As shown in Figures 10 and 11, in the manufacturing method of the semiconductor device DEV2, the stage STG cannot move the bonding head BH in a direction perpendicular to the horizontal plane. Therefore, as shown in Figure 11, if the capillary contact angle is adjusted to 90° when connecting the end BWb to the top surface US4, the capillary contact angle cannot be adjusted to 90° when connecting the end BWa to the top surface US2. If the capillary CP is tilted with respect to the top surface US2, ultrasonic waves are not uniformly supplied to the bonding interface. As a result, alloying does not proceed easily at the bonding interface, a sufficient bonding area is not obtained, and bonding reliability is insufficient. This problem is more pronounced when the bonding wire BW is made of copper or a copper alloy, because diffusion for alloying is difficult to occur. Note that, although not shown, adjusting the capillary contact angle to 90° when connecting the end BWa to the top surface US2 would result in a similar connection failure at the bonding interface between the end BWb and the top surface US4.

[0034] On the other hand, in the semiconductor device DEV1, the top surface US2 to which the bonding wire BW is connected is located at the same height as the top surface US4 to which the bonding wire BW is connected. Therefore, in the semiconductor device DEV1, the capillary contact angle when connecting the end BWa to the top surface US2 and the capillary contact angle when connecting the end BWb to the top surface US4 can both be set to 90°, thereby achieving good bonding at both the interface between the end BWa and the top surface US2 and the interface between the end BWb and the top surface US4, thereby improving the bonding reliability of the wire bonding.

[0035] <Modification> A modification of the semiconductor device DEV1 will be described below.

[0036] FIG. 12 shows a semiconductor device DEV3 as a modification of the semiconductor devices DEV1 and DEV2. As shown in FIG. 12, the semiconductor device DEV3 includes a lead frame LF, a semiconductor chip SC, bonding wires BW, and a sealing body EB. In this respect, the configuration of the semiconductor device DEV3 is common to that of the semiconductor device DEV1. However, while the lower surface BS3 of the die pad DP of the semiconductor devices DEV1 and DEV2 is covered with the sealing body EB as shown in FIGS. 1 to 9, in the semiconductor device DEV3, the lower surface BS3 of the die pad DP is exposed from the sealing body EB at the back surface RS of the sealing body EB as shown in FIG. 12. Therefore, the upper surface US1 of the semiconductor chip SC of the semiconductor device DEV3 is located lower than the upper surfaces US1 of the semiconductor chips SC of the semiconductor devices DEV1 and DEV2 (see FIGS. 1, 9, and 12).

[0037] 12, the inner lead IL has a base end ILa and a tip end ILb. The base end ILa is connected to the outer lead OL. The tip end ILb is located on the tip side of the inner lead IL. The tip end ILb is located lower than the base end ILa. That is, the tip end ILb is located closer to the back surface RS of the sealing body EB than the base end ILa. The bonding wire BW (end BWb) is connected to the top surface US4 located at the tip end ILb. That is, the top surface US4 located at the tip end ILb is located at the same height as the top surface US2 to which the bonding wire BW (end BWa) is connected. The tip end ILb located lower than the base end ILa is obtained by, for example, bending the inner lead IL. In this embodiment, the bending is performed at the stage of preparing the lead frame LF.

[0038] (Second embodiment) A semiconductor device DEV4 according to the second embodiment will be described below, focusing mainly on the differences from the semiconductor device DEV1, and overlapping descriptions will not be repeated.

[0039] 13, the semiconductor device DEV4 includes a lead frame LF, a semiconductor chip SC, bonding wires BW, and a sealing body EB. In the semiconductor device DEV4, the top surface US2 to which the bonding wires BW are connected is located at the same height as the top surface US4 to which the bonding wires BW are connected. In these respects, the configuration of the semiconductor device DEV4 is common to the configuration of the semiconductor device DEV1.

[0040] In the semiconductor device DEV4, the lower surfaces (lower surface BS2) of the outer leads OL are exposed from the sealing body EB at the back surface RS of the sealing body EB. That is, the semiconductor device DEV4 is a QFN (Quad Flat Non-leaded package). In the semiconductor device DEV4, the tip end ILb is located higher than the base end ILa. That is, the tip end ILb is located closer to the front surface FS of the sealing body EB than the base end ILa. In the semiconductor device DEV4, the bonding wire BW (end BWb) is connected to the top surface US4 located at the tip end ILb. As a result, in the semiconductor device DEV4, the top surface US4 connected to the bonding wire BW is located at the same height as the top surface US2 to which the bonding wire BW is connected. In these respects, the configuration of the semiconductor device DEV4 differs from the configuration of the semiconductor device DEV1. Note that, in the semiconductor device DEV4, a configuration in which the bottom surface BS3 of the die pad DP is exposed from the back surface RS of the sealing body EB has been described. However, the bottom surface BS3 of the die pad DP may be covered by the sealing body EB as in the semiconductor device DEV1.

[0041] In the semiconductor device DEV4, the tip end ILb located above the base end ILa is obtained by bending the inner lead IL. In the semiconductor device DEV4, the top surface US2 to which the bonding wire BW is connected is also located at the same height as the top surface US4 to which the bonding wire BW is connected, so that, similar to the semiconductor device DEV1, the capillary contact angle when connecting the end BWa to the top surface US2 and the capillary contact angle when connecting the end BWb to the top surface US4 can both be 90°, and good bonding can be obtained at both the interface between the end BWa and the top surface US2 and the interface between the end BWb and the top surface US4.

[0042] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0043] BAP bonding equipment, BH bonding head, BP bonding pad, BS1, BS2, BS3 bottom surface, BW bonding wire, BWa, BWb ends, CP capillary, CPa, CPb ends, DEV1, DEV2, DEV3, DEV4 semiconductor device, DIS distance, DP die pad, EB encapsulation body, FP frame holder, FS surface, HB heater block, IL inner lead, ILa base end, ILb tip end, JM bonding material, JIG holding jig, LD lead, LF lead frame, OL outer lead, PL plating film, RS back surface, S1, S2 preparation process, S3 semiconductor chip mounting process, S4 wire bonding process, S5 encapsulation process, SC semiconductor chip, SS side surface, STG stage, T1, T2 thickness, TD transducer, TDa, TDb ends, US1, US2, US3, US4 top surface.

Claims

1. A semiconductor chip; A die pad; Lead and a bonding wire; the semiconductor chip has a first lower surface and a first upper surface opposite the first lower surface; the semiconductor chip has bonding pads provided on the first top surface; the bonding pad has a second upper surface; the die pad has a third top surface; The leads include an outer lead and an inner lead, the inner lead has a fourth upper surface; the inner lead is connected to the outer lead, the semiconductor chip is disposed on the die pad such that the first lower surface faces the third upper surface; the bonding wire electrically connects the bonding pad and the inner lead to each other, A semiconductor device, wherein, in a cross-sectional view, the second upper surface of the bonding pad to which the bonding wire is connected is located at the same height as the fourth upper surface of the inner lead to which the bonding wire is connected.

2. Further, a bonding material is interposed between the first lower surface and the third upper surface, 2. The semiconductor device according to claim 1, wherein the sum of the thickness of said semiconductor chip and the thickness of said bonding material is equal to the height difference between said third upper surface and said fourth upper surface to which said bonding wire is connected.

3. further comprising an encapsulant covering the semiconductor chip, the die pad, the inner leads, and the bonding wires; The encapsulant has a side surface, The semiconductor device according to claim 1 , wherein the outer leads protrude from the side surfaces.

4. the die pad has a third lower surface; the sealing body has a front surface, a back surface opposite to the front surface, and the side surface located between the front surface and the back surface, the third lower surface of the die pad is exposed from the back surface of the sealing body, the inner lead has a base end connected to the outer lead and a tip end located closer to the back surface of the sealing body than the base end in a cross-sectional view, 4. The semiconductor device according to claim 3, wherein said bonding wire is connected to said fourth upper surface located at said tip end.

5. 5. The semiconductor device according to claim 4, wherein said outer leads have a gull-wing shape.

6. further comprising an encapsulant covering the semiconductor chip, the die pad, the inner leads, the outer leads, and the bonding wires; The encapsulant has a back surface, the outer lead has a second lower surface; The semiconductor device according to claim 1 , wherein the second lower surface is exposed from the sealing body at the rear surface.

7. the sealing body has a front surface, a back surface opposite to the back surface, and a side surface located between the front surface and the back surface, the inner lead has a base end connected to the outer lead and a tip end located closer to the back surface of the sealing body than the base end in a cross-sectional view, 7. The semiconductor device according to claim 6, wherein said bonding wire is connected to said fourth upper surface located at said tip end.

8. 2. The semiconductor device according to claim 1, wherein said bonding wires are made of copper or a copper alloy.

9. providing a semiconductor chip having a first lower surface, a first upper surface opposite the first lower surface, and a second upper surface, the semiconductor chip having bonding pads disposed on the first upper surface; providing a lead frame including a die pad having a third top surface and leads having inner leads having a fourth top surface; mounting the semiconductor chip on the die pad so that the first lower surface faces the third upper surface; and electrically connecting the bonding pad and the inner lead to each other via a bonding wire using a bonding device, the bonding apparatus includes a bonding head, a stage for moving the bonding head in a horizontal plane, a transducer having a first end and a second end and connected to the bonding head at the first end, and a capillary connected to the second end and holding the bonding wire; the bonding wire has one end and another end, The step of electrically connecting the second upper surface of the bonding pad and the fourth upper surface of the inner lead to each other via the bonding wire includes: connecting the one end to the second upper surface; a step of moving the bonding head until the other end is positioned above the fourth upper surface while causing the second end to move in an arc so that the extending direction of the capillary is inclined with respect to a normal direction of the horizontal surface; and connecting the other end to the fourth upper surface, A method for manufacturing a semiconductor device, wherein the extending direction of the capillary is parallel to the normal direction when the one end is connected to the second top surface and when the other end is connected to the fourth top surface.

10. In the step of mounting the semiconductor chip, a bonding material is interposed between the first lower surface and the third upper surface, 10. The method for manufacturing a semiconductor device according to claim 9, wherein in the step of preparing the semiconductor chip, the semiconductor chip is selected so that the sum of the thickness of the semiconductor chip and the thickness of the bonding material is equal to the height difference between the third upper surface and the fourth upper surface to which the other end is connected.

11. In the step of mounting the semiconductor chip, a bonding material is interposed between the first lower surface and the third upper surface, 10. The method for manufacturing a semiconductor device according to claim 9, wherein in the step of preparing the lead frame, the lead frame is selected so that the height difference between the third upper surface and the fourth upper surface to which the other end is connected is equal to the sum of the thickness of the semiconductor chip and the thickness of the bonding material.

12. the semiconductor device further includes an encapsulant covering the semiconductor chip, the die pad, the inner leads, and the bonding wires; the die pad has a third lower surface; the sealing body has a front surface, a back surface opposite to the front surface, and a side surface located between the front surface and the back surface, the third lower surface of the die pad is exposed from the back surface of the sealing body, the inner lead has a base end and a tip end, The lead has an outer lead connected to the inner lead, the base end is connected to the outer lead, 10. The method for manufacturing a semiconductor device according to claim 9, wherein the lead frame is bent so that the tip end is positioned closer to the back surface of the sealing body than the base end.

13. the semiconductor device further includes an encapsulant covering the semiconductor chip, the die pad, the inner leads, and the bonding wires; the die pad has a third lower surface; the sealing body has a front surface, a back surface opposite to the front surface, and a side surface located between the front surface and the back surface, the third lower surface of the die pad is exposed from the back surface of the sealing body, the inner lead has a base end and a tip end, The lead has an outer lead connected to the inner lead, the base end is connected to the outer lead, 10. The method for manufacturing a semiconductor device according to claim 9, wherein the lead frame is bent so that the tip end is positioned closer to the surface of the sealing body than the base end.

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