Semiconductor device

Abstract

To provide a semiconductor element having stable electric characteristics and improved reliability.SOLUTION: The main transistor includes a main channel layer 132m, a main gate 155m disposed on the main channel layer, a main gate layer 152m disposed between the main channel layer and the main gate, a source 170 and a drain 190 disposed at both sides of the main gate and connected to the main channel layer, and a field dispersion layer 310 disposed on the main channel layer and between the main gate and the drain.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices. [Background technology]

[0002] In modern society, semiconductor devices are closely related to daily life. In particular, the importance of power semiconductor devices, which are used in various fields such as transportation (e.g., electric vehicles, railways, and electric trams), renewable energy systems (e.g., solar power generation and wind power generation), and mobile devices, is gradually increasing. Power semiconductor devices are semiconductor devices used to handle high voltages and high currents, and perform functions such as power conversion and control in large power systems and high-power electronic devices. Power semiconductor devices have the ability and durability to handle high power, handle large amounts of current, and withstand high voltages. For example, power semiconductor devices can handle voltages from hundreds to thousands of volts and currents from tens to thousands of amperes. Power semiconductor devices can minimize power loss and improve electrical energy efficiency. Furthermore, power semiconductor devices can operate stably even in high-temperature environments.

[0003] These power semiconductor devices are categorized by material, such as SiC power semiconductor devices and GaN power semiconductor devices. By manufacturing power semiconductor devices using SiC or GaN instead of existing silicon (Si), it is possible to compensate for the disadvantage of silicon, which has unstable properties at high temperatures. SiC power semiconductor devices are resistant to high temperatures and have low power loss, making them suitable for electric vehicles and renewable energy systems. GaN power semiconductor devices are expensive but efficient in terms of speed, making them suitable for fast charging of mobile devices. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a semiconductor element having stable electrical characteristics and improved reliability. [Means for solving the problem]

[0005] In order to achieve the above object, according to one aspect of the present invention, a semiconductor device includes a main transistor and a sub-transistor connected to one end of the main transistor, wherein the main transistor includes a main channel layer, a main gate electrode located on the main channel layer, a main gate semiconductor layer located between the main channel layer and the main gate electrode, source and drain electrodes located on both sides of the main gate electrode and connected to the main channel layer, and a field distribution layer located on the main channel layer and between the main gate electrode and the drain electrode, and the sub-transistor includes a drift region having a two-dimensional electron gas, a sub-channel layer including a first contact portion connected to the source electrode, a second contact portion connected to the field distribution layer, and an extension portion connecting the first contact portion and the second contact portion, and a sub-gate electrode located on the extension portion of the sub-channel layer and connected to the main gate electrode.

[0006] According to another aspect of the present invention, there is provided a semiconductor device including a main channel layer, a gate electrode located on the main channel layer, a gate semiconductor layer located between the main channel layer and the gate electrode, source and drain electrodes located on both sides of the gate electrode and connected to the main channel layer, a field dispersion layer located on the main channel layer and between the gate electrode and the drain electrode, and a drift region having a two-dimensional electron gas, the sub-channel layer including a first contact portion connected to the source electrode, a second contact portion connected to the field dispersion layer, and an extension portion connecting the first contact portion and the second contact portion, wherein the gate electrode overlaps the extension portion of the sub-channel layer in a thickness direction of the sub-channel layer.

[0007] According to another aspect of the present invention, there is provided a semiconductor device including a main transistor and a sub-transistor connected to one end of the main transistor, the main transistor including a main channel layer including GaN, a barrier layer located on the main channel layer and including AlGaN, a main gate electrode located on the barrier layer, a main gate semiconductor layer located between the main channel layer and the main gate electrode and including GaN doped with p-type impurities, source and drain electrodes located on both sides of the main gate electrode and connected to the main channel layer, and a first gate electrode located on the main gate electrode and the barrier layer. the sub-transistor includes a protection layer and a field diffusion layer located on the first protection layer and between the main gate electrode and the drain electrode; the sub-transistor includes a sub-channel layer located on one side of the main channel layer, the sub-channel layer including a first contact portion made of the same material as the main channel layer and connected to the source electrode through the barrier layer, a second contact portion made of the same material as the main channel layer and connected to the field diffusion layer through the first protection layer and the barrier layer, and an extension portion connecting the first contact portion and the second contact portion; and a sub-gate electrode located on the extension portion of the sub-channel layer, connected to the main gate electrode, and made of the same material as the main gate electrode. [Effects of the Invention]

[0008] According to the present invention, even if a short circuit occurs in a specific circuit within a semiconductor device, it is possible to prevent destruction of a high electron mobility transistor due to a short circuit current, thereby making it possible to provide a semiconductor device including a high electron mobility transistor with improved reliability. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a circuit diagram illustrating a semiconductor device according to an embodiment. [Figure 2] 1 is a circuit diagram illustrating a semiconductor device according to an embodiment. [Figure 3] FIG. 3 is a plan view showing the semiconductor device of FIGS. 1 and 2. [Figure 4] FIG. 4 is a cross-sectional view taken along line AA' in FIG. [Figure 5] FIG. 4 is a cross-sectional view taken along line AA' in FIG. [Figure 6] FIG. 4 is a cross-sectional view taken along line BB' in FIG. [Figure 7] FIG. 4 is a cross-sectional view taken along the line CC' in FIG. [Figure 8] FIG. 4 is a cross-sectional view taken along the line DD' in FIG. [Figure 9] 4 is a cross-sectional view corresponding to line AA' of FIG. 3 showing a semiconductor device according to some embodiments. [Figure 10] 4 is a cross-sectional view corresponding to line BB' of FIG. 3 showing a semiconductor device according to some embodiments. [Figure 11] 4 is a cross-sectional view corresponding to line DD' of FIG. 3 illustrating a semiconductor device according to some embodiments. [Figure 12] FIG. 1 is a plan view of a semiconductor device according to some embodiments. [Figure 13] FIG. 1 is a plan view of a semiconductor device according to some embodiments. [Figure 14] FIG. 1 is a plan view of a semiconductor device according to some embodiments. [Figure 15] FIG. 1 is a plan view of a semiconductor device according to some embodiments. [Figure 16] FIG. 1 is a plan view of a semiconductor device according to some embodiments. [Figure 17] FIG. 1 is a plan view of a semiconductor device according to some embodiments. [Figure 18] FIG. 1 is a circuit diagram illustrating a semiconductor device according to some embodiments. [Figure 19] FIG. 19 is a plan view showing the semiconductor device according to the embodiment of FIG. 18. [Figure 20] FIG. 20 is a cross-sectional view taken along line EE' in FIG. [Figure 21] FIG. 20 is a cross-sectional view taken along line FF' in FIG. [Figure 22] FIG. 19 is a plan view showing the semiconductor device according to the embodiment of FIG. 18. [Figure 23] FIG. 23 is a cross-sectional view taken along line GG' in FIG. 22. [Figure 24] 1A to 1C are plan views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment. [Figure 25] 25 is a cross-sectional view taken along the lines HH' and II' in FIG. 24. [Figure 26] 25 is a cross-sectional view taken along the lines HH' and II' in FIG. 24. [Figure 27] 1A to 1C are plan views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment. [Figure 28] 28 is a cross-sectional view taken along lines JJ' and K-K' in FIG. 27. [Figure 29] 1A to 1C are plan views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment. [Figure 30] 30 is a cross-sectional view taken along lines LL' and MM' in FIG. 29. DETAILED DESCRIPTION OF THE INVENTION

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention may be embodied in various different forms and is not limited to the embodiments set forth herein.

[0011] Furthermore, the size and thickness of each component shown in the drawings are arbitrarily shown for the sake of convenience, and the present invention is not necessarily limited to those shown in the drawings. In the drawings, the thicknesses of some layers and regions are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for the sake of convenience.

[0012] Furthermore, when a layer, film, region, plate, or other part is said to be "on" another part, this does not only mean that it is "directly on" that part, but also includes cases where there is another part in between. Conversely, when a part is said to be "directly on" another part, it means that there is no other part in between. Furthermore, when a part is said to be "on" a reference part, it means that it is located above or below the reference part, and does not necessarily mean that it is located "on" in the opposite direction of gravity.

[0013] Also, throughout the specification, when a part is said to "comprise" a certain element, this means that it may further include other elements, rather than excluding other elements, unless specifically stated to the contrary.

[0014] Also, throughout the specification, when we say "in a plane," we mean when we look at the part in question from above, and when we say "in cross section," we mean when we look at a vertical cross section of the part in question from the side.

[0015] FIG. 1 is a circuit diagram showing a semiconductor device according to an embodiment.

[0016] First, as shown in FIG. 1, a semiconductor device according to an embodiment includes a main device region MA including a main transistor 100 and a peripheral circuit region PA including a sub-transistor 320.

[0017] The main transistor 100 is located within the main device region MA. For example, the main transistor 100 of the semiconductor device according to an embodiment is a normally-off high electron mobility transistor (HEMT). However, without being limited thereto, the main transistor 100 of the semiconductor device according to an embodiment may be a normally-on high electron mobility transistor. That is, the main device region MA in an embodiment refers to a region in which the main transistor 100 is located.

[0018] In one embodiment, the main transistor 100 includes a gate electrode G, a first electrode D, and a second electrode S. The main transistor 100 controls the drain-source current between the first electrode D and the second electrode S by a gate signal applied to the gate electrode G. For example, when a turn-on signal is applied to the gate electrode G of the main transistor 100, a current flows from the first electrode D to the second electrode S. The first electrode D is connected to a first power supply voltage V D is supplied to the second electrode S, and a second power supply voltage V S The second power supply voltage V S The magnitude of the first power supply voltage V D For example, the magnitude of the second power supply voltage V S is the ground voltage. Here, the first electrode D refers to the drain electrode (190 in FIG. 3) of the main transistor 100 according to an embodiment, and the second electrode S refers to the source electrode (170 in FIG. 3) of the main transistor 100 according to an embodiment. Also, the first power supply voltage V D means the voltage supplied to the drain electrode (190 in FIG. 3) of the main transistor 100. S means the voltage supplied to the source electrode (170 in FIG. 3) of the main transistor 100. In the examples shown herein, the terms "source electrode" and "drain electrode" are understood to mean the source terminal region and drain terminal region of either the main transistor 100 or the sub-transistor 320, respectively.

[0019] The main transistor 100 includes a field dispersion layer 310. The field dispersion layer 310 is located between the gate electrode G and the first electrode D of the main transistor 100 and serves to disperse the electric field concentrated around the gate electrode G of the main transistor 100. This reduces leakage current in the main transistor 100 and increases the breakdown voltage of the main transistor 100. This will be described in detail later with reference to FIG. 3.

[0020] According to an embodiment, the peripheral circuit region PA of the semiconductor device includes elements electrically connected to the main transistor 100. Specifically, according to an embodiment, the peripheral circuit region PA of the semiconductor device includes a sub-transistor 320 electrically connected to one end of the main transistor 100. According to an embodiment, the sub-transistor 320 provides insulation between the second electrode S of the main transistor 100 and the field distribution layer 310 and discharges charges electrified in the field distribution layer 310 of the main transistor 100 to the second electrode S of the main transistor 100. However, without being limited thereto, for example, the peripheral circuit region PA may further include passive elements such as a capacitor or an inductor in addition to the sub-transistor 320, or may further include active elements such as an integrated circuit (IC) chip. As another example, the peripheral circuit region PA may further include a current divider, a voltage divider, a voltage clipper, a protection element for the main transistor 100, etc. In one embodiment, the peripheral circuit area PA refers to the area where the sub-transistor 320 is arranged.

[0021] In one embodiment, the sub-transistor 320 includes a gate electrode Ga, a first electrode Da, and a second electrode Sa. The sub-transistor 320 controls the drain-source current between the first electrode Da and the second electrode Sa by a gate signal applied to the gate electrode Ga.

[0022] The sub-transistor 320 is electrically connected to one end of the main transistor 100. For example, a first electrode Da of the sub-transistor 320 is electrically connected to the field spreading layer 310, and a second electrode Sa of the sub-transistor 320 is electrically connected to the second electrode S of the main transistor 100. The second electrode Sa of the sub-transistor 320 is connected to a second power supply voltage V S The second power source is electrically connected to the second power source.

[0023] In addition, the gate electrode Ga of the sub-transistor 320 is electrically connected to the gate electrode G of the main transistor 100. Therefore, the same signal is applied to the gate electrode Ga of the sub-transistor 320 and the gate electrode G of the main transistor 100. For example, when a turn-on signal is applied to the gate electrode G of the main transistor 100, the same turn-on signal is also applied to the gate electrode Ga of the sub-transistor 320. In addition, when a turn-off signal is applied to the gate electrode G of the main transistor 100, the same turn-off signal is also applied to the gate electrode Ga of the sub-transistor 320. Therefore, when a turn-on signal is applied to the gate electrode G of the main transistor 100, a current flows from the first electrode D to the second electrode S of the main transistor 100, and a current flows from the first electrode Da to the second electrode Sa of the sub-transistor 320.

[0024] Here, the first electrode Da of the sub-transistor 320 corresponds to the field spreading layer (310 in FIG. 3) of the sub-transistor 320 according to an embodiment, the second electrode Sa of the sub-transistor 320 corresponds to the source electrode (170 in FIG. 3) of the main transistor 100 according to an embodiment, and the gate electrode Ga of the sub-transistor 320 corresponds to the sub-gate electrode (155s in FIG. 3) of the sub-transistor 320 according to an embodiment. The sub-transistor 320 is separated by an isolation structure (160 in FIG. 3) and is configured as a part of the main transistor 100 located in the peripheral circuit region PA, but is not limited to this.

[0025] Hereinafter, with further reference to FIG. 2, a method of operating a semiconductor device according to an embodiment will be described.

[0026] 2 is a circuit diagram of a semiconductor device according to an embodiment, showing the current flow when the main transistor 100 and the sub-transistor 320 are turned on.

[0027] 2 , in the first mode, the main transistor 100 is turned off. Since the gate electrode G of the main transistor 100 and the gate electrode Ga of the sub-transistor 320 are electrically connected as described above, when the main transistor 100 is turned off, the sub-transistor 320 is also turned off. Therefore, the field dispersion layer 310, which constitutes the first electrode Da of the sub-transistor 320, is electrically insulated from the second electrode S of the main transistor 100, which constitutes the second electrode Sa of the sub-transistor 320. That is, the field dispersion layer 310 is floating. The field dispersion layer 310 serves to disperse an electric field concentrated around the gate electrode G of the main transistor 100. Meanwhile, when a high voltage is applied to the first electrode D of the main transistor 100, electric charges are generated in the field dispersion layer 310 due to electric fields, leakage currents, and the like. The accumulation of electric charges in the field dispersion layer 310 can cause instability in the turn-on voltage of the main transistor 100.

[0028] Subsequently, in the second mode, a turn-on signal is applied to the gate electrode G of the main transistor 100, turning on the main transistor 100. In this case, current flows from the first electrode D to the second electrode S of the main transistor 100 along the first path I1. Meanwhile, as described above, since the gate electrode G of the main transistor 100 and the gate electrode Ga of the sub-transistor 320 are electrically connected, when the main transistor 100 is turned on, the sub-transistor 320 is also turned on. As a result, current flows from the first electrode Da to the second electrode Sa of the sub-transistor 320 together and then flows along the second path I2 to the second electrode S of the main transistor 100. As a result, charges stored in the field dispersion layer 310 are discharged to the second electrode S of the main transistor 100 along the second path I2. Therefore, the influence of charges stored in the field dispersion layer 310 is eliminated, and the field dispersion layer 310 can effectively distribute the electric field concentrated around the gate electrode G of the main transistor 100, thereby improving the reliability of the semiconductor device.

[0029] A semiconductor device according to an embodiment will be described below with reference to Fig. 3. Fig. 3 is a plan view showing a semiconductor device according to an embodiment.

[0030] 3, according to one embodiment, the peripheral circuit region PA of a semiconductor device is located apart from the main device region MA. For example, the peripheral circuit region PA is located apart from the main device region MA in the second direction (Y direction), but is not limited thereto. As another example, the peripheral circuit region PA may be located apart from the main device region MA in the first direction (X direction) or may surround the side of the main device region MA. Of course, various other modifications are possible. The main transistor 100 is located within the main device region MA, and the peripheral circuit region PA includes a sub-transistor 320 electrically connected to one end of the main transistor 100.

[0031] A semiconductor device according to one embodiment includes a channel layer 132 having a two-dimensional electron gas (2DEG) 134 located therein, a gate electrode 155 located on the channel layer 132, a gate semiconductor layer located between the channel layer 132 and the gate electrode 155, a source electrode 170 and a drain electrode 190 located on either side of the gate electrode 155 on the channel layer 132, and a field spreading layer 310 located on the channel layer 132 between the gate electrode 155 and the drain electrode 190.

[0032] In one embodiment, the channel layer 132, the gate electrode 155, and the gate semiconductor layer are located in the main device region MA and the peripheral circuit region PA.

[0033] For convenience of explanation, the portion of the channel layer 132 located in the main device region MA will be referred to as the main channel layer 132m, and the portion of the channel layer 132 located in the peripheral circuit region PA will be referred to as the sub-channel layer 132s. The portion of the gate electrode 155 located in the main device region MA will be referred to as the main gate electrode 155m, and the portion of the gate electrode 155 located in the peripheral circuit region PA will be referred to as the sub-gate electrode 155s. The portion of the gate semiconductor layer located in the main device region MA will be referred to as the main gate semiconductor layer 152m, and the portion of the gate semiconductor layer located in the peripheral circuit region PA will be referred to as the sub-gate semiconductor layer 152s.

[0034] Hereinafter, a main transistor of a semiconductor device according to an embodiment will be described with further reference to FIGS.

[0035] Figures 4 and 5 are cross-sectional views taken along line A-A' in Figure 3. Figure 4 shows a semiconductor device according to an embodiment in an off state, and Figure 5 shows a semiconductor device according to an embodiment in an on state.

[0036] 4, the main transistor 100 of the semiconductor device according to one embodiment includes a main channel layer 132m, a main gate electrode 155m located on the main channel layer 132m, a main gate semiconductor layer 152m located between the main channel layer 132m and the main gate electrode 155m, a source electrode 170 and a drain electrode 190 spaced apart from each other on the main channel layer 132m, and a field spreading layer 310 located on the main channel layer 132m and between the main gate electrode 155m and the drain electrode 190.

[0037] The main channel layer 132m forms a channel between the source electrode 170 and the drain electrode 190, and a two-dimensional electron gas (2DEG) 134 is located within the main channel layer 132m. The two-dimensional electron gas 134 is a charge transport model used in solid state physics, and refers to a group of electrons that can move freely in two dimensions (e.g., the xy plane) but cannot move in another dimension (e.g., the z direction) and are tightly confined within the two dimensions. That is, the two-dimensional electron gas 134 exists in a three-dimensional space in a two-dimensional, paper-like form. Such two-dimensional electron gas 134 primarily appears in semiconductor heterojunction structures, and in a semiconductor device according to an embodiment, the two-dimensional electron gas 134 is generated at the interface between the main channel layer 132m and the barrier layer 136. For example, the two-dimensional electron gas 134 is generated in a portion of the main channel layer 132m adjacent to the barrier layer 136. In an embodiment, the main channel layer 132m refers to a portion of the channel layer 132 located in the main device region MA.

[0038] The main channel layer 132m includes one or more materials selected from III-V group materials, such as nitrides containing Al, Ga, In, B, or a combination thereof. The main channel layer 132m is composed of a single layer or multiple layers. The main channel layer 132m includes Al x In y Ga 1-x-y N (0≦x≦1, 0≦y≦1, x+y≦1). For example, the main channel layer 132m includes AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof. The main channel layer 132m may be a layer doped with impurities or a layer that is not doped with impurities (undoped). The thickness of the main channel layer 132m is approximately several hundred nanometers or less.

[0039] The main channel layer 132m is located on a substrate 110, with a seed layer 121 and a buffer layer 120 located between the substrate 110 and the main channel layer 132m. The substrate 110, seed layer 121, and buffer layer 120 are layers necessary for forming the main channel layer 132m and may be omitted in some cases. For example, when a GaN substrate is used as the main channel layer 132m, at least one of the substrate 110, seed layer 121, and buffer layer 120 may be omitted. Considering the relatively high cost of GaN substrates, the GaN-containing main channel layer 132m is grown using a Si substrate 110. However, because the lattice structures of Si and GaN are different, it is not easy to grow the main channel layer 132m directly on the substrate 110. For this reason, the seed layer 121 and buffer layer 120 are first grown on the substrate 110, and then the main channel layer 132m is grown on the buffer layer 120. Additionally, at least one of the substrate 110, the seed layer 121, and the buffer layer 120 may be used in the manufacturing process and then removed in the final structure of the semiconductor device.

[0040] The substrate 110 includes a semiconductor material. For example, the substrate 110 includes sapphire, Si, SiC, AlN, GaN, or a combination thereof. The substrate 110 may also be an SOI (Silicon on Insulator) substrate. However, the material of the substrate 110 is not limited thereto, and any commonly used substrate may be used. In some cases, the substrate 110 may include an insulating material. For example, after various layers including the main channel layer 132m are first formed on a semiconductor substrate, the semiconductor substrate may be removed and replaced with an insulating substrate.

[0041] The seed layer 121 is located directly on the substrate 110. However, without being limited thereto, other predetermined layers may be located between the substrate 110 and the seed layer 121. The seed layer 121 is a layer that serves as a seed for growing the buffer layer 120 and is composed of a crystal lattice structure that serves as a seed for the buffer layer 120. The buffer layer 120 is located directly on the seed layer 121. However, without being limited thereto, other predetermined layers may be located between the seed layer 121 and the buffer layer 120. The seed layer 121 includes one or more materials selected from III-V group materials, for example, nitrides including Al, Ga, In, B, or a combination thereof. The seed layer 121 includes Al x In y Ga 1-x-y N, where 0≦x≦1, 0≦y≦1, x+y≦1. For example, the seed layer 121 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof.

[0042] The buffer layer 120 is located on the seed layer 121. The buffer layer 120 is located between the seed layer 121 and the main channel layer 132m. The buffer layer 120 is a layer for reducing the difference in lattice constant and thermal expansion coefficient between the seed layer 121 and the main channel layer 132m, and preventing leakage current from flowing through the main channel layer 132m. The buffer layer 120 includes one or more materials selected from III-V group materials, for example, nitrides including Al, Ga, In, B, or a combination thereof. The buffer layer 120 includes Al x In y Ga 1-x-y N, where 0≦x≦1, 0≦y≦1, x+y≦1. For example, the buffer layer 120 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof.

[0043] The buffer layer 120 of the semiconductor device according to one embodiment includes a superlattice layer 124 disposed on the seed layer 121 and a high-resistivity layer 126 disposed on the superlattice layer 124. The superlattice layer 124 and the high-resistivity layer 126 are sequentially disposed on the substrate 110.

[0044] The superlattice layer 124 is disposed on the seed layer 121. The superlattice layer 124 is disposed directly on the seed layer 121. However, without being limited thereto, other layers may be disposed between the seed layer 121 and the superlattice layer 124. The superlattice layer 124 relieves the difference in lattice constant and thermal expansion coefficient between the substrate 110 and the main channel layer 132m, thereby relieving the tensile stress and compressive stress generated between the substrate 110 and the main channel layer 132m, and thus relieving stress between all layers formed by growth in the final structure of the semiconductor device according to an embodiment. The superlattice layer 124 includes one or more materials selected from III-V group materials, for example, nitrides including Al, Ga, In, B, or a combination thereof. The superlattice layer 124 includes Al, Ga, In, B, or a combination thereof. x In y Ga 1-x-y N, where 0≦x≦1, 0≦y≦1, x+y≦1. For example, the superlattice layer 124 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof.

[0045] In one embodiment, the superlattice layer 124 is composed of multiple layers in which layers containing different materials are alternately stacked. For example, the superlattice layer 124 has a structure in which layers made of AlGaN and layers made of AlN are repeatedly stacked. That is, AlGaN / AlN / AlGaN / AlN / AlGaN / AlN are sequentially stacked to form the superlattice layer. The number of AlGaN layers and AlN layers constituting the superlattice layer 124 may vary, and the materials constituting the superlattice layer 124 may vary. As another example, the superlattice layer 124 may have a structure in which layers made of AlGaN and layers made of GaN are repeatedly stacked. That is, AlGaN / GaN / AlGaN / GaN / AlGaN / GaN are sequentially stacked to form the superlattice layer. In an exemplary embodiment, when the superlattice layer 124 includes GaN, InN, AlGaN, AlInN, InGaN, AlN, AlInGaN, or a combination thereof, the superlattice layer 124 has n-type semiconductor characteristics in which the electron concentration is greater than the hole concentration, but is not limited thereto.

[0046] The high-resistivity layer 126 is located on the superlattice layer 124. The high-resistivity layer 126 is located directly on the superlattice layer 124. However, without being limited thereto, other predetermined layers may be located between the superlattice layer 124 and the high-resistivity layer 126. The high-resistivity layer 126 is located between the superlattice layer 124 and the main channel layer 132m. The high-resistivity layer 126 is a layer for preventing degradation of the semiconductor device according to an embodiment by preventing leakage current from flowing through the main channel layer 132m. The high-resistivity layer 126 is made of a material with low conductivity to electrically insulate the substrate 110 from the main channel layer 132m. The high-resistivity layer includes one or more materials selected from III-V group materials, for example, nitrides including Al, Ga, In, B, or a combination thereof. The high-resistivity layer 126 includes Al x In y Ga 1-x-yN (0≦x≦1, 0≦y≦1, x+y≦1). For example, the high-resistivity layer 126 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof. The high-resistivity layer 126 may consist of a single layer or multiple layers.

[0047] The semiconductor device according to one embodiment further includes a barrier layer 136 located on the main channel layer 132m.

[0048] The barrier layer 136 is located on the main channel layer 132m. The barrier layer 136 is located directly above the main channel layer 132m. However, without being limited thereto, other layers may be located between the main channel layer 132m and the barrier layer 136. The region of the main channel layer 132m that overlaps with the barrier layer 136 between the source electrode 170 and the drain electrode 190 is the main drift region DTRm. The main drift region DTRm is located between the source electrode 170 and the drain electrode 190. The main drift region DTRm refers to the region where carriers move when a potential difference occurs between the source electrode 170 and the drain electrode 190.

[0049] In one embodiment, a semiconductor device is turned on / off depending on whether a voltage is applied to the main gate electrode 155m and / or the magnitude of the voltage applied to the main gate electrode 155m, thereby allowing or blocking the movement of carriers in the main drift region DTRm.

[0050] The barrier layer 136 includes one or more materials selected from III-V group materials, such as nitrides containing Al, Ga, In, B, or combinations thereof. x In y Ga 1-x-yN (0≦x≦1, 0≦y≦1, x+y≦1). The barrier layer 136 may include GaN, InN, AlGaN, AlInN, InGaN, AlN, AlInGaN, or a combination thereof. The energy bandgap of the barrier layer 136 is adjusted by the Al and / or In composition ratio. The barrier layer 136 is doped with a predetermined impurity. In this case, the impurity doped into the barrier layer 136 is a p-type dopant that provides holes. For example, the impurity doped into the barrier layer 136 is magnesium (Mg). By increasing or decreasing the impurity doping concentration of the barrier layer 136, the threshold voltage, on-resistance, etc. of the semiconductor device according to an embodiment can be adjusted.

[0051] The barrier layer 136 includes a semiconductor material having different properties from the main channel layer 132m. The barrier layer 136 differs from the main channel layer 132m in at least one of polarization characteristics, energy band gap, and lattice constant. For example, the barrier layer 136 includes a material having a different energy band gap from the main channel layer 132m. The barrier layer 136 has a higher energy band gap and higher electric polarity than the main channel layer 132m. The barrier layer 136 induces a two-dimensional electron gas 134 in the main channel layer 132m, which has a relatively low electric polarity. In this respect, the barrier layer 136 is referred to as a channel supply layer or two-dimensional electron gas supply layer. The two-dimensional electron gas 134 is formed in a portion of the main channel layer 132m located below the interface between the main channel layer 132m and the barrier layer 136. The two-dimensional electron gas 134 has very high electron mobility.

[0052] The barrier layer 136 may be a single layer or multiple layers. When the barrier layer 136 is multiple layers, the materials of the layers constituting the multiple layers have different energy bandgaps. In this case, the various layers constituting the barrier layer 136 are arranged so that the energy bandgaps are larger as they are closer to the main channel layer 132m.

[0053] The main gate electrode 155m is located on the barrier layer 136. The main gate electrode 155m overlaps a portion of the barrier layer 136 in the third direction (Z direction). The main gate electrode 155m overlaps a portion of the main drift region DTRm of the main channel layer 132m in the third direction (Z direction). The main gate electrode 155m is located between the source electrode 170 and the drain electrode 190. The main gate electrode 155m is spaced apart from the source electrode 170 and the drain electrode 190. For example, the main gate electrode 155m is located closer to the source electrode 170 than the drain electrode 190. That is, the distance between the main gate electrode 155m and the source electrode 170 is smaller than the distance between the main gate electrode 155m and the drain electrode 190, but is not limited thereto. In one embodiment, the main gate electrode 155m refers to a portion of the gate electrode 155 located in the main element region MA. Here, the third direction (Z direction) means the thickness direction of the main channel layer 132m.

[0054] The main gate electrode 155m includes a conductive material. For example, the main gate electrode 155m includes a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxynitride. For example, the main gate electrode 155m includes titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride ( The main gate electrode 155m may be formed of, but is not limited to, a single layer or multiple layers.

[0055] In an exemplary embodiment, the main gate electrode 155m further includes a hard mask layer positioned on the main gate electrode 155m. The hard mask layer is a hard mask used when patterning the gate electrode material layer and / or the gate semiconductor layer in the process of forming the main gate electrode 155m. However, the hard mask layer is removed by etching conditions during etching of the gate electrode material layer and / or the gate semiconductor layer or by cleaning conditions after etching. For example, the hard mask layer includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0056] The main gate semiconductor layer 152m is located between the barrier layer 136 and the main gate electrode 155m. That is, the main gate semiconductor layer 152m is located on the barrier layer 136, and the main gate electrode 155m is located on the main gate semiconductor layer 152m. The main gate electrode 155m makes Schottky contact or ohmic contact with the main gate semiconductor layer 152m. The main gate semiconductor layer 152m overlaps the main gate electrode 155m in the third direction (Z direction). In this case, the main gate semiconductor layer 152m completely overlaps the main gate electrode 155m in the third direction (Z direction), and the entire upper surface of the main gate semiconductor layer 152m is covered by the main gate electrode 155m. That is, the main gate semiconductor layer 152m has substantially the same planar shape as the main gate electrode 155m. However, the present invention is not limited to this, and the main gate electrode 155m is positioned so as to cover at least a part of the main gate semiconductor layer 152m.

[0057] The main gate semiconductor layer 152m is located between the source electrode 170 and the drain electrode 190. The main gate semiconductor layer 152m is spaced apart from the source electrode 170 and the drain electrode 190. The main gate semiconductor layer 152m is located closer to the source electrode 170 than to the drain electrode 190. That is, the distance between the main gate semiconductor layer 152m and the source electrode 170 is smaller than the distance between the main gate semiconductor layer 152m and the drain electrode 190, but is not limited to this.

[0058] In one embodiment, the main gate semiconductor layer 152m overlaps the main gate electrode 155m in the third direction (Z direction). For example, the main gate semiconductor layer 152m completely overlaps the main gate electrode 155m in the third direction (Z direction). That is, the side of the main gate semiconductor layer 152m is aligned with the side of the main gate electrode 155m. However, this is not limited thereto, and the main gate semiconductor layer 152m may partially overlap the main gate electrode 155m.

[0059] The main gate semiconductor layer 152m includes one or more materials selected from III-V group materials, for example, nitrides containing Al, Ga, In, B, or a combination thereof. x In y Ga 1-x-y N (0≦x≦1, 0≦y≦1, x+y≦1). For example, the main gate semiconductor layer 152m may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof. The main gate semiconductor layer 152m includes a material having a different energy bandgap from that of the barrier layer 136. For example, the main gate semiconductor layer 152m includes GaN, and the barrier layer 136 includes AlGaN. The main gate semiconductor layer 152m is doped with a predetermined impurity. In this case, the impurity doped into the main gate semiconductor layer 152m is a p-type dopant that provides holes. For example, the main gate semiconductor layer 152m includes GaN doped with p-type impurities. That is, the main gate semiconductor layer 152m is a p-GaN layer. However, the main gate semiconductor layer 152m is not limited thereto, and may be a p-AlGaN layer.

[0060] The main gate semiconductor layer 152m forms a depletion region DPR in the main channel layer 132m. The depletion region DPR is located in the main drift region DTRm and has a width narrower than that of the main drift region DTRm. The main gate semiconductor layer 152m, which has a different energy bandgap from that of the barrier layer 136, is located on the barrier layer 136, raising the energy band level of the portion of the barrier layer 136 overlapping with the main gate semiconductor layer 152m. This results in a depletion region DPR in the region of the main channel layer 132m overlapping with the main gate semiconductor layer 152m. The depletion region DPR is a region in the channel path of the main channel layer 132m where no two-dimensional electron gas 134 is formed or where the electron concentration is lower than that of the remaining region. In other words, the depletion region DPR refers to a region in the main drift region DTRm where the flow of two-dimensional electron gas 134 is blocked. Due to the occurrence of the depletion region DPR, a current does not flow between the source electrode 170 and the drain electrode 190, and the channel path is cut off, thereby causing the semiconductor device according to the embodiment to have normally off characteristics.

[0061] That is, the semiconductor device according to one embodiment is a normally-off high electron mobility transistor (HEMT). As shown in FIG. 4, in a normal state where no voltage is applied to the main gate electrode 155m, a depletion region DPR exists, and the semiconductor device according to one embodiment is in an off state. As shown in FIG. 5, when a voltage equal to or greater than a threshold voltage is applied to the main gate electrode 155m, the depletion region DPR disappears, and the two-dimensional electron gas 134 is continuously connected within the main drift region DTRm. That is, the two-dimensional electron gas 134 is formed throughout the entire channel path between the source electrode 170 and the drain electrode 190, and the semiconductor device according to one embodiment is in an on state. In summary, the semiconductor device according to one embodiment includes semiconductor layers with different electrical polarization characteristics, and a semiconductor layer with a relatively large polarizability induces two-dimensional electron gas 134 in another semiconductor layer heterojunction therewith. The two-dimensional electron gas 134 can be used as a channel between the source electrode 170 and the drain electrode 190, and the continuation or interruption of the flow of the two-dimensional electron gas 134 is controlled by a bias voltage applied to the main gate electrode 155m. When the gate is off, the flow of the two-dimensional electron gas 134 is interrupted, and no current flows between the source electrode 170 and the drain electrode 190. When the gate is on, the flow of the two-dimensional electron gas 134 continues, and so current flows between the source electrode 170 and the drain electrode 190.

[0062] Although the semiconductor device according to the above embodiment is a normally-off high electron mobility transistor (HEM), the present invention is not limited thereto. For example, the semiconductor device according to the embodiment may be a normally-on high electron mobility transistor (HEM). In the case of a normally-on high electron mobility transistor, the main gate semiconductor layer 152m is omitted, and the main gate electrode 155m is located directly on the barrier layer 136. That is, the main gate electrode 155m contacts the barrier layer 136. In this structure, when no voltage is applied to the main gate electrode 155m, the two-dimensional electron gas 134 serves as a channel, generating a current flow between the source electrode 170 and the drain electrode 190. Furthermore, when a negative voltage is applied to the main gate electrode 155m, a depletion region DPR is generated below the main gate electrode 155m, blocking the flow of the two-dimensional electron gas 134.

[0063] The seed layer 121, superlattice layer 124, high-resistance layer 126, main channel layer 132m, barrier layer 136, and main gate semiconductor layer 152m described above are sequentially stacked on the substrate 110. In a semiconductor device according to an embodiment, at least one of the seed layer 121, superlattice layer 124, high-resistance layer 126, main channel layer 132m, barrier layer 136, and main gate semiconductor layer 152m may be omitted. The seed layer 121, superlattice layer 124, high-resistance layer 126, main channel layer 132m, barrier layer 136, and main gate semiconductor layer 152m are made of the same base semiconductor material, and the material composition ratio of each layer may vary depending on the role of each layer and the performance required of the semiconductor device.

[0064] In one embodiment, the semiconductor device further includes a first protective layer 140 located on the barrier layer 136 .

[0065] The first protective layer 140 is positioned on the barrier layer 136 and the main gate electrode 155m. The first protective layer 140 covers the top and side surfaces of the main gate electrode 155m and the side surfaces of the main gate semiconductor layer 152m. The bottom surface of the first protective layer 140 contacts the barrier layer 136 and the main gate electrode 155m. As a result, the barrier layer 136, the main gate semiconductor layer 152m, and the main gate electrode 155m are protected by the first protective layer 140. However, the present invention is not limited thereto. The main gate electrode 155m may be connected to the main gate semiconductor layer 152m through the first protective layer 140, and the first protective layer 140 may not cover the top surface of the main gate electrode 155m. Alternatively, the bottom surface of the first protective layer 140 may contact the main gate semiconductor layer 152m. The first protective layer 140 includes an insulating material. For example, the first protective layer 140 may include an oxide such as SiO2 or Al2O3. As another example, the first protective layer 140 can include a nitride such as SiN or an oxynitride such as SiON.

[0066] Although the first protective layer 140 is shown as being made up of a single layer in FIGS. 4 and 5, the first protective layer 140 is not limited thereto, and may be made up of multiple layers containing different materials.

[0067] The source electrode 170 and the drain electrode 190 are located on the main channel layer 132m. The source electrode 170 and the drain electrode 190 are in direct contact with the main channel layer 132m and are electrically connected to the main channel layer 132m. The source electrode 170 is also electrically connected to the sub-channel layer 132s. For example, the source electrode 170 is electrically connected to a first contact portion CP1 of the sub-channel layer 132s. This will be described in detail below with reference to FIGS. 6 to 8.

[0068] The source electrode 170 and the drain electrode 190 extend in the second direction (Y direction). The source electrode 170 and the drain electrode 190 are spaced apart from each other, and the main gate electrode 155m and the main gate semiconductor layer 152m are located between the source electrode 170 and the drain electrode 190. The main gate electrode 155m and the main gate semiconductor layer 152m are spaced apart from the source electrode 170 and the drain electrode 190. For example, the source electrode 170 is electrically connected to the main channel layer 132m on one side of the main gate electrode 155m, and the drain electrode 190 is electrically connected to the main channel layer 132m on the other side of the main gate electrode 155m. The source electrode 170 and the drain electrode 190 are located outside the main drift region DTRm of the main channel layer 132m. The interface between the source electrode 170 and the main channel layer 132m is one edge of the main drift region DTRm. Similarly, the interface between the drain electrode 190 and the main channel layer 132m is the other side edge of the main drift region DTRm. In one embodiment, the drain electrode 190 refers to the portion of the drain electrode 190 located in the main element region MA.

[0069] However, the present invention is not limited thereto. The main channel layer 132m may not be recessed, and the source electrode 170 and the drain electrode 190 may be located on the upper surface of the main channel layer 132m. In this case, the bottom surfaces of the source electrode 170 and the drain electrode 190 contact the upper surface of the main channel layer 132m. The portions of the main channel layer 132m in contact with the source electrode 170 and the drain electrode 190 are heavily doped. In this case, carriers passing through the two-dimensional electron gas 134 pass through the heavily doped portion of the main channel layer 132m, i.e., the top of the two-dimensional electron gas 134, and are transferred to the source electrode 170 and the drain electrode 190. The source electrode 170 and the drain electrode 190 do not directly contact the two-dimensional electron gas 134 in the horizontal direction. Here, the horizontal direction refers to a direction parallel to the upper surface of the main channel layer 132m or the barrier layer 136.

[0070] Specifically, trenches that penetrate the first passivation layer 140 and the barrier layer 136 and recess the top surface of the main channel layer 132m are positioned spaced apart on both sides of the main gate electrode 155m. A source electrode 170 and a drain electrode 190 are positioned in the trenches on both sides of the main gate electrode 155m, respectively. The source electrode 170 and the drain electrode 190 are formed to fill the trenches. Within the trenches, the source electrode 170 and the drain electrode 190 contact the main channel layer 132m and the barrier layer 136. The main channel layer 132m forms the bottom and sidewalls of the trench, and the barrier layer 136 forms the sidewalls of the trench. Therefore, the source electrode 170 and the drain electrode 190 contact the top surface and side surfaces of the main channel layer 132m. The source electrode 170 and the drain electrode 190 also contact the side surfaces of the barrier layer 136. That is, the source electrode 170 and the drain electrode 190 cover the side surfaces of the main channel layer 132 m and the barrier layer 136 .

[0071] In one embodiment, the source electrode 170 and the drain electrode 190 cover at least a portion of the side surface of the first protective layer 140. For example, the source electrode 170 and the drain electrode 190 cover the side surface of the first protective layer 140. The top surfaces of the source electrode 170 and the drain electrode 190 protrude beyond the top surface of the first protective layer 140. Also, at least one of the source electrode 170 and the drain electrode 190 covers at least a portion of the top surface of the first protective layer 140. However, without being limited thereto, the source electrode 170 and the drain electrode 190 may cover at least a portion of the side surface of the first protective layer 140, but may not cover the remaining portion of the side surface of the first protective layer 140. In this case, the remaining portion of the first protective layer 140 is located on the top surfaces of the source electrode 170 and the drain electrode 190.

[0072] The source electrode 170 and the drain electrode 190 include a conductive material. For example, the source electrode 170 and the drain electrode 190 include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxynitride. For example, the source electrode 170 and the drain electrode 190 may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), or tantalum carbonitride. The source electrode 170 and the drain electrode 190 may include, but are not limited to, a single layer or multiple layers. The source electrode 170 and the drain electrode 190 make ohmic contact with the main channel layer 132m. The regions in the main channel layer 132m that contact the source electrode 170 and the drain electrode 190 are doped at a higher concentration than the other regions.

[0073] 4 and 5, the semiconductor device according to an embodiment includes a pair of source electrode 170 and drain electrode 190, but the number of source electrodes 170 and drain electrodes 190 is not limited thereto. For example, the source electrode 170 may include a plurality of source electrodes sequentially stacked in the third direction (Z direction) on the main channel layer 132m, and the drain electrode 190 may include a plurality of drain electrodes sequentially stacked in the third direction (Z direction) on the main channel layer 132m. This will be described later with reference to FIG. 9.

[0074] The field dispersion layer 310 is located between the main gate electrode 155m and the drain electrode 190. The field dispersion layer 310 is located between the source electrode 170 and the drain electrode 190. The field dispersion layer 310 is located on the first protective layer 140. The field dispersion layer 310 overlaps the main channel layer 132m in the third direction (Z direction). The field dispersion layer 310 also overlaps at least a portion of an isolation structure 160 and a sub-channel layer 132s (described later) in the third direction (Z direction), but is not limited to this. The field dispersion layer 310 does not overlap the main gate electrode 155m, the source electrode 170, and the drain electrode 190 in the third direction (Z direction), but is not limited to this.

[0075] The field dispersion layer 310 is spaced apart from the source electrode 170. The field dispersion layer 310 extends in the same direction as the source electrode 170. For example, but not limited to, the field dispersion layer 310 and the source electrode 170 extend in the second direction (Y direction). The field dispersion layer 310 is electrically connected to a sub-channel layer 132s of a sub-transistor 320 (to be described later). For example, the field dispersion layer 310 is directly connected to a second contact portion CP2 of the sub-channel layer 132s (to be described later). Thus, the field dispersion layer 310 is electrically connected to the source electrode 170 via the sub-channel layer 132s (to be described later). Specifically, when the sub-transistor 320 is turned on, the field dispersion layer 310 is electrically connected to the source electrode 170. When the sub-transistor 320 is turned off, the field dispersion layer 310 is electrically isolated from the source electrode 170 and is floating. This will be described later with reference to FIGS. 6 to 8.

[0076] In some embodiments, the field dispersion layer 310 is connected to the sub-channel layer 132s via a separate contact electrode, which will be described below with reference to FIG.

[0077] The field dispersion layer 310 includes the same material as the source electrode 170. The field dispersion layer 310 is located in the same layer as at least a portion of the source electrode 170. For example, the portion of the source electrode 170 located on the first passivation layer 140 is located in the same layer as the field dispersion layer 310. The field dispersion layer 310 may be formed simultaneously with and in the same process as the source electrode 170. However, without being limited thereto, the field dispersion layer 310 may be located in a different layer from the source electrode 170 and formed in a different process.

[0078] The field dispersion layer 310 serves to disperse the electric field concentrated around the main gate electrode 155m. Specifically, in the gate-off state, a very high concentration of two-dimensional electron gas 134 is present in the main channel layer 132m between the main gate electrode 155m and the source electrode 170 and in the main channel layer 132m between the main gate electrode 155m and the drain electrode 190. In this case, an electric field is concentrated in the main gate electrode 155m or the main gate semiconductor layer 152m. Meanwhile, the main gate electrode 155m and the main gate semiconductor layer 152m are vulnerable to electric fields, and when the electric field concentrates, leakage current increases, reducing the breakdown voltage of the main transistor 100. In this case, the field dispersion layer 310 disperses the electric field concentrated around the main gate electrode 155m or the main gate semiconductor layer 152m, reducing the leakage current and increasing the breakdown voltage. On the other hand, as described above, when the sub-transistor 320 is turned off, the field distribution layer 310 is floating, and therefore, an electric field around the field distribution layer 310 causes charges to be stored in the field distribution layer 310. When the sub-transistor 320 is turned on, the field distribution layer 310 is electrically connected to the source electrode 170 through the sub-transistor 320, and the charges stored in the field distribution layer 310 are discharged.

[0079] 4 and 5 show that the semiconductor device according to the embodiment includes one field dispersion layer 310, but the number of field dispersion layers 310 is not limited thereto. For example, the field dispersion layer 310 may include a plurality of field dispersion layers disposed on the first protective layer 140. As another example, a plurality of protective layers may be disposed on the first protective layer 140, and a plurality of field dispersion layers may be disposed on different protective layers. This will be described later with reference to FIG. 18.

[0080] The semiconductor device according to the embodiment further includes a second passivation layer 180 located on the field dispersion layer 310 and the first passivation layer 140 .

[0081] The second protective layer 180 covers the top surface of the first protective layer 140, the top surface and side surfaces of the field spreading layer 310, and the top surfaces of the source electrode 170 and the drain electrode 190. The second protective layer 180 includes trenches 141 and 143 that expose the source electrode 170 and the drain electrode 190. The trenches 141 and 143 allow the source electrode 170 and the drain electrode 190 to be electrically connected to wiring, respectively. The second protective layer 180 includes an insulating material. The second protective layer 180 may include the same material as the first protective layer 140, but is not limited to this. For example, the second protective layer 180 may include an oxide such as SiO2 or Al2O3. As another example, the second protective layer 180 may include a nitride such as SiN or an oxynitride such as SiON.

[0082] Hereinafter, a peripheral circuit element of a semiconductor device according to an embodiment will be described with reference to FIG. 3 and FIGS. 6 to 8. FIG.

[0083] Fig. 6 is a cross-sectional view taken along line BB' in Fig. 3. Fig. 7 is a cross-sectional view taken along line CC' in Fig. 3. Fig. 8 is a cross-sectional view taken along line DD' in Fig. 3. 3 and 6 to 8, a semiconductor device according to an embodiment includes a sub-transistor 320 connected to one end of a main transistor 100.

[0084] According to one embodiment, the sub-transistor 320 of the semiconductor device includes a sub-drift region DTR having a two-dimensional electron gas, a sub-channel layer 132s connected to a source electrode 170 and a field dispersion layer 310, and a sub-gate electrode 155s located on the sub-channel layer 132s and connected to a main gate electrode 155m. In one embodiment, the sub-channel layer 132s forms a channel of the sub-transistor 320, the field dispersion layer 310 forms a first electrode (Da in FIG. 1) of the sub-transistor 320, the source electrode 170 forms a second electrode (Sa in FIG. 1) of the sub-transistor 320, and the sub-gate electrode 155s forms a gate electrode (Ga in FIG. 1) of the sub-transistor 320.

[0085] The sub-channel layer 132s is located on the substrate 110. The sub-channel layer 132s is a layer that forms a channel between the source electrode 170 and the field spreading layer 310, and a two-dimensional electron gas (2DEG) 134 is located within the sub-channel layer 132s. In the semiconductor device according to one embodiment, the two-dimensional electron gas 134 is generated at the interface between the sub-channel layer 132s and the barrier layer 136. For example, the two-dimensional electron gas 134 is generated in a portion of the sub-channel layer 132s adjacent to the barrier layer 136. In one embodiment, the sub-channel layer 132s refers to a portion of the channel layer 132 that is located in the peripheral circuit region PA and forms the channel of the sub-transistor 320.

[0086] In one embodiment, the sub-channel layer 132s is located on one side of the main channel layer 132m. For example, the sub-channel layer 132s may be located on one side of the main channel layer 132m in the second direction (Y direction), but is not limited thereto. One end of the sub-channel layer 132s is connected to the source electrode 170, and the other end is connected to the field dispersion layer 310. The sub-channel layer 132s may have various shapes in a plan view. For example, the sub-channel layer 132s may include a portion extending in the second direction (Y direction) to connect to the source electrode 170, a portion extending in the second direction (Y direction) to connect to the field dispersion layer 310, and a portion extending in the first direction (X direction). However, the shape of the sub-channel layer 132s may be varied within the range of connection between the source electrode 170 and the field dispersion layer 310. This will be described later with reference to FIG. 17.

[0087] In one embodiment, the sub-channel layer 132s is integrally formed with the main channel layer 132m of the main transistor 100 by the same process. The sub-channel layer 132s is located in the same layer as the main channel layer 132m. The lower surface of the sub-channel layer 132s is located at the same level as the lower surface of the main channel layer 132m, and the upper surface of the sub-channel layer 132s is located at the same level as the upper surface of the main channel layer 132m. That is, the lower surface of the sub-channel layer 132s is located the same distance from the upper surface of the substrate 110 as the lower surface of the main channel layer 132m. Also, the upper surface of the sub-channel layer 132s is located the same distance from the upper surface of the substrate 110 as the upper surface of the main channel layer 132m. The thickness of the sub-channel layer 132s in the third direction (Z direction) is substantially the same as the thickness of the main channel layer 132m in the third direction (Z direction), but is not limited to this. At this time, the sub-channel layer 132s and the main channel layer 132m are separated by a separation structure 160, which will be described later.

[0088] In one embodiment, the sub-channel layer 132s includes the same material as the main channel layer 132m. For example, the sub-channel layer 132s includes one or more materials selected from III-V group materials, such as nitrides containing Al, Ga, In, B, or combinations thereof.

[0089] According to one embodiment, the sub-channel layer 132s of the semiconductor device includes a first contact portion CP1 connected to the source electrode 170, a second contact portion CP2 connected to the field dispersion layer 310, and an extension portion EP connecting the first contact portion CP1 and the second contact portion CP2.

[0090] The first contact portion CP1 is connected to the source electrode 170. The first contact portion CP1 contacts the source electrode 170. For example, as shown in FIG. 6, the source electrode 170 is electrically connected to the first contact portion CP1 through the first passivation layer 140 and the barrier layer 136. In this case, the source electrode 170 is located in a space where the first contact portion CP1 is recessed. The source electrode 170 contacts a side surface of the sub-channel layer 132s through the barrier layer 136. For example, the first contact portion CP1 is not recessed, and the source electrode 170 is located on an upper surface of the first contact portion CP1. The interface between the source electrode 170 and the sub-channel layer 132s is one side edge of the sub-drift region DTRs. The first contact portion CP1 refers to a portion of the sub-channel layer 132s to which the source electrode 170 is connected.

[0091] The second contact portion CP2 is connected to the field dispersion layer 310. The second contact portion CP2 contacts the field dispersion layer 310. For example, as shown in FIGS. 6 and 7, the field dispersion layer 310 is electrically connected to the second contact portion CP2 through the first passivation layer 140 and the barrier layer 136. In this case, the field dispersion layer 310 is located in the recessed space of the second contact portion CP2. The field dispersion layer 310 contacts the side of the sub-channel layer 132s through the barrier layer 136. However, this is not limiting. For example, the second contact portion CP2 may not be recessed, and the field dispersion layer 310 may be located on the upper surface of the second contact portion CP2. The interface between the field dispersion layer 310 and the sub-channel layer 132s is the other edge of the sub-drift region DTRs. The second contact portion CP2 refers to the portion of the sub-channel layer 132s to which the field dispersion layer 310 is connected. As a result, the field dispersion layer 310 overlaps with the main channel layer 132m in the third direction (Z direction), and overlaps with at least a part of the sub-channel layer 132s in the third direction (Z direction).

[0092] The extension portion EP is located between the first contact portion CP1 and the second contact portion CP2. The extension portion EP connects the first contact portion CP1 and the second contact portion CP2. The extension portion EP may have various shapes in a plan view. For example, as shown in FIG. 3, the extension portion EP includes a portion extending in the second direction (Y direction) to connect with the first contact portion CP1, a portion extending in the second direction (Y direction) to connect with the field dispersion layer 310, and a portion extending in the first direction (X direction). However, the shape of the extension portion EP is not limited thereto, and may be modified in various ways as long as it connects between the source electrode 170 and the field dispersion layer 310.

[0093] In one embodiment, a seed layer 121 and a buffer layer 120 are located between the substrate 110 and the sub-channel layer 132s. The substrate 110, seed layer 121, and buffer layer 120 are layers required to form the sub-channel layer 132s, but may be omitted in some cases. In one embodiment, the substrate 110, seed layer 121, and buffer layer 120 located in the peripheral circuit region PA are integrally formed by the same process as the substrate 110, seed layer 121, and buffer layer 120 located in the main device region MA, respectively.

[0094] According to an embodiment, the barrier layer 136 of the semiconductor device is further disposed on the sub-channel layer 132s. That is, the barrier layer 136 extends further onto the sub-channel layer 132s. The barrier layer 136 is disposed directly on the sub-channel layer 132s. However, without being limited thereto, other layers may be disposed between the sub-channel layer 132s and the barrier layer 136. The region of the sub-channel layer 132s overlapping with the barrier layer 136 forms a drift region. Specifically, the barrier layer 136 differs from the sub-channel layer 132s in at least one of polarization characteristics, energy band gap, and lattice constant, thereby inducing a two-dimensional electron gas 134 in the sub-channel layer 132s, which has a relatively low electrical polarization, by the barrier layer 136.

[0095] 6 and 7, in the peripheral circuit area PA, the sub-channel layer 132s includes a sub-drift region DTRs between the field dispersion layer 310 and the source electrode 170. That is, the sub-drift region DTRs refers to the region of the sub-channel layer 132s from one side of the sub-channel layer 132s in contact with the source electrode 170 to the field dispersion layer 310. The sub-drift region DTRs refers to the region of the sub-channel layer 132s that overlaps with the barrier layer 136 between the field dispersion layer 310 and the source electrode 170. For example, the boundary where the source electrode 170 and the sub-channel layer 132s intersect is one side edge of the sub-drift region DTRs, and the boundary where the field dispersion layer 310 and the sub-channel layer 132s intersect is the other side edge of the sub-drift region DTRs. In other words, the sub-drift regions DTRs refer to regions where carriers move between one side of the sub-channel layer 132s in contact with the source electrode 170 and the field spreading layer 310 in the peripheral circuit region PA.

[0096] The sub-gate electrode 155s is located in the peripheral circuit region PA. The sub-gate electrode 155s is located on the extension portion EP of the sub-channel layer 132s. For example, the sub-gate electrode 155s overlaps with the extension portion EP of the sub-channel layer 132s in the third direction (Z direction). That is, the sub-gate electrode 155s overlaps with a portion of the sub-drift region DTRs of the sub-channel layer 132s in the third direction (Z direction). In one embodiment, the sub-gate electrode 155s refers to a portion of the gate electrode 155 located in the peripheral circuit region PA. As a result, the gate electrode 155 overlaps with the extension portion EP of the sub-channel layer 132s in the third direction (Z direction).

[0097] The sub-gate electrode 155s is located on the barrier layer 136. The sub-gate electrode 155s is electrically connected to the main gate electrode 155m.

[0098] The sub-gate electrode 155s is located on the sub-channel layer 132s between the field distribution layer 310 and the source electrode 170. That is, the sub-gate electrode 155s is located between a first contact portion CP1 of the sub-channel layer 132s to which the source electrode 170 is connected and a second contact portion CP2 to which the field distribution layer 310 is connected. The sub-gate electrode 155s is spaced apart from the field distribution layer 310 and the source electrode 170. The sub-gate electrode 155s is located closer to the field distribution layer 310 than the source electrode 170, but is not limited to this. That is, the distance between the sub-gate electrode 155s and the field distribution layer 310 is smaller than the distance between the sub-gate electrode 155s and the source electrode 170, but is not limited to this.

[0099] In one embodiment, the sub-gate electrode 155s is integrated with the main gate electrode 155m of the main transistor 100. That is, the sub-gate electrode 155s is integrally formed by the same process as the main gate electrode 155m of the main transistor 100. For example, as shown in FIG. 8, the sub-gate electrode 155s is located in the same layer as the main gate electrode 155m. The bottom surface of the sub-gate electrode 155s is located at the same level as the bottom surface of the main gate electrode 155m, and the top surface of the sub-gate electrode 155s is located at the same level as the top surface of the main gate electrode 155m. That is, the bottom surface of the sub-gate electrode 155s is located at the same distance from the top surface of the substrate 110 as the bottom surface of the main gate electrode 155m. The thickness of the sub-gate electrode 155s in the third direction (Z direction) is substantially the same as the thickness of the main gate electrode 155m in the third direction (Z direction), but is not limited thereto.

[0100] However, without being limited thereto, in some embodiments, the sub-gate electrode 155s may not be integrally formed with the main gate electrode 155m, but even in this case, the sub-gate electrode 155s is electrically connected to the main gate electrode 155m via an upper wiring or the like.

[0101] The sub-gate electrode 155s includes a conductive material. The sub-gate electrode 155s includes the same material as the main gate electrode 155m. However, the present invention is not limited thereto, and the sub-gate electrode 155s may include a different material from the main gate electrode 155m.

[0102] In an example embodiment, the gate electrode 155s may further include a hard mask layer positioned on the sub-gate electrode 155s. The hard mask layer is a hard mask used when patterning the gate electrode material layer and / or the gate semiconductor layer in the process of forming the sub-gate electrode 155s. However, the hard mask layer is removed depending on the etching conditions during etching of the gate electrode material layer and / or the gate semiconductor layer or by cleaning conditions after etching. For example, the hard mask layer may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0103] The sub-gate semiconductor layer 152s is located between the barrier layer 136 and the sub-gate electrode 155s. The sub-gate semiconductor layer 152s overlaps the sub-gate electrode 155s in the third direction (Z direction). As an example, but not limited to, the sub-gate semiconductor layer 152s completely overlaps the sub-gate electrode 155s in the third direction (Z direction). Also, the sub-gate semiconductor layer 152s overlaps the isolation structure 160 in the third direction (Z direction). The sub-gate electrode 155s makes a Schottky contact or an ohmic contact with the sub-gate semiconductor layer 152s. The structural shapes of the sub-gate semiconductor layer 152s and the sub-gate electrode 155s are substantially the same as the structural shapes of the main gate semiconductor layer 152m and the main gate electrode 155m. However, without being limited thereto, in some embodiments, the sub-gate semiconductor layer 152s is not located between the sub-barrier layer 136 and the sub-gate electrode 155s. In this case, the lower surface of the sub-gate electrode 155s contacts the barrier layer 136.

[0104] In one embodiment, the sub-gate semiconductor layer 152s is located on the sub-channel layer 132s between the field distribution layer 310 and the source electrode 170. The sub-gate semiconductor layer 152s is located on the extension portion EP of the sub-channel layer 132s. That is, the sub-gate semiconductor layer 152s is located between the first contact portion CP1 of the sub-channel layer 132s, to which the source electrode 170 is connected, and the second contact portion CP2, to which the field distribution layer 310 is connected. The sub-gate semiconductor layer 152s is spaced apart from the field distribution layer 310 and the source electrode 170.

[0105] In one embodiment, the sub-gate semiconductor layer 152s is integrated with the main gate semiconductor layer 152m of the main transistor 100. That is, the sub-gate semiconductor layer 152s is integrally formed using the same process as the main gate semiconductor layer 152m of the main transistor 100. For example, as shown in FIG. 8, the sub-gate semiconductor layer 152s is located in the same layer as the main gate semiconductor layer 152m. The bottom surface of the sub-gate semiconductor layer 152s is located at the same level as the bottom surface of the main gate semiconductor layer 152m, and the top surface of the sub-gate semiconductor layer 152s is located at the same level as the top surface of the main gate semiconductor layer 152m. That is, the bottom surface of the sub-gate semiconductor layer 152s is located at the same distance from the top surface of the substrate 110 as the bottom surface of the main gate semiconductor layer 152m. The thickness of the sub-gate semiconductor layer 152s in the third direction (Z direction) is substantially the same as the thickness of the main gate semiconductor layer 152m in the third direction (Z direction), but is not limited thereto.

[0106] However, the present invention is not limited to this, and the sub-gate semiconductor layer 152s may be spaced apart from the main gate semiconductor layer 152m, which will be described later with reference to FIG.

[0107] The sub-gate semiconductor layer 152s includes a conductive material. The sub-gate semiconductor layer 152s may include the same material as the main gate semiconductor layer 152m. However, the sub-gate semiconductor layer 152s is not limited thereto, and may include a different material from the main gate semiconductor layer 152m.

[0108] A depletion region DPR is formed in the sub-channel layer 132s by the sub-gate semiconductor layer 152s. The depletion region DPR is located in the sub-drift region DTRs. Here, the depletion region DPR refers to a region in the sub-drift region DTRs where the flow of the two-dimensional electron gas 134 is interrupted. Due to the occurrence of the depletion region DPR, no current flows between the field distribution layer 310 and the source electrode 170, and the channel path is interrupted.

[0109] In summary, the sub-transistor 320 of the semiconductor device according to one embodiment is composed of the sub-channel layer 132s, the sub-gate electrode 155s, the source electrode 170, and the field distribution layer 310. A sub-drift region DTRs and a depletion region DPR are formed in the sub-channel layer 132s. The sub-transistor 320 is turned on by a signal from the sub-gate electrode 155s, thereby controlling the current flowing between the field distribution layer 310 and the source electrode 170.

[0110] Specifically, the sub-gate electrode 155s is electrically connected to the main gate electrode 155m. Therefore, when a turn-off signal is applied to the main gate electrode 155m, the turn-off signal is also applied to the sub-gate electrode 155s, turning off the sub-transistor 320. Therefore, the field dispersion layer 310, which constitutes the first electrode (Da in FIG. 1) of the sub-transistor 320, is electrically insulated from the source electrode 170, which constitutes the second electrode (Sa in FIG. 1) of the sub-transistor 320. That is, the field dispersion layer 310 is floating, and serves to disperse the electric field concentrated around the main gate electrode 155m of the main transistor 100. At this time, charges are accumulated in the field dispersion layer 310 due to the electric field and leakage current caused by the voltage. When charges are accumulated in the field dispersion layer 310, the voltages of the drain electrode 190, the main gate electrode 155m, etc. become unstable.

[0111] Meanwhile, when a turn-on signal is applied to the main gate electrode 155m, a turn-on signal is also applied to the sub-gate electrode 155s, turning on the sub-transistor 320. As a result, a current flows from the field dispersion layer 310 to the source electrode 170, and charges stored in the field dispersion layer 310 are discharged through the source electrode 170. Therefore, the influence of charges stored in the field dispersion layer 310 is eliminated, and the field dispersion layer 310 effectively distributes the electric field concentrated around the main gate electrode 155m of the main transistor 100, thereby improving the reliability of the semiconductor device.

[0112] According to an embodiment, the first and second protective layers 140 and 180 of the semiconductor device are further disposed in the peripheral circuit region PA. That is, the first and second protective layers 140 and 180 extend further onto the sub-channel layer 132s and the isolation structure 160 (described later). Thus, the first protective layer 140 covers the barrier layer 136 and the sub-gate electrode 155s disposed on the sub-channel layer 132s, and the second protective layer 180 covers the first protective layer 140.

[0113] The semiconductor device according to the embodiment further includes an isolation structure 160 located between the sub-transistor 320 and the main transistor 100 .

[0114] In one embodiment, the sub-transistor 320 is separated from the main transistor 100 by an isolation structure 160. For example, as shown in FIG. 3, the main transistor 100 and the sub-transistor 320 are spaced apart in the second direction (Y direction) by the isolation structure 160, but this is not limiting.

[0115] In one embodiment, the isolation structure 160 penetrates the barrier layer 136. For example, as shown in FIGS. 6 to 8, the isolation structure 160 penetrates the barrier layer 136, the channel layer 132, the seed layer 121, and the buffer layer 120 to recess at least a portion of the substrate 110. The isolation structure 160 is located between, but not limited to, the main gate semiconductor layer 152m and the sub-gate semiconductor layer 152s. This electrically insulates the sub-drift region DTRs of the sub-channel layer 132s from the main drift region DTRm of the main channel layer 132m. However, as another example, and not limited thereto, the isolation structure 160 penetrates the barrier layer 136 and the channel layer 132 and recesses at least a portion of the buffer layer 120. In one embodiment, the isolation structure 160 is formed by forming a barrier layer 136 on the main channel layer 132m and the sub-channel layer 132s, and then performing an ion implantation process in the barrier layer 136 located between the main transistor 100 and the sub-transistor 320. For example, little or no two-dimensional electron gas is formed in a region of the channel layer 132 that overlaps in the third direction (Z direction) with the region of the barrier layer 136 where the ion implantation process was performed. In this case, the ion implantation region of the barrier layer 136 and the corresponding region of the channel layer 132 correspond to the isolation structure 160. As another example, gate semiconductor layers 152m and 152s are formed on the barrier layer 136, and an ion implantation process is performed on the upper ends of the gate semiconductor layers 152m and 152s, followed by patterning. As a result, the exposed ion-implanted regions of the barrier layer 136, the channel layer 132, and the buffer layer 120 correspond to the isolation structure 160. Two-dimensional electron gas is absent or barely formed in the region of the channel layer 132 where the ion implantation process is performed. The material used in the ion implantation process is argon (Ar) ions. However, without being limited thereto, the isolation structure 160 can also be formed by forming a barrier layer 136 on the main channel layer 132m and the sub-channel layer 132s, forming a trench penetrating the barrier layer 136, and then filling the trench with an insulating material. The insulating material constituting the isolation structure 160 includes the same material as the first protective layer 140 and / or the second protective layer 180.For example, the insulating material forming the isolation structure 160 may include an oxide such as SiO2 or Al2O3. As another example, the insulating material forming the isolation structure 160 may include a nitride such as SiN or an oxynitride such as SiON. However, without being limited thereto, the insulating material forming the isolation structure 160 may include a material different from that of the first protective layer 140. In this case, at least a portion of the main channel layer 132m and / or the sub-channel layer 132s may be recessed together.

[0116] Resistance elements of semiconductor devices according to several embodiments will be described below with reference to FIGS.

[0117] 9 to 17 are diagrams illustrating semiconductor devices according to some embodiments.

[0118] Figures 9 to 17 show various modified examples of the semiconductor device according to the embodiment shown in Figures 1 to 8. The embodiments shown in Figures 9 to 17 correspond to the same parts as the embodiment shown in Figures 1 to 8, so a description thereof will be omitted and the description will focus on the differences. Also, the same reference numerals will be used for the same components as the previous embodiments.

[0119] 9 and 10, a semiconductor device according to some embodiments may include a plurality of source electrodes 170 and a plurality of drain electrodes 190.

[0120] 9, the source electrode 170 of the semiconductor device according to some embodiments includes a first source electrode 171 and a second source electrode 172 sequentially stacked in a third direction (Z direction) on the main channel layer 132m, and the drain electrode 190 includes a first drain electrode 191 and a second drain electrode 192 sequentially stacked in the third direction (Z direction) on the main channel layer 132m. The first source electrode 171 and the first drain electrode 191 are connected to the main channel layer 132m through the first passivation layer 140 and the barrier layer 136. The second source electrode 172 and the second drain electrode 192 are connected to the first source electrode 171 and the first drain electrode 191, respectively, through the second passivation layer 180. The first source electrode 171 and the first drain electrode 191 may include the same material as the second source electrode 172 and the second drain electrode 192, respectively, but may also include different materials.

[0121] Furthermore, in some embodiments, the field distribution layer 310 of the semiconductor device is located on the second passivation layer 180. The field distribution layer 310 is located on the second passivation layer 180 and spaced apart from the source electrode 170 and the drain electrode 190. The field distribution layer 310 includes the same material as the second source electrode 172. The field distribution layer 310 is formed by the same process as the second source electrode 172 and is located in the same layer as at least a portion of the second source electrode 172. However, without being limited thereto, the field distribution layer 310 may be located in a different layer from the second source electrode 172 and formed by a different process.

[0122] Still referring to FIG. 10, a semiconductor device according to some embodiments further includes a contact electrode 310C located between the field spreading layer 310 and the sub-channel layer 132s.

[0123] The contact electrode 310C is electrically connected to the sub-channel layer 132s through the first passivation layer 140 and the barrier layer 136. The contact electrode 310C is located in a recessed space of the sub-channel layer 132s. As a result, the contact electrode 310C contacts a portion of the side surface of the sub-channel layer 132s, but is not limited to this. The contact electrode 310C includes the same material as the first source electrode 171 and the first drain electrode 191. The contact electrode 310C is formed in the same process as the first source electrode 171 and the first drain electrode 191. However, the contact electrode 310C is not limited to this and may include a different material from the first source electrode 171 and the first drain electrode 191 and may be formed in a different process from the first source electrode 171 and the first drain electrode 191.

[0124] In some embodiments, the field dispersion layer 310 is connected to the contact electrode 310C through the second passivation layer 180. The field dispersion layer 310 overlaps the contact electrode 310C in the third direction (Z direction). The field dispersion layer 310 is electrically connected to the sub-channel layer 132s through the contact electrode 310C.

[0125] Referring to FIG. 11, in a semiconductor device according to some embodiments, a sub-gate semiconductor layer 152s is located spaced apart from a main gate semiconductor layer 152m.

[0126] In some embodiments, the sub-gate semiconductor layer 152s is located on the sub-channel layer 132s, and the main gate semiconductor layer 152m is located on the main channel layer 132m. In this case, the sub-gate semiconductor layer 152s is not located on the isolation structure 160 located between the main channel layer 132m and the sub-channel layer 132s. The sub-gate semiconductor layer 152s does not overlap with the isolation structure 160 in the third direction (Z direction). That is, the sub-gate semiconductor layer 152s is located only on the sub-channel layer 132s, but is not limited to this. In this case, the sub-gate electrode 155s covers the side and top surfaces of the sub-gate semiconductor layer 152s, and the main gate electrode 155m covers the side and top surfaces of the main gate semiconductor layer 152m, but is not limited to this. As another example, the sub-gate electrode 155s covers only the upper surface of the sub-gate semiconductor layer 152s, and the main gate electrode 155m covers only the upper surface of the main gate semiconductor layer 152m, and the sub-gate electrode 155s is electrically connected to the main gate electrode 155m via another upper wiring, etc.

[0127] 12 to 14, the field spreading layer 310 of the semiconductor device according to some embodiments may have various shapes.

[0128] In some embodiments, the field dispersion layer 310 has a shape that protrudes toward the drain electrode 190. For example, as shown in FIG. 12 , the field dispersion layer 310 includes a stepped portion 310S that has a step in the second direction (Y direction) in a plan view. The stepped portion 310S causes the field dispersion layer 310 to have a shape that protrudes toward the drain electrode 190 in a plan view. As a result, the width of the field dispersion layer 310 in the second direction (Y direction) includes a portion that decreases toward the drain electrode 190. As another example, as shown in FIG. 13 , the field dispersion layer 310 has a trapezoidal shape in a plan view. As a result, the width of the field dispersion layer 310 in the second direction (Y direction) decreases toward the drain electrode 190. As another example, as shown in FIG. 14 , the field dispersion layer 310 includes a protruding portion 310P that protrudes toward the drain electrode 190. The protruding portion 310P has a convex shape toward the drain electrode 190.

[0129] 15, according to some embodiments, the source electrode 170 of the semiconductor device further extends into the peripheral circuit region PA. In some embodiments, the source electrode 170 extends in the second direction (Y direction) and is located in the main device region MA and the peripheral circuit region PA. The source electrode 170 overlaps the sub-channel layer 132s in the third direction (Z direction). The source electrode 170 is connected to the sub-channel layer 132s in the peripheral circuit region PA.

[0130] 16, the sub-gate electrode 155s of a semiconductor device according to some embodiments may have various shapes. For example, the sub-gate electrode 155s overlaps the extension portion EP of the sub-channel layer 132s in the third direction (Z direction). The portion of the sub-gate electrode 155s that overlaps the extension portion EP in the third direction (Z direction) is located closer to the source electrode 170 than the field spreading layer 310. That is, the distance between the portion of the sub-gate electrode 155s that overlaps the extension portion EP in the third direction (Z direction) and the first contact portion CP1 is smaller than the distance between the portion of the sub-gate electrode 155s that overlaps the extension portion EP in the third direction (Z direction) and the second contact portion CP2. However, the present invention is not limited thereto, and the portion of the sub-gate electrode 155s that overlaps the extension portion EP in the third direction (Z direction) may be located farther from the source electrode 170 than the field spreading layer 310, or at substantially the same distance.

[0131] Referring to FIG. 17, a sub-channel layer 132s of a semiconductor device according to some embodiments is spaced apart from a main channel layer 132m.

[0132] In some embodiments, the sub-channel layer 132s is spaced apart from the main channel layer 132m in the second direction (Y direction), but is not limited thereto. A separation structure 160 is located between the sub-channel layer 132s and the main channel layer 132m. That is, the sub-channel layer 132s and the main channel layer 132m are separated by the separation structure 160. In some embodiments, the sub-channel layer 132s has a rectangular shape in plan view, but is not limited thereto.

[0133] Additionally, the source electrode 170, the sub-gate electrodes 155s, and the field spreading layer 310 of the semiconductor device according to some embodiments extend further into the peripheral circuit area PA.

[0134] For example, the source electrode 170, the sub-gate electrode 155s, and the field distribution layer 310 extend side by side. The source electrode 170, the sub-gate electrode 155s, and the field distribution layer 310 extend in the second direction (Y direction). The source electrode 170, the sub-gate electrode 155s, and the field distribution layer 310 are spaced apart from each other. The source electrode 170 and the field distribution layer 310 are connected to the sub-channel layer 132s. For example, the source electrode 170 is connected to the first contact portion CP1 of the sub-channel layer 132s through the first passivation layer 140 and the barrier layer 136. The field distribution layer 310 is connected to the second contact portion CP2 of the sub-channel layer 132s through the first passivation layer 140 and the barrier layer 136. The source electrode 170 and the field distribution layer 310 overlap the isolation structure 160 in the third direction (Z direction), but are not limited thereto.

[0135] In some embodiments, the sub-gate electrode 155s is located between the source electrode 170 and the field spreading layer 310. The sub-gate electrode 155s overlaps the sub-channel layer 132s in the third direction (Z direction). The sub-gate electrode 155s is located on the extension portion EP of the sub-channel layer 132s. That is, the sub-gate electrode 155s is located between the first contact portion CP1 and the second contact portion CP2 of the sub-channel layer 132s.

[0136] Hereinafter, a field distribution layer and a sub-transistor of a semiconductor device according to several embodiments will be described with reference to FIGS.

[0137] Fig. 18 is a circuit diagram showing a semiconductor device according to some embodiments. Fig. 19 is a plan view showing a semiconductor device according to the embodiment of Fig. 18. Fig. 20 is a cross-sectional view taken along line E-E' in Fig. 19. Fig. 21 is a cross-sectional view taken along line F-F' in Fig. 19. Figs. 19 to 21 are views showing a semiconductor device according to the embodiment of Fig. 18. Figs. 22 and 23 are views showing a semiconductor device according to the embodiment of Fig. 18.

[0138] Figures 18 to 23 show various modified examples of the semiconductor device according to the embodiment shown in Figures 1 to 8. The embodiments shown in Figures 18 to 23 correspond to the same parts as the embodiment shown in Figures 1 to 8, so a description thereof will be omitted and the description will focus on the differences. Also, the same reference numerals will be used for the same components as the previous embodiments.

[0139] 18, a semiconductor device according to some embodiments may include a plurality of field distribution layers 310. For example, a semiconductor device according to some embodiments may include first to third field distribution layers 311 to 313 located between the gate electrode G and the first electrode D of the main transistor 100. Also, a semiconductor device according to some embodiments may include a plurality of sub-transistors 320. For example, a semiconductor device according to some embodiments may include first to third sub-transistors 321 to 323 connected to the first to third field distribution layers 311 to 313, respectively.

[0140] The first to third field dispersion layers 311 to 313 serve to disperse the electric field concentrated around the gate electrode G of the main transistor 100. This reduces the leakage current in the main transistor 100 and increases the breakdown voltage of the main transistor 100.

[0141] Each of the first to third sub-transistors 321 to 323 controls a drain-source current according to a gate signal applied to the gate electrode. Each of the first to third sub-transistors 321 to 323 is electrically connected to one end of the main transistor 100. For example, a first electrode of each of the first to third sub-transistors 321 to 323 is electrically connected to a second electrode S of the main transistor 100, and a second power supply voltage V S A second electrode of the first sub-transistor 321 is electrically connected to the first field distribution layer 311, a second electrode of the second sub-transistor 322 is electrically connected to the second field distribution layer 312, and a second electrode of the third sub-transistor 323 is electrically connected to the third field distribution layer 313.

[0142] Furthermore, the gate electrodes of the first to third sub-transistors 321 to 323 are electrically connected to the gate electrode G of the main transistor 100. As a result, the same signal is applied to the gate electrodes of the first to third sub-transistors 321 to 323 and the gate electrode G of the main transistor 100, and the first to third sub-transistors 321 to 323 are turned on depending on whether the main transistor 100 is turned on or not.

[0143] 19 to 21, a semiconductor device according to some embodiments includes first to third field distribution layers 311 to 313 located between the main gate electrode 155m and the drain electrode 190, and first to third sub-transistors 321 to 323 connected to the first to third field distribution layers 311 to 313, respectively.

[0144] The first to third field dispersion layers 311 to 313 are located between the main gate electrode 155m and the drain electrode 190. For example, the first to third field dispersion layers 311 to 313 are located sequentially in a direction away from the main gate electrode 155m. That is, the first field dispersion layer 311 is located between the main gate electrode 155m and the second field dispersion layer 312, the second field dispersion layer 312 is located between the first field dispersion layer 311 and the third field dispersion layer 313, and the third field dispersion layer 313 is located between the second field dispersion layer 312 and the drain electrode 190.

[0145] The first to third field dispersion layers 311 to 313 are positioned spaced apart from one another. The first to third field dispersion layers 311 to 313 extend in a parallel direction. The first to third field dispersion layers 311 to 313 extend in a parallel direction to the main gate electrode 155m and the drain electrode 190. For example, the first to third field dispersion layers 311 to 313 extend in the second direction (Y direction) and are spaced apart from one another, but this is not limiting. Furthermore, the first to third field dispersion layers 311 to 313 are positioned spaced apart from the source electrode 170, the main gate electrode 155m, and the drain electrode 190.

[0146] In some embodiments, the first to third field dispersion layers 311 to 313 are located in the same layer. For example, as shown in FIG. 20, the first to third field dispersion layers 311 to 313 are located directly above the first protective layer 140. The first to third field dispersion layers 311 to 313 contact the upper surface of the first protective layer 140. However, this is not limited thereto, and the first to third field dispersion layers 311 to 313 may be located in different layers. This will be described later with reference to FIGS. 22 and 23.

[0147] In this case, a first distance D1 along the first direction (X direction) between the first field dispersion layer 311 and the second field dispersion layer 312 and a second distance D2 along the first direction (X direction) between the second field dispersion layer 312 and the third field dispersion layer 313 are substantially the same, but are not limited to this. Furthermore, the widths of the first to third field dispersion layers 311 to 313 are substantially the same. For example, a first width W1 along the first direction (X direction) of the first field dispersion layer 311, a second width W2 along the first direction (X direction) of the second field dispersion layer 312, and a third width W3 along the first direction (X direction) of the third field dispersion layer 313 are substantially the same, but are not limited to this. As another example, at least one of the first width W1 along the first direction (X-direction) of the first field dispersion layer 311, the second width W2 along the first direction (X-direction) of the second field dispersion layer 312, and the third width W3 along the first direction (X-direction) of the third field dispersion layer 313 may have different widths.

[0148] In some embodiments, the first to third field dispersion layers 311 to 313 are each connected to a sub-channel layer 132s. For example, the first field dispersion layer 311 is connected to the first sub-channel layer 132s1, the second field dispersion layer 312 is connected to the second sub-channel layer 132s2, and the third field dispersion layer 313 is connected to the third sub-channel layer 132s3. Here, the first to third sub-channel layers 132s1 to 132s3 refer to portions of the sub-channel layer 132s that constitute the channel layers of the first to third sub-transistors 321 to 323.

[0149] As a result, each of the first to third field dispersion layers 311 to 313 constitutes one electrode of one of the transistors. For example, the first field dispersion layer 311 constitutes one electrode of the first sub-transistor 321, the second field dispersion layer 312 constitutes one electrode of the second sub-transistor 322, and the third field dispersion layer 313 constitutes one electrode of the third sub-transistor 323.

[0150] In some embodiments, the sub-channel layer 132s includes first to third sub-channel layers 132s1 to 132s3 each connected to one field dispersion layer 310, and a connecting portion 132_C connected to the first to third sub-channel layers 132s1 to 132s3.

[0151] The first to third sub-channel layers 132s1 to 132s3 are spaced apart from one another. For example, as shown in Fig. 19, the first to third sub-channel layers 132s1 to 132s3 may extend in the second direction (Y direction) and be spaced apart from one another in the first direction (X direction), but this is not limiting. The first to third sub-channel layers 132s1 to 132s3 are connected to the first to third field dispersion layers 311 to 313. For example, the first field dispersion layer 311 is connected to the first sub-channel layer 132s1 through the first protective layer 140 and the barrier layer 136, the second field dispersion layer 312 is connected to the second sub-channel layer 132s2 through the first protective layer 140 and the barrier layer 136, and the third field dispersion layer 313 is connected to the third sub-channel layer 132s3 through the first protective layer 140 and the barrier layer 136. Here, the first to third sub-channel layers 132s1 to 132s3 refer to the sub-channel layer 132s portions constituting the channel layers of the first to third sub-transistors 321 to 323.

[0152] In some embodiments, the connecting portion 132_C is connected to the source electrode 170. For example, the source electrode 170 is connected to the connecting portion 132_C through the first passivation layer 140 and the barrier layer 136. The connecting portion 132_C is connected to the first to third sub-channel layers 132s1 to 132s3. As a result, the first to third sub-channel layers 132s1 to 132s3 are electrically connected to the source electrode 170 via the connecting portion 132_C.

[0153] In some embodiments, the sub-gate electrode 155s is located on the first to third sub-channel layers 132s1 to 132s3. The sub-gate electrode 155s overlaps the first to third sub-channel layers 132s1 to 132s3 in the third direction (Z direction) but does not overlap the connecting portion 132_C in the third direction (Z direction), but is not limited thereto. The sub-gate electrode 155s is located adjacent to the first to third field spreading layers 311 to 313, but is not limited thereto. The sub-gate electrode 155s extends to overlap the first to third sub-channel layers 132s1 to 132s3 in the third direction (Z direction). For example, the sub-gate electrode 155s extends in the first direction (X direction) and overlaps the first to third sub-channel layers 132s1 to 132s3 and the isolation structure 160 in the third direction (Z direction). The sub-gate electrodes 155s are located between a portion of the sub-channel layer 132s to which the source electrode 170 is connected and a portion of the sub-channel layer 132s to which the first field dispersion layer 311 is connected, between a portion of the sub-channel layer 132s to which the source electrode 170 is connected and a portion of the sub-channel layer 132s to which the second field dispersion layer 312 is connected, and between a portion of the sub-channel layer 132s to which the source electrode 170 is connected and a portion of the sub-channel layer 132s to which the third field dispersion layer 313 is connected. The sub-gate electrodes 155s are located spaced apart from the first to third field dispersion layers 311 to 313. The sub-gate electrodes 155s form gates of the first to third sub-transistors 321 to 323.

[0154] In some embodiments, the sub-gate semiconductor layer 152s is located between the barrier layer 136 and the sub-gate electrode 155s. The sub-gate semiconductor layer 152s is located on the first to third sub-channel layers 132s1 to 132s3. The sub-gate semiconductor layer 152s overlaps the first to third sub-channel layers 132s1 to 132s3 in the third direction (Z direction). For example, as shown in FIG. 21, the sub-gate semiconductor layer 152s overlaps each of the first to third sub-channel layers 132s1 to 132s3 in the third direction (Z direction). The sub-gate semiconductor layers 152s located on the first to third sub-channel layers 132s1 to 132s3, respectively, are spaced apart from each other. An isolation structure 160 is located between the sub-gate semiconductor layers 152s located on the first to third sub-channel layers 132s1 to 132s3, respectively. The sub-gate semiconductor layers 152s located on the first to third sub-channel layers 132s1 to 132s3, respectively, are separated from one another by, but not limited to, the isolation structure 160. The sub-gate semiconductor layers 152s located on the first to third sub-channel layers 132s1 to 132s3, respectively, do not overlap with the isolation structure 160 in the third direction (Z direction), but not limited to this.

[0155] The sub-gate semiconductor layer 152s forms a depletion region DPR in the sub-channel layer 132s. For example, as shown in Fig. 21, the sub-gate semiconductor layer 152s forms a first depletion region DPR1 in the first sub-channel layer 132s1, a second depletion region DPR2 in the second sub-channel layer 132s2, and a third depletion region DPR3 in the third sub-channel layer 132s3. The first to third depletion regions DPR1 to DPR3 refer to regions where the flow of the two-dimensional electron gas 134 is interrupted in the sub-drift region DTRs.

[0156] The sub-gate electrode 155s of the semiconductor device according to some embodiments overlaps in the third direction (Z direction) with the first to third sub-channel layers 132s1 to 132s3 constituting the channel layers of the first to third sub-transistors 321 to 323. Therefore, the first to third sub-transistors 321 to 323 are turned on or off together depending on a gate signal applied to the sub-gate electrode 155s. The operation method of the first to third sub-transistors 321 to 323 is substantially the same as the operation method of the sub-transistor 320 in the embodiment of FIGS. 1 to 8, and therefore will not be described here.

[0157] 22 and 23, a semiconductor device according to some embodiments further includes a third passivation layer 185 located on the second passivation layer 180, and the first to third field dispersion layers 311 to 313 are located in different layers.

[0158] In addition, according to some embodiments, the semiconductor device may include a plurality of source electrodes 170 and drain electrodes 190. For example, the source electrode 170 includes first to third source electrodes 171 to 173 sequentially stacked on the main channel layer 132m in the third direction (Z direction), and the drain electrode 190 includes first to third drain electrodes 191 to 193 sequentially stacked on the main channel layer 132m in the third direction (Z direction).

[0159] For example, the first field distribution layer 311 is located on the first protective layer 140. The first field distribution layer 311 is located directly on the top surface of the first protective layer 140. The first field distribution layer 311 is covered by the second protective layer 180. For example, the top and side surfaces of the first field distribution layer 311 are covered by the second protective layer 180. In this case, the first field distribution layer 311 is located in the same layer as at least a portion of the first source electrode 171. For example, the portion of the first source electrode 171 located on the first protective layer 140 is located in the same layer as the first field distribution layer 311, but is not limited to this. The first field distribution layer 311 includes the same material as the first source electrode 171. The first field distribution layer 311 is formed by the same process as the first source electrode 171. However, without being limited thereto, the first field distribution layer 311 may include a different material from the first source electrode 171 or may be formed by a different process.

[0160] The second field distribution layer 312 is located on the second protective layer 180. The second field distribution layer 312 is located directly on the top surface of the second protective layer 180. The second field distribution layer 312 is covered by the third protective layer 185. For example, the top and side surfaces of the second field distribution layer 312 are covered by the third protective layer 185. In this case, the second field distribution layer 312 is located in the same layer as at least a portion of the second source electrode 172. For example, the portion of the second source electrode 172 located on the second protective layer 180 is located in the same layer as the second field distribution layer 312, but this is not limiting. The second field distribution layer 312 includes the same material as the second source electrode 172. The second field distribution layer 312 is formed by the same process as the second source electrode 172. However, without limitation, the second field distribution layer 312 may include a different material from the second source electrode 172 or may be formed by a different process.

[0161] The third field distribution layer 313 is located on the third protective layer 185. The third field distribution layer 313 is located directly on the upper surface of the third protective layer 185. In this case, the third field distribution layer 313 is located on the same layer as at least a portion of the third source electrode 173. For example, the portion of the third source electrode 173 located on the third protective layer 185 is located on the same layer as the third field distribution layer 313, but is not limited to this.

[0162] The third field dispersion layer 313 includes the same material as the third source electrode 173. The third field dispersion layer 313 is formed together with the third source electrode 173 through the same process. However, without being limited thereto, the third field dispersion layer 313 may include a different material from the third source electrode 173 or may be formed through a different process.

[0163] Although FIG. 22 shows that the first to third field dispersion layers 311 to 313 are located on different layers, this is not limitative, and at least one of the first to third field dispersion layers 311 to 313 may be located on a different layer.

[0164] 18 to 23 illustrate the case where there are three field dispersion layers 310, but the number of field dispersion layers 310 is not limited thereto. For example, a semiconductor device according to some embodiments may include two field dispersion layers 310, or may include four or more field dispersion layers 310.

[0165] Hereinafter, a method for manufacturing a semiconductor device according to one embodiment will be described with reference to FIGS.

[0166] FIG. 24 is a plan view of an intermediate stage illustrating a method for manufacturing a semiconductor device according to an embodiment. FIG. 25 is a cross-sectional view taken along lines H-H' and I-I' in FIG. 24. FIG. 26 is a cross-sectional view taken along lines H-H' and I-I' in FIG. 24. FIG. 27 is a plan view of an intermediate stage illustrating a method for manufacturing a semiconductor device according to an embodiment. FIG. 28 is a cross-sectional view taken along lines J-J' and K-K' in FIG. 27. FIG. 29 is a plan view of an intermediate stage illustrating a method for manufacturing a semiconductor device according to an embodiment. FIG. 30 is a cross-sectional view taken along lines L-L' and M-M' in FIG. 29.

[0167] As shown in FIGS. 24 and 25, a seed layer 121, a buffer layer 120, a channel layer 132, a barrier layer 136, and a gate semiconductor material layer are sequentially formed on a substrate 110, an isolation structure 160 is formed, and a gate electrode 155 and a gate semiconductor layer 152 are formed.

[0168] First, in the main device region MA and the peripheral circuit region PA, a seed layer 121 and a buffer layer 120 are sequentially formed on a substrate 110. In one embodiment, the buffer layer 120 includes a superlattice layer 124 and a high-resistance layer 126.

[0169] The substrate 110 includes a semiconductor material. For example, the substrate 110 includes sapphire, Si, SiC, AlN, GaN, or a combination thereof. The substrate 110 may be a silicon-on-insulator (SOI) substrate. However, the material of the substrate 110 is not limited thereto, and any commonly used substrate may be used.

[0170] The seed layer 121 and the superlattice layer 124 are sequentially formed using an epitaxial growth method. The seed layer 121 and the superlattice layer 124 are made of the same semiconductor material. However, the material composition ratio of each layer may differ depending on the role of each layer and the performance required for the semiconductor device. The seed layer 121 and the superlattice layer 124 include one or more materials selected from III-V group materials, for example, nitrides containing Al, Ga, In, B, or a combination thereof. The seed layer 121 and the superlattice layer 124 include Alx In y Ga 1-x-y N, where 0≦x≦1, 0≦y≦1, x+y≦1. For example, the seed layer 121 and the superlattice layer 124 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof.

[0171] In one embodiment, the superlattice layer 124 is made up of multiple layers in which layers containing different materials are alternately stacked. For example, the superlattice layer 124 has a structure in which layers made of AlGaN and layers made of AlN are repeatedly stacked. That is, the superlattice layer 124 is formed by stacking AlGaN / AlN / AlGaN / AlN / AlGaN / AlN in this order.

[0172] The high-resistivity layer 126 is made of a material with low conductivity so as to provide electrical insulation between the substrate 110 and the channel layer 132. The high-resistivity layer includes one or more materials selected from III-V group materials, for example, nitrides containing Al, Ga, In, B, or a combination thereof. x In y Ga 1-x-y N (0≦x≦1, 0≦y≦1, x+y≦1). For example, the high-resistivity layer 126 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof. The high-resistivity layer 126 may consist of a single layer or multiple layers.

[0173] Next, a channel layer 132 and a barrier layer 136 are sequentially formed on the high resistance layer 126 in the main element region MA and the peripheral circuit region PA.

[0174] In one embodiment, the channel layer 132 and the barrier layer 136 are sequentially formed using an epitaxial growth method, for example, by forming the channel layer 132 on the high-resistivity layer 126 and then forming the barrier layer 136 on the channel layer 132.

[0175] The channel layer 132 and the barrier layer 136 are made of the same semiconductor material. However, the material composition ratio of each layer may differ depending on the role of each layer and the performance required for the semiconductor device. The channel layer 132 and the barrier layer 136 include one or more materials selected from III-V group materials, for example, nitrides containing Al, Ga, In, B, or combinations thereof. The channel layer 132 and the barrier layer 136 include Al x In y Ga 1-x-y N (0≦x≦1, 0≦y≦1, x+y≦1). For example, the channel layer 132 and the barrier layer 136 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof. The barrier layer 136 includes a material having a different energy bandgap than the channel layer 132. The barrier layer 136 has a higher energy bandgap than the channel layer 132.

[0176] In one example, the substrate 110 includes Si, the seed layer 121 includes AlN, and the superlattice layer 124 includes AlGaN and AlN. The high-resistivity layer 126 includes GaN, the channel layer 132 includes GaN, and the barrier layer 136 includes AlGaN. The channel layer 132 and the barrier layer 136 may be doped or undoped.

[0177] Subsequently, a gate semiconductor material layer is formed on the barrier layer 136. The gate semiconductor material layer is formed using an epitaxial growth method.

[0178] Subsequently, an ion implantation process is performed to form the isolation structure 160, which separates the main channel layer 132m and the sub-channel layer 132s from each other.

[0179] For example, an ion implantation process is performed on a portion of the gate semiconductor material layer and a portion of the barrier layer 136 located between the main device region MA and the peripheral circuit region PA to form the isolation structure 160. In this case, the ion implantation process is performed on at least a portion of the channel layer 132, the buffer layer 120, the seed layer 121, and the substrate 110. The isolation structure 160 recesses at least a portion of the substrate 110 through the gate semiconductor material layer, the barrier layer 136, the channel layer 132, the buffer layer 120, and the seed layer 121, but is not limited to this.

[0180] The channel layer 132 is separated into a main channel layer 132m and a sub-channel layer 132s by forming the isolation structure 160. However, without being limited thereto, the main channel layer 132m and the sub-channel layer 132s may be separated from each other by forming a trench penetrating the gate semiconductor material layer and the barrier layer 136 between the main device region MA and the peripheral circuit region PA.

[0181] Thereafter, a gate electrode material layer is formed on the gate semiconductor material layer in the main device region MA and the peripheral circuit region PA, and the gate semiconductor material layer and the gate electrode material layer are patterned to form the gate electrode 155 and the gate semiconductor layer 152.

[0182] Specifically, the gate electrode material layer is formed using a deposition process, for example, but not limited to, at least one of electron beam evaporation, sputtering, physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low pressure chemical vapor deposition (LP-CVD), plasma enhanced chemical vapor deposition (PE-CVD), or atomic layer deposition (ALD) techniques.

[0183] Subsequently, the gate electrode material layer and the gate semiconductor material layer are patterned using a photolithography and etching process to form the gate electrode 155 and the gate semiconductor layer 152. For example, a hard mask layer is formed on the gate electrode material layer, and then the gate semiconductor material layer is etched using the hard mask layer as a mask to remove at least a portion of the gate semiconductor material layer. As a result, the remaining portion of the gate electrode material layer becomes the gate electrode 155. The remaining portion of the gate semiconductor material layer becomes the gate semiconductor layer 152. The gate semiconductor layer 152 is located between the barrier layer 136 and the gate electrode 155. However, the present invention is not limited to this, and the gate electrode 155 and the gate semiconductor layer 152 may be formed by patterning using a photoresist pattern instead of the hard mask layer, or by patterning without using a hard mask layer. The gate electrode 155 forms a Schottky contact or an ohmic contact with the gate semiconductor layer 152.

[0184] In this case, the portion of the gate electrode 155 located in the main element region MA is referred to as the main gate electrode 155m, and the portion of the gate electrode 155 located in the peripheral circuit region PA is referred to as the sub-gate electrode 155s. Furthermore, the portion of the gate semiconductor layer located in the main element region MA is referred to as the main gate semiconductor layer 152m, and the portion of the gate semiconductor layer located in the peripheral circuit region PA is referred to as the sub-gate semiconductor layer 152s.

[0185] 26, a first protective layer 140 is formed on the barrier layer 136 and the gate electrode 155. For example, the first protective layer 140 is formed to cover the barrier layer 136 in the main device region MA, the gate electrode 155, and the barrier layer 136 in the peripheral circuit region PA. The first protective layer 140 is also formed on the isolation structure 160. The first protective layer 140 includes an insulating material. For example, the first protective layer 140 includes an oxide such as SiO2 or Al2O3. As another example, the first protective layer 140 may include a nitride such as SiN or an oxynitride such as SiON.

[0186] 27 and 28, the first protective layer 140 is patterned using a photolithography and etching process to form a first trench TR1 and a second trench TR2 in the main element region MA and a third trench TR3 in the peripheral circuit region PA, whereby not only the first protective layer 140 but also the barrier layer 136 and the channel layer 132 are patterned together.

[0187] For example, a photoresist pattern is formed on the first protective layer 140, and the first protective layer 140, the barrier layer 136, and the channel layer 132 are sequentially etched using the photoresist pattern as a mask. The first protective layer 140 and the barrier layer 136 are penetrated by the first trench TR1 and the second trench TR2, and the upper surface of the main channel layer 132m is recessed. The main channel layer 132m is not penetrated by the first trench TR1 or the second trench TR2. The first protective layer 140 and the barrier layer 136 are penetrated by the third trench TR3, and the upper surface of the sub-channel layer 132s is recessed. The sub-channel layer 132s is not penetrated by the third trench TR3.

[0188] In this case, the depth to which the upper surfaces of the main channel layer 132m and the sub-channel layer 132s are recessed is much smaller than the entire thickness of the main channel layer 132m. Also, the depth to which the upper surfaces of the main channel layer 132m and the sub-channel layer 132s are recessed is smaller than the thickness of the barrier layer 136. However, the present invention is not limited thereto, and the depth to which the upper surfaces of the main channel layer 132m and the sub-channel layer 132s are recessed may be variously changed.

[0189] The first trench TR1 and the second trench TR2 expose the side surfaces of the first protective layer 140 and the barrier layer 136 to the outside, and expose the top surface and side surfaces of the main channel layer 132m. The first trench TR1 exposes the side surfaces of the sub-channel layer 132s. The main channel layer 132m and the sub-channel layer 132s form the bottom surface and sidewalls of the first trench TR1, and the barrier layer 136 forms the sidewalls of the first trench TR1. The main channel layer 132m forms the bottom surface and sidewalls of the second trench TR2, and the barrier layer 136 forms the sidewalls of the second trench TR2.

[0190] The third trench TR3 exposes the side surfaces of the first protective layer 140 and the barrier layer 136 to the outside, and also exposes the top surface and side surfaces of the sub-channel layer 132s. The sub-channel layer 132s forms the bottom surface and sidewalls of the third trench TR3, and the barrier layer 136 forms the sidewalls of the third trench TR3.

[0191] The first trench TR1 and the second trench TR2 are spaced apart from each other. The first trench TR1 and the second trench TR2 are located on both sides of the gate electrode 155. The first trench TR1 is located on one side of the gate electrode 155 and spaced apart from the gate electrode 155. The second trench TR2 is located on the other side of the gate electrode 155 and spaced apart from the gate electrode 155. The distance from the first trench TR1 to the gate electrode 155 is smaller than the distance from the second trench TR2 to the gate electrode 155. The first trench TR1 and the second trench TR2 are shown to have similar shapes, such as width and depth, but are not limited thereto. The shapes of the first trench TR1 and the second trench TR2 may be variously modified.

[0192] As shown in FIGS. 29 and 30, a conductive material is deposited in the first trench TR1 to the third trench TR3 and then patterned to form the source electrode 170, the drain electrode 190, and the field dispersion layer 310.

[0193] In one embodiment, the source electrode 170 is formed to fill the first trench TR1. In the first trench TR1, the source electrode 170 contacts the main channel layer 132m and the barrier layer 136. The source electrode 170 contacts the side surfaces of the main channel layer 132m and the barrier layer 136. The source electrode 170 covers the side surfaces of the main channel layer 132m and the barrier layer 136. The source electrode 170 is electrically connected to the main channel layer 132m through the first trench TR1. The source electrode 170 is also electrically connected to the sub-channel layer 132s through the first trench TR1. An upper surface of the source electrode 170 protrudes from an upper surface of the first passivation layer 140.

[0194] The drain electrode 190 is formed to fill the second trench TR2. In the second trench TR2, the drain electrode 190 contacts the main channel layer 132m and the barrier layer 136. The drain electrode 190 contacts the side surfaces of the main channel layer 132m and the barrier layer 136. The drain electrode 190 covers the side surfaces of the main channel layer 132m and the barrier layer 136. The drain electrode 190 is electrically connected to the main channel layer 132m through the second trench TR2. An upper surface of the drain electrode 190 protrudes above an upper surface of the first passivation layer 140.

[0195] The source electrode 170 and the drain electrode 190 are in ohmic contact with the main channel layer 132m. The regions of the main channel layer 132m that contact the source electrode 170 and the drain electrode 190 are doped at a higher concentration than other regions. For example, the main channel layer 132m or the barrier layer 136 is doped by an ion implantation process, an annealing process, or the like. However, the doping process of the main channel layer 132m or the barrier layer 136 may include various other processes. The doping process of the main channel layer 132m or the barrier layer 136 is performed before forming the source electrode 170 and the drain electrode 190, but is not limited to this. In some cases, the main channel layer 132m and / or the barrier layer 136 may not be doped.

[0196] In one embodiment, the field dispersion layer 310 is formed to fill the third trench TR3. The field dispersion layer 310 is formed between the source electrode 170 and the drain electrode 190. The field dispersion layer 310 is also formed between the main gate electrode 155m and the drain electrode 190. The field dispersion layer 310 is formed on the first passivation layer 140 to extend in the same direction as the source electrode 170 and the drain electrode 190. The field dispersion layer 310 is formed to be spaced apart from the source electrode 170 and the drain electrode 190. For example, the field dispersion layer 310 extends in the second direction (Y direction) and is spaced apart from the source electrode 170 and the drain electrode 190 in the first direction (X direction), but is not limited thereto. In the third trench TR3, the field dispersion layer 310 contacts the sub-channel layer 132s. The field dispersion layer 310 contacts the side surfaces of the sub-channel layer 132s and the barrier layer 136. The field diffusion layer 310 is electrically connected to the sub-channel layer 132s through the third trench TR3. The field diffusion layer 310 may include, but is not limited to, the same material as the source electrode 170 and the drain electrode 190.

[0197] Although the embodiments of the present invention have been described in detail above, the technical scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention also belong to the technical scope of the present invention. [Explanation of symbols]

[0198] 100 Main Transistor 320 Sub-transistor 110 Substrate 132m main channel layer 132s subchannel layer 136 Barrier Layer 152 Gate semiconductor layer 155m Main gate electrode 170 Source electrode 190 drain electrode 310 Field Dispersion Layer 140 1st protective layer 120 buffer layer 121 seed layer

Claims

1. The main channel layer, a main gate electrode located on the main channel layer; a main gate semiconductor layer located between the main channel layer and the main gate electrode; a source electrode and a drain electrode located on both sides of the main gate electrode and connected to the main channel layer; a main transistor including a field diffusion layer located on the main channel layer and between the main gate electrode and the drain electrode; a sub-transistor connected to one end of the main transistor; Including, The sub-transistor is a sub-channel layer including a drift region having a two-dimensional electron gas, the sub-channel layer including a first contact portion connected to the source electrode, a second contact portion connected to the field dispersion layer, and an extension portion connecting the first contact portion and the second contact portion; a sub-gate electrode located on the extension of the sub-channel layer and connected to the main gate electrode.

2. The semiconductor device of claim 1 , wherein the field spreading layer extends in the same direction as the source electrode and is spaced apart from the source electrode.

3. a barrier layer located between the main channel layer and the main gate semiconductor layer, the barrier layer including a material having a different energy band gap from the main channel layer; a first protective layer covering the main gate electrode and the barrier layer, The semiconductor device of claim 1 , wherein the field dispersion layer is located on the first protective layer.

4. The semiconductor device of claim 3 , wherein the barrier layer and the first protective layer are located on the sub-channel layer.

5. the field dispersion layer is connected to the second contact portion of the sub-channel layer through the first protective layer and the barrier layer; 5. The semiconductor device of claim 4, wherein the source electrode is connected to the first contact portion of the sub-channel layer through the first passivation layer and the barrier layer.

6. The semiconductor device further includes a separation structure disposed between the main channel layer and the sub-channel layer, 6. The semiconductor device of claim 5, wherein at least a portion of the field dispersion layer overlaps the isolation structure and the sub-channel layer in a thickness direction.

7. a sub-gate semiconductor layer located between the sub-channel layer and the sub-gate electrode; The semiconductor device of claim 1 , wherein the sub-gate semiconductor layer is located in the same layer as the main gate semiconductor layer and includes the same material.

8. the sub-gate semiconductor layer includes the same material as the main gate semiconductor layer; 8. The semiconductor device according to claim 7, wherein the main gate electrode and the sub-gate electrode are integrally formed.

9. 10. The semiconductor device of claim 8, further comprising an isolation structure located between the main channel layer and the sub-channel layer, the isolation structure being further located between a sub-gate semiconductor layer and the main gate semiconductor layer.

10. 2. The semiconductor device of claim 1, wherein the main gate electrode and the sub-gate electrode are located in the same layer, contain the same material, and are integrally formed.

11. The semiconductor device of claim 1 , wherein the source electrode includes a portion that is made of the same material as the field diffusion layer and is located in the same layer as the field diffusion layer.

12. 2. The semiconductor device of claim 1, wherein at least a portion of the field dispersion layer overlaps the sub-channel layer in a thickness direction of the sub-channel layer.

13. The field dispersion layer comprises: a first field diffusion layer located on one side of the gate electrode; a second field dispersion layer located between the first field dispersion layer and the drain electrode, 2. The semiconductor device of claim 1, wherein the first field diffusion layer and the second field diffusion layer are respectively connected to the sub-channel layer and electrically connected to the source electrode.

14. a barrier layer located between the main channel layer and the main gate semiconductor layer, the barrier layer including a material having a different energy band gap from the main channel layer; a first protective layer covering the main gate electrode and the barrier layer; a second protective layer located on the first protective layer, the first field dispersion layer is located on the first protective layer; The semiconductor device of claim 13 , wherein the second field dispersion layer is located on the second passivation layer.

15. The source electrode is a first source electrode positioned on the sub-channel layer through the first protective layer; a second source electrode located on the first source electrode through the second protective layer; the first source electrode comprises the same material as the first field distribution layer; The semiconductor device of claim 14 , wherein the second source electrode comprises the same material as the second field spreading layer.

16. The main channel layer, a gate electrode located on the main channel layer; a gate semiconductor layer located between the main channel layer and the gate electrode; a source electrode and a drain electrode located on both sides of the gate electrode and connected to the main channel layer; a field diffusion layer located on the main channel layer and between the gate electrode and the drain electrode; a sub-channel layer including a drift region having a two-dimensional electron gas, the sub-channel layer including a first contact portion connected to the source electrode, a second contact portion connected to the field dispersion layer, and an extension portion connecting the first contact portion and the second contact portion; Including, The semiconductor device, wherein the gate electrode overlaps the extension of the sub-channel layer in a thickness direction of the sub-channel layer.

17. 17. The semiconductor device of claim 16, wherein the field spreading layer is spaced apart from the source electrode and the gate electrode in a thickness direction of the sub-channel layer.

18. a barrier layer located between the main channel layer and the gate semiconductor layer, the barrier layer including a material having a different energy band gap from the main channel layer; a first protective layer covering the gate electrode and the barrier layer, The semiconductor device of claim 16 , wherein the field dispersion layer is located on the first protective layer.

19. the field dispersion layer is connected to the second contact portion of the sub-channel layer through the first protective layer and the barrier layer; 20. The semiconductor device of claim 18, wherein the source electrode is connected to the first contact portion of the sub-channel layer through the first passivation layer and the barrier layer.

20. a main channel layer comprising GaN; a barrier layer located on the main channel layer and including AlGaN; a main gate electrode located on the barrier layer; a main gate semiconductor layer located between the main channel layer and the main gate electrode, the main gate semiconductor layer including GaN doped with p-type impurities; a source electrode and a drain electrode located on both sides of the main gate electrode and connected to the main channel layer; a first protective layer located on the main gate electrode and the barrier layer; a main transistor including a field diffusion layer located on the first passivation layer and between the main gate electrode and the drain electrode; a sub-transistor connected to one end of the main transistor; Including, The sub-transistor is a sub-channel layer located at one side of the main channel layer, including the same material as the main channel layer, and including: a first contact portion connected to the source electrode through the barrier layer; a second contact portion connected to the field dispersion layer through the first protective layer and the barrier layer; and an extension portion connecting the first contact portion and the second contact portion; a sub-gate electrode located on the extension of the sub-channel layer, connected to the main gate electrode, and made of the same material as the main gate electrode.

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