Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device capable of reducing stress acting on a bonding wire.SOLUTION: The semiconductor device includes a semiconductor element 40 in which a main electrode and a pad 44 are arranged on one surface of a semiconductor substrate 41, a bonding wire connected to the pad 44, and a sealing resin body. The semiconductor substrate 41 has an active region 45 and an outer peripheral region 46. The outer peripheral region 46 has a high temperature region 461 and a low temperature region 462 whose temperature is lower than that of the high temperature region 461 when the element is driven. The pad 44 is disposed on the low temperature region 462.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The disclosure herein relates to semiconductor devices and methods for manufacturing the same. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor element. The semiconductor element has a first main electrode and a pad on one side and a second main electrode on the back side. The contents of the prior art document are incorporated by reference as an explanation of the technical elements in this specification. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-27183 Summary of the Invention [Problem to be solved by the invention]

[0004] A bonding wire is connected to the pad. The semiconductor element and the bonding wire are encapsulated in an encapsulating resin. In such a configuration, thermal stress, such as that caused by a power cycle or a thermal cycle, acts on the bonding wire. In the above-mentioned respects and in other respects not mentioned, further improvements are required in semiconductor devices.

[0005] The present disclosure has been made in view of the above-mentioned problems, and has an object to provide a semiconductor device that can reduce the stress acting on bonding wires. [Means for solving the problem]

[0006] The semiconductor device disclosed herein comprises: a semiconductor substrate (41) having an active region (45) which is an element formation region and a peripheral region (46) surrounding the active region; a main electrode (42) arranged on one surface of the semiconductor substrate so as to overlap with the active region and electrically connected to the active region; and a pad (44) which is an electrode for signals arranged on the one surface so as to overlap with the peripheral region; a bonding wire (90) connected to the pad; an encapsulating resin body (30) that encapsulates the semiconductor element and the bonding wires; Equipped with The peripheral region has a high temperature region (461) and a low temperature region (462) that has a lower temperature than the high temperature region when the element is operating, The pad is disposed on the cold region. In one of the disclosures, The pads include pads arranged biased toward the edge of the semiconductor element between the active region and the edge (41c) of the semiconductor element, excluding the four corners of the semiconductor element having a rectangular planar shape. In another aspect of the disclosure, the active region has IGBT regions (45i) and diode regions (45d) alternately arranged with the IGBT regions in a predetermined direction; The pad is disposed between the active area and the edge (41c) of the semiconductor element in a predetermined direction; A diode region is disposed at the end of the active region on the pad side. Another disclosure is a protective portion (35) provided around the bonding portion of the bonding wire with the pad, interposed between the sealing resin body and the bonding wire, and protecting the bonding wire from expansion and contraction of the sealing resin body; The protective portion has lower rigidity than the sealing resin body. Another disclosure is a protective portion (35) provided around the bonding portion of the bonding wire with the pad, interposed between the sealing resin body and the bonding wire, and protecting the bonding wire from expansion and contraction of the sealing resin body; The protective portion is a hollow portion. In another aspect of the disclosure, The semiconductor element has a first main electrode that is a main electrode arranged on one surface, and a second main electrode (43) that is arranged on a back surface that is the surface opposite to the first surface, a first wiring member (50) electrically connected to the first main electrode; a second wiring member (60) electrically connected to the second main electrode; a conductive spacer (70) interposed between the first main electrode and the first wiring member, one of whose end faces is connected to the first main electrode and the other of whose end faces is connected to the first wiring member; The conductive spacer has a roughened portion (71) provided on the side surface connected to the end face except the surface facing the pad, and a non-roughened portion (72) provided on the surface facing the pad.

[0007] According to the disclosed semiconductor device, since the pad is disposed in a low-temperature region, the amount of heat received by the bonding wire can be reduced compared to a configuration in which the pad is disposed in a high-temperature region, thereby reducing the stress acting on the bonding wire.

[0008] The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The reference numerals in parentheses in the claims and in this section are intended to exemplify correspondences with the following embodiments and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become more apparent by reference to the following detailed description and the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram showing a schematic configuration of a vehicle drive system to which a semiconductor device according to a first embodiment is applied; [Figure 2] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. [Figure 4]FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 2. [Figure 5] FIG. 1 is a plan view showing a semiconductor element. [Figure 6] FIG. 10 is a diagram showing the temperature distribution of a semiconductor element. [Figure 7] FIG. [Figure 8] FIG. [Figure 9] FIG. 10 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 10] FIG. [Figure 11] FIG. [Figure 12] FIG. [Figure 13] FIG. [Figure 14] FIG. 10 is a cross-sectional view showing the periphery of a bonded portion between a bonding wire and a pad in a semiconductor device according to a third embodiment. [Figure 15] FIG. 10 is a cross-sectional view showing the periphery of a bonded portion of a bonding wire to a pad in a semiconductor device according to a fourth embodiment. [Figure 16] FIG. 10 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. [Figure 17] 1 is a plan view showing a connection structure between a semiconductor element and a conductive spacer; [Figure 18] FIG. 10 is a diagram showing the relationship between the presence or absence of a non-roughened portion and the equivalent plastic strain amplitude. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, several embodiments will be described with reference to the drawings. Note that in each embodiment, corresponding components are designated by the same reference numerals, and redundant description may be omitted. When only a portion of the configuration is described in each embodiment, the configuration of another embodiment previously described may be applied to the remaining portion of the configuration. Furthermore, in addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations of several embodiments may be partially combined together even if not explicitly stated, provided that there is no particular problem with the combination.

[0011] The semiconductor device of this embodiment is applied to, for example, a power conversion device of a mobile object using a rotating electric machine as a drive source. The mobile object may be, for example, an electric vehicle such as a battery electric vehicle (BEV), a hybrid electric vehicle (HEV), or a plug-in hybrid electric vehicle (PHEV), an aircraft such as an electric vertical take-off and landing aircraft or a drone, a ship, a construction machine, or an agricultural machine. An example of application to a vehicle will be described below.

[0012] (First embodiment) First, the schematic configuration of a vehicle drive system will be described with reference to FIG.

[0013] <Vehicle drive system> As shown in FIG. 1, a vehicle drive system 1 includes a DC power supply 2, a motor generator 3, and a power conversion device 4.

[0014] The DC power supply 2 is a DC voltage source made up of a rechargeable secondary battery. The secondary battery is, for example, a lithium-ion battery or a nickel-metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a drive source for the vehicle, i.e., an electric motor. The motor generator 3 functions as a generator during regeneration. The power conversion device 4 converts power between the DC power supply 2 and the motor generator 3.

[0015] <Power conversion device> As shown in FIG. 1, the power conversion device 4 includes a smoothing capacitor 5 and an inverter 6.

[0016] The smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to a P line 7, which is a power line on the high potential side, and an N line 8, which is a power line on the low potential side. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. Similarly, the negative electrode is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

[0017] The inverter 6 is a DC-AC conversion circuit. The inverter 6 converts a DC voltage into a three-phase AC voltage in accordance with switching control by a control circuit (not shown) and outputs the voltage to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to rotational force from the wheels into a DC voltage in accordance with switching control by the control circuit and outputs the DC voltage to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power supply 2 and the motor generator 3.

[0018] The inverter 6 is configured with upper and lower arm circuits 9 for three phases. The upper and lower arm circuits 9 are sometimes referred to as legs. Each upper and lower arm circuit 9 has an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side. The connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase in the motor generator 3 via an output line 10. The inverter 6 has six arms. At least a portion of each of the P line 7, the N line 8, and the output line 10 is made up of a conductive member such as a bus bar.

[0019] The elements constituting each arm include an insulated gate bipolar transistor 11 (hereinafter referred to as IGBT 11) which is a switching element, and a freewheeling diode 12. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. In this embodiment, an n-channel IGBT 11 is used. The diode 12 is connected in anti-parallel to the corresponding IGBT 11. In the upper arm 9H, the collector of the IGBT 11 is connected to the P line 7. In the lower arm 9L, the emitter of the IGBT 11 is connected to the N line 8. The emitter of the IGBT 11 in the upper arm 9H and the collector of the IGBT 11 in the lower arm 9L are connected to each other. The anode of the diode 12 is connected to the emitter of the corresponding IGBT 11, and the cathode is connected to the collector.

[0020] The power conversion device 4 may further include a converter as a power conversion circuit. The converter is a DC-DC conversion circuit that converts a DC voltage into a DC voltage of a different value. The converter is provided between the DC power supply 2 and the smoothing capacitor 5. The converter is configured with, for example, a reactor and the above-mentioned upper and lower arm circuits 9. This configuration allows for voltage increase and decrease. The power conversion device 4 may also include a filter capacitor that removes power supply noise from the DC power supply 2. The filter capacitor is provided between the DC power supply 2 and the converter.

[0021] The power conversion device 4 may include a drive circuit for a switching element constituting the inverter 6 or the like. The drive circuit supplies a drive voltage to the gate of the IGBT 11 of the corresponding arm based on a drive command from the control circuit. The drive circuit drives the corresponding IGBT 11, i.e., turns it on and off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0022] The power conversion device 4 may include a control circuit for the switching elements. The control circuit generates a drive command for operating the IGBT 11 and outputs it to the drive circuit. The control circuit generates the drive command based on a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. The various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as the drive command. The control circuit is configured to include, for example, a processor and a memory. ECU is an abbreviation for Electronic Control Unit. PWM is an abbreviation for Pulse Width Modulation.

[0023] <Semiconductor device> Fig. 2 is a plan view showing the semiconductor device. Fig. 2 is a top plan view of the semiconductor device. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 2. Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 2.

[0024] In the following, the thickness direction of a semiconductor element (semiconductor substrate) is referred to as the Z direction. The direction perpendicular to the Z direction is referred to as the X direction. The direction perpendicular to both the Z direction and the X direction is referred to as the Y direction. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is referred to as the planar shape. Furthermore, the planar view from the Z direction may sometimes be simply referred to as the planar view.

[0025] 2 to 4, the semiconductor device 20 includes a sealing resin body 30, a semiconductor element 40, wiring members 50 and 60, a conductive spacer 70, an external connection terminal 80, and a bonding wire 90. The semiconductor device 20 further includes bonding materials 100 to 102. The semiconductor device 20 constitutes one of the arms described above. Thus, two semiconductor devices 20 constitute an upper and lower arm circuit 9 for one phase.

[0026] The encapsulating resin body 30 encapsulates some of the other elements that constitute the semiconductor device 20. The remaining parts of the other elements are exposed to the outside of the encapsulating resin body 30. An example of the resin that constitutes the encapsulating resin body is an epoxy resin. The encapsulating resin body 30 is molded, for example, by a transfer molding method. The encapsulating resin body 30 may also be called a molded resin, a resin molded body, or the like.

[0027] As shown in FIGS. 2 to 4, the sealing resin body 30 has a generally rectangular planar shape. The sealing resin body 30 has, as surfaces forming an outer periphery, one surface 30a and a back surface 30b opposite to the one surface 30a in the Z direction. The one surface 30a and the back surface 30b are, for example, generally flat surfaces. The sealing resin body 30 also has side surfaces 30c, 30d, 30e, and 30f continuous with the one surface 30a and the back surface 30b. The side surface 30c is the surface from which the main terminals 81 and 82 of the external connection terminals 80 protrude. The side surface 30d is the surface opposite to the side surface 30c in the Y direction. The side surface 30d is the surface from which the signal terminal 83 protrudes. The side surfaces 30e and 30f are surfaces from which the external connection terminals 80 do not protrude. The side surface 30e is the surface opposite to the side surface 30f in the X direction.

[0028] The semiconductor element 40 includes a semiconductor substrate 41, an emitter electrode 42, a collector electrode 43, and a pad 44. The semiconductor element 40 is sometimes referred to as a semiconductor chip. The semiconductor substrate 41 is made of a material such as silicon (Si) or a wide bandgap semiconductor with a wider bandgap than silicon, and a vertical element is formed on the semiconductor substrate 41. Examples of wide bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond.

[0029] The vertical element is configured to pass a main current in the thickness direction of the semiconductor substrate 41 (semiconductor element 40), i.e., in the Z direction. The vertical element of this embodiment is an IGBT 11 and a diode 12 that form one arm. The vertical element is an IGBT with the diode 12 connected in reverse parallel, i.e., an RC (Reverse Conducting)-IGBT. The vertical element is a heat-generating element that generates heat when current is applied. A gate electrode (not shown) is formed on the semiconductor substrate 41. The gate electrode has, for example, a trench structure.

[0030] The semiconductor substrate 41 has one surface 41a and a back surface 41b as plate surfaces on which main electrodes are provided. The one surface 41a is the surface of the semiconductor substrate 41 facing the one surface 30a of the sealing resin body 30. The back surface 41b is the surface opposite to the one surface 41a in the plate thickness direction. An emitter electrode 42, which is one of the main electrodes, is disposed on the one surface 41a of the semiconductor substrate 41. A collector electrode 43, which is the other of the main electrodes, is disposed on the back surface 41b of the semiconductor substrate 41.

[0031] When the IGBT 11 is turned on, a current (main current) flows between the emitter electrode 42, which is a main electrode (first main electrode), and the collector electrode 43, which is a main electrode (second main electrode). The emitter electrode 42 also serves as the anode electrode of the diode 12. The collector electrode 43 also serves as the cathode electrode of the diode 12. The collector electrode 43 is formed on almost the entire back surface 41b of the semiconductor substrate 41. The emitter electrode 42 is formed on a portion of one surface 41a of the semiconductor substrate 41.

[0032] The pads 44 are electrodes for signals. The pads 44 are formed on one surface 41a of the semiconductor substrate 41 in an area different from the area where the emitter electrode 42 is formed. The pads 44 are formed at the end opposite the area where the emitter electrode 42 is formed in the Y direction. The pads 44 are provided alongside the emitter electrode 42 in the Y direction. The number of pads 44 is not particularly limited. The pads 44 include at least a pad for a gate electrode. Details of the semiconductor element 40 will be described later.

[0033] The semiconductor element 40 has a protective film (not shown) disposed on one surface 41a of the semiconductor substrate 41. The protective film is an insulating film provided on one surface 41a of the semiconductor substrate 41. Examples of materials that can be used for the protective film include polyimide and silicon nitride. The protective film 56 has openings that define the junction regions of the emitter electrode 42 and the pad 44.

[0034] The wiring member 50 is electrically connected to the emitter electrode 42 and provides a wiring function. Similarly, the wiring member 60 is electrically connected to the collector electrode 43 and provides a wiring function. The wiring members 50, 60 are arranged to sandwich the semiconductor element 40 in the Z direction. The wiring members 50, 60 are arranged so that at least a portion of each of them faces each other in the Z direction. The wiring members 50, 60 enclose the semiconductor element 40 in a plan view. The wiring member 50 is sometimes referred to as a first wiring member, and the wiring member 60 is sometimes referred to as a second wiring member.

[0035] The wiring members 50, 60 provide a heat dissipation function for dissipating heat generated by the semiconductor element 40. The wiring members 50, 60 may also be referred to as heat sinks or heat sinks. The wiring members 50, 60 of this embodiment are metal plates made of a metal with good conductivity, such as Cu or a Cu alloy. The metal plate is provided, for example, as part of a lead frame. Instead of a metal plate, a substrate having a metal body disposed on the surface of an insulating base material may be used. The wiring members 50, 60 may have a plating film of Ni, Au, or the like on the surface.

[0036] The wiring member 50 has an opposing surface 50a, which is the surface facing the semiconductor element 40, and a back surface 50b, which is the surface opposite the opposing surface 50a. Similarly, the wiring member 60 also has an opposing surface 60a and a back surface 60b. The wiring members 50 and 60 have, for example, a substantially rectangular planar shape. The back surfaces 50b and 60b of the wiring members 50 and 60, respectively, are exposed from the encapsulating resin body 30. The back surfaces 50b and 60b are sometimes referred to as heat dissipation surfaces or exposed surfaces. The back surface 50b of the wiring member 50 is substantially flush with one surface 30a of the encapsulating resin body 30. The back surface 60b of the wiring member 60 is substantially flush with the back surface 30b of the encapsulating resin body 30.

[0037] The conductive spacer 70 is interposed between the semiconductor element 40 and the wiring member 50. The conductive spacer 70 functions as a spacer to ensure a predetermined distance between the semiconductor element 40 and the wiring member 50. For example, the conductive spacer 70 ensures a height sufficient to electrically connect the corresponding signal terminal 83 to the pad 44 of the semiconductor element 40. The conductive spacer 70 is located midway along the electrical and thermal conduction paths between the emitter electrode 42 of the semiconductor element 40 and the wiring member 50, and provides wiring and heat dissipation functions.

[0038] The conductive spacer 70 contains a metal material such as Cu that has good electrical and thermal conductivity. The conductive spacer 70 may have a plating film on its surface. The conductive spacer 70 may also be called a terminal, a terminal block, a metal block, or the like. The conductive spacer 70 of this embodiment is a columnar body that is substantially rectangular in plan view.

[0039] The external connection terminals 80 are terminals for electrically connecting the semiconductor device 20 to external devices. The external connection terminals 80 are formed using a metal material with good conductivity, such as copper. The external connection terminals 80 are, for example, a plate material. The external connection terminals 80 are sometimes called leads. The external connection terminals 80 include main terminals 81 and 82 and a signal terminal 83. The main terminals 81 and 82 are external connection terminals 80 electrically connected to main electrodes of the semiconductor element 40.

[0040] The main terminal 81 is electrically connected to the emitter electrode 42. The main terminal 81 is sometimes referred to as an emitter terminal. The main terminal 81 is connected to one end of the wiring member 50 in the Y direction. The thickness of the main terminal 81 is thinner than that of the wiring member 50. The main terminal 81 is connected to the wiring member 50 so as to be, for example, substantially flush with the opposing surface 50a. The main terminal 81 may be connected by being provided continuously and integrally with the wiring member 50, or may be provided as a separate member and connected by joining.

[0041] The main terminal 81 in this embodiment is provided integrally with the wiring member 50 as part of the lead frame. The main terminal 81 extends in the Y direction from the wiring member 50 and protrudes to the outside from the side surface 30c of the sealing resin body 30. The main terminal 81 has a bent portion midway through the portion covered by the sealing resin body 30, and protrudes from near the center in the Z direction on the side surface 30c.

[0042] The main terminal 82 is electrically connected to the collector electrode 43. The main terminal 82 is sometimes referred to as a collector terminal. The main terminal 82 is connected to the collector electrode 43 via the wiring member 60. The main terminal 82 is connected to one end of the wiring member 60 in the Y direction. The thickness of the main terminal 82 is thinner than that of the wiring member 60. The main terminal 82 is connected to the wiring member 60 so as to be substantially flush with the opposing surface 60a, for example. The main terminal 82 may be connected by being provided continuously and integrally with the wiring member 60, or may be provided as a separate member and connected by joining.

[0043] The main terminal 82 of this embodiment is provided integrally with the wiring member 60 as part of a lead frame separate from the main terminal 81. The main terminal 82 extends in the Y direction from the wiring member 60 and protrudes to the outside from the same side surface 30c as the main terminal 81. The main terminal 82 also has a bent portion midway through the portion covered by the sealing resin body 30, and protrudes from near the center in the Z direction on the side surface 30c. The two main terminals 81, 82 are arranged side by side in the X direction with their side surfaces facing each other.

[0044] The signal terminals 83 are electrically connected to the corresponding pads 44 of the semiconductor element 40. The signal terminals 83 are electrically connected to the pads 44 via bonding wires 90. The signal terminals 83 extend in the Y direction and protrude from the side surface 30d of the sealing resin body 30 to the outside. The semiconductor device 20 of this embodiment has five signal terminals 83 corresponding to the pads 44. The five signal terminals 83 are arranged side by side in the X direction. The signal terminals 83 are formed on a lead frame that is common to the wiring member 60 and the main terminals 82, for example. The multiple signal terminals 83 are electrically isolated from each other by cutting tie bars (not shown).

[0045] The emitter electrode 42 of the semiconductor element 40 is bonded to the conductive spacer 70 via a bonding material 100. The conductive spacer 70 is bonded to the wiring member 50 via a bonding material 101. The collector electrode 43 of the semiconductor element 40 is bonded to the wiring member 60 via a bonding material 102. The bonding materials 100 to 102 are conductive bonding materials. For example, solder can be used as the bonding materials 100 to 102. One example of solder is a multi-component lead-free solder containing Cu, Ni, and the like in addition to Sn. A sinter-based bonding material such as sintered silver may be used instead of solder. The bonding materials 100 to 102 may be made of the same material or different materials. In this embodiment, solder is used as the bonding materials 100, 101, and 102.

[0046] As described above, in the semiconductor device 20, the semiconductor element 40 constituting one arm is encapsulated by the encapsulating resin body 30. The encapsulating resin body 30 integrally encapsulates the semiconductor element 40, a portion of the wiring member 50, a portion of the wiring member 60, the conductive spacer 70, a portion of each of the external connection terminals 80, the bonding wires 90, and the bonding materials 100 to 102.

[0047] In the Z direction, the semiconductor element 40 is disposed between the wiring members 50 and 60. The semiconductor element 40 is sandwiched between the wiring members 50 and 60, which are disposed opposite each other. This allows heat from the semiconductor element 40 to be dissipated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 50b of the wiring member 50 is substantially flush with one surface 30a of the sealing resin body 30. The back surface 60b of the wiring member 60 is substantially flush with the back surface 30b of the sealing resin body 30. Because the back surfaces 50b and 60b are exposed surfaces, heat dissipation can be improved.

[0048] <Semiconductor element> FIG. 5 is a plan view showing one surface of a semiconductor element 40. For convenience, the active region including the IGBT region and the diode region is shown by a solid line in FIG. 5. The emitter electrode 42 is also omitted from the illustration. In the following, the terms "inside" and "outside" refer to a relative positional relationship with the center of the active region of the semiconductor element as the reference position. The side closer to the center is the inside, and the side farther from the center is the outside.

[0049] As shown in Fig. 5, the semiconductor substrate 41 has a generally rectangular shape in plan view. The semiconductor substrate 41 has an active region 45. The active region 45 is a region where elements (vertical elements) are formed. The active region 45 may also be referred to as a main region, a main cell region, a cell region, an element region, etc. The active region 45 has, for example, a generally rectangular shape in plan view.

[0050] The active region 45 has an IGBT region 45i where the IGBT is formed and a diode region 45d where the diode is formed of the RC-IGBT. The IGBT regions 45i and the diode regions 45d are alternately provided in the X direction. The active region 45 has a plurality of cells (unit structural parts). The plurality of cells are connected in parallel to each other to form the RC-IGBT.

[0051] The semiconductor substrate 41 has a peripheral region 46 that surrounds the active region 45. In a plan view, the peripheral region 46 is a region that is located outside the peripheral edge of the active region 45. Although not shown, a breakdown voltage structure such as a guard ring is formed in the peripheral region 46.

[0052] The emitter electrode 42 is disposed on the surface 41a so as to overlap the active region 45 in a plan view. For example, the emitter electrode 42 substantially coincides with the active region 45 in a plan view. The emitter electrode 42 is electrically connected to the active region 45. The emitter electrode 42 is electrically connected to the IGBT region 45i (emitter region) and the diode region 45d (anode region). The emitter electrode 42 is electrically isolated from the gate electrode.

[0053] As described above, the pads 44 are arranged alongside the emitter electrodes 42 in the Y direction. That is, the pads 44 are arranged in the Y direction between the outer peripheral edge of the active region 45 and the edge 41c of the semiconductor substrate 41. The semiconductor element 40 of this embodiment has five pads 44.

[0054] The five pads 44 include one for the gate electrode, one for the Kelvin emitter that detects the emitter potential of the IGBT 11, one for current sensing, and one for the anode potential and cathode potential of a temperature sensing diode (temperature sensing element) that detects the temperature of the semiconductor element 40. The Kelvin emitter pad 44 is electrically connected to the emitter electrode 42. The other pads 44 are electrically isolated from the emitter electrode 42.

[0055] <Temperature of semiconductor element> Fig. 6 is a diagram showing the temperature distribution of the semiconductor element 40. Fig. 6 shows the results of a simulation of the temperature when the element is operating. The pad 44 is omitted here. The configuration of the semiconductor element 40 is the same as that shown in Fig. 5, except for the pad 44.

[0056] As shown in FIG. 6, the temperature is highest near the center 45c of the active region 45, and decreases with increasing distance from the center 45c. The center 45c is the center in a plan view and is sometimes referred to as the element center. The temperature of the active region 45 is higher than the temperature of the peripheral region 46. In the active region 45, the temperature of the IGBT region 45i is higher than the temperature of the diode region 45d. The temperature of the peripheral region 46 is lower than the temperature of the active region 45. The temperature of the portion of the peripheral region 46 closer to the center 45c is higher than the temperature of the portion farther from the center 45c.

[0057] 5, the peripheral region 46 of the semiconductor substrate 41 has a high-temperature region 461 and a low-temperature region 462 that has a lower temperature than the high-temperature region 461 when the device is operating. The high-temperature region 461 is a portion near the center of the semiconductor substrate 41 in the X direction and adjacent to the active region 45. In FIG. 5, the high-temperature region 461 is indicated by a dashed line. The portion between the peripheral edge of the active region 45 and the end 41c of the semiconductor substrate 41, excluding the high-temperature region 461, is the low-temperature region 462. In FIG. 5, only the high-temperature region between the peripheral edge of the active region 45 and the end 41c of the semiconductor substrate 41 is shown.

[0058] <Pad placement> As shown in FIG. 5, five pads 44 are formed together on one end side in the Y direction of the semiconductor substrate 41, which has a generally rectangular shape in plan view. The five pads 44 are arranged in the peripheral region 46 between the active region 45 and the end 41c. The five pads 44 are lined up in the X direction. The five pads 44 are arranged along the end 41c of the semiconductor substrate 41. The five pads 44 are arranged biased toward the end 41c in the Y direction. In other words, the distance between the five pads 44 and the end 41c is smaller than the distance between the five pads 44 and the active region 45. The five pads 44 are arranged in the low temperature region 462.

[0059] <Summary of the First Embodiment> According to the semiconductor device 20 of this embodiment, the pad 44 is disposed on the low-temperature region 462 of the peripheral region 46. The temperature of the low-temperature region 462 is lower than that of the high-temperature region 461 when the element is operating. Therefore, the amount of heat received by the bonding wire 90 can be reduced compared to a configuration in which the pad 44 is disposed on the high-temperature region 461. This reduces the stress acting on the bonding wire 90, specifically, the thermal stress due to the difference in the linear expansion coefficients between the semiconductor element 40 and the bonding wire 90. Since the stress acting on the bonded portion of the bonding wire 90 with the pad 44 can be reduced, it is possible to prevent cracks from occurring at the bonded portion and prevent the bonding wire 90 from breaking.

[0060] <Modification> The arrangement of the pads 44 is not limited to the above example. For example, as shown in FIG. 7, the pads 44 may be arranged between the active region 45 and the end 41c near the end in the X direction. Of the five pads 44, three are arranged on one side and the remaining two are arranged on the other end. In addition, each pad 44 is arranged so that its longitudinal direction is in the Y direction. As described above, the five pads 44 can be arranged while avoiding the high-temperature region 461 near the center. In other words, all pads 44 can be arranged in the low-temperature region 462. As in FIG. 5, FIG. 7 illustrates only the high-temperature region 461 between the outer periphery of the active region 45 and the end 41c of the semiconductor substrate 41.

[0061] As shown in FIG. 8, the arrangement of the IGBT regions 45i and the diode regions 45d may be different from the examples shown in FIGS. 5 and 7. In FIG. 8, the IGBT regions 45i and the diode regions 45d are alternately arranged in the Y direction. In addition, the diode regions 45d are provided at the ends in the alternating direction. As a result, the diode regions 45d form the outer periphery of the active region 45 facing the end 41c. As described above, the temperature of the diode regions 45d is lower than the temperature of the IGBT regions 45i. As a result, the entire area between the active region 45 and the end 41c becomes a low-temperature region 462. Because there is no high-temperature region 461 between the active region 45 and the end 41c, the degree of freedom in arranging the pads 44 can be improved.

[0062] (Second embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used.

[0063] Fig. 9 is a cross-sectional view showing the semiconductor device 20 of this embodiment. Fig. 9 corresponds to Fig. 3. As shown in Fig. 9, the semiconductor device 20 of this embodiment further includes a protective portion .

[0064] The protective portion 35 protects the bonding wire 90 from expansion and contraction of the encapsulating resin body 30. For example, when the encapsulating resin body 30 expands, the protective portion 35 prevents the bonding wire 90 from being pressed by the expanded encapsulating resin body 30, causing stress to the bonding wire 90. The protective portion 35 is provided around the bonded portion of the bonding wire 90 with the pad 44, and is interposed between the encapsulating resin body 30 and the bonding wire 90 around the bonded portion. In the case of a non-conductive protective portion 35, it may be provided individually for each bonding wire 90, or may be provided integrally for multiple bonding wires 90.

[0065] As an example, the protective portion 35 of this embodiment is a protective portion 351 having a linear expansion coefficient smaller than that of the sealing resin body 30. The protective portion 351 has a linear expansion coefficient smaller than that of the sealing resin body 30, for example, by adjusting the filler in the epoxy resin. Alternatively, a resin material different from that of the sealing resin body 30 and having a smaller linear expansion coefficient may be used.

[0066] The protective portion 351 is applied (filled) around the bonding portion of the bonding wire 90 with the pad 44 by a method such as potting. Then, after the protective portion 351 is provided, the sealing resin body 30 is molded. The protective portion 351 is a primary molded portion, and the sealing resin body 30 is a secondary molded portion. The other configurations are the same as those described in the first embodiment. In other words, the arrangement of the pads 44 is the same as in the first embodiment.

[0067] <Summary of the second embodiment> According to the semiconductor device 20 of this embodiment, the linear expansion coefficient of the protective portion 351 is smaller than the linear expansion coefficient of the sealing resin body 30. This reduces the amount of resin expansion around the bonded portion of the bonding wire 90 with the pad 44. For example, near the bonded portion, the upward force caused by the expansion of the resin located below the bonding wire 90 is reduced. The effects of the arrangement of the pad 44 and the protective portion 351 effectively reduce the stress acting on the bonding wire 90.

[0068] <Modification> The protective portion 35 is not limited to the above example. For example, the rigidity of the protective portion 35 may be lower than that of the sealing resin body 30. In other words, the protective portion 35 may be softer than the sealing resin body 30.

[0069] 10 is made of gel, which is softer than the sealing resin body 30. Therefore, the stress acting on the bonding wires 90 can be reduced.

[0070] The protective portion 353 shown in Fig. 11 is made of polyamideimide (PAI). This protective portion 353 is softer than the sealing resin body 30. Therefore, it is possible to reduce the stress acting on the bonding wire 90. Note that Fig. 11 is an enlarged view of the region XI indicated by the dashed dotted line in Fig. 10. For convenience, the sealing resin body 30 is omitted from Fig. 11.

[0071] 11, the protective portion 353 overlaps the protective film 47 disposed on one surface 41a of the semiconductor substrate 41. The protective portion 353 overlaps a peripheral portion of the protective film 47 around an opening 471 that defines the pad 44. When the protective film 47 is made of polyimide, the overlapping polyimide-based film can firmly adhere the protective portion 353 and the protective film 47. The protective portion 353 is less likely to peel off from the protective film 47 than the sealing resin body 30.

[0072] The protective portion 354 shown in FIG. 12 is made of solder. The protective portion 354 can be formed by applying solder to the pads 44 exposed from the openings 471. The protective portion 354 is softer than the sealing resin body 30. Therefore, the stress acting on the bonding wires 90 can be reduced. FIG. 12 corresponds to FIG. 11. When the protective portion 354 is conductive, it can be provided individually for each bonding wire 90.

[0073] The protective portion 355 shown in FIG. 13 is a hollow portion. The protective portion 355 controls the flow of resin by controlling the gate position, temperature, injection pressure, etc. of the molding die, and sets conditions that prevent the resin from flowing around the junction of the bonding wire 90 with the pad 44. This makes it possible to intentionally form a hollow portion. By providing the protective portion 355, the encapsulating resin body 30, which expands and contracts, is not present around the junction of the bonding wire 90 with the pad 44. This makes it possible to reduce the stress acting on the bonding wire 90.

[0074] Although the example in which the protective portion 35 is combined with the arrangement of the pads 44 described in the previous embodiment has been shown, the present invention is not limited to this. It is also possible to combine the protective portion 35 with a configuration in which the pads 44 are arranged in the high temperature region 461.

[0075] (Third embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used.

[0076] Fig. 14 is a cross-sectional view showing the periphery of the bonded portion of the bonding wire 90 with the pad 44 in the semiconductor device 20 of this embodiment. Fig. 14 corresponds to Fig. 11. As shown in Fig. 14, the bonding wire 90 has a bonded portion 91, a tip portion 92, and a connecting portion 93.

[0077] The joint portion 91 is located between the tip portion 92 and the connecting portion 93 in the extension direction of the bonding wire 90. The joint portion 91 is the portion bonded to the pad 44. The joint portion 91 is sometimes referred to as a bond portion. The joint portion 91 is crushed by the load from the tool during ultrasonic bonding. The joint portion 91 has a substantially trapezoidal shape in the YZ cross section. Of the upper surface 90a and the lower surface 90b of the bonding wire 90, the portion of the joint portion 91 is substantially parallel to the surface of the pad 44. The portion of the upper surface 90a of the joint portion 91 is substantially flat. The lower surface 90b of the joint portion 91 is in contact with the pad 44.

[0078] The tip portion 92 is connected to the bonding portion 91 at the tip side of the bonding wire 90. The tip portion 92 is the portion that is not bonded to the pad 44. The tip portion 92 is sometimes referred to as a feed portion. The tip portion 92 extends diagonally upward from the boundary with the bonding portion 91. The portion of the lower surface 90b that is the tip portion 92 is not in contact with the pad 44. The end of the tip portion 92 opposite the bonding portion 91 is a cut end 92a.

[0079] The connecting portion 93 is connected to the bonding portion 91 on the opposite side to the tip portion 92. The connecting portion 93 is also a portion that is not bonded to the pad 44. The connecting portion 93 is a portion between the bonding portion 91 with the pad 44 and the bonding portion with the signal terminal 83, and connects the bonding portions together. The connecting portion 93 is a portion that connects the bonding portion 91, which is the first bond portion, to the bonding portion with the signal terminal 83, which is the second bond portion. The portion of the lower surface 90b that is the connecting portion 93 is not in contact with the pad 44.

[0080] The bonding wire 90 further has a notch 94. The notch 94 opens to an upper surface 90a of the bonding wire 90 and has a predetermined depth from the upper surface 90a. The notch 94 is provided closer to the tip than the bonding portion 91. The notch 94 may be provided in the range from one of the ends of the bonding portion 91, i.e., the boundary between the bonding portion 91 and the tip portion 92, to the cut end 92a of the tip portion 92.

[0081] The position of the notch 94 is preferably closer to the lower end 91a of the bonding portion 91. The lower end 91a is the end of the bonding interface between the bonding portion 91 and the pad 44, closer to the tip 92. The lower end 91a is the end of the lower surface 90b, closer to the tip 92, of the bonding portion 91. In this embodiment, the notch 94 is provided at the boundary between the bonding portion 91 and the tip 92. The notch 94 extends toward the lower end 91a. The length of the notch 94 in the width direction of the bonding wire 90 is not particularly limited. The notch 94 may be provided in a portion of the width direction, or may be provided from one end to the other. The other configurations are the same as those described in the first embodiment. In other words, the arrangement of the pads 44 is the same as that in the first embodiment.

[0082] <Summary of the third embodiment> According to the semiconductor device 20 of this embodiment, a notch 94 is provided in the bonding wire 90 closer to the tip than the bond portion 91. In other words, a mechanically weak portion is intentionally provided. Therefore, when stress acts on the bonding wire 90 and a crack propagates from the lower end 91a, which is the boundary with the sealing resin body 30, the crack extends toward the notch 94. The crack propagates toward the tip than the bond portion 91. Therefore, it is possible to prevent the crack from propagating in the extension direction at the bond interface between the pad 44 and the bonding wire 90. In other words, it is possible to ensure electrical connection between the pad 44 and the bonding wire 90.

[0083] As described above, the arrangement of the pads 44 is the same as in the previous embodiment. This reduces the stress acting on the bonding wires 90. Even if cracks occur due to the stress, the direction of crack propagation can be controlled.

[0084] In this embodiment, a notch 94 is provided at the boundary between the bonding portion 91 and the tip portion 92. Therefore, the distance between the notch 94 and the lower end 91a is short, and cracks tend to propagate toward the notch 94 as shown by the dashed arrow in Fig. 14. This makes it possible to more reliably prevent cracks from propagating in the extension direction of the bonding interface between the pad 44 and the bonding wire 90.

[0085] Although the cutout 94 is combined with the arrangement of the pad 44 described in the previous embodiment, the cutout 94 is not limited to this. It can also be combined with a configuration in which the pad 44 is arranged in the high temperature region 461.

[0086] (Fourth embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used.

[0087] 15 is a cross-sectional view showing the periphery of the bonded portion of the bonding wire 90 with the pad 44 in the semiconductor device 20 of this embodiment. Fig. 15 corresponds to Fig. 11. The semiconductor device 20 is provided with an adhesion inhibiting film 95 that covers the surface of the bonding wire 90 as shown in Fig. 15. The adhesion inhibiting film 95 inhibits adhesion between the bonding wire 90 and the sealing resin body 30.

[0088] The adhesion inhibitor film 95 is formed by applying an organic solvent to which the sealing resin body 30 does not adhere well after bonding the bonding wire 90 to the pad 44 and before molding the sealing resin body 30. One example of an organic solvent is glycerin. Glycerin has a relatively high viscosity and is easily applied to wires. The adhesion inhibitor film 95 is formed on at least the portion of the surface (outer surface) of the bonding wire 90 that is covered by the sealing resin body 30.

[0089] Although not shown in the drawings, the sealing resin body 30 does not adhere to the bonding wires 90 covered with the adhesion inhibitor film 95. In the semiconductor device 20, there is a gap between the sealing resin body 30 and the bonding wires 90 covered with the adhesion inhibitor film 95. The other configurations are the same as those described in the first embodiment. In other words, the arrangement of the pads 44 is the same as in the first embodiment.

[0090] <Summary of the Fourth Embodiment> According to the semiconductor device 20 of this embodiment, an adhesion inhibiting film 95 is provided on the surface of the bonding wire 90. This creates a gap between the encapsulating resin body 30 and the bonding wire 90 covered with the adhesion inhibiting film 95. This makes it possible to suppress stress from being generated in the bonding wire 90 due to expansion and contraction of the encapsulating resin body 30. The effects of the arrangement of the pads 44 and the effect of the adhesion inhibiting film 95 make it possible to effectively reduce the stress acting on the bonding wire 90.

[0091] Although the adhesion inhibiting film 95 is combined with the arrangement of the pads 44 described in the previous embodiment, the present invention is not limited to this. It can also be combined with a configuration in which the pads 44 are arranged in the high temperature region 461.

[0092] (Fifth embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used.

[0093] Fig. 16 is a cross-sectional view showing the semiconductor device 20 of this embodiment. Fig. 16 corresponds to Fig. 3. Fig. 17 is a plan view showing the connection structure between the semiconductor element 40 and the conductive spacer 70 in the semiconductor device 20.

[0094] 16 and 17, the conductive spacer 70 has a generally rectangular shape in plan view. The conductive spacer 70 has end faces 70a and 70b and side faces 70c, 70d, 70e, and 70f as surfaces forming its outer contour. The end face 70a is the face opposite the end face 70b in the Z direction. In the Z direction, the end face 70a faces the emitter electrode 42, and the end face 70b faces the wiring member 50. The end face 70a is connected to the emitter electrode 42, and the end face 70b is connected to the wiring member 50.

[0095] The side surfaces 70c, 70d, 70e, and 70f are surfaces continuing to the end surfaces 70a and 70b. The side surface 70c is the surface opposite the side surface 70d in the Y direction. In the Y direction, the side surface 70c is located on the pad 44 side, i.e., on the end surface 41c side of the semiconductor substrate 41. The side surface 70c is located on the side surface 30c side of the sealing resin body 30, and the side surface 70d is located on the side surface 30d side. The side surface 70e is the surface opposite the side surface 70f in the X direction. In the X direction, the side surface 70e is located on the side surface 30e side of the sealing resin body 30, and the side surface 70f is located on the side surface 30f side.

[0096] The conductive spacer 70 has a roughened portion 71 and a non-roughened portion 72. The roughened portion 71 is provided on the side surfaces 70c, 70d, 70e, and 70f except for the surfaces facing the pads 44 in a plan view. The non-roughened portion 72 is provided on the side surfaces 70c, 70d, 70e, and 70f facing the pads 44 in a plan view. In this embodiment, the roughened portion 71 is provided on the side surfaces 70c, 70e, and 70f, and the non-roughened portion 72 is provided on the side surface 70d.

[0097] Roughening treatments that can be used to form the roughened portion 71 include roughening plating, sandblasting, chemical treatment, and laser roughening. In this embodiment, laser roughening is used. The conductive spacer 70 is formed by providing a Ni-containing plating film on the surface of a copper-containing base material. By irradiating the plating film on the conductive spacer surface with laser light, a nickel oxide film with a continuously uneven surface is formed. Of the side surfaces 70c, 70d, 70e, and 70f, the portions on which the uneven oxide film is formed by laser light irradiation are the roughened portions 71, and the portions on which the uneven oxide film is not formed are the non-roughened portions 72.

[0098] <Summary of the Fifth Embodiment> According to the semiconductor device 20 of this embodiment, the conductive spacer 70 has roughened portions 71 on its side surfaces 70c, 70e, and 70f, and a non-roughened portion 72 on its side surface 70d. That is, the non-roughened portions 72 are provided on the surfaces of the side surfaces 70c, 70d, 70e, and 70f facing the pads 44 in a plan view, and the roughened portions 71 are provided on the remaining surfaces. The encapsulating resin body 30 adheres closely to the side surfaces 70c, 70e, and 70f, but does not adhere easily to the side surface 70d. Therefore, a gap exists between the encapsulating resin body 30 and the side surface 70d of the conductive spacer 70. This suppresses stress on the bonding wire 90 due to expansion and contraction of the encapsulating resin body 30. The arrangement of the pads 44 and the localized non-roughened portions 72 effectively reduce stress acting on the bonding wire 90.

[0099] FIG. 18 shows the relationship between the presence or absence of the non-roughened portion 72 and the equivalent plastic strain amplitude. The vertical axis represents the average value of the equivalent plastic strain amplitude of the aluminum wire. As shown in FIG. 18, when the non-roughened portion 72 is provided, the equivalent plastic strain amplitude can be reduced by 40% compared to a configuration in which the roughened portion 71 is provided over the entire side surface, i.e., a configuration in which there is no non-roughened portion. This result also clearly shows that the stress acting on the bonding wire 90 can be reduced by providing the non-roughened portion 72.

[0100] Although the roughened portion 71 and the non-roughened portion 72 are combined with the arrangement of the pads 44 described in the preceding embodiment, the present invention is not limited to this. A combination with a configuration in which the pads 44 are arranged in the high-temperature region 461 is also possible.

[0101] (Other embodiments) The disclosure in this specification and drawings, etc. is not limited to the exemplified embodiments. The disclosure encompasses the exemplified embodiments and modifications thereto by those skilled in the art. For example, the disclosure is not limited to the combinations of parts and / or elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure encompasses the omission of parts and / or elements from the embodiments. The disclosure encompasses the substitution or combination of parts and / or elements between one embodiment and another embodiment. The disclosed technical scope is not limited to the description of the embodiments. Some disclosed technical scopes are defined by the claims, and should be interpreted as including all modifications within the meaning and scope equivalent to the claims.

[0102] The disclosure in the specification, drawings, etc. is not limited by the claims. The disclosure in the specification, drawings, etc. encompasses the technical ideas described in the claims, and extends to more diverse and broader technical ideas than the technical ideas described in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification, drawings, etc. without being bound by the claims.

[0103] When an element or layer is referred to as being "on," "coupled," "connected," or "coupled," it may be directly on, coupled, connected, or coupled to another element or layer, and intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly coupled," "directly connected," or "directly coupled" to another element or layer, there are no intervening elements or layers present. Other language used to describe relationships between elements should be construed in a similar manner (e.g., "between" vs. "directly between," "adjacent" vs. "directly adjacent," etc.). As used in this specification, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0104] Spatially relative terms such as "inside," "outside," "back," "below," "low," "top," "top," and the like are used herein to facilitate the description of one element or feature's relationship to other elements or features, as illustrated. Spatially relative terms may be intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures were turned over, elements described as "below" or "directly below" other elements or features would then be oriented "above" the other elements or features. Thus, the term "bottom" can encompass both an orientation of top and bottom. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in this specification would be interpreted accordingly.

[0105] The vehicle drive system 1 is not limited to the above-described configuration. For example, although an example has been shown in which one motor generator 3 is provided, this is not limiting. Multiple motor generators may be provided. Although an example has been shown in which the power conversion device 4 is provided with an inverter 6 as a power conversion unit, this is not limiting. For example, a configuration with multiple inverters may be provided. A configuration with at least one inverter and a converter may be provided. Or only a converter may be provided.

[0106] Although an RC-IGBT has been shown as an example of a vertical element configured in the active region 45 of the semiconductor substrate 41, the present invention is not limited to this. An IGBT may be configured on the semiconductor substrate 41, and the diode 12 may be externally attached.

[0107] The switching element is not limited to the IGBT 11. For example, a MOSFET may be used. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0108] Although an example has been shown in which the back surfaces 50b, 60b of the wiring members 50, 60 are exposed from the sealing resin body 30, this is not limiting. At least one of the back surfaces 50b, 60b may be covered by the sealing resin body 30. At least one of the back surfaces 50b, 60b may be covered by an insulating member (not shown) that is separate from the sealing resin body 30. Although an example has been shown in which the semiconductor device 20 includes the sealing resin body 30, this is not limiting. A configuration without the sealing resin body 30 may also be used.

[0109] Although the example has been shown in which the semiconductor device 20 includes only one semiconductor element 40 that configures one arm, the present invention is not limited to this. The semiconductor device 20 may also include multiple semiconductor elements 40 that configure one arm. In other words, multiple semiconductor elements 40 may be connected in parallel to configure one arm. In this case, the conductive spacer 70 is provided individually for each semiconductor element 40. The semiconductor device 20 may also include multiple semiconductor elements 40 that configure upper and lower arm circuits 9 for one phase. The semiconductor device 20 may also include multiple semiconductor elements 40 that configure upper and lower arm circuits 9 for multiple phases. [Explanation of symbols]

[0110] 1... drive system, 2... DC power supply, 3... motor generator, 3a... winding, 4... power conversion device, 5... smoothing capacitor, 6... inverter, 7... P line, 8... N line, 9... upper and lower arm circuits, 9H... upper arm, 9L... lower arm, 10... output line, 11... IGBT, 12... diode, 20... semiconductor device, 30... sealing resin body, 30a... one surface, 30b... back surface, 30c, 30d, 30e, 30f... side, 35, 351, 352, 353, 354, 355... protective portion, 40... semiconductor element, 41... semiconductor substrate, 41a... one surface, 41b... back surface, 41c... edge, 42... emitter electrode, 43... collector electrode, 44... pad, 45... active area, 45c... center 45d...diode region, 45i...IGBT region, 46...peripheral region, 461...high temperature region, 462...low temperature region, 47...protective film, 471...opening, 50...wiring member, 50a...opposing surface, 50b...rear surface, 60...wiring member, 60a...opposing surface, 60b...rear surface, 70...conductive spacer, 70a, 70b...end surface, 70c, 70d, 70e, 70f...side surface, 71...roughened portion, 72...non-roughened portion, 80...external connection terminal, 81, 82...main terminal, 83...signal terminal, 90...bonding wire, 90a...upper surface, 90b...lower surface, 91...joint portion, 91a...lower end, 92...tip portion, 92a...cut end, 93...connection portion, 94...notch, 95...adhesion inhibitor film, 100, 101, 102...joint material

Claims

1. a semiconductor element (40) having a semiconductor substrate (41) having an active region (45) which is an element formation region and a peripheral region (46) surrounding the active region, a main electrode (42) arranged on one surface of the semiconductor substrate so as to overlap with the active region and electrically connected to the active region, and a pad (44) which is an electrode for signals arranged on the one surface so as to overlap with the peripheral region; a bonding wire (90) connected to the pad; an encapsulating resin body (30) that encapsulates the semiconductor element and the bonding wires; Equipped with The peripheral region has a high temperature region (461) and a low temperature region (462) whose temperature is lower than that of the high temperature region when the element is driven, the pad is disposed on the low temperature region; The semiconductor device includes pads arranged biased toward the end (41c) of the semiconductor element between the active region and the end (41c) of the semiconductor element, excluding the four corners of the semiconductor element which has a rectangular shape in plan view.

2. a semiconductor element (40) having a semiconductor substrate (41) having an active region (45) which is an element formation region and a peripheral region (46) surrounding the active region, a main electrode (42) arranged on one surface of the semiconductor substrate so as to overlap with the active region and electrically connected to the active region, and a pad (44) which is an electrode for signals arranged on the one surface so as to overlap with the peripheral region; a bonding wire (90) connected to the pad; an encapsulating resin body (30) that encapsulates the semiconductor element and the bonding wires; Equipped with The peripheral region has a high temperature region (461) and a low temperature region (462) whose temperature is lower than that of the high temperature region when the element is driven, the pad is disposed on the low temperature region; The active region has IGBT regions (45i) and diode regions (45d) alternately arranged with the IGBT regions in a predetermined direction, The pad is disposed between the active area and an end (41c) of the semiconductor element in the predetermined direction; The semiconductor device, wherein the diode region is disposed at an end of the active region on the pad side.

3. 3. The semiconductor device according to claim 1, further comprising a protective portion (35) provided around the bonding portion of the bonding wire with the pad, interposed between the sealing resin body and the bonding wire, and protecting the bonding wire from expansion and contraction of the sealing resin body.

4. The semiconductor device according to claim 3 , wherein the protective portion has a linear expansion coefficient smaller than that of the sealing resin body.

5. The semiconductor device according to claim 3 , wherein the protection portion has a lower rigidity than the sealing resin body.

6. The semiconductor device according to claim 3 , wherein the protective portion is a cavity.

7. 3. The semiconductor device according to claim 1, wherein the bonding wire has a notch (94) that is provided on a tip side of the bonding wire with respect to the bonding portion with the pad and that opens to an upper surface.

8. 3. The semiconductor device according to claim 1, further comprising an adhesion inhibiting film (95) that covers the surface of said bonding wire and inhibits adhesion between said bonding wire and said sealing resin body.

9. The semiconductor element has a first main electrode, which is the main electrode, arranged on the one surface, and a second main electrode (43) arranged on a back surface, which is the surface opposite to the one surface, a first wiring member (50) electrically connected to the first main electrode; a second wiring member (60) electrically connected to the second main electrode; a conductive spacer (70) interposed between the first main electrode and the first wiring member, one of the end faces connected to the first main electrode and the other of the end faces connected to the first wiring member, 3. The semiconductor device according to claim 1, wherein the conductive spacer has a roughened portion (71) provided on a side surface connected to the end face, excluding a surface facing the pad, and a non-roughened portion (72) provided on a surface facing the pad.

10. a semiconductor element (40) having a semiconductor substrate (41) having an active region (45) which is an element formation region and a peripheral region (46) surrounding the active region, a main electrode (42) arranged on one surface of the semiconductor substrate so as to overlap with the active region and electrically connected to the active region, and a pad (44) which is an electrode for signals arranged on the one surface so as to overlap with the peripheral region; a bonding wire (90) connected to the pad; an encapsulating resin body (30) that encapsulates the semiconductor element and the bonding wires; Equipped with The peripheral region has a high temperature region (461) and a low temperature region (462) whose temperature is lower than that of the high temperature region when the element is driven, the pad is disposed on the low temperature region; a protective portion (35) provided around a bonded portion of the bonding wire with the pad, interposed between the sealing resin body and the bonding wire, and protecting the bonding wire from expansion and contraction of the sealing resin body; The semiconductor device, wherein the protection portion has a lower rigidity than the sealing resin body.

11. a semiconductor element (40) having a semiconductor substrate (41) having an active region (45) which is an element formation region and a peripheral region (46) surrounding the active region, a main electrode (42) arranged on one surface of the semiconductor substrate so as to overlap with the active region and electrically connected to the active region, and a pad (44) which is an electrode for signals arranged on the one surface so as to overlap with the peripheral region; a bonding wire (90) connected to the pad; an encapsulating resin body (30) that encapsulates the semiconductor element and the bonding wires; Equipped with The peripheral region has a high temperature region (461) and a low temperature region (462) whose temperature is lower than that of the high temperature region when the element is driven, the pad is disposed on the low temperature region; a protective portion (35) provided around a bonded portion of the bonding wire with the pad, interposed between the sealing resin body and the bonding wire, and protecting the bonding wire from expansion and contraction of the sealing resin body; The semiconductor device, wherein the protective portion is a cavity.

12. a semiconductor element (40) having a semiconductor substrate (41) having an active region (45) which is an element formation region and a peripheral region (46) surrounding the active region, a main electrode (42) arranged on one surface of the semiconductor substrate so as to overlap with the active region and electrically connected to the active region, and a pad (44) which is an electrode for signals arranged on the one surface so as to overlap with the peripheral region; a bonding wire (90) connected to the pad; an encapsulating resin body (30) that encapsulates the semiconductor element and the bonding wires; Equipped with The peripheral region has a high temperature region (461) and a low temperature region (462) whose temperature is lower than that of the high temperature region when the element is driven, the pad is disposed on the low temperature region; The semiconductor element has a first main electrode, which is the main electrode, arranged on the one surface, and a second main electrode (43) arranged on a back surface, which is the surface opposite to the one surface, a first wiring member (50) electrically connected to the first main electrode; a second wiring member (60) electrically connected to the second main electrode; a conductive spacer (70) interposed between the first main electrode and the first wiring member, one of the end faces connected to the first main electrode and the other of the end faces connected to the first wiring member, The semiconductor device, wherein the conductive spacer has a roughened portion (71) provided on a surface of the side surface continuing to the end face, excluding the surface facing the pad, and a non-roughened portion (72) provided on the surface facing the pad.

Images