Semiconductor device

Abstract

To provide a semiconductor device provided with a memory cell having a ferroelectric capacitor with a new configuration.SOLUTION: The semiconductor device includes a first transistor, a second transistor, a first capacitor, a second capacitor, and a wiring. The first transistor is electrically connected to the first capacitor. The second transistor is electrically connected to the second capacitor. The wiring is positioned below the first transistor and the second transistor and is electrically connected to the first transistor or the second transistor. The first capacitor and the second capacitor each include a ferroelectric layer. The first capacitance and the second capacitance are arranged on the same plane. The first capacitor and the second capacitor may overlap with each other in a region. Each of the first transistor and the second transistor preferably includes an oxide semiconductor in a channel. The ferroelectric layer preferably contains one or more of hafnium, zirconium, and elements belonging to Groups 13 to 15.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device, a method for driving the semiconductor device, or an electronic device including the semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, imaging devices, display devices, light-emitting devices, power storage devices, memory devices, display systems, electronic devices, lighting devices, input devices, input / output devices, and driving methods thereof or manufacturing methods thereof. Note that a semiconductor device generally refers to a device that utilizes semiconductor characteristics, and a memory device is a semiconductor device. [Background technology]

[0003] In recent years, the development of semiconductor devices has progressed, and LSIs, CPUs, memories, etc. are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) processed from semiconductor wafers and formed into chips, and on which electrodes serving as connection terminals are formed.

[0004] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components in a variety of electronic devices.

[0005] Furthermore, a technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials and oxide semiconductors are known as semiconductor thin films applicable to transistors.

[0006] Furthermore, as shown in Non-Patent Document 1, research and development of memory cells using ferroelectrics is being actively conducted. Furthermore, for the next generation of ferroelectric memories, research on hafnium oxide is also being actively conducted, including research on ferroelectric HfO2-based materials (Non-Patent Document 2), research on the ferroelectricity of hafnium oxide thin films (Non-Patent Document 3), and research on the ferroelectricity of HfO2 thin films (Non-Patent Document 4). [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] TSBoescke,et al,“Ferroelectricity in hafnium oxide thin films”,APL99,2011 [Non-patent document 2] Zhen Fan,et al,“Ferroelectric HfO2-based materials for next-generation ferroelectric memories”,JOURNAL OF ADVANCED DIELECTRICS,Vol.6,No.2,2016 [Non-patent document 3] Jun Okuno,et al,“SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2”,VLSI 2020 [Non-patent document 4] Akira Toriumi, "Ferroelectricity of HfO2 Thin Films," The Japan Society of Applied Physics, Vol. 88, No. 9, 2019 Summary of the Invention [Problem to be solved by the invention]

[0008] In memory cells using ferroelectrics, the electrical properties of the ferroelectric are important, so it is necessary to form a layer (ferroelectric layer) that has a ferroelectric material with excellent electrical properties.

[0009] Alternatively, in a memory cell using a ferroelectric, the data read operation is performed by utilizing the presence or absence of polarization reversal of the ferroelectric. In this case, the data stored in the memory cell is reversed during the data read operation. In other words, a memory cell using a ferroelectric is a destructive read. A memory cell using a ferroelectric, which is a destructive read, requires a data rewrite operation every time data is read. The data rewrite operation requires the application of a high voltage to the ferroelectric, which may result in increased power consumption, etc.

[0010] An object of one embodiment of the present invention is to provide a novel semiconductor device and a driving method thereof.An object of one embodiment of the present invention is to provide a semiconductor device from which data can be read without destroying the data and a driving method thereof.An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption and a driving method thereof.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a driving method thereof.

[0011] The problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention solves at least one of the problems listed above and / or other problems. [Means for solving the problem]

[0012] One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, a first capacitor, a second capacitor, and wiring, wherein the first transistor is electrically connected to the first capacitor, the second transistor is electrically connected to the second capacitor, the wiring is located below the first transistor and the second transistor and is electrically connected to the first transistor or the second transistor, the first capacitor and the second capacitor each have a ferroelectric layer, and the first capacitor and the second capacitor are arranged on the same plane.

[0013] One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, a first capacitor, a second capacitor, and wiring, wherein the first transistor is electrically connected to the first capacitor, the second transistor is electrically connected to the second capacitor, the wiring is located below the first transistor and the second transistor and is electrically connected to the first transistor or the second transistor, the first capacitor and the second capacitor each have a ferroelectric layer, and the first capacitor and the second capacitor have an overlapping region.

[0014] In one embodiment of the present invention, the first transistor and the second transistor preferably include an oxide semiconductor in a channel.

[0015] In one embodiment of the present invention, the ferroelectric layer preferably contains one or more elements selected from hafnium, zirconium, and elements of Groups 13 to 15 of the semiconductor device.

[0016] Another embodiment of the present invention is an electronic device including the semiconductor device and a CPU.

[0017] Other aspects of the present invention will be described in the following embodiments and in the drawings. [Effects of the Invention]

[0018] One embodiment of the present invention can provide a novel semiconductor device and a driving method thereof.One embodiment of the present invention can provide a semiconductor device from which data can be read without destroying the data and a driving method thereof.Another embodiment of the present invention can provide a semiconductor device with low power consumption and a driving method thereof.Another embodiment of the present invention can provide a highly reliable semiconductor device and a driving method thereof.

[0019] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and / or other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0020] [Figure 1] 1A and 1B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 2] 2A and 2B are diagrams showing an example of the configuration of a semiconductor device. [Figure 3] 3A and 3B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 4] 4A, 4B, and 4C are diagrams showing configuration examples of a semiconductor device. [Figure 5] 5A and 5B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 6] FIG. 6 is a diagram illustrating a configuration example of a semiconductor device. [Figure 7] 7A and 7B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 8] FIG. 8 is a timing chart of the semiconductor device. [Figure 9]FIG. 9 is a timing chart of the semiconductor device. [Figure 10] FIG. 10 is a diagram illustrating a configuration example of a semiconductor device. [Figure 11] FIG. 11 is a timing chart of the semiconductor device. [Figure 12] FIG. 12 is a timing chart of the semiconductor device. [Figure 13] FIG. 13 is a diagram illustrating a configuration example of a semiconductor device. [Figure 14] 14A and 14B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 15] 15A and 15B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 16] FIG. 16A is a diagram illustrating the classification of crystal structures, FIG. 16B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 16C is a diagram illustrating the electron microbeam diffraction pattern of crystalline IGZO. [Figure 17] Fig. 17A is a perspective view showing an example of a semiconductor wafer, Fig. 17B is a perspective view showing an example of a chip, Fig. 17C and Fig. 17D are perspective views showing an example of an electronic component. [Figure 18] 18A to 18J are diagrams illustrating an example of an electronic device. [Figure 19] 19A to 19E are diagrams illustrating an example of an electronic device. [Figure 20] 20A to 20C are diagrams illustrating an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0022] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0023] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated explanations thereof may be omitted.

[0024] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply as "OSs"). For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, when the term "OS FET" or "OS transistor" is used, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0025] (Embodiment 1) In this embodiment, a configuration example of a semiconductor device will be described. By using a configuration according to one embodiment of the present invention, a semiconductor device having a ferroelectric layer with excellent electrical characteristics can be obtained. Furthermore, the design flexibility of the semiconductor device can be increased. Furthermore, by stacking elements included in a memory cell, the integration degree of the semiconductor device can be increased.

[0026] 1A is an example of a top view of a semiconductor device of one embodiment of the present invention, and FIG. 1B is an example of a cross-sectional view taken along dashed line X1-X2 in FIG. 1A. The semiconductor device of one embodiment of the present invention illustrated in FIGS. 1A and 1B includes, for example, a transistor 500A, a transistor 500B, a capacitor 600A, a capacitor 600B, and a wiring 401.

[0027] The transistor 500A is electrically connected to one electrode of the capacitor 600A. The transistor 500B is electrically connected to one electrode of the capacitor 600B. The wiring 401 is located below the transistors 500A and 500B and is electrically connected to the transistors 500A and 500B. The capacitors 600A and 600B each have a ferroelectric layer. The wiring 410 shown in FIG. 1A is connected to the other electrode of the capacitor 600A and the other electrode of the capacitor 600B. The wiring 410 is also called a plate line. 503A and 503B shown in FIGS. 1A and 1B are wirings that function as backgate electrodes of the transistors 500A and 500B. 560A and 560B shown in FIGS. 1A and 1B are wirings that function as gate electrodes of the transistors 500A and 500B.

[0028] A transistor A and a capacitor 600A, and a transistor B and a capacitor 600B each constitute one memory cell. Each memory cell can increase memory density by sharing the wiring 401 that functions as a bit line.

[0029] The wiring 401 can be provided above a transistor having silicon in a channel formation region (a Si transistor), for example. The wiring 401 is electrically connected to a transistor in a lower layer. The wiring 401 is also electrically connected to the transistors 500A and 500B through a conductor 402. The wiring 401 shares an electrode for electrically connecting the wiring 401 to the transistors 500A and 500B with the conductor 402, thereby increasing memory density.

[0030] A signal for driving a memory cell having a transistor 500A and a capacitor 600A (or a transistor 500B and a capacitor 600B) is applied to the wiring 401 functioning as a bit line. When a bit line driver circuit or the like is configured using Si transistors, the wiring connecting the bit line and the bit line driver circuit can be shortened by providing it in a layer below the wiring 401.

[0031] Furthermore, by providing the wiring 401 below the transistors 500A and 500B, it is possible to increase the area in which the capacitors 600A and 600B are provided. By increasing the area in which the capacitors 600A and 600B are provided, it is possible to provide the ferroelectric layer on a surface with improved flatness.

[0032] The transistors 500A and 500B are transistors (OS transistors) having a metal oxide in a channel formation region. The transistors 500A and 500B have characteristics of low off-state current and little change in field-effect mobility even at high temperatures. By using the transistors 500A and 500B in a semiconductor device, a semiconductor device whose operating capability is less likely to deteriorate even at high temperatures can be realized.

[0033] The transistors 500A and 500B can be provided above the wiring 401. The capacitors 600A and 600B are provided above the transistors 500A and 500B. By using OS transistors as the transistors 500A and 500B, the transistors can be stacked over an insulating layer.

[0034] The oxide 530 functioning as a semiconductor in the transistors 500A and 500B preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0035] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 530. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 530.

[0036] By using an OS transistor as the transistors 500A and 500B, a semiconductor device with less variation in transistor characteristics, high reliability, and excellent electrical characteristics can be provided.

[0037] The capacitors 600A and 600B each include a ferroelectric layer 630 between the electrodes 610A and 620A (or the electrodes 610B and 620B). The capacitors 600A and 600B each include the ferroelectric layer 630 and are also called ferroelectric capacitors.

[0038] In one embodiment of the present invention, the capacitors 600A and 600B can be arranged on a layer different from the wiring 401 functioning as a bit line, and the capacitors 600A and 600B can be arranged on the same plane. This configuration allows the area of ​​the surface on which the ferroelectric layer is formed to be increased. Therefore, a layer (ferroelectric layer) having a ferroelectric substance with excellent electrical properties can be formed. For example, a memory cell can be formed having the capacitors 600A and 600B with enhanced polarization (Pr) of the ferroelectric layer.

[0039] 1A and 1B show a configuration in which the capacitors 600A and 600B are provided on the same insulating layer, but other configurations are also possible. For example, by arranging the ferroelectric layer 630A of the capacitor 600A and the ferroelectric layer 630B of the capacitor 600B on different layers as shown in FIG. 2A, the area in which the capacitors 600A and 600B are provided can be further increased. Also, while FIG. 2A shows a configuration in which the ferroelectric layers are arranged on two different layers, this is not a limitation of one embodiment of the present invention. As shown in FIG. 2B, the ferroelectric layers can be arranged on three to ten different layers to provide a capacitor (capacitor 600N in FIG. 2B) and further increase the area of ​​the capacitor.

[0040] As shown in FIGS. 2A and 2B, in one embodiment of the present invention, the capacitors 600A and 600B can be arranged in a layer different from the wiring 401 functioning as a bit line, and the capacitors 600A and 600B can be arranged in an overlapping region. This configuration can further increase the area of ​​the surface on which the ferroelectric layer is formed. Therefore, a layer (ferroelectric layer) having a ferroelectric substance with excellent electrical properties can be formed. For example, a memory cell can be formed having the capacitors 600A and 600B with enhanced polarization (Pr) of the ferroelectric layer. This memory cell may also be referred to as a universal memory.

[0041] In one embodiment of the present invention, the transistor is an OS transistor, and when combined with a capacitor having a ferroelectric layer, elements such as the transistor and the capacitor constituting the memory cell can be stacked. By stacking the transistor and the capacitor, the area of ​​the surface on which the ferroelectric layer is provided can be increased, as described with reference to FIGS. 1A, 1B, 2A, and 2B. Therefore, a layer (ferroelectric layer) having a ferroelectric substance with excellent electrical properties can be formed.

[0042] Examples of materials that can be used for the ferroelectric layer 630 and have ferroelectric properties include hafnium oxide, zirconium oxide, and cerium oxide. Examples of materials that can have ferroelectric properties include materials in which an element J1 (here, element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added to hafnium oxide, and materials in which element J2 (here, element J2 is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added to zirconium oxide. For example, hafnium zirconium oxide (HfZrO) is obtained by adding zirconium to hafnium oxide. X :X is a real number greater than 0) is preferred.

[0043] Furthermore, as a material that can have ferroelectricity, piezoelectric ceramics having a perovskite structure, such as lead titanate, barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may be used. Furthermore, as a material that can have ferroelectricity, for example, a plurality of materials selected from the materials listed above, or a laminate structure consisting of a plurality of materials selected from the materials listed above, may be used. Incidentally, hafnium oxide, zirconium oxide, HfZrO X and materials in which the element J1 is added to hafnium oxide, the crystal structure (characteristics) of which may change not only depending on the film formation conditions but also on various processes, etc., and therefore in this specification etc., not only materials that exhibit ferroelectricity are called ferroelectrics, but also materials that can have ferroelectricity or materials that can be made to have ferroelectricity are called ferroelectrics.

[0044] Furthermore, materials that can have ferroelectricity include aluminum scandium nitride (Al 1-a Sc a N b(where a is a real number greater than 0 and less than 0.5, and b is 1 or a value close to 1.) Examples of materials that can exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum (Al), gallium (Ga), indium (In), etc., and element M2 is one or more elements selected from boron (B), scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), neodymium (Nd), europium (Eu), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without element M2. Ferroelectric materials include the above-mentioned metal nitrides to which element M3 is added. Element M3 is one or more elements selected from magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), cadmium (Cd), etc. The ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be appropriately set. Because the above-mentioned metal nitrides contain at least a Group 13 element and nitrogen, a Group 15 element, these metal nitrides are sometimes referred to as Group 13-Group 15 ferroelectrics or Group 13 nitride ferroelectrics.

[0045] Among these, HfZrO is used as a material for the ferroelectric layer. X is preferable because it can retain ferroelectricity even when processed into a thin film of a few nm. Here, the film thickness of the ferroelectric layer can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically 2 nm to 9 nm). By using a ferroelectric layer that can be thinned, it can be made into a semiconductor device combined with a miniaturized transistor.

[0046] In addition, HfZrO is a material that can have ferroelectric properties. X When using a ferroelectric material, it is preferable to form the film using atomic layer deposition (ALD), particularly thermal ALD. Furthermore, when using thermal ALD to form a film of a material that may have ferroelectricity, it is preferable to use a material that does not contain hydrocarbons (also referred to as Hydro Carbon, HC) as a precursor. If the material that may have ferroelectricity contains either or both of hydrogen and carbon, this may inhibit the crystallization of the material that may have ferroelectricity. Therefore, as described above, it is preferable to use a precursor that does not contain hydrocarbons to reduce the concentration of either or both of hydrogen and carbon in the material that may have ferroelectricity. For example, a chlorine-based material can be used as a precursor that does not contain hydrocarbons. Furthermore, as a material that may have ferroelectricity, a material containing hafnium oxide and zirconium oxide (HfZrO x ) is used, HfCl4 and / or ZrCl4 may be used as the precursor.

[0047] When a film is formed using a material that can have ferroelectricity, impurities in the film, in this case at least one of hydrogen, hydrocarbon, and carbon, are thoroughly removed, thereby forming a film having high-purity intrinsic ferroelectricity. The film having high-purity intrinsic ferroelectricity and the high-purity intrinsic oxide semiconductor shown in the embodiment described later have very high compatibility in manufacturing processes. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0048] In addition, HfZrO is a material that can have ferroelectric properties. X When using hafnium oxide and zirconium oxide, it is preferable to use a thermal ALD method to alternately form films of hafnium oxide and zirconium oxide in a 1:1 ratio.

[0049] Furthermore, when a film of a material that may have ferroelectricity is formed using a thermal ALD method, the oxidizing agent may be H2O or O3. However, the oxidizing agent for the thermal ALD method is not limited to these. For example, the oxidizing agent for the thermal ALD method may include one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0050] Furthermore, the crystal structure of the material capable of exhibiting ferroelectricity is not particularly limited. For example, the crystal structure of the material capable of exhibiting ferroelectricity may be one or more selected from the group consisting of cubic, tetragonal, orthorhombic, and monoclinic. In particular, the material capable of exhibiting ferroelectricity preferably has an orthorhombic crystal structure, since ferroelectricity is exhibited. Alternatively, the material capable of exhibiting ferroelectricity may have a composite structure having an amorphous structure and a crystalline structure.

[0051] Furthermore, it is preferable that the film (e.g., a conductor) underlying the ferroelectric layer has a good flatness on the top surface. For example, the roughness of the top surface of the underlying conductor may be set to 2 nm or less, preferably 1 nm or less, more preferably 0.8 nm or less, even more preferably 0.5 nm or less, and even more preferably 0.4 nm or less, in terms of arithmetic mean roughness (Ra) or root mean square roughness (RMS). In this way, by improving the flatness of the top surface of the conductor, the crystallinity of the ferroelectric layer can be improved, thereby enhancing the ferroelectricity.

[0052] Furthermore, for example, when the ferroelectric layer contains layered crystals, a layer for enhancing crystallinity may be formed on the upper and / or lower side of the ferroelectric layer. For example, it is preferable to use a layer containing at least one of the elements contained in the ferroelectric layer as the layer for enhancing crystallinity. It is also preferable that the composition of the layer for enhancing crystallinity differs from the composition of the ferroelectric layer. For example, when HfZrOx is used for the ferroelectric layer, it is preferable to use a metal oxide such as hafnium oxide or zirconium oxide, or hafnium or zirconium as the layer for enhancing crystallinity.

[0053] The composition of the layer that enhances crystallinity does not need to contain elements contained in the ferroelectric layer. In this case, elements that can be used include silicon, yttrium, aluminum, and scandium. By providing a layer that enhances crystallinity, the crystallinity of the ferroelectric layer can be improved, thereby enhancing the ferroelectricity. Since improving the crystallinity of the ferroelectric layer enhances the ferroelectricity, the layer that enhances crystallinity can be rephrased as a layer that increases the remanent polarization of the ferroelectric layer.

[0054] By applying the structure described in this embodiment to a semiconductor device using a transistor having an oxide semiconductor and a capacitor having a ferroelectric layer, miniaturization or high integration can be achieved.

[0055] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0056] (Embodiment 2) In this embodiment mode, a method for driving a semiconductor device having the memory cell described in Embodiment Mode 1 will be described.

[0057] One aspect of the present invention relates to a semiconductor device having memory cells. A semiconductor device having memory cells can be called a memory device. The memory cells have a function of retaining data. Specifically, the memory cells have a capacitor (capacitance). The capacitor has a configuration having a ferroelectric layer between a first electrode and a second electrode. A capacitor having a ferroelectric layer is sometimes called a ferroelectric capacitor (ferroelectric capacitance).

[0058] When a voltage (electric or electric field) is applied between the electrodes of a ferroelectric capacitor, the direction and amount of polarization of the ferroelectric layer changes depending on the direction and amount of the applied voltage. A memory cell equipped with a ferroelectric capacitor stores (writes) signals (data) by utilizing the change in the polarization state of the ferroelectric layer. In a ferroelectric capacitor, polarization remains in the ferroelectric layer (residual polarization) even when the voltage between the electrodes is reduced to zero. To rewrite the polarization, a voltage (polarization reversal voltage) is applied to reverse the polarization (polarization reversal).

[0059] When reading data from a memory cell, if a voltage exceeding the polarization inversion voltage is applied to a ferroelectric capacitor, the polarization state of the ferroelectric layer (the polarization direction of the remanent polarization) changes, and an operation to restore the polarization state is required. In other words, when a voltage exceeding the polarization inversion voltage is applied to a ferroelectric capacitor to read data from the ferroelectric capacitor, data refresh is required. In other words, when a voltage exceeding the polarization inversion voltage is applied to a ferroelectric capacitor to read data, the operation of reading data from a memory cell is a destructive read.

[0060] One aspect of the present invention provides a method for driving a semiconductor device that can read data from a memory cell having a ferroelectric capacitor without performing destructive reading.

[0061] Specifically, during a read operation of a memory cell having a ferroelectric capacitor, the read operation is performed by gradually increasing the voltage on the opposite electrode of the ferroelectric capacitor so as not to destroy the polarization of the ferroelectric capacitor. The data read operation from the memory cell is performed by applying a voltage to the ferroelectric capacitor that does not cause polarization reversal of the ferroelectric layer. The next data read operation from the memory cell is performed using a driving method in which a voltage that does not cause polarization reversal of the ferroelectric layer is applied to the ferroelectric capacitor that is higher than the voltage applied in the previous read operation.

[0062] In one aspect of the present invention, a voltage not exceeding the polarization inversion voltage is applied to the ferroelectric capacitor during a data read operation, thereby maintaining the polarization direction of the remanent polarization of the ferroelectric layer before and after data read. Therefore, the semiconductor device of one aspect of the present invention can retain data for a long period of time. This reduces the frequency of refresh (rewriting data to a memory cell), thereby reducing the power consumption of the semiconductor device of one aspect of the present invention. Furthermore, a ferroelectric capacitor having a ferroelectric layer between electrodes can retain data for a long period of time without employing a structure for increasing capacitance, such as a trench structure. This allows for a semiconductor device with an easy-to-manufacture structure.

[0063] 3A is a circuit diagram of a memory cell MC having a ferroelectric capacitor. The memory cell MC is also called a cell. The memory cell MC has a transistor M1 and a ferroelectric capacitor C1.

[0064] The ferroelectric capacitor C1 is illustrated schematically as a capacitor having a ferroelectric layer FE between electrodes UE and LE. For example, a read operation of the memory cell MC involves setting the wiring BL (also called a bit line) connected to the transistor M1 at a predetermined potential and electrically floating, and then controlling the wiring WL (also called a word line) to turn on the transistor M1, thereby changing the voltage of the wiring PL (also called a plate line) on the electrode UE side. This changes the potential of the wiring BL due to capacitive coupling of the ferroelectric capacitor. This change in the potential of the wiring BL depends on the polarization state of the ferroelectric layer in the ferroelectric capacitor, so a potential corresponding to the written data can be read out to the wiring BL.

[0065] FIG. 3B is a graph showing the magnitude of polarization (amount of polarization) depending on the electric field applied to the ferroelectric layer FE. In FIG. 3B, the change in polarization with respect to the electric field of the ferroelectric layer FE is shown as a straight line for ease of understanding, but the actual measured data is expressed as a curve. In FIG. 3B, the horizontal axis represents the electric field E applied to the ferroelectric layer, and the vertical axis represents the polarization P of the ferroelectric layer. The difference between the positive and negative polarizations when the electric field is 0 is expressed as 2P R is illustrated as

[0066] As the electric field applied to the ferroelectric layer FE increases, the polarization of the ferroelectric layer increases. H After applying an electric field E to the ferroelectric layer, if the electric field applied to the ferroelectric layer is reduced, the positive charges will be biased to one electrode side of the capacitance and the negative charges will be biased to the other electrode side of the capacitance, so that when the electric field becomes 0, the positive polarization will remain. If the electric field applied to the ferroelectric layer FE is reduced, the polarization of the ferroelectric layer will become smaller. If the electric field E L After applying an electric field E to the ferroelectric layer, if the electric field applied to the ferroelectric layer is increased, the positive charges will be biased to the other electrode side of the capacitance C1 and the negative charges will be biased to one electrode side of the capacitance, so that when the electric field becomes 0, a negative polarization will remain. H and electric field E L The voltage for applying this polarity inversion voltage can be called a polarization inversion voltage. By applying the polarization inversion voltage to the ferroelectric capacitor C1, data can be written to the memory cell MC.

[0067] When reading data from a memory cell MC, if a voltage exceeding the polarization inversion voltage is applied to the capacitor C1, the polarization state (polarization direction of the remanent polarization) of the ferroelectric layer FE changes, and an operation to restore the polarization state is required. In other words, when reading data from a memory cell MC by applying a voltage exceeding the polarization inversion voltage to the capacitor C1, the data needs to be refreshed.

[0068] In one aspect of the present invention, when data is read from a memory cell MC, a voltage not exceeding the polarization inversion voltage is applied to the ferroelectric capacitor C1, and the ferroelectric capacitor C1 is operated so as to maintain the polarization direction of the remanent polarization of the ferroelectric layer FE. Specifically, when data is read from the memory cell MC, the electric field is increased stepwise so as to maintain the polarization direction of the remanent polarization of the ferroelectric layer FE. Specifically, the electric field E shown in FIG. H Electric fields E1 to E4 not exceeding 100 V are sequentially applied for each read operation. The voltages for applying the electric fields E1 to E4 to the ferroelectric layer FE can be said to be voltages that do not cause polarization inversion. In one embodiment of the present invention, data can be read from the memory cell MC without performing so-called destructive read.

[0069] When the polarization direction of the remanent polarization of the ferroelectric layer FE is reversed by repeated read operations from the ferroelectric capacitor, it is preferable to perform a data refresh operation, which is an operation of writing data again.

[0070] In the read operation of one aspect of the present invention described above, it is preferable that the magnitude of polarization (amount of polarization) varies when different electric fields are applied in the graph shown in Figure 3B, which shows the magnitude of polarization (amount of polarization) depending on the electric field to the ferroelectric layer FE. In addition, in the read operation of one aspect of the present invention, it is preferable that the magnitude of polarization varies when different electric fields are applied in the graph shown in Figure 3B, which shows the magnitude of polarization (amount of polarization) depending on the electric field to the ferroelectric layer FE .... For example, as shown in Figure 4A, in the shape of the graph showing the magnitude of polarization (amount of polarization) depending on the electric field to the ferroelectric layer FE, the degree of change T of polarization with respect to the change in electric field is VS It is preferable that the gradient (slope) is positive. In addition, it is preferable that the change in polarization with respect to the change in electric field is not large. By adopting this configuration, when the polarization direction of the remanent polarization of the ferroelectric layer FE is operated to be partially reversed rather than completely reversed, it is possible to reduce the degree of change in the remanent polarization for each read operation.

[0071] In actuality, the electric field and polarization in the ferroelectric layer change in a curved manner as shown in FIG. VS The gradient can be expressed as the gradient of a tangent line. This is also valid for the graph shape shown in Figure 4C.

[0072] On the other hand, in the read operation of one embodiment of the present invention described above, it is not preferable if the degree of change (slope) of polarization with respect to the change in electric field is positive, and the change in polarization with respect to the change in electric field is large and steep, as shown in the graph shape of Figure 5A. In this case, the degree of change in polarization with respect to the change in electric field becomes large, making it difficult to operate to partially reverse the polarization direction of the remanent polarization of the ferroelectric layer FE. As shown in Figure 5B, the same can be said for the shape of the graph as in Figure 5A.

[0073] <Configuration example of semiconductor device> 6 is a block diagram showing a configuration example of a semiconductor device 10 which is a semiconductor device according to one embodiment of the present invention. The semiconductor device 10 can be, for example, a memory device.

[0074] The semiconductor device 10 is provided with a memory cell array MCA in which memory cells MC are arranged in a matrix of m rows and n columns (m and n are integers equal to or greater than 1). The semiconductor device 10 also has a word line drive circuit WD, a plate line drive circuit PD, a potential generation circuit SD, and a bit line drive circuit BD.

[0075] The word line driving circuit WD is electrically connected to the memory cells MC via wiring WL, and is also electrically connected to the memory cells MC via wiring RWL. The plate line driving circuit PD is electrically connected to the memory cells MC via wiring PL. The bit line driving circuit BD is electrically connected to the memory cells MC via wiring BL.

[0076] Here, memory cells MC in the same row can be electrically connected to the word line driving circuit WD via the same wiring WL and to the plate line driving circuit PD via the same wiring PL, and memory cells MC in the same column can be electrically connected to the bit line driving circuit BD via the same wiring BL.

[0077] In this specification, for example, the memory cell MC in the first row and first column is referred to as memory cell MC[1,1], and the memory cell MC in the mth row and nth column is referred to as memory cell MC[m,n]. Furthermore, for example, the wiring WL and wiring PL electrically connected to the memory cell MC in the first row are referred to as wiring WL[1] and wiring PL[1], respectively, and the wiring WL and wiring PL electrically connected to the memory cell MC in the mth row are referred to as wiring WL[m] and wiring PL[m], respectively. Furthermore, for example, the wiring BL electrically connected to the memory cell MC in the first column is referred to as wiring BL[1], and the wiring BL electrically connected to the memory cell MC in the nth column is referred to as wiring BL[n]. Similar notations may be used for other elements.

[0078] The word line driver circuit WD has a function of controlling the potential of the wiring WL, specifically, the word line driver circuit WD has a function of selecting a memory cell MC to which data is written by controlling the potential of the wiring WL.

[0079] The plate line driving circuit PD has a function of controlling the potential of the wiring PL.

[0080] The bit line driver circuit BD has a function of generating data to be written to the memory cells MC and supplying the data to the memory cells MC in a predetermined column, and also has a function of reading and outputting the data written to the memory cells MC.

[0081] The bit line driver circuit BD will be described in detail. The bit line driver circuit BD includes sense amplifier circuits SA[1] to SA[n]. The sense amplifier circuits SA are electrically connected to the wirings BL, REF, EL, and PRE. The sense amplifier circuits SA[1] to SA[n] are also electrically connected to the wirings OUT[1] to OUT[n].

[0082] The sense amplifier circuit SA has the function of amplifying the difference between the potential of the wiring BL and the potential of the wiring REF. For example, when the potential of the wiring BL is higher than the potential of the wiring REF, the sense amplifier circuit SA can output a high potential. On the other hand, when the potential of the wiring BL is lower than the potential of the wiring REF, the sense amplifier circuit SA can output a low potential. This allows the bit line driver circuit BD to write binary data, specifically binary digital data, to the memory cell MC and to read the binary data written to the memory cell MC. For example, when the potential of the wiring BL is higher than the potential of the wiring REF, it can be assumed that a "0" is written to the memory cell MC or a "0" is read from the memory cell MC. On the other hand, when the potential of the wiring BL is lower than the potential of the wiring REF, it can be assumed that a "1" is written to the memory cell MC or a "1" is read from the memory cell MC.

[0083] An enable signal that controls whether the sense amplifier circuit SA is activated can be supplied to the wiring EL. The enable signal can be, for example, a binary digital signal. For example, when the potential of the wiring EL is high, the sense amplifier circuit SA can be activated, and the difference between the potential of the wiring BL and the potential of the wiring REF is amplified. On the other hand, when the potential of the wiring EL is low, the sense amplifier circuit SA can be deactivated, and the above amplification is not performed.

[0084] A precharge signal that controls whether the potentials of the wiring BL and the wiring REF are precharged can be supplied to the wiring PRE. The precharge signal can be, for example, a binary digital signal. For example, when the potential of the wiring PRE is high, the wiring BL can be precharged to a high potential. Furthermore, the potential of the wiring REF can be set to a potential between the potential of the wiring BL when data with a value of "0" is read from the memory cell MC and the potential of the wiring BL when data with a value of "1" is read from the memory cell MC.

[0085] Note that the potential supplied to the wirings EL[1] to EL[n] may be common to each other. In this case, the wirings EL[1] to EL[n] may be electrically connected to each other. Furthermore, the potential supplied to the wirings PRE[1] to PRE[n] may be common to each other. In this case, the wirings PRE[1] to PRE[n] may be electrically connected to each other.

[0086] Data output from the sense amplifier circuit SA is output from the wiring OUT. Data from the sense amplifier circuit SA[1] can be output from the wiring OUT[1]. Data from the sense amplifier circuit SA[n] can be output from the wiring OUT[n].

[0087] <Memory cell configuration example 1> 7A shows a circuit diagram of a memory cell applicable to the memory cell MC1 of FIG. 6. The memory cell MC1 has a transistor M1 and a ferroelectric capacitor C1. In the memory cell MC1, each element of the transistor M1 and the ferroelectric capacitor C1 is connected to a wiring BL, a wiring PL, and / or a wiring WL as shown in FIG. 7A. In FIG. 7A, the wiring electrically connecting the transistor M1 and the ferroelectric capacitor C1 is shown as a node N1.

[0088] FIG. 7B is a diagram illustrating the electrical connection between each component of the memory cell MC1, such as the transistor M1 and ferroelectric capacitor C1, and the sense amplifier circuit SA. The sense amplifier circuit SA is connected to the wiring BL, the wiring REF, and the wiring OUT as shown in FIG. 7B. The sense amplifier circuit SA amplifies the difference between the potential of the wiring BL and the potential of the wiring REF. The wiring BL and the wiring REF are provided with loads CBL and CREF, which are parasitic capacitances, respectively. The loads CBL and CREF are provided as equivalent loads. The configuration shown in FIG. 7B is the same as that described in FIG. 7A.

[0089] Data is written to the memory cell MC1 by applying a voltage to the ferroelectric capacitor C1. By controlling the signals supplied to the wiring WL and the wiring BL so as to apply an H level potential to the node N1 and an L level potential to the wiring PL, the ferroelectric substance in the ferroelectric capacitor C1 is polarized to the state "1." By applying an L level potential to the node N1 and an H level potential to the wiring PL, the ferroelectric substance in the ferroelectric capacitor C1 is polarized to the state "0." The voltages applied to the node N1 and the wiring PL can be set to 0V for the L level and 2.5V or 3.3V for the H level.

[0090] 8 and 9 are timing charts showing a case where a read operation according to one embodiment of the present invention is applied to the memory cell MC1 shown in Fig. 7A and Fig. 7B. Fig. 8 is a timing chart showing a data read operation when the ferroelectric substance in the ferroelectric capacitor C1 is polarized to the state "0", and Fig. 9 is a timing chart showing a data read operation when the ferroelectric substance in the ferroelectric capacitor C1 is polarized to the state "1".

[0091] 8 and 9, at time T0, the line WL is set to H level, turning on the transistor M1. At time T1, the line PL is set to voltage Va, and the voltage of the line BL is boosted by capacitive coupling via the ferroelectric capacitor C1. At this time, the precharge voltage of the line REF is set to voltage Va' corresponding to voltage Va. Here, in FIG. 8, the ferroelectric capacitor C1 is polarized to state "0," so the voltage of the line BL after boosting is smaller than the voltage of the line REF. On the other hand, in FIG. 9, the ferroelectric capacitor C1 is polarized to state "1," so the voltage of the line BL after boosting is larger than the voltage of the line REF.

[0092] At time T2, the line EL is set to H level. An enable signal for the sense amplifier circuit SA is given to the line EL, and setting this enable signal to H level activates the sense amplifier circuit SA. By setting the line EL to H level, the sense amplifier circuit SA amplifies the potential difference between the line REF and the line BL. A signal corresponding to this potential difference is output to the line OUT.

[0093] Compared to destructive reads of data from the ferroelectric capacitor C1, the voltage required to read data in one embodiment of the present invention does not exceed the polarization inversion voltage. Therefore, the polarization direction of the ferroelectric layer is maintained before and after the read operation. This eliminates the need to apply a high voltage to write back data.

[0094] At time T3, the lines PL and EL are set to the L level, the sense amplifier circuit SA is deactivated, and at time T4, the line WL is set to the L level, turning off the transistor M1 and completing the read operation.

[0095] Subsequently, a second read operation is performed after time T5.

[0096] At time T5, the line WL is set to H level, turning on the transistor M1. At time T6, the line PL is set to voltage Vb (>voltage Va), and the voltage of the line BL is boosted by capacitive coupling via the ferroelectric capacitor C1. At this time, the precharge voltage of the line REF is set to voltage Vb' corresponding to voltage Vb. Here, in FIG. 9, the ferroelectric capacitor C1 is polarized to state "0," so the voltage of the line BL after boosting is smaller than the voltage of the line REF. On the other hand, in FIG. 9, the ferroelectric capacitor C1 is polarized to state "1," so the voltage of the line BL after boosting is larger than the voltage of the line REF.

[0097] At time T7, the line EL is set to H level, activating the sense amplifier circuit SA. When the line EL becomes H level, the sense amplifier circuit SA amplifies the potential difference between the lines REF and BL. A signal corresponding to this potential difference is output to the line OUT.

[0098] At time T8, the lines PL and EL are set to L level, and the sense amplifier circuit SA is deactivated. At time T9, the line WL is set to L level, turning off the transistor M1 and completing the read operation.

[0099] Subsequently, a third read operation is performed after time T10.

[0100] At time T10, the line WL is set to H level, turning on the transistor M1. At time T11, the line PL is set to voltage Vc (> voltage Vb), and the voltage of the line BL is boosted by capacitive coupling via the ferroelectric capacitor C1. At this time, the precharge voltage of the line REF is set to voltage Vc' corresponding to voltage Vc. Here, in FIG. 9, the ferroelectric capacitor C1 is polarized to state "0," so the voltage of the line BL after boosting is smaller than the voltage of the line REF. On the other hand, in FIG. 9, the ferroelectric capacitor C1 is polarized to state "1," so the voltage of the line BL after boosting is larger than the voltage of the line REF.

[0101] At time T12, the line EL is set to H level, activating the sense amplifier circuit SA. When the line EL becomes H level, the sense amplifier circuit SA amplifies the potential difference between the lines REF and BL. A signal corresponding to this potential difference is output to the line OUT.

[0102] At time T13, the lines PL and EL are set to L level, and the sense amplifier circuit SA is deactivated. At time T14, the line WL is set to L level, turning off the transistor M1 and completing the read operation.

[0103] As described above, by gradually increasing the drive voltage of the wiring PL and the precharge voltage of the wiring REF each time a read operation is performed, multiple read operations can be realized without performing a write-back operation to the ferroelectric capacitor C1.

[0104] It is preferable to perform a data refresh operation when the voltage of the wiring PL is increased by a certain voltage or more (for example, 3.3 V). In this case, a high voltage is applied to the ferroelectric capacitor C1 to perform the data refresh operation.

[0105] It is effective to use a transistor having an oxide semiconductor in a channel formation region (OS transistor) as the transistor M1 in FIGS. 7A and 7B. Because OS transistors have excellent breakdown voltage, using them in combination with a ferroelectric capacitor with a high drive voltage allows for miniaturization of each element in a memory cell. Furthermore, OS transistors have an extremely small off-state current, making it possible to maintain the voltage at node N1 for a long period of time. Although there is concern that the voltage at node N1 may drop due to leakage current through the ferroelectric capacitor C1, this leakage current can be suppressed if the electric field applied to the ferroelectric capacitor C1 is small.

[0106] 3, it is also possible to read data using the charge held at node N1. Specifically, the charge held at node N1 can be distributed to wiring BL, and the change in potential can be amplified by a sense amplifier to read data. Furthermore, if the charge held at node N1 disappears, wiring PL can be set to 3.0 V or higher to replenish the charge at node N1 via ferroelectric capacitor C1.

[0107] <Memory cell configuration example 2> FIG. 10 shows an example of a configuration different from that shown in FIG. 7B. FIG. 10 illustrates the electrical connections between a memory cell MC1, a memory cell MC1B storing inverted data of data written to the memory cell MC1, and a sense amplifier circuit SA. FIG. 10 illustrates the transistor M1B, ferroelectric capacitor C1B, and node N1B of the memory cell MC1, which is paired with the memory cell MC1. Hereinafter, the method of reading data from a memory cell storing paired data is referred to as the twin-cell type. FIG. 8 also illustrates the wiring BLB to which the memory cell MC1B is connected. The sense amplifier circuit SA amplifies the difference between the potentials of the wirings BL and BLB. The wirings BL and BLB are provided with parasitic capacitance loads CBL and CBLB, respectively. The loads CBL and CBLB are provided as equivalent loads.

[0108] 11 and 12 are timing charts showing the case where a read operation according to one aspect of the present invention is applied to the memory cells MC1 and MC1B shown in Fig. 10. Fig. 11 is a timing chart showing the case where the ferroelectric in the ferroelectric capacitor C1 is polarized to the state "0", and Fig. 12 is a timing chart showing the case where the ferroelectric in the ferroelectric capacitor C1 is polarized to the state "1". Note that the ferroelectric in the ferroelectric capacitor C1B is polarized to a state different from that of the ferroelectric capacitor C1.

[0109] The circuit configuration in FIG. 10 is of a twin cell type, and therefore does not have the line REF shown in FIG. 7B. Therefore, there is no need to change the precharge voltage of line REF to match the voltage of line PL. During a data read operation, the precharge of lines BL and BLB may be set to, for example, an L-level potential. Because the circuit configuration in FIG. 10 is of a twin cell type, inverted data is written to memory cells MC1 and MC1B.

[0110] 11 and 12, at time T0, the line WL is set to H level, turning on the transistor M1 and the transistor M1B. At time T1, the line PL is set to voltage Va, and the voltages of the lines BL and BLB are boosted by capacitive coupling via the ferroelectric capacitors C1 and C1B. In FIG. 11, the ferroelectric capacitor C1 is polarized to state "0" (the ferroelectric capacitor C1B is polarized to state "1"), so the voltage of the line BL after boosting is smaller than the voltage of the line BLB. On the other hand, in FIG. 12, the ferroelectric capacitor C1 is polarized to state "1" (the ferroelectric capacitor C1B is polarized to state "0"), so the voltage of the line BL after boosting is larger than the voltage of the line BLB.

[0111] At time T2, the line EL is set to H level. The line EL is an enable signal for the sense amplifier circuit SA, and when it goes to H level, the sense amplifier circuit SA is activated. When the line EL goes to H level, the potential difference between the lines BLB and BL is amplified. A signal corresponding to this potential difference is output to the line OUT.

[0112] Compared to destructive reads of data from the ferroelectric capacitor C1, the voltage required to read data in one embodiment of the present invention does not exceed the polarization inversion voltage. Therefore, the polarization direction of the ferroelectric layer is maintained before and after the read operation. This eliminates the need to apply a high voltage to write back data.

[0113] At time T3, the lines PL and EL go to L level, deactivating the sense amplifier circuit SA. At time T4, the line WL goes to L level, turning off the transistors M1 and M1B and completing the read operation.

[0114] Subsequently, a second read operation is performed after time T5.

[0115] At time T5, the line WL is set to the H level, turning on the transistors M1 and M1B. At time T6, the line PL is set to voltage Vb (>voltage Va), and the voltages of the lines BL and BLB are boosted by capacitive coupling via the ferroelectric capacitors C1 and C1B. In FIG. 11, the ferroelectric capacitor C1 is polarized to state "0" (the ferroelectric capacitor C1B is polarized to state "1"), so the voltage of the line BL after boosting is smaller than the voltage of the line BLB. On the other hand, in FIG. 12, the ferroelectric capacitor C1 is polarized to state "1" (the ferroelectric capacitor C1B is polarized to state "0"), so the voltage of the line BL after boosting is larger than the voltage of the line BLB.

[0116] At time T7, the line EL is set to H level, activating the sense amplifier circuit SA. When the line EL becomes H level, the sense amplifier circuit SA amplifies the potential difference between the lines BLB and BL. A signal corresponding to this potential difference is output to the line OUT.

[0117] At time T8, the lines PL and EL are set to L level, deactivating the sense amplifier circuit SA. At time T9, the line WL is set to L level, turning off the transistors M1 and M1B, and the read operation ends.

[0118] Subsequently, a third read operation is performed after time T10.

[0119] At time T11, the line WL is set to the H level, turning on the transistor M1 and the transistor M1B. At time T12, the line PL is set to voltage Vc (>voltage Vb), and the voltages of the lines BL and BLB are boosted by capacitive coupling via the ferroelectric capacitors C1 and C1B. In FIG. 11, the ferroelectric capacitor C1 is polarized to state "0" (the ferroelectric capacitor C1B is polarized to state "1"), so the voltage of the line BL after boosting is smaller than the voltage of the line BLB. On the other hand, in FIG. 12, the ferroelectric capacitor C1 is polarized to state "1" (the ferroelectric capacitor C1B is polarized to state "0"), so the voltage of the line BL after boosting is larger than the voltage of the line BLB.

[0120] At time T12, the line EL is set to H level, activating the sense amplifier circuit SA. When the line EL becomes H level, the sense amplifier circuit SA amplifies the potential difference between the lines BLB and BL. A signal corresponding to this potential difference is output to the line OUT.

[0121] At time T13, the lines PL and EL are set to L level, deactivating the sense amplifier circuit SA. At time T14, the line WL is set to L level, turning off the transistors M1 and M1B, and the read operation ends.

[0122] As described above, by increasing the drive voltage of the wiring PL stepwise every time a read operation is performed, multiple read operations can be realized without performing a write-back operation to the ferroelectric capacitor C1.

[0123] It is preferable to perform a data refresh operation when the voltage of the wiring PL is increased by a certain voltage or more (for example, 3.3 V). In this case, a high voltage is applied to the ferroelectric capacitor C1 and the ferroelectric capacitor C1B to perform the data refresh operation.

[0124] Note that similarly to the transistor M1 in FIGS. 7A and 7B, it is effective to use a transistor including an oxide semiconductor in a channel formation region (OS transistor) for the transistors M1 and M1B in FIG.

[0125] <Memory cell configuration example 3> FIG. 13 shows a circuit diagram of a memory cell different from the memory cell MC1 described above. The memory cell MC2 in FIG. 13 has transistors M1, M2, M3, and a ferroelectric capacitor C1. In the memory cell MC2, the transistors M1 to M3 and the ferroelectric capacitor C1 are connected to the wiring WBL (also referred to as a write bit line), wiring RBL (also referred to as a read bit line), wiring PL, wiring SL (also referred to as a source line), wiring WWL (also referred to as a write word line), and / or wiring RWL (also referred to as a read word line) as shown in FIG. 13. In FIG. 13, the wiring electrically connecting the transistor M1, the transistor M2, and the ferroelectric capacitor C1 is shown as a node SN.

[0126] 13, by changing the voltage of the wiring PL, the potential of the node SN changes due to the capacitive coupling of the ferroelectric capacitor C1. At this time, a difference in the potential of the node SN occurs depending on the difference in polarization of the ferroelectric layer of the ferroelectric capacitor C1, and this difference can be amplified and read out by the transistor M2.

[0127] By configuring the wiring functioning as a bit line to be separated into wiring WBL and wiring RBL, a high voltage (e.g., 3.3 V) can be applied to wiring WBL, and data can be read out from wiring RBL at a low voltage (e.g., 1.2 V or less).

[0128] 13, when the read operation is performed multiple times, it is effective to increase the voltage of the wiring PL in stages. When the voltage of the wiring PL is increased in stages, the voltage of the node SN increases each time the read operation is performed. Therefore, the read circuit connected to the wiring RBL has a function of adjusting the range of the read voltage depending on the number of reads.

[0129] By driving in this way, during normal read operations, only the wiring RBL that can operate at a low voltage is activated, and the wiring WBL that requires a high voltage is deactivated, thereby reducing power consumption.

[0130] 13, it is effective to use transistors having an oxide semiconductor in the channel formation region (OS transistors). OS transistors have an extremely small off-state current, which allows them to maintain the voltage of node SN for a long time. Although there is a concern that the voltage of node SN may drop due to leakage current through ferroelectric capacitor C1, this leakage current can be suppressed when the electric field applied to ferroelectric capacitor C1 is small.

[0131] 3, it is also possible to read data by utilizing the charge stored in node SN. Specifically, data can be read by utilizing the fact that the amount of current flowing through transistor M2 is determined according to the potential corresponding to the charge stored in node SN. Furthermore, if the charge stored in node SN disappears, the line PL can be set to 3.0 V or higher to replenish the charge in node SN via ferroelectric capacitor C1.

[0132] <Modification of memory cell> 14A is a circuit diagram showing a modification of the memory cell MC1 described above. The memory cell MC1_A shown in FIG. 14A has a back gate voltage V BG14A shows a configuration having a back gate electrode to which a voltage is applied. The configuration of FIG. 14A can increase the amount of current flowing through each transistor.

[0133] 14B is a circuit diagram showing a modification of the memory cell MC2 described above. The memory cell MC2_A shown in FIG. 14B applies a back gate voltage V BG 14B shows a configuration having a back gate electrode to which a voltage is applied. By using the configuration of FIG. 14B, the amount of current flowing through each transistor can be increased. Note that the back gate voltage applied to the back gate of each transistor may be the same voltage or different voltages.

[0134] Fig. 15A is a circuit diagram showing a modified example of the memory cell MC2 described above. The memory cell MC2_B shown in Fig. 15A shows a configuration in which the wiring WBL and the wiring RBL in the memory cell MC2 of Fig. 13 are replaced by a common wiring BL. By using the configuration of Fig. 15A, the number of wirings connected to the memory cell can be reduced.

[0135] FIG. 15B is a circuit diagram showing a modification of the memory cell MC2 described above. The memory cell MC2_C shown in FIG. 15B is a circuit diagram in which the transistor M3 in the memory cell MC2 of FIG. 13 is omitted and the wiring RWL is connected to the back gate of the transistor M2. The selection signal given to the wiring RWL controls the threshold voltage of the transistor M2, thereby controlling whether or not a current flows between the wiring RWL and the wiring SL. The configuration of FIG. 15B allows the number of transistors in the memory cell to be reduced.

[0136] As described above, in one aspect of the present invention, in the operation of applying an electric field for reading data, the polarization direction of the remanent polarization of the ferroelectric layer FE is not completely reversed, but is instead partially reversed. Since the balance of the polarization direction of the remanent polarization of the ferroelectric layer FE is lost through the read operation, the read operation is performed by gradually increasing the voltage on the opposite electrode side of the ferroelectric capacitor so as not to destroy the polarization of the ferroelectric capacitor. With this configuration, data can be read even if the remanent polarization of the ferroelectric layer FE is reduced by repeated read operations.

[0137] This embodiment mode can be appropriately combined with other embodiment modes shown in this specification and the like.

[0138] (Embodiment 3) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0139] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0140] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 16A. Fig. 16A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0141] As shown in FIG. 16A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). The "Crystalline" classification excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0142] The structure within the bold frame shown in Figure 16A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "Amorphous" and "Crystal."

[0143] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 16B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline" (the vertical axis represents intensity in arbitrary units (au)). The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 16B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 16B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 16B is 500 nm.

[0144] As shown in Figure 16B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 16B, the peak near 2θ = 31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0145] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 16C. Figure 16C shows a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 16C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0146] As shown in FIG. 16C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0147] <<Oxide semiconductor structure>> Note that oxide semiconductors may be classified differently from those shown in FIG. 16A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0148] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0149] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0150] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0151] In an In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0152] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0153] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0154] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. The distortion may also have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0155] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0156] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities or the formation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0157] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0158] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0159] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0160] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0161] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0162] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0163] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0164] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0165] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0166] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0167] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0168] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0169] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0170] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than or equal to 1×10 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm-3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0171] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0172] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0173] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0174] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0175] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17atoms / cm 3 The following applies.

[0176] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0177] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0178] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0179] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0180] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0181] (Fourth embodiment) In this embodiment mode, an example of a semiconductor wafer on which the semiconductor device or the like described in the above embodiment mode is formed and an example of an electronic component in which the semiconductor device is incorporated will be described.

[0182] <Semiconductor wafer> First, an example of a semiconductor wafer on which semiconductor devices and the like are formed will be described with reference to FIG. 17A.

[0183] 17A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that on the upper surface of the wafer 4801, a portion where the circuit portions 4802 are not present is a spacing 4803, which is a region for dicing.

[0184] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801 and allows for miniaturization of the component.

[0185] The next step is the dicing process. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes called dicing lines or cutting lines) indicated by dashed lines. To facilitate the dicing process, spacing 4803 is preferably arranged so that multiple scribe lines SCL1 are parallel to each other, multiple scribe lines SCL2 are parallel to each other, and scribe lines SCL1 and SCL2 are perpendicular to each other.

[0186] By performing a dicing process, chips 4800a as shown in FIG. 17B can be cut out from semiconductor wafer 4800. Chip 4800a has wafer 4801a, circuit portion 4802, and spacing 4803a. It is preferable to make spacing 4803a as small as possible. In this case, it is sufficient that the width of spacing 4803 between adjacent circuit portions 4802 is approximately the same length as the cutting margin of scribe line SCL1 or the cutting margin of scribe line SCL2.

[0187] Note that the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in Figure 17A. For example, the semiconductor wafer may have a rectangular shape. The shape of the element substrate can be changed as appropriate depending on the manufacturing process and the apparatus for manufacturing the element.

[0188] <Electronic components> 17C is a perspective view of an electronic component 4700 and a substrate (mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in FIG. 17C includes a chip 4800a in a mold 4711. A memory device or the like according to one embodiment of the present invention can be used as the chip 4800a.

[0189] 17C omits some parts to show the interior of electronic component 4700. Electronic component 4700 has lands 4712 on the outside of mold 4711. Lands 4712 are electrically connected to electrode pads 4713, and electrode pads 4713 are electrically connected to chip 4800a via wires 4714. Electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined and electrically connected on printed circuit board 4702 to complete mounted board 4704.

[0190] 17D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 4730 has an interposer 4731 provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and multiple semiconductor devices 4710 provided on interposer 4731.

[0191] The semiconductor device 4710 may be, for example, a chip 4800a, the semiconductor device described in the above embodiment, a high bandwidth memory (HBM), etc. The semiconductor device 4735 may be an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a memory device.

[0192] A ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 4732. A silicon interposer, a resin interposer, or the like can be used for the interposer 4731.

[0193] The interposer 4731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect the integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 4731, and the integrated circuits and the package substrate 4732 are electrically connected using the through electrodes. In addition, in a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0194] It is preferable to use a silicon interposer as the interposer 4731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0195] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0196] Furthermore, in SiP or MCM using a silicon interposer, a decrease in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use a silicon interposer in a 2.5D package (2.5-dimensional mounting) in which multiple integrated circuits are arranged horizontally on the interposer.

[0197] A heat sink (heat sink) may be provided overlapping the electronic component 4730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 4731. For example, in the electronic component 4730 shown in this embodiment, it is preferable to align the height of the semiconductor device 4710 and the height of the semiconductor device 4735.

[0198] In order to mount electronic component 4730 on another substrate, electrodes 4733 may be provided on the bottom of package substrate 4732. Fig. 17D shows an example in which electrodes 4733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 4732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 4733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 4732, PGA (Pin Grid Array) mounting can be achieved.

[0199] The electronic component 4730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0200] The structure described in this embodiment mode can be combined as appropriate with structures described in other embodiments.

[0201] (Embodiment 5) In this embodiment, application examples of a semiconductor device according to one embodiment of the present invention will be described.

[0202] The semiconductor device according to one embodiment of the present invention can be applied to, for example, memory devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording / playback devices, navigation systems, game consoles, and the like). It can also be used in image sensors, IoT (Internet of Things) devices, healthcare-related devices, and the like. Note that the term "computer" as used herein refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system.

[0203] 18A to 18J and 19A to 19E illustrate examples of electronic devices including an electronic component 4700 or an electronic component 4730 including the semiconductor device according to one embodiment of the present invention.

[0204] [mobile phone] 18A is a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As input interfaces, a touch panel is provided on the display unit 5511 and buttons are provided on the housing 5510.

[0205] By applying the semiconductor device according to one embodiment of the present invention, the information terminal 5500 can hold temporary files (for example, caches when using a web browser) generated when an application is executed.

[0206] [Wearable devices] 18B illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0207] Like the above-described information terminal 5500, the wearable terminal can hold temporary files generated when an application is executed by applying a semiconductor device according to one embodiment of the present invention.

[0208] [Information terminal] 18C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0209] Like the above-described information terminal 5500, the desktop information terminal 5300 can hold temporary files generated when an application is executed by applying a semiconductor device according to one embodiment of the present invention.

[0210] 18A to 18C are taken as examples of electronic devices, and are illustrated in Fig. 18A to 18C, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0211] [electric appliances] 18D also illustrates an electric refrigerator-freezer 5800 as an example of an electrical appliance. Electric refrigerator-freezer 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, etc. For example, electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0212] The semiconductor device according to one embodiment of the present invention can be applied to an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information about food ingredients stored in the electric refrigerator-freezer 5800, such as expiration dates of the food ingredients, to and from an information terminal or the like via the Internet or the like. The electric refrigerator-freezer 5800 can store a temporary file generated when transmitting the information in the semiconductor device.

[0213] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, audio-visual equipment, etc.

[0214] [Game consoles] 18E shows a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0215] FIG. 18F further illustrates a stationary game console 7500, which is an example of a game console. The stationary game console 7500 includes a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a cable. Although not shown in FIG. 18F, the controller 7522 can include a display unit that displays game images, a touch panel that serves as an input interface other than buttons, a stick, a rotary knob, a sliding knob, or the like. The shape of the controller 7522 is not limited to the shape shown in FIG. 18F, and the shape of the controller 7522 may be changed in various ways depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller shaped like a gun with a trigger as a button can be used. In a music game, for example, a controller shaped like a musical instrument, music equipment, or the like can be used. Furthermore, the stationary game console may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures and / or voice.

[0216] Furthermore, the images of the above-mentioned game machine can be output by a display device such as a television device, a display for a personal computer, a game display, or a head-mounted display.

[0217] A low-power portable game machine 5200 or a low-power stationary game machine 7500 can be realized by applying the semiconductor device described in the above embodiments to the portable game machine 5200 or the stationary game machine 7500. Furthermore, the low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0218] Furthermore, by applying the semiconductor device described in the above embodiments to the portable game machine 5200 or the stationary game machine 7500, temporary files and the like necessary for calculations occurring during game execution can be stored.

[0219] 18E shows a portable game machine as an example of a game machine. Also, FIG. 18F shows a home-use stationary game machine. Note that the electronic device of one embodiment of the present invention is not limited to this. Examples of the electronic device of one embodiment of the present invention include an arcade game machine installed in an entertainment facility (such as an arcade or amusement park) and a pitching machine for batting practice installed in a sports facility.

[0220] [Moving object] The semiconductor device described in the above embodiment modes can be applied to automobiles, which are moving objects, and to the vicinity of a driver's seat of an automobile.

[0221] FIG. 18G illustrates an automobile 5700 as an example of a moving object.

[0222] An instrument panel that provides various information by displaying a speedometer or tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A display device that shows this information may also be provided around the driver's seat.

[0223] In particular, the display device can compensate for the field of view obstructed by pillars, blind spots around the driver's seat, and the like, thereby improving safety by displaying an image from an imaging device (not shown) provided on the automobile 5700. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, blind spots can be compensated for and safety can be improved.

[0224] The semiconductor device described in the above embodiment can temporarily store information. Therefore, the semiconductor device can be used to store necessary temporary information in an automatic driving system for the automobile 5700, a system that provides road guidance, hazard prediction, or the like. The display device may be configured to display temporary information such as road guidance and hazard prediction. Alternatively, the display device may be configured to store video images from a driving recorder installed in the automobile 5700.

[0225] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies may include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, rockets, etc.).

[0226] [camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0227] 18H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation switches 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0228] A low-power digital camera 6240 can be realized by applying the semiconductor device described in the above embodiment modes to the digital camera 6240. Furthermore, low power consumption can reduce heat generation from the circuit, thereby reducing the influence of heat generation on the circuit itself, peripheral circuits, and modules.

[0229] [Video camera] The semiconductor device described in the above embodiment can be applied to a video camera.

[0230] 18I illustrates a video camera 6300, which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. An image on the display unit 6303 may be switched depending on the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0231] When recording video captured by the video camera 6300, it is necessary to encode the video according to the data recording format. By using the semiconductor device described above, the video camera 6300 can store temporary files generated during encoding.

[0232] [ICD] The semiconductor device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0233] 18J is a cross-sectional schematic diagram showing an example of an ICD. ICD main body 5400 has at least battery 5401, electronic components 4700, a regulator, a control circuit, antenna 5404, wire 5402 to the right atrium, and wire 5403 to the right ventricle.

[0234] The ICD body 5400 is surgically placed in the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0235] The ICD main unit 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve with pacing and rapid ventricular tachycardia or ventricular fibrillation persists, treatment with an electric shock is performed.

[0236] The ICD main body 5400 must constantly monitor the heart rate in order to properly perform pacing and administer electric shocks. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 can also store in the electronic component 4700 the heart rate data acquired by the sensor, the number of pacing treatments performed, the duration, etc.

[0237] Furthermore, the antenna 5404 can receive power, which is then charged into the battery 5401. Furthermore, the ICD main body 5400 can improve safety by having multiple batteries. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can still function, so the ICD main body 5400 can also function as an auxiliary power source.

[0238] In addition to the antenna 5404 that can receive power, an antenna that can transmit physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0239] [PC expansion device] The semiconductor device described in the above embodiment can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.

[0240] Figure 19A shows an example of such an expansion device: a portable expansion device 6100 that is external to a PC and equipped with a chip capable of storing information. The expansion device 6100 can store information using the chip by connecting to a PC via, for example, a USB (Universal Serial Bus). Note that while Figure 19A shows a portable expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this; for example, it may be a relatively large expansion device equipped with a cooling fan or the like.

[0241] The expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with circuits that drive the semiconductor devices and the like described in the above embodiments. For example, an electronic component 4700 and a controller chip 6106 are attached to the board 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0242] [SD card] The semiconductor device described in the above embodiment can be applied to an SD card which can be attached to an electronic device such as an information terminal or a digital camera.

[0243] FIG. 19B is a schematic diagram of the external appearance of an SD card, and FIG. 19C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a substrate 5113. The connector 5112 functions as an interface for connecting to an external device. The substrate 5113 is housed in the housing 5111. A semiconductor device and a circuit for driving the semiconductor device are provided on the substrate 5113. For example, an electronic component 4700 and a controller chip 5115 are attached to the substrate 5113. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation. For example, the write circuit, row driver, read circuit, etc. provided in the electronic component may be incorporated into the controller chip 5115 rather than the electronic component 4700.

[0244] The capacity of the SD card 5110 can be increased by providing the electronic component 4700 also on the back side of the substrate 5113. A wireless chip with a wireless communication function may be provided on the substrate 5113. This allows wireless communication between an external device and the SD card 5110, and enables reading and writing of data from and to the electronic component 4700.

[0245] [SSD] The semiconductor device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to electronic devices such as information terminals.

[0246] FIG. 19D is a schematic diagram of the external appearance of an SSD, and FIG. 19E is a schematic diagram of the internal structure of the SSD. The SSD 5150 includes a housing 5151, a connector 5152, and a circuit board 5153. The connector 5152 functions as an interface for connecting to an external device. The circuit board 5153 is housed in the housing 5151. The circuit board 5153 is provided with a semiconductor device and a circuit for driving the semiconductor device. For example, the circuit board 5153 is provided with an electronic component 4700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing an electronic component 4700 on the back side of the circuit board 5153 as well. The memory chip 5155 incorporates a work memory. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, and the like. The circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0247] [Calculator] 20A is an example of a large-scale computer. The computer 5600 has a rack 5610 storing a plurality of rack-mounted computers 5620.

[0248] Computer 5620 can have the configuration shown in the perspective view of Fig. 20B, for example. In Fig. 20B, computer 5620 has motherboard 5630, which has multiple slots 5631 and multiple connection terminals. PC card 5621 is inserted into slot 5631. In addition, PC card 5621 has connection terminal 5623, connection terminal 5624, and connection terminal 5625, which are each connected to motherboard 5630.

[0249] PC card 5621 shown in FIG. 20C is an example of a processing board including a CPU, a GPU, a semiconductor device, and the like. PC card 5621 includes board 5622. Board 5622 includes connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that FIG. 20C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 may be referred to.

[0250] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of a motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0251] Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Examples of standards for outputting video signals from connection terminals 5623, 5624, and 5625 include HDMI (registered trademark).

[0252] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0253] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU. For example, the electronic component 4730 can be used as the semiconductor device 5627.

[0254] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a semiconductor device. For example, the electronic component 4700 can be used as the semiconductor device 5628.

[0255] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0256] By using the semiconductor device of one embodiment of the present invention in the various electronic devices, power consumption of the electronic devices can be reduced.

[0257] The structure described in this embodiment mode can be combined as appropriate with structures described in other embodiments.

[0258] (Notes regarding the present specification) The above-described embodiments and the respective components in the embodiments will be described below with additional notes.

[0259] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. Furthermore, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0260] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or with the content (or even a part of the content) described in one or more other embodiments.

[0261] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0262] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0263] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0264] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0265] In this specification and the like, when describing the connection relationship of a transistor, the term "one of the source or drain" (or first electrode or first terminal) is used, and the other of the source and drain is referred to as "the other of the source or drain" (or second electrode or second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0266] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0267] Furthermore, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0268] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0269] In this specification, a switch refers to a device that has the function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows.

[0270] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0271] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0272] In this specification, "A and B are connected" includes not only a direct connection between A and B, but also an electrical connection between A and B. Here, "A and B are electrically connected" means that when an object having some kind of electrical effect exists between A and B, it enables the exchange of electrical signals between A and B. [Explanation of symbols]

[0273] BL: wiring, FE: ferroelectric layer, LE: electrode, MC: memory cell, M1: transistor, PL: wiring, UE: electrode, WL: wiring

Claims

[Claim 1] a first transistor; a second transistor; and a first capacitance; and a second capacitance; and wiring, the first transistor is electrically connected to the first capacitor; the second transistor is electrically connected to the second capacitor; the wiring is located below the first transistor and the second transistor, electrically connected to the first transistor or the second transistor, the first capacitor and the second capacitor each have a ferroelectric layer; The first capacitor and the second capacitor are arranged on the same plane. Semiconductor device.

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