Semiconductor device

Abstract

To provide a semiconductor device capable of increasing the number of semiconductor devices (the number of chips) obtained from one wafer.SOLUTION: A SiC layer of a first conductivity type having a front surface, a back surface, and an end face surrounding the front surface and the back surface, the SiC layer having a semiconductor element structure formed therein; a voltage relaxation layer of a second conductivity type formed in the SiC layer so as to be exposed at an end of the front surface of the SiC layer; A front surface electrode having a selectively exposed pad area, wherein the insulating layer has a structure composed of a plurality of layers including a first layer and a second layer laminated in order from the SiC layer, and the second layer is formed on the entire front surface of the SiC layer.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, when measuring the electrical characteristics of a high-voltage semiconductor device, there has been a problem of discharge occurring in the atmosphere.

[0003] As a countermeasure, for example, Patent Document 1 discloses a method for manufacturing a semiconductor device, which includes the steps of forming a base region and an emitter region in a semiconductor wafer, patterning the base electrode and the emitter electrode, and then depositing and patterning a polyimide film on the surface to cover the dicing region and other regions excluding the electrode bonding portion. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 60-50937 [Patent Document 2] Japanese Patent Application Publication No. 54-45570 [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-243837 [Patent Document 4] Japanese Patent Application Laid-Open No. 2001-176876 [Patent Document 5] Republished Patent Publication WO2009 / 101668 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device that allows the number of semiconductor devices (number of chips) obtained from one wafer to be increased compared to conventional methods. [Means for solving the problem]

[0006] The semiconductor device includes a first conductivity type SiC layer having a front surface, a back surface, and end surfaces surrounding the front surface and the back surface, and having a semiconductor element structure formed thereon; a second conductivity type voltage buffer layer formed on the SiC layer so as to be exposed at the end of the front surface of the SiC layer; an insulating layer formed on the SiC layer so as to cover the voltage buffer layer; and a front surface electrode connected to the front surface of the SiC layer through the insulating layer and having a selectively exposed pad area, wherein the insulating layer has a structure consisting of multiple layers including a first layer and a second layer stacked in order from the SiC layer, and the second layer is formed on the entire front surface of the SiC layer. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view taken along the line II-II in FIG. [Figure 3] FIG. 3 is a flowchart illustrating an example of a manufacturing process for the semiconductor device. [Figure 4] FIG. 4 is a diagram for explaining the effect associated with the distance X1 from the edge of the pad area to the end face of the SiC layer. [Figure 5] FIG. 5 is a diagram for explaining the effect associated with the distance X2 from the end of the connection portion of the anode electrode with the SiC layer to the end face. [Figure 6] FIG. 6 is a cross-sectional view illustrating the configuration of a semiconductor device according to a second embodiment of the present invention. [Figure 7] FIG. 7 is a cross-sectional view illustrating the configuration of a semiconductor device according to a third embodiment of the present invention. [Figure 8] FIG. 8 is a cross-sectional view illustrating the configuration of a semiconductor device according to a fourth embodiment of the present invention. [Figure 9] FIG. 9 is a cross-sectional view illustrating the configuration of a semiconductor device according to a first embodiment of the present invention. [Figure 10] FIG. 10 is a cross-sectional view illustrating the configuration of a semiconductor device according to a fifth embodiment of the present invention. [Figure 11] FIG. 11 is a cross-sectional view illustrating the configuration of a semiconductor device according to a sixth embodiment of the present invention. [Figure 12] FIG. 12 is a cross-sectional view illustrating the configuration of a semiconductor device according to a second embodiment of the present invention. [Figure 13] FIG. 13 is a cross-sectional view illustrating the configuration of a semiconductor device according to a seventh embodiment of the present invention. [Figure 14] FIG. 14 is a diagram for explaining an example of a planar structure of the semiconductor device of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0009] Fig. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view taken along the line II-II in Fig. 1. In Fig. 1 and Fig. 2, in order to facilitate understanding of the invention, the semiconductor device is shown before being separated from a wafer.

[0010] The semiconductor device 1 is an element that employs silicon carbide (SiC). During the manufacturing process, a large number of semiconductor devices 1 are formed in a regular array on a single SiC wafer 2. The SiC wafer 2 (hereinafter also referred to as "SiC layer 2") has dicing regions 4 with a predetermined width α (for example, 30 μm to 80 μm) that partition a plurality of element regions 3. In this embodiment, the dicing regions 4 are formed in a lattice pattern, and the plurality of element regions 3 are arranged in a matrix pattern as a whole. One semiconductor device 1 is formed in each element region 3, and the SiC wafer 2 is cut along the dicing regions 4 to be individualized. The semiconductor device 1 according to the first embodiment is a Schottky barrier diode.

[0011] The SiC layer 2 of each semiconductor device 1 cut out by dicing has a front surface 2A, a back surface 2B, and an end surface 2C surrounding the front surface 2A and the back surface 2B. The end surface 2C is a cut surface (side surface) of the SiC layer that appears by dicing and defines the outer periphery of the front surface 2A and the back surface 2B. In this embodiment, each semiconductor device 1 is, for example, a square chip in plan view. Its size is 0.5 mm to 20 mm in length in each of the vertical and horizontal directions on the plane of FIG. 1. That is, the chip size of the semiconductor device 1 is, for example, 0.5 mm square to 20 mm square.

[0012] The SiC layer 2 is n + A substrate 5 made of type SiC and an n-type SiC film formed on the substrate 5 - and an epitaxial layer 6 made of type SiC. The thickness of the substrate 5 is 50 μm to 1000 μm, and the thickness of the epitaxial layer 6 may be 5 μm or more (preferably 6 μm to 20 μm). Examples of n-type dopants that can be used in the substrate 5 and the epitaxial layer 6 include N (nitrogen), P (phosphorus), and As (arsenic) (the same applies below). The relationship between the dopant concentrations of the substrate 5 and the epitaxial layer 6 is such that the dopant concentration of the substrate 5 is relatively high, and the dopant concentration of the epitaxial layer 6 is relatively low compared to the substrate 5. Specifically, the dopant concentration of the substrate 5 is 1×10 17 ~1×10 22 cm -3 and the dopant concentration of the epitaxial layer 6 is 1×10 16 cm -3 or less (preferably 1 × 10 15 ~9×10 15 cm -3 ) may also be used.

[0013] A p-type voltage buffer layer 7 is formed on the surface of the epitaxial layer 6 so as to be exposed at the edge of the surface 2A. In this embodiment, the voltage buffer layer 7 is formed in a ring shape along the outer periphery of the SiC layer 2 so as to be exposed at a corner of the SiC layer 2 on the surface 2A side, which is formed by the surface 2A and the end face 2C of the SiC layer 2. As a result, the voltage buffer layer 7 is exposed on both the surface 2A and the end face 2C, and the areas exposed on each face 2A, 2C are integrated at the corner of the SiC layer 2. In addition, examples of p-type dopants included in the voltage buffer layer 7 include boron (B) and aluminum (Al). In addition, the voltage buffer layer 7 is formed so that its bottom is located on the surface 2A side of the boundary between the substrate 5 and the epitaxial layer 6. Specifically, the depth of the voltage buffer layer 7 may be, for example, 1000 Å to 10000 Å.

[0014] An insulating layer 8 and an anode electrode 9 serving as a surface electrode are formed on the SiC layer 2. The insulating layer 8 is formed so as to cover the voltage buffer layer 7, and has a structure consisting of multiple layers including a first layer 81 and a second layer 82 that are stacked in this order from the SiC layer 2. If the insulating layer 8 has a structure consisting of multiple layers, the type of insulating layer 8 can be changed in a wide variety of ways depending on the magnitude of the maximum applied voltage (BV) required for the Schottky barrier diode.

[0015] In this embodiment, the first layer 81 is formed over the entire surface 2A of the SiC layer 2. On the other hand, the second layer 82 is formed so as to expose the corner portions of the surface 2A of the SiC layer 2 in the first layer 81, and has an outer circumferential edge 83 that is recessed inward of the SiC layer 2 with respect to the end face 2C. Specifically, the voltage relaxation layer 7 covered with the insulating layer 8 is formed so as to overlap the outer circumferential edge 83 of the second layer 82 in the thickness direction of the SiC layer 2. That is, the inner circumferential edge 71 of the voltage relaxation layer 7 is located more inward in the SiC layer 2 than the outer circumferential edge 83 of the second layer 82. Furthermore, the first layer 81 has a contact hole 84 that selectively exposes the surface 2A of the SiC layer 2.

[0016] The anode electrode 9 includes a lower end 91 embedded in the contact hole 84 and an upper end 92 protruding upward from the first layer 81, and the bottom surface of the lower end 91 is connected to the surface 2A of the SiC layer 2 within the contact hole 84 as a connection portion 93. The upper end 92 of the anode electrode 9 further includes a drawn portion 94 as a peripheral portion that is uniformly drawn out in the lateral direction (the direction along the surface 2A of the SiC layer 2) from the outer periphery of the contact hole 84. As a result, the anode electrode 9 is formed with a size larger than the opening diameter of the contact hole 84 in a plan view.

[0017] Furthermore, the periphery of the upper end portion 92 of the anode electrode 9 is covered by the upper second layer 82. That is, a contact hole 85 is formed in the second layer 82 to selectively expose the center portion of the anode electrode 9 as a pad area 95. The contact hole 85 is formed so that the relative position of the outer periphery with respect to the end face 2C of the SiC layer 2 is more inward than the outer periphery of the contact hole 84. The specific size of the contact hole 85 is, for example, about 500 μm × 300 μm when a bonding wire with a diameter of 125 μm is connected to the pad area 95.

[0018] In this embodiment, the insulating layer 8 has a first layer 81 made of silicon oxide (SiO2) having a thickness of 1 μm or more, and a second layer 82 made of polyimide having a thickness of 0.2 μm or more. However, the material of the insulating layer 8 is not limited to this. For example, the first layer 81 may be made of polyimide having a thickness of 0.2 μm or more, or silicon nitride (SiN) having a thickness of 1 μm or more. Of these, SiO2 is most preferable from the viewpoint of adhesion with the SiC layer 2.

[0019] The anode electrode 9 can be made of a material that forms a Schottky barrier or a heterojunction with the n-type SiC layer 2, specifically, examples of the former include Mo (molybdenum), Ti (titanium), Ni (nickel), and Al (aluminum), and examples of the latter include polysilicon. That is, the anode electrode 9 that forms a Schottky barrier in this semiconductor device 1 may be either a metal electrode that forms a Schottky barrier with the SiC layer 2, or a semiconductor electrode made of a semiconductor having a band gap different from the band gap of the SiC layer 2 and that forms a heterojunction with the SiC layer 2 (a junction that forms a potential barrier with the SiC layer 2 by utilizing the band gap difference).

[0020] In this semiconductor device 1, when a forward bias state is established in which a positive voltage is applied to the anode electrode 9 and a negative voltage is applied to the cathode electrode (not shown), electrons (carriers) move from the cathode electrode to the anode electrode 9 via the SiC layer 2, causing a current to flow. This causes the semiconductor device 1 (Schottky barrier diode) to operate.

[0021] Next, a method for manufacturing the semiconductor device 1 will be described with reference to Figures 1 to 3. Figure 3 is a flow chart for explaining an example of a manufacturing process for the semiconductor device.

[0022] First, a SiC wafer 2 is prepared, which is composed of a substrate 5 and an epitaxial layer 6. As described above, this SiC wafer 2 has an element region 3 in which a plurality of semiconductor devices 1 are formed, and a dicing region 4 that partitions the element region 3 and defines end faces 2C of a plurality of semiconductor devices 1 that will ultimately be singulated and separated from one another, set in a grid pattern.

[0023] Next, for example, a voltage buffer layer 7 is formed by selectively implanting ions into the surface 2A of the SiC layer 2 and performing an annealing process (step S1). During manufacturing, the voltage buffer layer 7 is formed along the dicing region 4 so as to straddle adjacent element regions 3, with a width β wider than the width α of the dicing region 4. That is, in this embodiment, the voltage buffer layer 7 is formed in a lattice shape with a width β wider than the width α of the dicing region 4 (see the dashed dotted line in FIG. 1).

[0024] Next, first layer 81 is formed on the entire surface 2A of SiC layer 2 by a known film formation method such as CVD (step S2).

[0025] Next, contact holes 84 that selectively expose surface 2A of SiC layer 2 are formed in first layer 81, and then a material for anode electrode 9 is deposited by, for example, sputtering and patterned to form anode electrode 9 (step S3). Anode electrode 9 is connected to SiC layer 2 (epitaxial layer 6) through contact holes 84 in first layer 81.

[0026] Next, a second layer 82 is formed on the first layer 81 by a known film formation method such as CVD so as to cover the entire anode electrode 9 (step S4). Next, the second layer 82 is patterned to form a contact hole 85 that selectively exposes the center of the anode electrode 9 as a pad area 95 (step S5). At the same time, a lattice-shaped portion of the second layer 82 along the dicing region 4 is selectively removed, and the outer periphery 83 of the second layer 82 is recessed toward the inside of each element region 3 with respect to the line that becomes the end face 2C. Through the above steps, a Schottky barrier diode (semiconductor element structure) is formed in each element region 3 by the junction between the SiC layer 2 and the anode electrode 9.

[0027] The next step is to measure the electrical characteristics of each Schottky barrier diode (step S6). Specifically, the anode electrode 9 of one element region 3 is set to 0 V, and the back surface of the SiC wafer 2 is set to 1000 V or more (for example, 1700 V). This applies a maximum applied voltage (BV) that generates a potential difference of 1000 V or more between the anode electrode 9 and the SiC wafer 2, and the breakdown voltage of each Schottky barrier diode is measured.

[0028] In this case, the n-type portion of the SiC wafer 2, including a portion of the dicing region 4 (a portion other than the voltage buffer layer 7), is fixed at a potential of 1000 V or more, resulting in a potential difference of 1000 V or more between the dicing region 4 and the anode electrode 9. Even in such a case, according to this embodiment, the voltage buffer layer 7 is formed along the dicing region 4, and the voltage buffer layer 7 is further covered with the insulating layer 8. Therefore, the maximum applied voltage (BV) of 1000 V or more applied between the dicing region 4 and the anode electrode 9 can be buffered in two stages: the insulating layer 8 and the voltage buffer layer 7. This reduces the burden of the voltage applied in the atmosphere between the dicing region 4 and the anode electrode 9. In other words, as shown in FIG. 2, the voltage applied between the dicing region 4 and the anode electrode 9 can be shared among the atmosphere section 10, the insulating layer section 11, and the voltage buffer layer section 12. Therefore, even if the discharge inception voltage V in the atmosphere section 10 is lower than in the conventional case, the relationship of discharge inception voltage V > maximum applied voltage (BV) can be maintained.

[0029] According to Paschen's law, the discharge inception voltage V between two electrodes is expressed as a function of the product of the gas pressure P and the electrode distance (in this embodiment, the distance X1 from the edge of the pad area 95 (the outer periphery of the contact hole 85) to the dicing region 4), i.e., V=f(P·X1). With this semiconductor device 1, the discharge inception voltage V in the atmospheric section 10 can be made lower than in the past, and therefore, according to Paschen's law, the distance X1 can be made shorter than in the past.

[0030] Therefore, when the size (chip size) of the semiconductor device 1 is made the same as in the conventional case, the outer edge of the pad area 95 can be expanded toward the end face 2C of the SiC layer 2, making the pad area 95 wider than in the conventional case. On the other hand, when the pad area 95 is made the same size as in the conventional case, the end face 2C of the SiC layer 2 can be reduced toward the pad area 95, making it possible to increase the number of semiconductor devices 1 (number of chips) obtained from one SiC wafer 2 compared to the conventional case.

[0031] Furthermore, even if a defect (such as a hole due to a process defect) occurs in either the insulating layer 8 or the voltage relaxation layer 7, the defect can be covered by the other, thereby effectively preventing discharge between the dicing region 4 and the anode electrode 9.

[0032] Furthermore, the electrical characteristics of the Schottky barrier diode can be measured in a gas atmosphere such as air, nitrogen (N2), hydrogen (H2), argon (Ar), neon (Ne), helium (He), etc. The gas pressure P at this time is preferably, for example, 720 Torr to 1520 Torr.

[0033] According to the function V=f(P·X1) of Paschen's law, the discharge inception voltage V increases as the gas pressure P increases. Therefore, by setting the gas pressure P within the above range during measurement of the electrical characteristics, the distance X1 from the end of the pad area 95 to the dicing region 4 (end surface 2C of the SiC layer 2) can be further shortened.

[0034] Thereafter, the electrical characteristics of the Schottky barrier diodes in all of the element regions 3 are measured by the same method. After the measurements, the SiC wafer 2 is cut along the dicing regions 4 to separate the individual semiconductor devices 1. In this way, the semiconductor devices 1 having the structure shown in FIG. 2 and the like are obtained.

[0035] Next, with reference to FIG. 4, the effects associated with the distance X1 from the end of the pad area 95 to the end face 2C of the SiC layer 2 will be described.

[0036] In the semiconductor device 1, it is preferable that the maximum applied voltage (BV)Y (≧1000 V) applied to the Schottky barrier diode and the distance X1 from the end of the pad area 95 to the end face 2C of the SiC layer 2 satisfy the following relational expression (1): In the manufacturing process, when the second layer 82 is patterned to expose the pad area 95 (step S5), it is preferable to set the size of the pad area 95 (the size of the contact hole 85) so that the maximum applied voltage (BV)Y (≧1000 V) applied to the Schottky barrier diode and the distance X1 from the end of the pad area 95 to the dicing region 4 satisfy the following relational expression (1).

[0037]

number

[0038] As described above, by providing the insulating layer 8 and the voltage buffer layer 7, an insulating layer section 11 and a voltage buffer layer section 12 are interposed between the dicing region 4 and the anode electrode 9 in addition to the atmospheric section 10. The presence of the insulating layer 8 and the voltage buffer layer 7 effectively prevents discharge between the dicing region 4 and the anode electrode 9.

[0039] On the other hand, between the anode electrode 9 of one element region 3 and the anode electrode 9 of the element region 3 adjacent to that element region 3 (section 13), the exposed pad areas 95 are connected to each other only through the atmosphere. Therefore, when measuring the electrical characteristics of the Schottky barrier diode (step S6), if the maximum applied voltage (BV) (≧1000 V) exceeds the discharge inception voltage V in the atmosphere, discharge may occur between the adjacent anode electrodes 9.

[0040] According to the function V=f(P·X1) of Paschen's law, the discharge inception voltage V in the atmosphere decreases as the distance X1 decreases. That is, although the distance X1 from the edge of the pad area 95 to the dicing region 4 (the end surface 2C of the SiC layer 2) can be shortened as a result of this embodiment, the discharge inception voltage V in the section 13 connected only via the atmosphere also decreases accordingly. Therefore, it is necessary to prevent discharge in the section 13 by preventing the maximum applied voltage (BV) from exceeding the discharge inception voltage V in the atmosphere while maintaining the distance X1 as short as possible.

[0041] Therefore, in this semiconductor device 1, by satisfying the above relational expression (1), it is possible to shorten the distance X1 from the end of the pad area 95 to the dicing region 4 (end surface 2C of the SiC layer 2) compared to the conventional case, while reliably preventing discharge between adjacent anode electrodes 9.

[0042] Specifically, the inventors have investigated the relationship between the discharge inception voltage V and the discharge distance between two electrodes connected to each other only through the atmosphere, as shown in the graph of FIG. 4(a) (Y=1.053E+03e 5.846E-04X ) In this formula, "E" represents a power of 10 (the same applies below). For example, 1.053E+03 is 1.053 x 10 3 Also, e 5.846E-04X is exp(5.846×10 -04 -X). According to FIG. 4(a), when the discharge distance (the distance between the two electrodes) is 200 μm, 400 μm, or 700 μm, a discharge may occur when a potential difference of 1200 V or more, 1300 V or more, or 1600 V or more occurs between the two electrodes, respectively. In other words, in FIG. 4(a), a discharge may occur when the coordinates fall within the upper region (shaded area) of the graph.

[0043] The inventor further studied the relationship between the maximum applied voltage (BV)Y and the distance X1 in the semiconductor device 1 based on FIG. 4(a). In the semiconductor device 1, the distance corresponding to the discharge distance in FIG. 4(a) is the shortest distance between adjacent anode electrodes 9. This shortest distance corresponds to twice the distance X1 (2(X1)) from the edge of each pad area 95 (the outer edge of the contact hole 85) to the dicing region 4 (strictly speaking, it is 2(X1) + α, but the width α is ignored here). Therefore, when the distance X1 is 100 μm, 200 μm, or 350 μm in the semiconductor device 1, if a potential difference of 1200 V or more, 1300 V or more, or 1600 V or more occurs between adjacent anode electrodes 9 during measurement of the electrical characteristics of the Schottky barrier diode (step S6), a discharge may occur between them. That is, when the maximum applied voltage (BV) that generates the potential difference is applied to the anode electrode 9 of one element region 3, there is a risk of discharge occurring between the element region 3 and the anode electrode 9 of the element region 3 adjacent to that element region 3.

[0044] In view of the above, the graph of FIG. 4(b) shows the relationship between the maximum applied voltage (BV) Y and the distance X1 in the semiconductor device 1. The graph of FIG. 4(b) shows the relationship between the maximum applied voltage (BV) Y and the distance X1. 1.169E-03X1 This represents a function of the distance X1. Converting this to an equation for X1 gives X1 = 855 ln(Y / 1053). In Figure 4(b), there is a risk of discharge occurring when the coordinates fall within the upper region of the graph (shaded area), and there is little chance of discharge occurring when they fall within the lower region. Therefore, to reliably prevent discharge from occurring between adjacent anode electrodes 9, the coordinates of the maximum applied voltage (BV) Y and the distance X1 must fall within the lower region of the graph.

[0045] However, even if the coordinates are included in the lower region, it is preferable that the distance X1 be as short as possible in order to achieve the effect of widening the pad area 95 and increasing the number of semiconductor devices 1 that can be obtained.

[0046] Therefore, in this embodiment, as described above, the maximum applied voltage (BV)Y and the distance X1 are set so as to satisfy the following relational expression (1).

[0047]

number

[0048] This relational expression (1) indicates that the coordinates of the maximum applied voltage (BV) Y and the distance X1 are included in the area (shaded area) surrounded by X1 = 855 · ln(Y / 1053) and X1 = 855 · ln(Y / 1053) + 100 in Figure 4(b). This makes it possible to shorten the distance X1 from the edge of the pad area 95 to the dicing region 4 (end surface 2C of the SiC layer 2) compared to conventional methods, while also reliably preventing discharge between adjacent anode electrodes 9.

[0049] Next, with reference to FIG. 5, the effect relating to distance X2 from the end of connection portion 93 of anode electrode 9 with SiC layer 2 to end face 2C will be described.

[0050] In the semiconductor device 1, it is preferable that a distance X2 from an end (outer periphery of the contact hole 84) of a connection portion 93 of the anode electrode 9 with the SiC layer 2 to the end face 2C be longer than a width X3 of a depletion layer 14 that spreads laterally from the connection portion 93 along the surface 2A of the SiC layer 2 when a maximum applied voltage (BV) is applied to the Schottky barrier diode. In the manufacturing process, when the contact hole 84 is formed in the first layer 81 and the anode electrode 9 is connected to the SiC layer 2 through the contact hole 84 (step S3), it is preferable to set the relative position of the connection portion 93 with respect to the dicing region 4 so that the distance X2 from the end of the connection portion 93 to the dicing region 4 is longer than the width X3 of the depletion layer 14.

[0051] It is generally said that a depletion layer in a semiconductor layer made of SiC extends approximately twice as far in the direction perpendicular to the thickness direction (vertical direction) of the semiconductor layer (horizontal direction). If distance X2 is shorter than width X3 of depletion layer 14 when the maximum applied voltage (BV) is applied, depletion layer 14 may extend to end surface 2C of SiC layer 2 when the maximum applied voltage (BV) is applied to each individual semiconductor device 1. Therefore, in this semiconductor device 1, by making distance X2 greater than width X3, depletion layer 14 can be prevented from reaching end surface 2C of SiC layer 2.

[0052] Furthermore, in this semiconductor device 1, the outer periphery of contact hole 85, which is the starting point of distance X1, is located more inward with respect to end face 2C of SiC layer 2 than the outer periphery of contact hole 84, which is the starting point of distance X2. Therefore, distance X1 and distance X2 satisfy the relationship X1>X2. Therefore, if distance X2 is set to satisfy the above-mentioned relational expression (1), exposure of depletion layer 14 at end face 2C can be prevented, and discharge between adjacent anode electrodes 9 can also be reliably prevented.

[0053] Here, an example of the distance X2 will be given using specific values. For example, when the impurity concentration of the epitaxial layer 6 is 7×10 15 cm -3 When the thickness is 7 μm, the maximum applied voltage (BV) is theoretically 1450 V. In this case, the depletion layer 14 theoretically extends 15.2 μm in the vertical direction of the epitaxial layer 6. Therefore, theoretically, the width X3 of the depletion layer 14 in the horizontal direction is 30.4 μm. Since the distance X2 only needs to be longer than the width X3, under this condition, the distance X2 is greater than 30.4 μm.

[0054] On the other hand, when the maximum applied voltage (BV) is 1450 V, the discharge distance in the atmosphere is 550 μm, as shown in FIG. 4(a). To reliably prevent discharge between adjacent anode electrodes 9, the distance X2 needs to be longer than half of this discharge distance, so the distance X2 is greater than 275 μm.

[0055] That is, if only exposure of the depletion layer 14 at the end surface 2C is to be prevented, the distance X2 should be greater than 30.4 μm, and if discharge between adjacent anode electrodes 9 is to be prevented at the same time, the distance X2 should be greater than 275 μm.

[0056] 6 to 14 are diagrams illustrating the configurations of semiconductor devices according to other embodiments of the present invention and a reference embodiment of the present invention, respectively. In Fig. 6 to Fig. 14, parts corresponding to those shown in Fig. 2 are denoted by the same reference numerals.

[0057] In a semiconductor device 102 according to the second embodiment shown in FIG. 6, a termination structure 15 is further formed on the SiC layer 2. The termination structure 15 is formed in a ring shape around the periphery of the anode electrode 9, spanning the inside and outside of the contact hole 84 in the first layer 81. This termination structure 15 makes it possible to adjust the extent of the expansion of the depletion layer 14 (see FIG. 5) from the connection portion 93 of the anode electrode 9. Furthermore, the maximum applied voltage (BV) of the Schottky barrier diode can be adjusted by adjusting the impurity concentration of the termination structure 15. Furthermore, a plurality of termination structures may be formed concentrically, as in a semiconductor device 103 (third embodiment) shown in FIG. 7.

[0058] In the first embodiment, the voltage buffer layer 7 is formed so as to overlap the outer peripheral edge 83 of the second layer 82 in the thickness direction of the SiC layer 2. However, as in the semiconductor device 104 (fourth embodiment) of FIG. 8 , the voltage buffer layer 7 may be formed so as not to overlap the outer peripheral edge 83 of the second layer 82. That is, the inner peripheral edge 71 of the voltage buffer layer 7 may be located outside the SiC layer 2 with respect to the outer peripheral edge 83 of the second layer 82.

[0059] In addition, in the first embodiment, only the first layer 81 was formed on the entire surface 2A of the SiC layer 2, but as in the semiconductor device 105 (first reference embodiment) of Figure 9, both the first layer 81 and the second layer 82 may be formed on the entire surface 2A of the SiC layer 2.

[0060] 10 and 11 according to the fifth and sixth embodiments, the second layer 82 has a protrusion 86 that selectively penetrates the first layer 81 and reaches the surface 2A of the SiC layer 2. As shown in FIG. 10, only one protrusion 86 may be formed, or as shown in FIG. 11, multiple protrusions 86 may be formed. With this configuration, even if the first layer 81 peels off from the end surface 2C of the SiC layer 2, the peeling can be stopped by the protrusion 86 of the second layer 82. Therefore, the adhesion of the insulating layer 8 to the SiC layer 2 can be improved.

[0061] Furthermore, in the first embodiment, the insulating layer 8 had a structure consisting of multiple layers including a first layer 81 and a second layer 82, but it may also have a structure consisting of a single layer, as in the semiconductor device 108 (second reference embodiment) of Figure 12.

[0062] In the first embodiment described above, the semiconductor element structure formed in the SiC layer 2 is a Schottky barrier diode structure having the SiC layer 2 and the anode electrode 9 forming a Schottky barrier between the SiC layer 2 and the anode electrode 9. However, in the semiconductor device 109 of FIG. 13, an MIS (Metal Insulator Semiconductor) transistor structure is formed as the semiconductor element structure.

[0063] The MIS transistor structure includes a SiC layer 2, a p-type channel region 16, and an n + a source region 17 of type p + The semiconductor device 109 includes a channel contact region 18, a gate insulating film 19, and a gate electrode 20. The semiconductor device 109 also includes an interlayer insulating film 21 and a source electrode 22 as a surface electrode as components associated with the MIS transistor structure.

[0064] The channel regions 16 are selectively formed in the surface portion of the epitaxial layer 6, for example, in a plurality of regions that are periodically and discretely arranged on the SiC layer 2. The channel regions 16 may be arranged, for example, in a matrix, staggered, or striped pattern.

[0065] The source region 17 is formed in an inner region of the channel region 16. The source region 17 is selectively formed in the surface portion of the channel region 16 in this region. The source region 17 is formed in the channel region 16 so as to be located a predetermined distance inward from the interface between the channel region 16 and the epitaxial layer 6. As a result, in the surface region of the semiconductor layer including the epitaxial layer 6, the channel region 16, etc., the surface portion of the channel region 16 is interposed between the source region 17 and the epitaxial layer 6, and this interposed surface portion provides a channel portion 23.

[0066] The channel contact region 18 passes through the source region 17 and is connected to the channel region 16 .

[0067] The gate insulating film 19 may be made of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a hafnium oxide film, an alumina film, a tantalum oxide film, etc. The gate insulating film 19 is formed so as to cover at least the surface of the channel region 16 in the channel portion 23.

[0068] The gate electrode 20 is formed to face the channel portion 23 via the gate insulating film 19. The gate electrode 20 may be made of, for example, polysilicon with low resistance due to impurity implantation. In this embodiment, the gate electrode 20 is formed in substantially the same pattern as the gate insulating film 19, and covers the surface of the gate insulating film 19. This forms a planar gate structure.

[0069] Interlayer insulating film 21 can be formed, for example, as an extension of first layer 81 drawn along surface 2A of SiC layer 2. Interlayer insulating film 21 covers the upper and side surfaces of gate electrode 20 and is formed in a pattern having contact holes 24 in the central region of channel region 16 and in the inner edge region of source region 17 connected to this region.

[0070] The source electrode 22 is made of aluminum (Al) or another metal. The source electrode 22 covers the surface of the interlayer insulating film 21 and is embedded in the contact hole 24. As a result, the source electrode 22 forms an ohmic contact with the source region 17. Examples of the planar shape of the source electrode 22 include those shown in FIGS. 14(a) to 14(c). In FIGS. 14(a) to 14(c), the source electrode 22 is formed to cover almost the entire surface of the semiconductor device 109. A removed region 25 is selectively formed in a portion of each source electrode 22. A terminal electrically connected to the gate electrode 20 is formed in the removed region 25. Specifically, gate pads 26 and 27 are formed in FIGS. 14(a) and 14(b), and a gate finger 28 is formed in FIG. 14(c). A portion of the source electrode 22 is exposed as a pad area 221 through a contact hole 85 in the second layer 82 of the insulating layer 8.

[0071] Furthermore, this semiconductor device 109 may include a p-type annular region 29 surrounding the MIS transistor structure in the SiC layer 2, and a contact region 30 formed on the surface of the annular region 29. The annular region 29 and the contact region 30 may be exposed through a contact hole 84 in the first layer 81. That is, when the source electrode 22 as a surface electrode is connected at multiple points on the SiC layer 2, the outermost connection portion (in this embodiment, the connection portion 222 to the contact region 30) corresponds to the "connection portion of the surface electrode with the SiC layer" of the present invention.

[0072] In the seventh embodiment, a planar gate structure is shown as an example of the MIS transistor structure, but the MIS transistor structure may also be a trench gate structure.

[0073] Although the embodiment of the present invention has been described above, the present invention can be embodied in other forms.

[0074] For example, a configuration may be adopted in which the conductivity types of the semiconductor portions of the aforementioned semiconductor devices 1, 101 to 109 are reversed. For example, in semiconductor device 1, the p-type portions may be n-type, and the n-type portions may be p-type.

[0075] Furthermore, the voltage buffer layer 7 must have a different conductivity type from the SiC layer 2 (p-type in the above-described embodiment and reference embodiment), but may have a portion of the same conductivity type as the SiC layer 2 in its inner region. For example, the voltage buffer layer 7 may have an n-type region located a predetermined distance inward from the interface between the voltage buffer layer 7 and the epitaxial layer 6. If an n-type region is formed, for example, in the configuration of FIG. 13, n + This can prevent charge-up when forming the source region 17 of the mold by ion implantation.

[0076] The semiconductor device (semiconductor power device) of the present invention can be incorporated into a power module used in an inverter circuit that constitutes a drive circuit for driving an electric motor used as a power source for electric vehicles (including hybrid vehicles), trains, industrial robots, etc. It can also be incorporated into a power module used in an inverter circuit that converts the power generated by a solar cell, a wind power generator, or other power generation device (particularly a private power generation device) so that it is compatible with the power of a commercial power source.

[0077] Furthermore, the features understood from the disclosure of the above embodiments can be combined with each other between different embodiments, and the components described in each embodiment can be combined within the scope of the present invention.

[0078] In addition, various design modifications can be made within the scope of the claims.

[0079] Furthermore, from the description in this specification and drawings, the following features can be extracted in addition to the invention described in the claims.

[0080] The semiconductor device has a front surface, a back surface, and end surfaces surrounding the front surface and the back surface, and includes a first conductivity type SiC layer on which a semiconductor element structure is formed, a second conductivity type voltage buffer layer formed on the SiC layer so as to be exposed at the end of the front surface of the SiC layer, an insulating layer formed on the SiC layer so as to cover the voltage buffer layer, and a front surface electrode connected to the front surface of the SiC layer through the insulating layer and having a selectively exposed pad area (Item 1).

[0081] This semiconductor device can be manufactured by a semiconductor device manufacturing method (item 20) that includes, for example, forming a semiconductor device structure in each element region in a first conductivity type SiC wafer having a front surface and a back surface and a dicing region of a predetermined width that divides a plurality of element regions, forming a voltage buffer layer of a second conductivity type wider than the width of the dicing region along the dicing region so as to straddle adjacent element regions, forming an insulating layer on the SiC wafer to cover the voltage buffer layer, and forming a surface electrode for each element region so as to be connected to the surface of the SiC wafer through the insulating layer and a portion of which is selectively exposed as a pad area, applying a maximum applied voltage (BV) that generates a potential difference of 1000 V or more between the surface electrode of one element region and the SiC wafer, and measuring the electrical characteristics of the semiconductor device structure in the element region, and cutting the SiC wafer along the dicing region to separate the SiC wafer into a plurality of semiconductor devices.

[0082] To prevent discharges from occurring between the dicing area and the surface electrode when measuring the electrical characteristics of semiconductor device structures, the discharge inception voltage V between the dicing area and the surface electrode must be higher than the maximum applied voltage (BV) (≥ 1000V). The maximum applied voltage (BV) represents the voltage (breakdown voltage: BV) at which the semiconductor device structure experiences avalanche breakdown, and a potential difference equivalent to this maximum applied voltage (BV) is generated between the dicing area and the surface electrode. On the other hand, the discharge inception voltage V represents the voltage at which an insulator, such as air, between the dicing area and the surface electrode breaks down and current begins to flow between them. In other words, as long as the discharge inception voltage V > maximum applied voltage (BV) relationship is satisfied, the insulation between the dicing area and the surface electrode is maintained.

[0083] Therefore, in the semiconductor device, a voltage buffer layer is formed along the dicing region, and the voltage buffer layer is further covered with an insulating layer. Therefore, when measuring the electrical characteristics of the semiconductor element structure, the maximum applied voltage (BV) can be buffered in two stages: the insulating layer and the voltage buffer layer. This reduces the burden of the voltage applied in the air between the dicing region and the front electrode. In other words, because the voltage applied between the dicing region and the front electrode can be shared by the air, the insulating layer, and the voltage buffer layer, the relationship of discharge inception voltage V > maximum applied voltage (BV) can be maintained even if the discharge inception voltage V in the air is lower than in the past.

[0084] According to Paschen's law, the discharge inception voltage V between two electrodes is expressed as a function of the product of the gas pressure P and the electrode spacing (in the semiconductor device, this is the distance X1 from the edge of the pad area to the dicing area), i.e., V=f(P·X1). With the semiconductor device, the discharge inception voltage V in the atmosphere can be made lower than in the past, and therefore, according to Paschen's law, the distance X1 from the edge of the pad area to the dicing area (the edge face of the SiC layer) can be made shorter than in the past.

[0085] Therefore, if the size of the semiconductor device (chip size) is to be the same as in the past, the outer edge of the pad area can be expanded toward the end face of the SiC layer, making the pad area of ​​the front electrode wider than in the past. On the other hand, if the pad area of ​​the front electrode is to be the same size as in the past, the end face of the SiC layer can be reduced toward the pad area, making it possible to increase the number of semiconductor devices (number of chips) obtained from one SiC wafer compared to the past.

[0086] Furthermore, even if a defect (such as a hole due to a process defect) occurs in either the insulating layer or the voltage buffer layer, the defect can be covered by the other layer, effectively preventing discharge between the dicing region and the surface electrode.

[0087] In the semiconductor device, it is preferable that the maximum applied voltage (BV)Y (≧1000V) of the semiconductor element structure and the distance X1 from the edge of the pad area to the end face of the SiC layer satisfy the following relational expression (1) (Item 2). Regarding the manufacturing method, it is preferable that the step of forming the front surface electrode includes a step of setting the size of the pad area so that the maximum applied voltage (BV)Y (≧1000V) of the semiconductor element structure and the distance X1 from the edge of the pad area to the dicing region satisfy the following relational expression (1) (Item 21).

[0088]

number

[0089] As described above, by providing the insulating layer and the voltage buffer layer, at least several layers other than the air and the first conductivity type SiC are interposed between the dicing area and the front surface electrode, which effectively prevents discharge between the dicing area and the front surface electrode.

[0090] On the other hand, the exposed pad areas between the surface electrodes of one element region and the adjacent element region are connected only through the atmosphere, so when measuring the electrical characteristics of the semiconductor element structure, if the maximum applied voltage (BV) (≧1000V) exceeds the discharge inception voltage V in the atmosphere, discharge may occur between the adjacent surface electrodes.

[0091] According to the function V=f(P·X1) of Paschen's law, the discharge inception voltage V decreases as X1 decreases. In other words, even if the distance X1 from the edge of the pad area to the dicing region (edge ​​surface of the SiC layer) can be shortened as a result of the semiconductor device, the discharge inception voltage V between the surface electrodes connected only through the atmosphere also decreases accordingly. Therefore, it is necessary to prevent discharge between the surface electrodes by preventing the maximum applied voltage (BV) from exceeding the discharge inception voltage V in the atmosphere while maintaining the distance X1 as short as possible.

[0092] Therefore, in this configuration, by satisfying the above relational expression (1), the distance X1 from the edge of the pad area to the dicing region (end surface of the SiC layer) can be made shorter than in the conventional case, while reliably preventing discharge between adjacent surface electrodes.

[0093] Furthermore, in the semiconductor device, it is preferable that a distance X2 from an end of a connection portion of the front surface electrode with the SiC layer to the end face of the SiC layer is longer than a width of a depletion layer that spreads laterally from the connection portion along the surface of the SiC layer when a maximum applied voltage (BV) is applied to the semiconductor element structure (Item 3). With regard to the manufacturing method, it is preferable that the step of forming the front surface electrode includes a step of setting a relative position of the connection portion with respect to the dicing region so that a distance X2 from an end of the connection portion of the front surface electrode with the SiC wafer to the dicing region is longer than a width of a depletion layer that spreads laterally from the connection portion along the surface of the SiC wafer when a maximum applied voltage (BV) is applied to the semiconductor element structure (Item 22).

[0094] With this configuration, in the semiconductor devices cut into individual pieces, it is possible to prevent the depletion layer that spreads laterally from the connection portion of the front surface electrode with the SiC layer from reaching the end face of the SiC layer.

[0095] Moreover, it is preferable that the semiconductor device further includes a second conductivity type termination structure formed in a ring shape along the periphery of the front surface electrode in the SiC layer (item 4).

[0096] This configuration allows for adjustment of the extent of the depletion layer extending from the connection portion of the front electrode with the SiC layer. Furthermore, by adjusting the impurity concentration of the termination structure, the maximum applied voltage (BV) of the semiconductor device structure can be adjusted. In this case, multiple termination structures may be formed concentrically (Item 5).

[0097] In addition, in the semiconductor device, it is preferable that the insulating layer has a structure consisting of multiple layers including a first layer and a second layer stacked in order from the SiC layer (Item 6). With this configuration, the type of insulating layer can be changed in a wide variety of ways depending on the magnitude of the maximum applied voltage (BV) required for the semiconductor element structure.

[0098] In the semiconductor device, the first layer may be formed on the entire surface of the SiC layer, and the second layer may be formed to expose a portion of the first layer on the edge of the surface of the SiC layer, and may have an outer periphery that is recessed inward from the edge of the SiC layer (item 7). In this case, the voltage buffer layer may be formed to overlap the outer periphery of the second layer in the thickness direction of the SiC layer (item 8), or may be formed not to overlap the outer periphery of the second layer (item 9).

[0099] In the semiconductor device, the second layer preferably includes a protrusion that selectively penetrates the first layer and reaches the surface of the SiC layer (item 10). In this case, the second layer may have a plurality of protrusions (item 11).

[0100] With this configuration, even if the first layer peels off from the end face of the SiC layer, the peeling can be stopped by the protrusions of the second layer, thereby improving the adhesion of the insulating layer to the SiC layer.

[0101] In the semiconductor device, both the first layer and the second layer may be formed on the entire surface of the SiC layer (item 12).

[0102] In the semiconductor device, the first layer may be made of any of silicon oxide (SiO2) having a thickness of 1 μm or more, polyimide having a thickness of 0.2 μm or more, and silicon nitride (SiN) having a thickness of 1 μm or more (items 13 to 15).

[0103] In the semiconductor device, the insulating layer may have a single-layer structure (item 16).

[0104] In the semiconductor device, the semiconductor element structure may include a Schottky barrier diode structure formed by the front surface electrode being made of a material that forms a Schottky barrier between the front surface electrode and the SiC layer (Item 17).The semiconductor element structure may also include an MIS transistor structure having a second conductivity type channel region selectively formed in the SiC layer, a first conductivity type source region formed so as to contact the channel region, a gate insulating film formed on the channel region, and a gate electrode facing the channel region via the gate insulating film (Item 18).

[0105] In the semiconductor device, the SiC layer includes a SiC substrate and a SiC epitaxial layer formed on the SiC substrate, and the SiC epitaxial layer has a surface roughness of 1×10 16 cm -3 The thickness may be 5 μm or more and the impurity concentration may be as follows:

[0106] Furthermore, in the method for manufacturing a semiconductor device, it is preferable that the step of measuring the breakdown voltage of the semiconductor element structure is performed under a pressure of 720 Torr to 1520 Torr (item 23).

[0107] According to the function V=f(P·X1) of Paschen's law, the discharge inception voltage V increases as the gas pressure P increases. Therefore, by keeping the gas pressure P within the above range when measuring the electrical characteristics, the distance X1 from the edge of the pad area to the dicing region (the edge surface of the SiC layer) can be further shortened. [Explanation of symbols]

[0108] 1 semiconductor device, 2 SiC wafer (SiC layer), 2A front surface, 2B back surface, 2C end surface, 3 element region, 4 dicing region, 5 substrate, 6 epitaxial layer, 7 voltage relaxation layer, 8 insulating layer, 81 first layer, 82 second layer, 83 outer periphery, 86 protrusion, 9 anode electrode, 93 connection portion, 95 pad area, 14 depletion layer, 15 termination structure, 16 channel region, 17 source region, 19 gate insulating film, 20 gate electrode, 22 source electrode, 221 pad area, 222 connection portion, 102 semiconductor device, 103 semiconductor device, 104 semiconductor device, 105 semiconductor device, 106 semiconductor device, 107 semiconductor device, 108 semiconductor device, 109 semiconductor device

Claims

1. a first conductivity type SiC layer having a front surface, a back surface, and end surfaces surrounding the front surface and the back surface, and having a semiconductor element structure formed thereon; a voltage buffer layer of a second conductivity type formed on the SiC layer so as to be exposed at an end of the surface of the SiC layer; an insulating layer formed on the SiC layer so as to cover the voltage buffer layer; a surface electrode connected to the surface of the SiC layer through the insulating layer and having a selectively exposed pad area; Including, the insulating layer has a structure made up of multiple layers including a first layer and a second layer stacked in this order from the SiC layer, The semiconductor device, wherein the second layer is formed on the entire surface of the SiC layer.

2. 2. The semiconductor device according to claim 1, wherein a maximum applied voltage (BV) Y (≧1000 V) of the semiconductor element structure and a distance X1 from an end of the pad area to the end surface of the SiC layer satisfy the following relational expression (1): [Equation 1]

3. 3. The semiconductor device according to claim 1, wherein a distance X2 from an end of a connection portion of the front surface electrode with the SiC layer to the end surface of the SiC layer is longer than a width of a depletion layer that spreads laterally from the connection portion along the surface of the SiC layer when a maximum applied voltage (BV) is applied to the semiconductor element structure.

4. 4. The semiconductor device according to claim 1, further comprising a termination structure of a second conductivity type formed in an annular shape along a periphery of said surface electrode in said SiC layer.

5. The semiconductor device according to claim 4 , wherein a plurality of said termination structures are formed concentrically.

6. 6. The semiconductor device according to claim 1, wherein the voltage relaxation layer is formed so as not to overlap an outer periphery of the second layer in a thickness direction of the SiC layer.

7. 7. The semiconductor device according to claim 1, wherein the second layer includes a protrusion that selectively penetrates the first layer and reaches the surface of the SiC layer.

8. The semiconductor device according to claim 7 , wherein a plurality of said protrusions are formed on said second layer.

9. The semiconductor device according to claim 1 , wherein said first layer is formed on said entire surface of said SiC layer.

10. The first layer is made of silicon oxide (SiO ２ 10. The semiconductor device according to claim 1, wherein

11. 10. The semiconductor device according to claim 1, wherein the first layer is made of polyimide having a thickness of 0.2 μm or more.

12. 10. The semiconductor device according to claim 1, wherein the first layer is made of silicon nitride (SiN) having a thickness of 1 μm or more.

13. The semiconductor device structure includes:

13. The semiconductor device according to claim 1, further comprising a Schottky barrier diode structure formed by the front surface electrode being made of a material that forms a Schottky barrier between itself and the SiC layer.

14. The semiconductor device structure includes: a second conductivity type channel region selectively formed in the SiC layer; a first conductivity type source region formed in contact with the channel region; a gate insulating film formed on the channel region; a gate electrode facing the channel region via the gate insulating film; 14. The semiconductor device according to claim 1, comprising a MIS transistor structure having:

15. the SiC layer includes a SiC substrate and a SiC epitaxial layer formed on the SiC substrate; The SiC epitaxial layer has a thickness of 1×10 １６ cm －３ 15. The semiconductor device according to claim 1, having an impurity concentration of at most 1000 .mu.m and a thickness of at least 5 .mu.m.

Images