Semiconductor Devices

Abstract

To provide a semiconductor device suitable for miniaturization and high density. A first transistor, a first insulating film on the first transistor, and a first insulating film on the first transistor. a second insulating film on the insulating film; a second transistor on the second insulating film; and a first transistor. a first conductive film electrically connected to the first transistor; and a second conductive film electrically connected to the first conductive film and the second transistor. The first conductive film penetrates the first insulating film, and the second conductive film is 2 and the semiconductor film and the source electrode or the drain electrode of the second transistor. The channel formation region of the first transistor has a single-crystal semiconductor, and the channel formation region of the second transistor has a single-crystal semiconductor. The channel formation region includes an oxide semiconductor, and the width of the bottom of the second conductive film is 5 nm or less. A semiconductor device.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device including a field-effect transistor.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an article, a method, or a manufacturing method. One aspect of the invention is a process, machine, manufacture, or composition of matter. Therefore, the present invention disclosed in this specification more specifically relates to the In one embodiment, the present invention relates to a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, and the like. Examples of the present invention include a power storage device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof. These can be listed as follows.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0004] The technology of constructing transistors using semiconductor materials is attracting attention. Electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices) Silicon-based semiconductor materials are widely used as semiconductor materials for transistors. However, oxide semiconductors are attracting attention as other materials.

[0005] For example, zinc oxide or In-Ga-Zn oxide semiconductor is used as the oxide semiconductor. Techniques for fabricating transistors using this method have been disclosed (see Patent Documents 1 and 2).

[0006] In recent years, with the increasing performance, miniaturization, and weight reduction of electronic devices, miniaturized transistors have become increasingly common. There is a growing demand for integrated circuits that integrate semiconductor elements such as transistors at high density. Tri-Gate transistor and COB (capacitor over bitlin e) structure of an MIM capacitor has been introduced (Non-Patent Document 1). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Non-patent literature]

[0008] [Non-Patent Document 1] R.Brain et al.,”A 22nm High Performance Embedded DRAM SoC Technology Featuring Tri-gate Transistors and MIMCAP COB”,2013 SYMPOSIUM ON VLSI TECHNOLOGY 2-1 Summary of the Invention [Problem to be solved by the invention]

[0009] An object of one aspect of the present invention is to provide a semiconductor device suitable for miniaturization and high density. Another object is to provide a semiconductor device with favorable electrical characteristics.

[0010] Another object is to provide a semiconductor device with a high writing speed. It is an object of the present invention to provide a semiconductor device having high speed or low power consumption. Another object of the present invention is to provide a semiconductor device having high reliability. Another object of the present invention is to provide a semiconductor device having a novel structure.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] (1) One aspect of the present invention is a semiconductor device including a first transistor and a first insulating film disposed on the first transistor. a second insulating film on the first insulating film; a second transistor on the second insulating film; and a first a first conductive film electrically connected to the transistor; and a first conductive film and a second transistor. and a second conductive film electrically connected to the first insulating film, the first conductive film passing through the first insulating film, The conductive film is a second insulating film, a semiconductor film of the second transistor, and a source electrode or a drain electrode. The channel formation region of the first transistor is formed of a single-crystal semiconductor. The channel formation region of the transistor includes an oxide semiconductor, and the width of the bottom of the second conductive film is 5. The semiconductor device is characterized by a surface roughness of 100 nm or less.

[0013] (2) Alternatively, in one embodiment of the present invention, the first conductive film is a source region of the first transistor or The semiconductor device according to (1) is characterized in that it is in contact with the drain region.

[0014] (3) Alternatively, one embodiment of the present invention is a structure including first to fourth isosceles triangles and a square. The vertices of the inverted square pyramid, in which the vertex angles of the first to fourth isosceles triangles are 120° or less, are designated as the first triangle. When the center of the top surface of the gate electrode of the transistor is taken as the center, the bottom surface of the semiconductor film is contained in a square area. The semiconductor device according to (1) is characterized in that:

[0015] (4) Alternatively, in one embodiment of the present invention, a center of the top surface of the gate electrode of the first transistor and a center of the top surface of the gate electrode of the second transistor are The centers of the upper surfaces of the gate electrodes of the first and second transistors overlap each other, and the gate electrodes of the second and third transistors are The center of the upper surface of the electrode and the center of the upper surface of the semiconductor film overlap each other. The semiconductor device is as described above.

[0016] (5) Alternatively, one embodiment of the present invention includes a capacitor, and the capacitor is The semiconductor device according to (1) is characterized in that the second transistor is located between the first and second transistors.

[0017] (6) Another embodiment of the present invention is a semiconductor device according to (1), a display device, a microwave a phone, a speaker, operation keys, a touch panel, or an antenna. It is an electronic device.

[0018] (7) Alternatively, one embodiment of the present invention is a semiconductor device including a first transistor and a first transistor provided on the first transistor. a second insulating film on the first insulating film; a second transistor on the second insulating film; a first conductive film electrically connected to the first transistor; and a second conductive film electrically connected to the transistor, the first conductive film penetrating the first insulating film. The second conductive film is a second insulating film, a first semiconductor film of the second transistor, and a second semiconductor film. The channel forming region of the first transistor is formed through the body film and the source electrode or the drain electrode. a channel formation region of the second transistor including a single-crystal semiconductor; and a channel formation region of the second transistor including an oxide semiconductor. The semiconductor device is characterized in that the width of the bottom surface of the second conductive film is 5 nm or less.

[0019] (8) Alternatively, in one aspect of the present invention, in claim 7, the first conductive film is a first transistor. The semiconductor device according to (7), characterized in that the semiconductor layer is in contact with the source region or the drain region of the capacitor. be.

[0020] (9) Alternatively, one aspect of the present invention is a semiconductor device according to claim 7, further comprising: a second semiconductor film, a source electrode, and and a third semiconductor film on the drain electrode, and the electron affinity of the second semiconductor film is The electron affinity of the first semiconductor film is larger than that of the second semiconductor film and the electron affinity of the third semiconductor film (7 ) is a semiconductor device according to the present invention.

[0021] (10) Alternatively, one embodiment of the present invention is a structure including first to fourth isosceles triangles and a square. The vertices of the inverted square pyramid, in which the vertex angles of the first to fourth isosceles triangles are 120° or less, are determined as the first When the center of the top surface of the gate electrode of the transistor is taken as the center, the bottom surface of the first semiconductor film is in a square area. The semiconductor device according to (7) is characterized in that it fits within the range.

[0022] (11) Alternatively, in one embodiment of the present invention, a center of the top surface of the gate electrode of the first transistor and a The centers of the upper surfaces of the gate electrodes of the second transistor overlap each other, and the gate electrode of the first transistor The center of the upper surface of the gate electrode and the center of the upper surface of the first semiconductor film are aligned with each other. The semiconductor device according to (10) above.

[0023] (12) Alternatively, one embodiment of the present invention includes a capacitor, and the capacitor includes a first transistor and the second transistor. .

[0024] (13) Another embodiment of the present invention is a semiconductor device according to (7), a display device, a microcomputer, or the like. The device has a phone, a speaker, operation keys, a touch panel, or an antenna. It is an electronic device that exhibits

[0025] (14) Another embodiment of the present invention is a first transistor having a channel made of a single crystal semiconductor. forming a first insulating film on the first transistor; and forming an oxide semiconductor on the first insulating film. a first conductive film on the oxide semiconductor film; and an inorganic film on the first conductive film. forming a first mask on the inorganic film; and processing the inorganic film using the first mask as a mask; A second mask is formed, and the first conductive film, the oxide semiconductor film, and the second conductive film are formed using the second mask as a mask. and forming an opening in the first insulating film, and depositing the first conductive film, the oxide semiconductor film, and the first insulating film in the opening. A second conductive film is formed to penetrate the insulating film, the first mask is a resist mask, and the first conductive film is The second conductive film and the oxide semiconductor film are included in the second transistor, and the second conductive film is included in the first transistor. and a method for manufacturing a semiconductor device, the method comprising: electrically connecting a first transistor and a second transistor to each other; is.

[0026] (15) Alternatively, in one aspect of the present invention, an organic resin film is formed between the inorganic film and the first mask. The method for manufacturing a semiconductor device according to (14) is characterized in that:

[0027] (16) Alternatively, one aspect of the present invention is characterized in that the method includes a step of polishing the second conductive film. The method for manufacturing a semiconductor device according to (14) above is also provided. [Effects of the Invention]

[0028] According to one aspect of the present invention, a semiconductor device suitable for miniaturization and high density can be provided. do.

[0029] Alternatively, it is possible to impart good electrical characteristics to the semiconductor device. It is possible to provide a semiconductor device with a high read speed. Alternatively, a semiconductor device with low power consumption can be provided. It is possible to provide a highly reliable semiconductor device. The description of these effects does not preclude the existence of other effects. It should be noted that one embodiment of the present invention does not necessarily have to have all of these effects. Effects other than these will become apparent from the description, drawings, claims, etc. It is possible to extract other effects from the description, drawings, claims, etc. It is Noh. [Brief explanation of the drawings]

[0030] [Figure 1] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to an embodiment; [Figure 2] 1A to 1C are diagrams illustrating an area occupied by a semiconductor device according to an embodiment; [Figure 3]FIG. 1 is a schematic diagram showing an example of an etching apparatus. [Figure 4] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 5] 1A to 1C are diagrams illustrating band structures according to an embodiment. [Figure 6] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 7] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 8] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 9] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 10] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 11] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 12] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 13] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 14] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 15] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 16] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 17] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 18] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 19] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 20] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 21] FIG. 1 is a circuit diagram according to an embodiment. [Figure 22] FIG. 22 is a diagram illustrating an example of a schematic cross-sectional view of the circuit diagram in FIG. 21. [Figure 23] FIG. 22 is a diagram illustrating an example of a schematic cross-sectional view of the circuit diagram in FIG. 21. [Figure 24]1 shows an example of the configuration of an RFID tag according to an embodiment. [Figure 25] 1 shows an example of the configuration of a CPU according to an embodiment. [Figure 26] FIG. 2 is a circuit diagram of a memory element according to an embodiment. [Figure 27] 1A and 1B are a top view and a circuit diagram of a display device according to an embodiment. [Figure 28] 1. An electronic device according to an embodiment. [Figure 29] 10 shows an example of how RFID is used according to an embodiment. [Figure 30] 1 is a cross-sectional STEM photograph of an example sample. [Figure 31] Cross-sectional STEM photograph of a comparative example sample. [Figure 32] Cross-sectional STEM image of a semiconductor device. [Figure 33] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 34] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 35] 10A and 10B illustrate structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 36] Electron diffraction pattern of CAAC-OS. [Figure 37] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 38] Schematic diagram illustrating the film formation model of CAAC-OS and nc-OS. [Figure 39] A diagram explaining InGaZnO4 crystals and pellets. [Figure 40] Schematic diagram illustrating a film formation model of CAAC-OS. DETAILED DESCRIPTION OF THE INVENTION

[0031] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiments, and various changes and modifications may be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention is based on the following embodiments. The present disclosure should not be construed as being limited to the contents of the preceding paragraph.

[0032] In the configuration of the invention described below, the same parts or parts having similar functions The same reference numerals are used in common between different drawings, and repeated explanations will be omitted. When referring to similar functions, the hatch pattern may be the same and no particular reference numeral may be given.

[0033] In each figure described in this specification, the size, layer thickness, or area of ​​each component is The figures may be exaggerated for clarity and are not necessarily limited to that scale. stomach.

[0034] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The number is not a numerical limitation.

[0035] A transistor is a type of semiconductor device that controls the amplification of current and voltage, and conduction or non-conduction. In this specification, the transistor can be , IGFET(Insulated Gate Field Effect Trans istor) and thin film transistor (TFT) ) is included.

[0036] In this specification, the term "electrode" can be replaced with "plug." In particular, to electrically connect the upper and lower wiring, a conductive film is embedded in the opening. The rollers are often called "plugs."

[0037] The words "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be replaced with "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0038] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case of -5° or more and 5° or less. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0039] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0040] (Embodiment 1) FIG. 1A shows an example of a top view of a semiconductor device. FIG. 1B shows a dot-chain structure shown in FIG. 1B is a cross-sectional view corresponding to the line A1-A2. As shown in FIG. 1B, the semiconductor device has a first transistor. The second transistor 100 is a first transistor 110. The first transistor 110 and the second transistor 111 are connected to each other. A barrier film 120 is provided between the stars 100 .

[0041] The first transistor 110 is provided on a semiconductor substrate 111. The semiconductor film 112, the gate insulating film 114, the gate electrode 115, and the source region The gate electrode 113 has a low resistance layer 113a and a low resistance layer 113b which function as a drain region.

[0042] The first transistor 110 may be either a p-channel type or an n-channel type. It is preferable to use a channel type. Alternatively, an appropriate transistor may be used depending on the circuit configuration and driving method. Just use the .

[0043] The region where the channel of the semiconductor film 112 is formed and the region nearby, the source region or the drain region In the low resistance layer 113a and the low resistance layer 113b which become the drain region, a silicon-based semiconductor It is preferable that the semiconductor material contains a semiconductor such as silicon dioxide, and it is preferable that the semiconductor material contains single crystal silicon. e (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), It may be formed of a material having a crystal structure such as GaAlAs (gallium aluminum arsenide). A silicon structure in which the effective mass is controlled by applying stress to the molecules and changing the lattice spacing. Alternatively, the first transistor 1 may be made of GaAs and AlGaAs. 10 is HEMT (High Electron Mobility Transistor) r) can also be used.

[0044] The low resistance layer 113a and the low resistance layer 113b are made of a semiconductor material applied to the semiconductor film 112. In addition, elements that impart n-type conductivity, such as arsenic and phosphorus, or p-type conductivity, such as boron, are added. Contains elements that impart

[0045] The gate electrode 115 is made of an element such as arsenic or phosphorus that provides n-type conductivity, or a p-type Semiconductor materials such as silicon, metal materials, and alloy materials that contain elements such as boron that provide conductivity Conductive materials such as metal oxide materials can be used. It is preferable to use a high melting point material such as tungsten or molybdenum, which has a high melting point. It is preferable to use stainless steel.

[0046] Here, a transistor 160 as shown in FIG. 4 is used in place of the first transistor 110. A cross section of the transistor 160 in the channel length direction is shown on the left side of the dashed line in FIG. The cross section in the channel width direction is shown on the right side of the dashed line. The semiconductor film 112 (part of the semiconductor substrate) on which the panel is formed has a convex shape, and the side and top A gate insulating film 114, a gate electrode 115a, and a gate electrode 115b are provided along the surface. The gate electrode 115a may be made of a material that adjusts the work function. The transistor 160 is a FIN type transistor because it utilizes a protruding portion of a semiconductor substrate. It is also called a mask that comes into contact with the top of the convex portion and functions as a mask for forming the convex portion. The semiconductor substrate may have an insulating film. However, the SOI substrate may be processed to form a semiconductor film having a convex shape.

[0047] The first transistor 110 is covered with an insulating film 121, an insulating film 122, an insulating film 123, and Insulating films 124 are provided in layers in order.

[0048] When the semiconductor film 112 is made of a silicon-based semiconductor material, the insulating film 122 contains hydrogen. It is preferable that the insulating film 122 containing hydrogen is provided over the first transistor 110 and heat treatment is performed. By this, dangling bonds in the semiconductor film 112 are terminated by hydrogen in the insulating film 122. As a result, the reliability of the first transistor 110 can be improved.

[0049] The insulating film 123 is formed by a step caused by the first transistor 110 and the like provided in the layer below it. The upper surface of the insulating film 123 functions as a planarizing film that flattens the difference. Chemical Mechanical Polishing (CMP) The surface may be planarized by a planarization process using a method such as the .

[0050] The insulating film 124 may function as a barrier film. It is not necessary to provide such a system.

[0051] The insulating films 121, 122, 123, and 124 are provided with the low resistance layer 113. a, plugs 161 and 163 electrically connected to the low resistance layer 113b are embedded, A plug 162 electrically connected to the gate electrode 115 of the first transistor 110 is filled in. In this specification and the like, the electrodes and the wiring electrically connected to the electrodes are the same. That is, a part of the wiring may function as an electrode, or a part of the electrode may function as an electrode. It may also function as wiring.

[0052] An electrode 136 is provided on the upper portion of the insulating film 124 and on the upper portion of the plug 162. 136 is electrically connected to a plug 162 .

[0053] The materials of the plugs (plugs 161 to 163) and the electrodes 136 are metal materials. Conductive materials such as alloys, metal oxides, or the like can be used. High-melting-point materials such as tungsten, molybdenum, titanium, and titanium nitride are used, which are also conductive. It is preferable to use tungsten, and it is particularly preferable to use tungsten. It is also possible to use a multi-layer film of two or more metals. For example, A two-layer structure using tungsten may also be used.

[0054] The electrode 136 is embedded in the insulating film 125. The surface is preferably flattened.

[0055] The barrier film 120 is provided to cover the upper surface of the insulating film 125 .

[0056] The barrier film 120 also has openings in which plugs 164 and 166 (to be described later) are embedded. It has a department.

[0057] An insulating film 126 is provided on the barrier film 120. The insulating film 126 is partially It is preferable to use an oxide material from which oxygen is released.

[0058] As an oxide material that releases oxygen by heating, it is possible to The oxide insulating film containing oxygen has a TDS (Thermal Desorption Spectroscopy) In the NMR spectroscopy analysis, the amount of oxygen released was 1.0 x 1018 in terms of oxygen atoms. atoms / cm3 or more, preferably 3.0×1020 atoms / cm3 or more The substrate temperature during the TDS analysis was 100°C or higher and 70°C or lower. A temperature of 0°C or lower, or a temperature in the range of 100°C to 500°C is preferred.

[0059] For example, such a material may include silicon oxide or silicon oxynitride. Alternatively, a metal oxide can also be used. Silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen. Silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0060] The second transistor 100 is provided on the insulating film 126 .

[0061] The second transistor 100 has an oxide semiconductor film 101a in contact with the top surface of the insulating film 126 and a , an oxide semiconductor film 101b in contact with the upper surface of the oxide semiconductor film 101a, and an oxide semiconductor film 101b The electrode 103a and the electrode 103b are in contact with the top surface of the oxide semiconductor film 101b and are spaced apart from each other in a region overlapping with the oxide semiconductor film 101b. The electrode 103b, the top surface of the oxide semiconductor film 101b, the top surface of the electrode 103a, and the electrode 103 an oxide semiconductor film 101c in contact with the top surface of b; and a gate insulating film on the oxide semiconductor film 101c. 104, and the oxide semiconductor film 101c via the gate insulating film 104 and the oxide semiconductor film 101c. 1b and a gate electrode 105 that overlaps the second transistor 100. An insulating film 107, an insulating film 108, and an insulating film 127 are provided.

[0062] The plug 161 and the plug 164 electrically connected to the electrode 103a are formed on the insulating film 125. , a barrier film 120, an insulating film 126, an oxide semiconductor film 101a, an oxide semiconductor film 101b, and is provided so as to be embedded in the electrode 103a.

[0063] In addition, the oxide semiconductor film 131a and the oxide semiconductor film 131b are formed simultaneously with the second transistor 100. 131b and an electrode 103c are formed, and are electrically connected to the plug 163 and the electrode 103c. The plug 166 is formed by insulating film 125, barrier film 120, insulating film 126, and oxide semiconductor film 131. a) and the oxide semiconductor film 131b, and the electrode 103c.

[0064] At least a part (or all) of the electrode 103a (and / or electrode 103b) ) is a semiconductor such as the oxide semiconductor film 101b (and / or the oxide semiconductor film 101a). The membrane is provided on at least a part (or all) of the surface, side, upper surface, and / or lower surface. It is being done.

[0065] Alternatively, at least a part (or all) of the electrode 103a (and / or the electrode 103b) The oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) is a semiconductor film. It is in contact with at least a part (or all) of the surface, side, upper surface, and / or lower surface of the body membrane. Or, at least a part of the electrode 103a (and / or the electrode 103b) (or all of) the oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) The semiconductor film is in contact with at least a part (or all) of the semiconductor film.

[0066] Alternatively, at least a part (or all) of the electrode 103a (and / or the electrode 103b) The oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) is a semiconductor film. At least a part (or all) of the surface, side, upper surface, and / or lower surface of the body membrane and Alternatively, at least one of the electrodes 103a (and / or 103b) is electrically connected. At least a part (or all) of the oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) and a part (or the whole) of the semiconductor film.

[0067] Alternatively, at least a part (or all) of the electrode 103a (and / or the electrode 103b) The oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) is a semiconductor film. Near at least a portion (or all) of the surface, side, upper surface, and / or lower surface of the body membrane Alternatively, at least one of the electrodes 103a (and / or 103b) is arranged in contact with the other. At least a part (or all) of the oxide semiconductor film 101b (and / or the oxide semiconductor film 101a)).

[0068] Alternatively, at least a part (or all) of the electrode 103a (and / or the electrode 103b) The oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) is a semiconductor film. Lateral surfaces of at least part (or all) of the surface, side, upper and / or lower surfaces of the body membrane Alternatively, at least one of the electrodes 103a (and / or 103b) is disposed A part (or all) of the oxide semiconductor film 101b (and / or the oxide semiconductor film 10 1a) is disposed on the side of part (or all) of the semiconductor film.

[0069] Alternatively, at least a part (or all) of the electrode 103a (and / or the electrode 103b) The oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) is a semiconductor film. Oblique movement of at least part (or all) of the surface, side, upper and / or lower surface of the body membrane Alternatively, at least one of the electrodes 103a (and / or 103b) is At least a part (or all) of the oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) and the like.

[0070] Alternatively, at least a part (or all) of the electrode 103a (and / or the electrode 103b) The oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) is a semiconductor film. On at least part (or all) of the surface, side, upper surface, and / or lower surface of the body membrane Alternatively, at least one of the electrodes 103a (and / or 103b) is disposed A part (or all) of the oxide semiconductor film 101b (and / or the oxide semiconductor film 10 1a) is disposed on the upper side of a part (or the whole) of a semiconductor film.

[0071] For example, the oxide semiconductor may contain at least indium (In) or zinc (Zn It is preferable that the oxide contains In-M-Zn (wherein M is Al, Ti, Metals such as Ga, Ge, Y, Zr, Sn, La, Ce or Hf) nothing.

[0072] In particular, the semiconductor film has a plurality of crystal portions, and the c-axis of the crystal portions is aligned with the surface on which the semiconductor film is formed. Or, the crystals are oriented perpendicular to the upper surface of the semiconductor film and do not have grain boundaries between adjacent crystal portions. An oxide semiconductor film is preferably used.

[0073] By using such materials as semiconductor films, fluctuations in electrical characteristics are suppressed, and reliability is improved. High-performance transistors can be realized.

[0074] Note that preferred forms of oxide semiconductors that can be used for semiconductor films and their formation methods are as follows: This will be explained in detail in a later embodiment.

[0075] A semiconductor device according to one embodiment of the present invention includes an oxide semiconductor film and an insulating film overlapping the oxide semiconductor film. At least one metal element among metal elements constituting the oxide semiconductor film is a constituent element between the It is preferable that the first oxide semiconductor film contains the oxide semiconductor as an element. and an insulating film overlapping the oxide semiconductor film. It is possible.

[0076] That is, one embodiment of the present invention is a method for forming a semiconductor film by forming a semiconductor layer on at least a channel formation region of the oxide semiconductor film. The top and bottom surfaces of the oxide semiconductor film are formed of an oxide material which functions as a barrier film for preventing the formation of interface states in the oxide semiconductor film. It is preferable that the oxide semiconductor film is in contact with the oxide semiconductor film. The formation of oxygen vacancies and the incorporation of impurities, which are factors that cause carrier generation in the conductor film and at the interface, are prevented. Since the amount of the oxide semiconductor film can be suppressed, the oxide semiconductor film can be highly purified and made intrinsic. The term "to make the oxide semiconductor film intrinsic" means to make the oxide semiconductor film intrinsic or substantially intrinsic. A highly reliable semiconductor device is obtained by suppressing fluctuations in the electrical characteristics of a transistor including the oxide semiconductor film. It will be possible to provide a place for

[0077] Note that in this specification and the like, when the term "substantially intrinsic" is used, the carrier density of the oxide semiconductor film is , 1×10 17 / cm 3 Less than 1×10 15 / cm 3 Less than or equal to 1 x 10 13 / cm 3 By making the oxide semiconductor film highly purified and intrinsic, the transistor has stable electrical characteristics. Sex can be assigned.

[0078] The oxide semiconductor film 101a is provided between the insulating film 126 and the oxide semiconductor film 101b. are.

[0079] The oxide semiconductor film 101c is provided between the oxide semiconductor film 101b and the gate insulating film 104. More specifically, the oxide semiconductor film 101c has a bottom surface that is in contact with the electrode 103a and the The gate insulating film 104 is provided in contact with the upper surface of the electrode 103b and the lower surface of the gate insulating film 104. are.

[0080] The oxide semiconductor film 101a and the oxide semiconductor film 101c are the oxide semiconductor film 10 It includes oxides containing one or more of the same metal elements as 1b.

[0081] Note that the boundary between the oxide semiconductor film 101b and the oxide semiconductor film 101a and the oxide semiconductor film The boundary between the oxide semiconductor film 101b and the oxide semiconductor film 101c may be unclear.

[0082] For example, the oxide semiconductor film 101a and the oxide semiconductor film 101c may contain In or Ga. Representative examples include In-Ga oxides, In-Zn oxides, and In-M-Zn oxides. (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf) and oxide A material whose conduction band lower end energy is closer to the vacuum level than the semiconductor film 101b is used. Specifically, the energy minimum of the conduction band of the oxide semiconductor film 101a and the oxide semiconductor film 101c is and the energy difference between the bottom of the conduction band of the oxide semiconductor film 101b and the bottom of the conduction band of the oxide semiconductor film 101b is 0.05 eV or more. , 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 e It is preferable that the electron transport energy is 0.5 eV or less, 0.5 eV or less, or 0.4 eV or less.

[0083] The oxide semiconductor film 101a and the oxide semiconductor film 101b are provided so as to sandwich the oxide semiconductor film 101a and the oxide semiconductor film 101b. The conductive film 101c contains Ga, which functions as a stabilizer compared to the oxide semiconductor film 101b. By using an oxide with a high content, release of oxygen from the oxide semiconductor film 101b is suppressed. It can be controlled.

[0084] The oxide semiconductor film 101b may have a composition of In:Ga:Zn=1:1:1, 4:2:4, for example. When using In-Ga-Zn oxides with an atomic ratio of 1 or 3:1:2, oxide semiconductors The oxide semiconductor film 101a or the oxide semiconductor film 101c may be, for example, In:Ga:Zn=1:3: 2, 1:3:4, 1:3:6, 1:6:4, 1:6:8, 1:6:10, or 1:9: In-Ga-Zn oxides with atomic ratios of 6 or more can be used. The atomic ratios of the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the oxide semiconductor film 101c are The error includes a variation of ±20% of the atomic ratio above. The oxide semiconductor film 101a and the oxide semiconductor film 101c may be made of materials having the same composition or different compositions. Materials of the following composition may also be used.

[0085] In addition, when an In-M-Zn-based oxide is used as the oxide semiconductor film 101b, the oxide semiconductor The target used to form the semiconductor film that becomes the conductor film 101b is When the atomic ratio of the metal elements is In:M:Zn=x1:y1:z1, x1 / y The value of 1 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less. It is preferable to use an oxide having an atomic ratio of 1 to 6. By setting / y1 to 6 or less, a CAAC-OS film, which will be described later, is easily formed. Typical examples of atomic ratios of metal elements in a ZnO alloy are In:M:Zn=1:1:1, 4:2:4 Examples include .1, 3:1:2, etc.

[0086] The oxide semiconductor film 101a and the oxide semiconductor film 101c are made of In-M-Zn oxide. When a material is used, the oxide semiconductor film 101a and the oxide semiconductor film 101c are formed by the oxide semiconductor. The target used for forming the film has an atomic ratio of the metal elements contained in the target. When In:M:Zn=x2:y2:z2, x2 / y2 <x1 / y1であり、z2 The value of / y2 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less, and an oxide having an atomic ratio is used. By setting z2 / y2 to 6 or less, a CAAC-OS film as described below can be formed. A typical example of the atomic ratio of the target metal elements is In:M:Zn. =1:3:4, 1:3:6, 1:3:8, 1:2:4, etc.

[0087] In addition, the oxide semiconductor film 101a and the oxide semiconductor film 101c are By using a material whose conduction band lower edge energy is closer to the vacuum level than b, A channel is mainly formed in the semiconductor film 101b, and the oxide semiconductor film 101b is the main current path. In this way, the oxide semiconductor film 101b in which the channel is formed is made of the same metal element. By sandwiching the oxide semiconductor film 101a containing the compound and the oxide semiconductor film 101c, The generation of interface states from these is suppressed, and the reliability of the electrical characteristics of the transistor is improved.

[0088] However, the present invention is not limited to these, and may be applied to any semiconductor material having the required semiconductor properties and electrical properties (field-effect mobility). It is sufficient to use an appropriate atomic ratio depending on the required properties (e.g., the degree of diffusion, threshold voltage, etc.). In order to obtain semiconductor characteristics of a transistor, the oxide semiconductor film 101a and the oxide semiconductor film 10 The carrier density, impurity concentration, defect density, metal element and oxide density of the oxide semiconductor film 101b and the oxide semiconductor film 101c are It is preferable to make the atomic ratio, interatomic distance, density, etc. of the elements appropriate.

[0089] Here, an oxide semiconductor is provided between the oxide semiconductor film 101a and the oxide semiconductor film 101b. In some cases, the oxide semiconductor film 101a and the oxide semiconductor film 101b are mixed. Between the conductive film 101b and the oxide semiconductor film 101c, there is a layer of the oxide semiconductor film 101b and the oxide semiconductor film 101c. The mixed region may have a low interface state density. Therefore, the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the oxide semiconductor film 101c are In the O1c laminate, the energy changes continuously near each interface (continuous (also called a junction.) This results in a band structure.

[0090] Here, the band structure will be explained. For ease of understanding, the band structure is shown as an insulating film 1 25, the oxide semiconductor film 101a, the oxide semiconductor film 101b, the oxide semiconductor film 101c, and The energy (Ec) of the bottom of the conduction band of the gate insulating film 104 is shown.

[0091] As shown in FIGS. 5A and 5B, the oxide semiconductor film 101a and the oxide semiconductor film 10 1b, in the oxide semiconductor film 101c, the energy of the bottom of the conduction band changes continuously. This is because the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the oxide semiconductor film 101c This can also be understood from the fact that oxygen easily diffuses between the two materials due to the common constituent elements. Therefore, the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the oxide semiconductor film 101c Although it is a laminate of layers with different compositions, it can also be said to be physically continuous.

[0092] The oxide semiconductor film, which is stacked with a common main component, is not simply stacked, but is continuously Junction (here, specifically, a U-shaped well where the energy of the bottom of the conduction band changes continuously between layers) In other words, trap centers and recombination centers are formed at the interfaces of each layer. The layered structure is formed so that there are no impurities that would create defect levels like this. If impurities are present between the layers of a laminated multilayer film, the continuity of the energy band is lost. At the interface, carriers are trapped or disappear due to recombination.

[0093] Note that in FIG. 5A, the oxide semiconductor film 101a and the oxide semiconductor film 101c have the same Ec. However, they may be different from each other. For example, an oxide semiconductor When the Ec of the oxide semiconductor film 101c is higher than that of the oxide semiconductor film 101a, the band A portion of the structure is shown in Figure 5(B).

[0094] As shown in FIGS. 5A and 5B, the oxide semiconductor film 101b serves as a well, and the second In the transistor 100, a channel is formed in the oxide semiconductor film 101b. It is understood that the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the oxide semiconductor film 10 1c is a U-shaped well (U Shape well) because the energy of the conduction band edge changes continuously. The channel formed in this configuration can be called a buried well. It can also be called an embedded channel.

[0095] Note that the oxide semiconductor film 101a and the oxide semiconductor film 101c are not formed on a silicon oxide film or the like. Trap levels due to impurities or defects can be formed near the interface with the insulating film. The presence of the semiconductor film 101a and the oxide semiconductor film 101c allows the oxide semiconductor film 101 However, the oxide semiconductor film 101a or b can be separated from the trap states. The energy difference between Ec of the oxide semiconductor film 101c and Ec of the oxide semiconductor film 101b is When the capacitance is small, electrons in the oxide semiconductor film 101b are transferred to the oxide semiconductor film 101a or the oxide semiconductor film 101b. Electrons in the film 101c may exceed the energy difference and reach the trap level. When electrons are trapped in the gate level, a negative fixed charge is generated at the interface of the insulating film, and the transistor The threshold voltage of the capacitor is shifted in the positive direction.

[0096] Therefore, in order to reduce the fluctuation in the threshold voltage of the transistor, the oxide semiconductor film 10 The energy between the oxide semiconductor film 101a and the oxide semiconductor film 101c and the oxide semiconductor film 101b is It is necessary to provide a difference between the respective energies. The difference between the respective energies is preferably 0.1 eV or more. It is preferable that the electron energy is 0.15 eV or more.

[0097] Note that the oxide semiconductor films 101a, 101b, and 101c It is preferable that the crystal portion is included. In particular, by using crystals oriented along the c-axis, the transistor This allows the starter to have stable electrical characteristics.

[0098] In addition, in the band structure shown in FIG. 5B, the oxide semiconductor film 101c is not provided. An In-Ga oxide (for example, a GaAs oxide) is formed between the oxide semiconductor film 101b and the gate insulating film 104. The atomic ratio of In:Ga may be 7:93.

[0099] The oxide semiconductor film 101b is thicker than the oxide semiconductor film 101a and the oxide semiconductor film 101c. For example, an oxide having a high electron affinity is used as the oxide semiconductor film 101b. The electron affinity is 0.07 eV or more higher than that of the semiconductor film 101a and the oxide semiconductor film 101c. 3 eV or less, preferably 0.1 eV to 0.7 eV, and more preferably 0.15 eV The electron affinity is determined by the relationship between the vacuum level and the bottom of the conduction band. is the difference in energy between

[0100] Here, the thickness of the oxide semiconductor film 101b is at least greater than that of the oxide semiconductor film 101a. The thicker the oxide semiconductor film 101b, the faster the on-state of the transistor. In addition, the oxide semiconductor film 101a can be formed by the oxide semiconductor film 101b. The thickness is sufficient as long as it does not lose the effect of suppressing the generation of interface states. The thickness of the semiconductor film 101b is more than one time the thickness of the oxide semiconductor film 101a. , preferably 2 times or more, more preferably 4 times or more, and even more preferably 6 times or more. However, this does not apply when it is not necessary to increase the on-state current of the transistor. The thickness of the semiconductor film 101a may be equal to or greater than the thickness of the oxide semiconductor film 101b.

[0101] In addition, the oxide semiconductor film 101c is also formed by the same method as the oxide semiconductor film 101a. It is sufficient if the thickness is such that the effect of suppressing the generation of interface states of O1b is not lost. For example, The thickness of the oxide semiconductor film 101a may be equal to or less than that of the oxide semiconductor film 101b. If 1c is thick, the electric field from the gate electrode may not easily reach the oxide semiconductor film 101b. Therefore, it is preferable that the oxide semiconductor film 101c be formed thin. It is only necessary that the thickness of the oxide semiconductor film 101b is thinner than that of the oxide semiconductor film 101b. The thickness of 1c is determined in consideration of the withstand voltage of the gate insulating film 104 and in response to the voltage for driving the transistor. It can be set appropriately according to the situation.

[0102] Here, for example, if the oxide semiconductor film 101b is an insulating film having a different constituent element (for example, an oxide semiconductor film), When the material comes into contact with an insulating film containing silicon, an interface state is formed at the interface. The level may form a channel. In such a case, a second transistor with a different threshold voltage is formed. The transistor appears and the apparent threshold voltage of the transistor may change. However, in the transistor having this structure, the metal constituting the oxide semiconductor film 101b Since the oxide semiconductor film 101a contains one or more elements, the oxide semiconductor film 101 Therefore, the interface state is less likely to be formed at the interface between the oxide semiconductor film 101a and the oxide semiconductor film 101b. By providing the dielectric film 101a, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced. This can reduce noise and fluctuations.

[0103] In addition, a channel is formed at the interface between the gate insulating film 104 and the oxide semiconductor film 101b. In this case, interfacial scattering may occur at the interface, resulting in a decrease in the field-effect mobility of the transistor. However, in the transistor having this structure, the oxide semiconductor film 101b Since the oxide semiconductor film 101c contains one or more metal elements, the oxide semiconductor film 1 At the interface between the oxide semiconductor film 101b and the oxide semiconductor film 101c, carrier scattering is unlikely to occur. The field effect mobility of the GaN layer can be increased.

[0104] One of the electrodes 103a and 103b functions as a source electrode, and the other functions as a drain electrode. It functions as a pole.

[0105] The electrodes 103a and 103b are made of aluminum, titanium, chromium, nickel, copper, or iron. Monolithic alloys consisting of tritium, zirconium, molybdenum, silver, tantalum, or tungsten The metal or alloy containing it as the main component is used as a single layer structure or a laminated structure. , a single layer structure of aluminum film containing silicon, and a two-layer structure of aluminum film stacked on titanium film. Layer structure, two-layer structure with aluminum film laminated on tungsten film, copper-magnesium-aluminum Two-layer structure with copper film laminated on aluminum alloy film, two-layer structure with copper film laminated on titanium film, Two-layer structure with copper film laminated on tungsten film, titanium film or titanium nitride film and its titanium An aluminum film or a copper film is laminated on the silicon film or titanium nitride film, and then an aluminum film or a copper film is laminated on top of that. Three-layer structure forming titanium film or titanium nitride film, molybdenum film or molybdenum nitride film Then, an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film. There are three-layer structures, such as a layer of silicon dioxide and a molybdenum film or molybdenum nitride film formed on top of that. It is to be noted that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0106] The gate insulating film 104 is made of, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. , aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, zirconium titanate Lead Zirconate (PZT), Strontium Titanate (SrTiO3) or (Ba,Sr)T The insulating film containing high-k material such as iO3 (BST) is used as a single layer or a laminate. Alternatively, these insulating films may be coated with, for example, aluminum oxide, bismuth oxide, or oxide. Germanium, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, tungsten oxide Alternatively, these insulating films may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride is laminated on the insulating film. That's fine.

[0107] The gate insulating film 104 is made of an acid having a stoichiometric composition, similar to the insulating film 126. It is preferable to use an oxide insulating film containing more oxygen than silicon.

[0108] In addition, when a specific material is used for the gate insulating film, electrons are captured in the gate insulating film under specific conditions. For example, silicon oxide and hafnium oxide can be used to increase the threshold voltage. Like the stacked film of hafnium, a part of the gate insulating film is made of hafnium oxide, aluminum oxide, and oxide. By using a material with many electron capture levels, such as tantalum, and by using it at a higher temperature (the operating temperature of the semiconductor device), Or higher than the storage temperature, or 125°C or higher and 450°C or lower, typically 1 Under the temperature range of 50°C to 300°C, the potential of the gate electrode is set to the potential of the source electrode and drain electrode. By maintaining a higher state for at least one second, typically at least one minute, the gate voltage is released from the semiconductor film. Electrons move towards the poles, and some of them are captured by the electron capture levels.

[0109] In this way, a transistor that has captured the necessary number of electrons in the electron capture level has a threshold voltage The amount of electrons captured is controlled by controlling the voltage of the gate electrode. This allows the threshold voltage to be controlled. The process for adding the conductive layer may be performed during the manufacturing process of the transistor.

[0110] For example, after forming wiring that connects to the source electrode or drain electrode of a transistor, Or, after the end of the pre-process (wafer processing) or after the wafer dicing process, It is advisable to do this at some stage before shipping, such as after the cage. It is preferable not to expose to temperatures above 25°C for more than 1 hour.

[0111] The gate electrode 105 is made of, for example, aluminum, chromium, copper, tantalum, titanium, or molybdenum. a metal selected from the group consisting of tungsten, tungsten, or an alloy containing the above-mentioned metals, or It can be formed by using an alloy of metals. In addition, impurity elements such as phosphorus may be used. Semiconductors such as polycrystalline silicon doped with silicon, and silicides such as nickel silicide For example, a two-layer structure in which a titanium film is laminated on an aluminum film, a titanium nitride film, etc. Two-layer structure with titanium film stacked on titanium film, two-layer structure with tungsten film stacked on titanium nitride film Two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film The structure is a titanium film, an aluminum film is laminated on the titanium film, and a titanium film is laminated on top of that. There are also three-layer structures that can be formed using aluminum, titanium, tantalum, tungsten, A combination of one or more metals selected from molybdenum, chromium, neodymium, and scandium Alternatively, an alloy film made of these metals or a nitride film thereof may be used.

[0112] The gate electrode 105 is made of indium tin oxide, indium containing tungsten oxide, or the like. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide A light-transmitting conductive material such as indium tin oxide may also be used. Alternatively, the light-transmitting conductive material and the metal may be laminated together.

[0113] A plug 167 electrically connected to the plug 164 is formed on the insulating film 127, the insulating film 108, The insulating film 107 is embedded therein. The insulating film 107 is electrically connected to the gate electrode 105. The plug 168 is set so as to be embedded in the insulating film 127, the insulating film 108, and the insulating film 107. In addition, a plug 169 electrically connected to the plug 166 is formed on the insulating film 127. 108 is provided so as to be embedded in the insulating film 107.

[0114] In addition, an In-Ga-Zn-based oxynitride semiconductor is formed between the gate electrode 105 and the gate insulating film 104. Conductor film, In-Sn oxynitride semiconductor film, In-Ga oxynitride semiconductor film, In-Zn Oxynitride semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (I These films may have a resistivity of 5 eV or more, preferably 5.5 eV or more. Since the work function is higher than the electron affinity of the oxide semiconductor, The threshold voltage of the transistor using the material can be shifted to the positive side, For example, an In-Ga-Zn oxynitride semiconductor can be used. When a dielectric film is used, the nitrogen concentration is at least higher than that of the oxide semiconductor film 101b, specifically, 7 An In-Ga-Zn based oxynitride semiconductor film with an atomic percentage of 0.1 or more is used.

[0115] The insulating film 107 may be made of a material that is difficult for water and hydrogen to permeate, similar to the barrier film 120. It is particularly preferable to use a material that is less permeable to oxygen for the insulating film 107. It's nice.

[0116] By covering the oxide semiconductor film 101b with the insulating film 107 containing a material that is difficult for oxygen to permeate, The oxide semiconductor film 101b is prevented from releasing oxygen above the insulating film 107. Furthermore, oxygen desorbed from the insulating film 126 can be trapped below the insulating film 107. Therefore, the amount of oxygen that can be supplied to the oxide semiconductor film 101b can be increased. This can be done.

[0117] In addition, the insulating film 107, which is impermeable to water and hydrogen, prevents the oxide semiconductor from being exposed to the outside. The inclusion of impurities such as water and hydrogen can be suppressed, and the electrical characteristics of the second transistor 100 can be improved. This suppresses fluctuations in the resistance, thereby achieving a highly reliable transistor.

[0118] Note that, similar to the insulating film 126, a film from which oxygen is desorbed by heating is formed below the insulating film 107. The insulating film is provided, and oxygen is also supplied from above the oxide semiconductor film 101b through the gate insulating film 104. It may be configured to supply the

[0119] Here, a semiconductor device including the first transistor 110 and the second transistor 100 The occupied area will be explained with reference to FIG.

[0120] FIG. 2A shows the first transistor 110 and the second transistor 10 in FIG. 1B. This is a cross-sectional view including the part 0. In the semiconductor device shown in FIG. 1, a first transistor 110 and a second transistor 100 are stacked. In particular, the gate electrode 115 of the first transistor 110 and the gate electrode 116 of the second transistor 111 are preferably It is preferable that the gate electrodes 105 of the transistors 110 overlap each other.

[0121] 2A is a point O on the top surface of the gate electrode 115 of the first transistor 110. When the long side of the bottom surface of the oxide semiconductor film 101a is set to fit within the center and the line segment B1-B2, The angle B1-O-B2 of the triangle B1-O-B2 shown in FIG. 2(A) is preferably 120° or less. It is preferable that the angle be 90° or less, and more preferably 60°. The smaller the size, the smaller the area occupied by the semiconductor device can be.

[0122] Also, Figure 2(B) shows an inverted square pyramid (hereinafter referred to as an inverted square pyramid). The first to fourth isosceles triangles and a square are included. The center of the top surface of the gate electrode 115 of the transistor 110 and the bottom surface of the oxide semiconductor film 101a are positive. The inverted pyramid fits within a rectangular area and has an isosceles triangle with a vertex angle of 120° or less. It is preferable that the transistor 100 is accommodated in the isosceles triangle, and the apex angle of the isosceles triangle is 90° or less. It is more preferable that the apex angle of the isosceles triangle is 60° or less. The smaller the apex angle of the equilateral triangle, the more the area occupied by the semiconductor device can be reduced.

[0123] Also, Figure 2(C) shows an inverted right circular cone (hereafter referred to as an inverted right circular cone). The surface of the inverted right circular cone that passes through the apex of the inverted right circular cone and the center of the circle has an isosceles triangle. The apex of the equilateral triangle is the center of the top surface of the gate electrode 115 of the first transistor 110, and the oxide The bottom surface of the semiconductor film 101a is contained within a circular area, and the apex angle of the isosceles triangle is 120° or less. It is preferable that the second transistor 100 is contained in an inverted right circular cone, and the apex angle of the isosceles triangle is 9. It is more preferable that the apex angle of the isosceles triangle is 0° or less, and it is even more preferable that the apex angle of the isosceles triangle is 60° or less. The smaller the apex angle of the isosceles triangle, the smaller the area occupied by the semiconductor device. .

[0124] In addition, a structural example of a transistor applicable to the second transistor 100 is shown. 6(A) is a schematic top view of the transistor exemplified below, and Figs. 6(B) and 6(C) are These are schematic cross-sectional views taken along the cutting lines A1-A2 and B1-B2 in Figure 6(A), respectively. Note that Figure 6(B) corresponds to a cross section of the transistor in the channel length direction, and Figure 6(C) This corresponds to a cross section in the channel width direction of a transistor.

[0125] As shown in FIG. 6C, in the cross section of the transistor in the channel width direction, the gate electrode are provided facing the top surface and side surface of the oxide semiconductor film 101b, The channel is formed not only near the top surface of 01b but also near the side surface, and the effective channel width is This increases the current in the on-state (on-state current), making it possible to increase the current in the on-state (on-state current). The width of the film 101b is extremely small (for example, 50 nm or less, preferably 30 nm or less, more preferably In the case where the thickness is preferably 20 nm or less, a channel is formed inside the oxide semiconductor film 101b. Since the area covered by the gate electrode is wider, the contribution to the on-current increases as the gate electrode becomes smaller.

[0126] As shown in FIGS. 7A, 7B, and 7C, the width of the gate electrode 105 is narrowed. In that case, for example, the electrodes 103a and 103b and the gate electrode 105 argon, hydrogen, phosphorus, boron, or the like is applied to the oxide semiconductor film 101b or the like using the above as a mask. As a result, in the oxide semiconductor film 101b and the like, A low resistance region 109a and a low resistance region 109b can be provided. The low resistance region 109a and the low resistance region 109b may not necessarily be provided. In this drawing, the width of the gate electrode 105 can also be narrowed.

[0127] The transistors shown in FIGS. 8(A) and 8(B) have the following characteristics compared to the transistor shown in FIG. The oxide semiconductor film 101c is provided in contact with the lower surfaces of the electrodes 103a and 103b. The main difference is that

[0128] With this structure, the oxide semiconductor film 101a, the oxide semiconductor film 101b, and When each film constituting the oxide semiconductor film 101c is formed, the film is not exposed to the air. Since the films can be formed continuously without any gaps, defects at each interface can be reduced.

[0129] In the above description, the oxide semiconductor film 101a and the oxide semiconductor film 101b are in contact with each other. Although the structure in which the semiconductor film 101c is provided has been described, the oxide semiconductor film 101a or the oxide semiconductor film 101b may be used. One or both of the membranes 101c may be omitted.

[0130] In addition, in FIG. 8, the width of the gate electrode 105 can be narrowed in the same manner as in FIG. Examples of this case are shown in Figures 9(A) and 9(B). In addition to Figures 6 and 8, other In the drawing, the width of the gate electrode 105 can also be narrowed.

[0131] 10(A) and 10(B), the oxide semiconductor film 101b and the electrode 103 and between the oxide semiconductor film 101b and the electrode 103b. It can be structured so as to be in contact with 47b.

[0132] The layers 147a and 147b may be made of, for example, a transparent conductor, an oxide semiconductor, or a nitride semiconductor. The layer 147a and the layer 147b may be made of, for example, a conductor or an oxynitride semiconductor. A layer containing indium, tin and oxygen, a layer containing indium and zinc, a layer containing indium, tin and oxygen, a layer containing tin and zinc, a layer containing tin and zinc, and a layer containing zinc and gallium , a layer containing zinc and aluminum, a layer containing zinc and fluorine, a layer containing zinc and boron a layer containing tin and antimony, a layer containing tin and fluorine, or a layer containing titanium and nickel Alternatively, a layer containing hydrogen, carbon, nitrogen, silicon, or the like may be used. It may also contain germanium or argon.

[0133] The layers 147a and 147b may have a property of transmitting visible light. The layers 147a and 147b do not reflect or reflect visible light, ultraviolet light, infrared light, or X-rays. It is acceptable for the light source to have the property of blocking transmission by absorbing the light. This may make it possible to suppress fluctuations in the electrical characteristics of the transistor due to stray light.

[0134] The layers 147a and 147b are not short-circuited with the oxide semiconductor film 101b and the like. It may be preferable to use a layer that does not form a key barrier. The on-state characteristics can be improved.

[0135] The layers 147a and 147b have a higher resistance than the electrodes 103a and 103b. In some cases, it may be preferable to use layers 147a and 147b. It may be preferable to use a layer with a lower resistance than the channel of the transistor. For example, layers 147a and The resistivity of the layer 147b is set to 0.1 Ωcm or more and 100 Ωcm or less, and 0.5 Ωcm or more and 50 Ωcm or less. The layer 147a and the layer 147b may have a resistivity of 1 Ωcm or less, or 1 Ωcm or more and 10 Ωcm or less. By setting the resistivity of b within the above range, the electric field at the boundary between the channel and the drain Therefore, the fluctuation of the electrical characteristics of the transistor can be reduced. In addition, it is possible to reduce punch-through current caused by the electric field generated from the drain. Therefore, it is possible to improve the saturation characteristics even in transistors with short channel lengths. In addition, if the circuit configuration does not swap the source and drain, the layer 147a Alternatively, it is preferable to dispose only one of the layers 147b (for example, the drain side). There are cases where this happens.

[0136] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part of the semiconductor through which current flows when the transistor is on). The source (source region or source electrode) in the region where the channel is formed. The distance between the transistor and the drain (drain region or drain electrode) is In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. The channel length is any one of the values, maximum and minimum, in the region where the channel is formed. The value is the average value.

[0137] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The area where the gate electrode overlaps with the gate electrode (the area where current flows) or the area where the channel is formed. The length of the part where the source and drain face each other is called the length of one transistor. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. The channel width is any one of the values, maximum and minimum, in the region where the channel is formed. The value is the average value.

[0138] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width shown in the figure becomes larger, and the effect becomes non-negligible. For example, in a transistor with a fine, three-dimensional structure, the upper surface of the semiconductor The ratio of the channel region formed on the side of the semiconductor to the ratio of the channel region formed on the inside of the semiconductor In this case, the apparent channel width shown in the top view may be The effective channel width where the channel is actually formed is larger than the actual channel width.

[0139] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order for deposition to occur, it is necessary to assume that the shape of the semiconductor is known. It is difficult to accurately measure the effective channel width if the channel conditions are not precisely known. .

[0140] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent thickness is the length of the part where the source and drain face each other in the region where the The channel width is referred to as "Surrounded Channel Width (SCW)". In this specification, when simply referred to as the channel width, This may refer to the enclosed channel width or apparent channel width. In the detailed description, when simply referred to as a channel width, it may refer to an effective channel width. In addition, channel length, channel width, effective channel width, apparent channel width, and enclosure The channel width can be determined by acquiring a cross-sectional TEM image and analyzing the image. , values ​​can be determined.

[0141] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0142] The second transistor 100 has been described above.

[0143] The insulating film 127 covering the second transistor 100 is a flat film that covers the uneven shape of the underlying layer. The insulating film 108 also functions as a protective film when the insulating film 127 is formed. The insulating film 108 may not be provided if it is not necessary.

[0144] The plug 170 is provided so as to be buried in the insulating film 128, and is electrically connected to the plug 167. The plug 171 is embedded in the insulating film 128. The plug 172 is electrically connected to the plug 168. The plug 172 is buried in the insulating film 128. The connector 162 is provided so as to be electrically connected to the plug 169 .

[0145] The electrode 173 is electrically connected to the plug 170, and the electrode 174 is electrically connected to the plug 171. The electrode 175 is electrically connected to the plug 172 .

[0146] The semiconductor device of one embodiment of the present invention includes a first transistor 110 and a Since the second transistor 100 is located above the first transistor 100, these are stacked. This allows the area occupied by the element to be reduced. The barrier film 120 provided between the first and second transistors 100 prevents the This can prevent impurities such as water and hydrogen present in the second transistor 100 from diffusing to the second transistor 100 side.

[0147] The above is a description of the configuration example.

[0148] [Example of manufacturing method] An example of a method for manufacturing the semiconductor device shown in the above configuration example will be described below with reference to FIGS. 6 will be used to explain.

[0149] First, a semiconductor substrate 111 is prepared. The semiconductor substrate 111 is, for example, a single crystal silicon substrate. semiconductor substrates (including p-type semiconductor substrates and n-type semiconductor substrates), silicon carbide and nitride semiconductor substrates A compound semiconductor substrate made of lithium or the like can be used. In the following, a single crystal silicon substrate is used as the semiconductor substrate 111. We will explain the case where a

[0150] Subsequently, an element isolation layer (not shown) is formed on the semiconductor substrate 111. The element isolation layer is formed by LOC. OS (Local Oxidation of Silicon) method or STI (Sh The insulating layer 11 may be formed by using a method such as a trench isolation method.

[0151] When forming p-type and n-type transistors on the same substrate, the semiconductor substrate 1 An n-well or p-well may be formed in a part of the n-type semiconductor substrate 11. 1 is doped with impurity elements such as boron to give it p-type conductivity, forming a p-well. An n-type transistor and a p-type transistor may be formed on the substrate.

[0152] Next, an insulating film that will become the gate insulating film 114 is formed on the semiconductor substrate 111. For example, After the surface nitriding treatment, an oxidation treatment is performed to oxidize the interface between silicon and silicon nitride, forming silicon oxynitride. For example, a silicon nitride film may be formed on the surface at 700°C in an NH3 atmosphere. After the formation of the silicon oxynitride film, oxygen radical oxidation is performed to obtain a silicon oxynitride film.

[0153] The insulating film is formed by sputtering, CVD (Chemical Vapor Deposition), sition) method (thermal CVD method, MOCVD (Metal Organic CVD) method , PECVD (Plasma Enhanced CVD) method, etc.), MBE (Mo lecular beam epitaxy) method, ALD (Atomic Layer Deposition) method, or PLD (Pulsed Laser Deposit) Alternatively, the film may be formed by a film formation method such as an ion method.

[0154] Next, a conductive film is formed to become the gate electrode 115. The conductive film is made of tantalum, tantalum, or the like. a metal selected from the group consisting of tin, titanium, molybdenum, chromium, niobium, etc., or It is preferable to use an alloy material or a compound material whose main component is a metal. In addition, the metal nitride film and the above-mentioned polycrystalline silicon film can be used. A laminated structure of metal films may be used. Examples of metal nitrides include tungsten nitride and molybdenum nitride. By providing a metal nitride film, the density of the metal film can be improved. The adhesion of the gate electrode 115 can be improved and peeling can be prevented. A metal film for controlling the work function may be provided.

[0155] Conductive films are formed by sputtering, evaporation, CVD (thermal CVD, MOCVD, PEC It is possible to form films by methods such as the VD method. In addition, damage caused by plasma is reduced. For this purpose, the thermal CVD method, the MOCVD method or the ALD method is preferred.

[0156] Subsequently, a resist mask is formed on the conductive film by lithography or the like. The unnecessary part of the film is removed. Then, the resist mask is removed to reveal the gate electrode. 115 can be formed.

[0157] Here, a method for processing a film to be processed will be described. When processing a film to be processed finely, Various microfabrication techniques can be used. For example, a resist formed by lithography or the like can be used. A method of slimming the mask may be used. A dummy pattern is formed, a sidewall is formed on the dummy pattern, and then the dummy pattern is The turn is removed, and the film to be processed is etched using the remaining sidewall as a mask. In addition, in order to achieve a high aspect ratio when etching the film to be processed, It is preferable to use anisotropic dry etching. A hard mask may also be used.

[0158] The light used to form the resist mask is, for example, i-line (wavelength 365 nm) or g-line (wavelength 43 6nm), H-line (wavelength 405nm), or a mixture of these can be used. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can also be used. Alternatively, the exposure may be performed by an immersion exposure technique. Light (EUV: Extreme Ultraviolet) or X-rays may also be used. Instead of light used for exposure, electron beams can also be used. The use of an electron beam is preferable because it allows for extremely fine processing. When exposure is performed by scanning a beam such as a photomask, no photomask is required.

[0159] In addition, before forming the resist film that will become the resist mask, the film to be processed and the resist film are closely An organic resin film having a function of improving adhesion may be formed. By using a pin coating method or the like, the step of the lower layer is covered and the surface is flattened. This makes it possible to reduce variations in the thickness of the resist mask provided on the organic resin film. In particular, when fine processing is performed, the organic resin film is preferably resistant to the light used for exposure. It is preferable to use a material that functions as an anti-reflection film against the reflection of light. As the organic resin film, for example, BARC (Bottom Anti-Reflection The organic resin film is removed at the same time as the resist mask is removed. It may be removed after removing the resist mask.

[0160] After the gate electrode 115 is formed, a sidewall is formed to cover the side surface of the gate electrode 115. The sidewall may be formed by depositing an insulating film thicker than the gate electrode 115, and then Anisotropic etching is performed to leave the insulating film only on the side surfaces of the gate electrode 115. It can be formed by:

[0161] When the sidewalls are formed, the insulating film that will become the gate insulating film 114 is also etched at the same time. As a result, the gate insulating film 114 is formed under the gate electrode 115 and the sidewall. Alternatively, after the gate electrode 115 is formed, the gate electrode 115 or the gate electrode 11 The insulating film is etched using the resist mask for processing 5 as an etching mask. Alternatively, the gate insulating film 114 may be formed by etching the insulating film. It may also be used as the gate insulating film 114 as it is without being processed by etching.

[0162] Next, the gate electrode 115 (and sidewalls) of the semiconductor substrate 111 is provided. In the region where there is no conductivity, elements such as phosphorus that give n-type conductivity or boron that give p-type conductivity are added. The element to be added is added. The cross-sectional view at this stage is shown in FIG. 11(A).

[0163] Subsequently, after forming the insulating film 121, the above-mentioned element for imparting conductivity is activated. A first heat treatment is carried out.

[0164] The insulating film 121 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or silicon nitride. Silicon, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride The insulating film 121 may be formed by a sputtering method. , CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method Alternatively, the insulating film can be formed by a PLD method or the like. In particular, the insulating film can be formed by a CVD method, preferably a Alternatively, it is preferable to form the film by plasma CVD, since this can improve the coating property. In addition, to reduce damage caused by plasma, thermal CVD, MOCVD or A The LD method is preferred.

[0165] The first heat treatment is performed in an inert gas atmosphere such as a rare gas or a nitrogen gas atmosphere, or in a reduced pressure atmosphere. The heating can be carried out at, for example, 400° C. or higher and below the strain point of the substrate.

[0166] At this stage, the first transistor 110 is formed.

[0167] Subsequently, the insulating film 122 and the insulating film 123 are formed.

[0168] The insulating film 122 may be made of a material that can be used for the insulating film 121, or a nitrogen-containing material containing oxygen and hydrogen. By using silicon hydride (SiNOH), the amount of hydrogen released by heating can be increased. In addition, the insulating film 123 can be made of a material that can be used for the insulating film 121. In addition, TEOS (Tetra-Ethyl-Ortho-Silicate) or Si Silicon oxide with good step coverage formed by reacting ore with oxygen or nitrous oxide. It is preferable to use con.

[0169] The insulating film 122 and the insulating film 123 are formed by, for example, a sputtering method or a CVD method (thermal CVD method). (including MOCVD, PECVD, etc.), MBE, ALD, PLD, etc. In particular, the insulating film can be formed by a CVD method, preferably a plasma CVD method. It is preferable to form the film by plasma, since it is possible to improve the coating property. To reduce damage caused by the deposition, thermal CVD, MOCVD, or ALD is preferred.

[0170] Subsequently, the upper surface of the insulating film 123 is planarized using a CMP method or the like.

[0171] Then, the dangling bonds in the semiconductor film 112 are removed by hydrogen released from the insulating film 122. Then, a second heat treatment is performed to terminate the wire.

[0172] The second heat treatment can be carried out under the conditions exemplified in the description of the first heat treatment above.

[0173] Subsequently, an insulating film 124 is formed on the insulating film 123 .

[0174] Subsequently, the low resistance layer 11 is formed on the insulating film 121, the insulating film 122, the insulating film 123, and the insulating film 124. 3a, the low resistance layer 113b, and the gate electrode 115 are formed. A conductive film is formed so as to fill the opening, and a flat layer is formed on the conductive film so that the upper surface of the insulating film 124 is exposed. By carrying out a flattening process, plugs 161, 162, 163, etc. are formed. The conductive film is formed by, for example, sputtering, CVD (thermal CVD, MOCVD, PE It can be formed by using a method such as CVD, MBE, ALD, or PLD. The cross-sectional view at this stage is shown in FIG. 11(B).

[0175] An electrode 136 is formed on the insulating film 124 (see FIG. 11C).

[0176] Next, an insulating film 125 is formed to cover the electrode 136, and the upper surface of the insulating film 125 is polished by a CMP method or the like. The insulating film that becomes the insulating film 125 is made of the same material and by the same method as the insulating film 121. It can be formed more easily.

[0177] After the insulating film 125 is formed, third heat treatment is preferably performed. This allows the water and hydrogen contained in each layer to be desorbed, thereby reducing the water and hydrogen content. A third heat treatment is performed immediately before forming the barrier film 120, which will be described later, to form the barrier film 120. After thoroughly removing hydrogen and water contained in the layer below 120, the barrier film 120 is formed. By doing so, water and hydrogen may be diffused and released again below the barrier film 120 in a subsequent process. This can prevent this from happening.

[0178] The third heat treatment can be carried out under the conditions exemplified in the description of the first heat treatment above.

[0179] Subsequently, the barrier film 120 is formed on the insulating film 125 (see FIG. 11(D)).

[0180] The barrier film 120 can be formed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD method, (including PECVD, etc.), MBE, ALD, PLD, etc. In particular, the barrier film can be formed by a CVD method, preferably a plasma CVD method. In addition, it is preferable to use a plasma treatment because it can improve the coating property. To reduce this, thermal CVD, MOCVD or ALD is preferred.

[0181] After the barrier film 120 is formed, the water and hydrogen contained in the barrier film 120 are reduced or removed. A heat treatment may be carried out to suppress gas release.

[0182] An insulating film that will become the insulating film 126 is formed on the barrier film 120. The film can be formed by, for example, sputtering, CVD (thermal CVD, MOCVD, PECVD, etc.) In particular, the layer can be formed by using a method such as MBE, ALD, or PLD. When the insulating film is formed by a CVD method, preferably a plasma CVD method, the covering property is improved. In addition, to reduce damage caused by plasma, The VD method, the MOCVD method or the ALD method is preferred.

[0183] In order to make the insulating film that will become the insulating film 126 contain excess oxygen, for example, The insulating film that becomes the insulating film 126 may be formed by the above-described method. Oxygen may be introduced into the insulating film to form a region containing excess oxygen, or both methods may be combined. You can also match them.

[0184] For example, the insulating film that will become the insulating film 126 after film formation is not subjected to oxygen (at least oxygen radicals, oxygen atoms, etc.). The oxygen-rich region is formed by introducing oxygen atoms (containing either oxygen atoms or oxygen ions). The methods of introducing elements include ion implantation, ion doping, and plasma immersion ion implantation. The ion implantation method, plasma treatment, etc. can be used.

[0185] The oxygen introduction treatment can be performed using a gas containing oxygen. Oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc. can be used. In the oxygen introduction process, a rare gas may be contained in the oxygen-containing gas. For example, A mixture of carbon dioxide, hydrogen and argon can be used.

[0186] After forming the insulating film that will become the insulating film 126, a CM A planarization process using a P method or the like is performed to form an insulating film 126 (see FIG. 12(A)).

[0187] Next, the oxide semiconductor film 102a that will become the oxide semiconductor film 101a and the oxide semiconductor film 1 The oxide semiconductor film 102b is then formed as a thin film. It is preferable to form the films continuously without causing any cracks.

[0188] After the oxide semiconductor film 102b is formed, fourth heat treatment is preferably performed. , at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, The reaction may be carried out in a gas atmosphere, an atmosphere containing 10 ppm or more of oxidizing gas, or under reduced pressure. The heat treatment atmosphere is an inert gas atmosphere, and then the desorbed oxygen is replaced by The heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more. The oxide semiconductor film 102b may be processed to form island-shaped oxide films. The heat treatment may be performed after the formation of the insulating film 126. Oxygen is supplied to the oxide semiconductor film, and oxygen vacancies in the semiconductor film can be reduced.

[0189] Next, a conductive film 103 serving as a hard mask and an insulating film 106 are formed on the oxide semiconductor film 102b. The conductive film 103 is formed by a sputtering method, a vapor deposition method, and a C Films can be formed by VD methods (including thermal CVD, MOCVD, PECVD, etc.) In addition, to reduce damage caused by plasma, thermal CVD, MOCVD or The insulating film 106 is preferably formed by the ALD method. For example, an inorganic film such as a silicon oxide nitride film can be used. method (including thermal CVD, MOCVD, PECVD, etc.), MBE method, ALD method or P The insulating film can be formed by using the LD method or the like. In particular, the insulating film can be formed by the CVD method, preferably by the proton beam. It is preferable to form the film by the plasma CVD method, since this can improve the coating properties. In addition, to reduce damage caused by plasma, thermal CVD, MOCVD, or ALD methods are used. is preferred.

[0190] The insulating film 106 and the conductive film 103 are used as a hard mask to form an oxide semiconductor film. 102b, the oxide semiconductor film 102a, the insulating film 126, the barrier film 120, and the insulating film 125. 1. An example of a method for forming fine openings that reach the plug 161, the plug 163, and the electrode 136. is shown below.

[0191] A resist mask 141 is formed on the insulating film 106 by the same method as described above. In order to improve the adhesion between the insulating film 106 and the resist mask, An organic resin film may be formed between them.

[0192] Next, the organic resin film is etched using the resist mask 141 (see FIG. 12(C)). Subsequently, the insulating film 106 is etched to form an insulating film 106a. It is preferable to make the etching rate of the resist mask lower than the etching rate of the film. In other words, by suppressing the etching rate of the resist mask, the opening in the insulating film can be reduced. This can prevent the mouth from spreading laterally (see FIG. 13(A)).

[0193] Next, the conductive film 103 is dry-etched using the insulating film 106a as a mask. Here, the etching rate of the insulating film 106a is kept low. The reason why this is preferable is the same as that described above. The resist mask 141 and the organic resin film 140a are also etched, and the recessed resist mask 1 41a and a recessed organic resin film 140b are formed.

[0194] By carrying out the above steps, a two-layer hard mask consisting of the insulating film 106a and the conductive film 103 is formed. This can be achieved (see FIG. 13(B)).

[0195] Using this two-layer hard mask, the oxide semiconductor film 102b, the oxide semiconductor film 102a, By dry etching the insulating film 126, the barrier film 120 and the insulating film 125, the plate It is possible to form minute openings that reach the groove 161 and the plug 163. The oxide semiconductor film 146a and the oxide semiconductor film 146b are formed on the surface of the substrate. During etching, the resist mask 141a and the organic resin film 140b are and disappears (see Figure 14(A)).

[0196] The insulating film 106a of the two-layer hard mask is made of the oxide semiconductor film 102b and the oxide Dry etching of the semiconductor film 102a, the insulating film 126, the barrier film 120, and the insulating film 125 However, if the hard mask is lost during the etching, In order to prevent the conductive film 103 from being excessively etched, the insulating film 106a is The insulating film 106a is etched away by about 10% of its thickness. It is advisable to adjust the etching time appropriately so that the etching is performed properly (see FIG. 14(A)). Alternatively, the insulating film 106a may be intentionally left. In this case, the insulating film 106a This can be achieved by appropriately adjusting the thickness of the insulating film 106a. The conductive film 103a1 functions as a stopper film when detecting the end point of the CMP process. It is possible to prevent the thickness from becoming small. The parasitic capacitance between the gate electrode and the source electrode, and the parasitic capacitance between the gate electrode and the drain electrode Alternatively, the leakage current of the gate electrode and source electrode and the gate The leakage current between the electrode and the drain electrode can be reduced.

[0197] Here, a two-layer hard mask consisting of an insulating film 106a and a conductive film 103 is formed. The oxide semiconductor film 102b, the oxide semiconductor film 102a, and the insulating film 102b are formed by using the two-layer hard mask. The insulating film 126, the barrier film 120, and the insulating film 125 are dry-etched to form a plug 161. Regarding a dry etching apparatus for forming a fine opening that reaches the plug 163, This will be explained using the schematic diagram of the etching apparatus shown in FIG.

[0198] The etching equipment shown in Figure 3 has three etching chambers and a substrate is placed in each etching chamber. A transfer chamber is used to temporarily hold substrates while they are being moved to another chamber. a gas supply system that supplies etching gas etc. to each etching chamber; Although not shown, it has a power supply system, a pump system, a gas abatement system, etc. .

[0199] To form a multilayer film made of multiple film types and fine openings, a parallel plate type electron microscope is used. It is desirable to use an etching device, especially one with a high density plasma source. It is preferable that the etching apparatus is an etching apparatus having a plurality of etching chambers. Alternatively, the etching gas may be an optimal gas for etching each etching layer. It has a gas supply system that can select and combine multiple gases. It is preferable that:

[0200] A multilayer film having a plurality of film types and a fine opening is formed in one etching chamber. In this method, the optimum etching gas for each etching layer is used. The etching chamber is simply introduced. The etching equipment has multiple chambers. Etching equipment can process multiple substrates simultaneously in parallel, improving production efficiency. This is preferable because it can increase the etching efficiency. This is an example of an etching device.

[0201] When etching a multilayer film in one etching chamber, the etching chamber must have the following: The gas is switched to the optimum one depending on the type of film to be etched, and then introduced and etched. Various etching products can adhere and deposit on the walls of the etching chamber. During etching, the particles may peel off from the etching chamber wall and fly away. If it adheres to the substrate, it may cause etching defects.

[0202] As a method for preventing the generation of such particles, it is necessary to separate the etching chamber for each film type. For example, a film that will become a hard mask is etched in a chamber. The following describes the method of etching in chamber A and etching other films in chamber B. This will be explained in.

[0203] First, the substrate is inserted into the etching chamber A, and the organic resin film, the insulating film 106, and the conductive film 1 The organic resin film may be etched using, for example, CF4 gas. The insulating film 106 may be etched using a mixed gas of CHF3 gas and O2 gas, for example. The conductive film 103 is etched using a mixture of CF4 gas, Cl2 gas, and O2 gas. Next, the substrate is transferred from the etching chamber A to the transfer chamber B. The substrate is inserted into an etching chamber B through a member, and the oxide semiconductor film 102b and the oxide The semiconductor film 102a, the insulating film 126, the barrier film 120, and the insulating film 125 are etched. The etching gas for the oxide semiconductor film 102b and the oxide semiconductor film 102a is, for example, C A mixed gas of HF3 gas and Ar gas may be used. For example, a mixture of C4F6 gas, Ar gas, and O2 gas may be used. The etching gas for the film 120 and the insulating film 125 is, for example, CHF3 gas plus Ar gas. A mixed gas may also be used. Next, the substrate is removed from the etching chamber B and etched in the same manner as above. The wafer is then moved to the etching chamber C where it is ashed. Ashing gas is, for example, O2 gas. It may be used.

[0204] Even if the structure is a multi-layer film, fine openings can be achieved by following the above procedure. A mouth can be formed.

[0205] In the above example, the etching apparatus must have multiple etching chambers. However, even when transferring the substrate between chambers, it is always transferred under vacuum and never in an atmospheric environment. Since the etching is not exposed to the atmosphere, it is possible to perform etching with good reproducibility. Since etching is performed in a single chamber, the processing time in each chamber can be shortened. This can increase production efficiency.

[0206] Next, a conductive film is formed on the conductive film 103a1 and in the opening formed above. The conductive film is embedded in the insulating film. The conductive film can be formed by sputtering, vapor deposition, CVD ( The film can be formed by a method such as thermal CVD, MOCVD, or PECVD. In addition, to reduce damage caused by plasma, thermal CVD, MOCVD, or ALD Next, the conductive film formed on the conductive film 103a1 is polished by the CMP method. The surface of the insulating film 106a is polished until the surface of the insulating film 106a is exposed. The insulating film 106a functions as a stopper film for CMP. Lugs 166 may be formed (see FIG. 14(B)).

[0207] Next, a resist mask is formed in the same manner as above, and unnecessary portions of the conductive film 103a1 are removed. Then, the island-shaped conductive film 103a2 is etched to form the island-shaped conductive film 103a2. The unnecessary portions of the oxide semiconductor film are removed by etching as a mask. By removing the oxide semiconductor film 101a, the oxide semiconductor film 101b is removed. A laminated structure of b can be formed (see FIG. 15(A)).

[0208] At the same time, the electrode 103c, the island-shaped oxide semiconductor film 131a, and the island-shaped oxide semiconductor film 131b are A laminated structure 31b can be formed.

[0209] Next, a resist mask is formed on the island-shaped conductive film 103a2 by the same method as above. By etching unnecessary portions of the island-shaped conductive film 103a2 using a mask, the source electrode Alternatively, the electrode 103a and the electrode 103b that function as drain electrodes can be formed. (See Figure 15(B)).

[0210] Subsequently, the oxide semiconductor film 101c, the gate insulating film 104, and the gate electrode 105 are formed. (See FIG. 16(A)).

[0211] At this stage, the second transistor 100 is formed.

[0212] Subsequently, the insulating film 107 is formed. The insulating film 107 is formed by, for example, a sputtering method or a CVD method. method (including thermal CVD, MOCVD, PECVD, etc.), MBE method, ALD method or P The insulating film can be formed by using the LD method or the like. In particular, the insulating film can be formed by the CVD method, preferably by the proton beam. It is preferable to form the film by the plasma CVD method, since this can improve the coating properties. In addition, to reduce damage caused by plasma, thermal CVD, MOCVD, or ALD methods are used. is preferred.

[0213] After the insulating film 107 is formed, fifth heat treatment is preferably performed. Oxygen is supplied to the oxide semiconductor film 101b from the film 126 or the like, and the oxide semiconductor film 101b In addition, oxygen vacancies in the insulating film 126 can be reduced. is blocked by the barrier film 120 and the insulating film 107, and the layer below the barrier film 120 Since the oxygen does not diffuse into the layer above the insulating film 107, the oxygen can be effectively trapped. Therefore, the amount of oxygen that can be supplied to the oxide semiconductor film 101b can be increased. Therefore, oxygen vacancies in the oxide semiconductor film 101b can be effectively reduced.

[0214] Next, the insulating film 108 and the insulating film 127 are formed in this order (see FIG. 16B). 108 and the insulating film 127 are formed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD method, etc. D method, PECVD method, APCVD (Atmospheric Pressure CVD ) method, etc.), MBE method, ALD method, PLD method, etc. In particular, when the insulating film 108 is formed by DC sputtering, a film with high barrier properties can be produced with high productivity. It is preferable because it can form a thick film well. In addition, when forming a film by the ALD method, ion damage occurs. This is preferable because it can reduce the amount of the insulating film 127 and improve the coverage. When using organic insulating materials such as organic resin, a coating method such as spin coating is used. After the insulating film 127 is formed, the upper surface thereof may be subjected to a planarization process. It is also preferable to carry out a heat treatment to fluidize and flatten the surface. In order to improve the performance, after forming the insulating film 127, an insulating film is laminated by using the CVD method. After that, it is preferable to perform a flattening process on the upper surface.

[0215] Next, openings are formed in the insulating film 127, the insulating film 108, and the insulating film 107 in the same manner as above. The plug 167 reaches the plug 164, and the plug 16 reaches the gate electrode 105. 8. Form a plug 169 that reaches the plug 166 (see FIG. 16(B)).

[0216] Next, the insulating film 128 is formed. The description of the insulating film 127 is applied to the insulating film 128. It is possible.

[0217] Next, an opening is formed in the insulating film 128 by the same method as above, and the opening reaches the plug 167. Plug 170 reaches plug 168, plug 171 reaches plug 169, and plug 17 Form 2.

[0218] Next, an electrode 173 electrically connected to the plug 170 and an electrode 174 electrically connected to the plug 171 are and an electrode 175 electrically connected to the plug 172 (FIG. 1(B)). reference).

[0219] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0220] <Variation 1> As a modification of this embodiment, as shown in FIG. 17, the first transistor 110 A capacitor 130 may be provided between the first transistor and the second transistor 100. The position of the capacitor 13 may be set above the second transistor 100. One electrode 136 of the transistor 100 is connected to one of the source and drain of the second transistor 100. and the gate of the first transistor 110. An insulating film 137 is provided on one electrode 136, and the other electrode of the capacitor 130 is provided on the insulating film 137. An electrode 138 is provided. The electrode 138 is electrically connected to the wiring CL. The electrode 136 is electrically connected to the electrode 103b via a plug 165.

[0221] With the above configuration, the second transistor 10 is located within the area occupied by the first transistor 110. 0 and a capacitance element 130 are provided, which allows the area occupied by each element to be reduced.

[0222] In addition, a wiring 180 may be provided between the plug 161 and the plug 164, or the plug 16 A wiring 181 may be provided between the plug 166 and the wiring 181. Similarly, wiring may be provided between the plugs. By using such a configuration, the mask height can be improved. This eliminates the need for high alignment accuracy and can prevent a decrease in the manufacturing yield of semiconductor devices. Cut.

[0223] <Variation 2> As a modification of this embodiment, a configuration as shown in FIG. 18 may be used. The difference is that the insulating film 106a of the two-layer hard mask is intentionally left. The insulating film 106a functions as a stopper film for CMP, and the thickness of the conductive film 103a1 is small. Alternatively, the parasitic capacitance of the gate electrode and the source electrode and the gate The parasitic capacitance between the gate electrode and the drain electrode can be reduced. This reduces the leakage current of the source electrode and the leakage current between the gate electrode and the drain electrode. It is possible.

[0224] <Variation 3> As a modification of this embodiment, as shown in FIG. 19, the first transistor 110 The position of the gate electrode 115 of the first transistor 100 and the gate electrode 105 of the second transistor 100 overlap each other. It may also be configured not to do so.

[0225] <Variation 4> As a modification of this embodiment, as shown in FIG. 20(A), an insulating film 128 is formed. After that, the low resistance layer 113a, the low resistance layer 113b, and the second An opening is provided that reaches the gate electrode 105 of the transistor 100, and a low resistance layer 113a is provided. a plug 170 that reaches the gate electrode 105 of the second transistor 100; Then, a plug 172 is formed that reaches the low resistance layer 113b, and then the plug 170 is electrically connected to the plug 172. an electrode 173 electrically connected to the plug 171; an electrode 174 electrically connected to the plug 172; In this way, a multilayer structure of different film types may be formed. When forming an opening in the membrane, a constriction is formed in which a part of the membrane recedes as shown in Figure 20(B). This is because the etching rate of the film at the constricted portion is This shape may occur when the membrane is larger than the membranes above and below the membrane, but this does not affect the formation of a plug. Also, the area of ​​electrical contact at the constricted part is large, so the transistor The on-state characteristics may also be improved.

[0226] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0227] (Embodiment 2) In this embodiment, a transistor included in the semiconductor device described in the above embodiment is In this section, one embodiment applicable to an oxide semiconductor film will be described.

[0228] Oxide semiconductors are classified into, for example, non-single-crystal oxide semiconductors and single-crystal oxide semiconductors. Alternatively, oxide semiconductors can be divided into, for example, crystalline oxide semiconductors and amorphous oxide semiconductors. can be.

[0229] Note that as a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Semiconductors, microcrystalline oxide semiconductors, amorphous oxide semiconductors, etc. The materials include single-crystalline oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxides. Semiconductors, etc.

[0230] First, let me explain about CAAC-OS.

[0231] CAAC-OS is an oxide semiconductor having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0232] Transmission Electron Microscope (TEM) The CAAC-OS bright-field image and diffraction pattern were analyzed by the IR scope. By observing the high-resolution TEM image, multiple pellets can be identified. On the other hand, high-resolution TEM images also clearly show the boundaries between pellets, i.e., grain boundaries. Therefore, CAAC-OS cannot check the boundary. It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0233] For example, as shown in FIG. 33(A), a cross section of the CAAC-OS is taken from a direction substantially parallel to the sample surface. Here, a high-resolution TEM image of the sample is observed. The TEM image is observed using the spherical convergence corrector function. Hereafter, high-resolution TEM images using the differential correction function will be referred to as Cs-corrected high-resolution TEM images. Note that Cs-corrected high-resolution TEM images can be obtained using, for example, an atomic resolution TEM manufactured by JEOL Ltd. This can be done using an analytical electron microscope such as the JEM-ARM200F.

[0234] An enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 33(A) is shown in FIG. 33(B). From Figure 33(B), it can be seen that the metal atoms are arranged in layers in the pellet. Each layer of metal atoms is formed on the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). The shape reflects the unevenness of the surface, and is aligned parallel to the surface on which the CAAC-OS is formed or the top surface. .

[0235] In Figure 33(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines. From Figure 33(B) and Figure 33(C) The size of each pellet is about 1 nm to 3 nm, and the inclination between pellets is It can be seen that the size of the gap caused by the crack is about 0.8 nm. The nanocrystals can also be called nanocrystals (nc).

[0236] Here, from the Cs-corrected high-resolution TEM image, it is clear that the CAAC-OS pellet 5 on the substrate 5120 A schematic representation of the arrangement of 100 would resemble a stack of bricks or blocks. (See Figure 33(D)). The tilt between the pellets observed in Figure 33(C) The area where this occurs corresponds to the area 5161 shown in FIG.

[0237] Also, for example, as shown in FIG. 34(A), the CAAC-OS Observe the Cs-corrected high-resolution TEM image of the plane of area (1) and area (2) in Figure 34(A). The Cs-corrected high-resolution TEM images of the enlarged area (3) are shown in Figure 34(B) and Figure 3 34(B), 34(C) and 34(D). The pellets are made by ensuring that the metal atoms are arranged in a triangular, square, or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different pellets.

[0238] For example, for CAAC-OS with InGaZnO4 crystals, X-ray diffraction (XRD) Construction by out-of-plane method using a Ray Diffraction (RF) device When structural analysis was performed, a peak appeared at a diffraction angle (2θ) of approximately 31°, as shown in Figure 35(A). This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the CAAC-OS crystal has a c-axis orientation, and the c-axis is approximately perpendicular to the surface on which the CAAC-OS is formed or the upper surface. You can see that it is pointing in the right direction.

[0239] In addition, the out-of-plane method of CAAC-OS with InGaZnO4 crystals In the structural analysis, in addition to the peak at 2θ around 31°, a peak also appeared at 2θ around 36°. The peak at 2θ around 36° is due to the c-axis orientation in some CAAC-OS. This indicates that the CAAC-OS contains crystals that do not have a peak at 2θ around 31°. It is preferable that the spectrum shows a peak at 2θ of around 36° and that the spectrum does not show a peak at 2θ of around 36°.

[0240] On the other hand, in-plan X-ray irradiation is performed on the CAAC-OS in a direction approximately perpendicular to the c-axis. When structural analysis is performed using the e method, a peak appears at 2θ around 56°. This peak is due to In It is attributed to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was fixed at approximately 100°, and the analysis was performed while rotating the sample around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears as shown in Figure 35(B). However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ is When scanning is performed, the peaks attributable to the crystal plane equivalent to the (110) plane are as shown in Figure 35(C). Therefore, from the structural analysis using XRD, it is clear that CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0241] Next, the In-Ga-Zn oxide CAAC-OS was subjected to a process parallel to the sample surface. Diffraction pattern when an electron beam with a lobe diameter of 300 nm is incident (selected area transmission electron diffraction) ) is shown in FIG. 36(A). From FIG. 36(A), for example, InGaZn The spots due to the (009) plane of the O4 crystal are confirmed. However, the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is aligned with the surface on which the film is formed or the On the other hand, for the same sample, the direction perpendicular to the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident from the direction of the ) is shown. From Figure 36(B), a ring-shaped diffraction pattern is confirmed. Diffraction analysis also revealed that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. It can be seen that the first ring in Figure 36(B) is the InGaZnO4 crystal. This is thought to be due to the (010) and (100) planes. The second ring is thought to be due to the (110) plane.

[0242] In this way, the c-axis of each pellet (nanocrystal) is approximately perpendicular to the surface on which it is formed or the upper surface. Because of the direction, CAAC-OS is aligned with CANC (C-Axis Aligned It can also be called an oxide semiconductor having nanocrystals.

[0243] CAAC-OS is an oxide semiconductor with a low concentration of impurities. The impurities are hydrogen, carbon, and silicon. Elements other than the main components of oxide semiconductors, such as silicon and transition metal elements. The elements that bond with oxygen more strongly than the metal elements that make up the oxide semiconductor are By removing oxygen from the oxide semiconductor, the atomic arrangement of the oxide semiconductor is disturbed, which causes a decrease in crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have atomic radii (or molecular radii). Because of their large radius, when they are contained inside an oxide semiconductor, they disrupt the atomic arrangement of the oxide semiconductor. Impurities contained in an oxide semiconductor can cause a decrease in crystallinity. This may be a source of loops or carriers.

[0244] In addition, the CAAC-OS is an oxide semiconductor with a low density of defect states. Oxygen vacancies in the body act as carrier traps or trap hydrogen, which can increase the carrier It can be a source of odor.

[0245] In addition, transistors using CAAC-OS show changes in their electrical characteristics when irradiated with visible light or ultraviolet light. The fluctuation is small.

[0246] Next, a microcrystalline oxide semiconductor will be described.

[0247] Microcrystalline oxide semiconductors are regions where crystals can be confirmed in high-resolution TEM images. The microcrystalline oxide semiconductor has a region in which no clear crystal part can be identified. The crystal part contained in the crystal is 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less. In particular, microcrystals of 1 nm to 10 nm or 1 nm to 3 nm are often present. The oxide semiconductor having nanocrystals is called nc-OS (nanocrystalline The nc-OS is also called a high-performance semiconductor. In high-resolution TEM images, the grain boundaries may not be clearly visible. It is possible that the pellets in AAC-OS have the same origin. The crystalline part of c-OS is sometimes called a pellet.

[0248] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 nm). The atomic arrangement is periodic in the region of less than 100 nm. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, there is an XRD device that uses X-rays with a diameter larger than that of the pellet for nc-OS. When structural analysis is performed using the out-of-plane method, No peak is detected. Also, for nc-OS, the probe diameter (e.g., When electron diffraction (also called selected area electron diffraction) is performed using an electron beam of, for example, 50 nm or more, On the other hand, for nc-OS, a halo-like diffraction pattern is observed. Nanobeam electron diffraction using an electron beam with a probe diameter close to the pellet size or smaller than the pellet size When nanobeam electron diffraction is performed on nc-OS, spots are observed. In some cases, a bright area that appears circular (ring-shaped) may be observed. When nanobeam electron diffraction is performed on the OS, multiple spots are observed within the ring-shaped region. This may be the case.

[0249] In this way, the crystal orientation of each pellet (nanocrystal) is not regular. nc-OS has NANC (Non-Aligned nanocrystals) It can also be called an oxide semiconductor.

[0250] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower defect state density than the amorphous oxide semiconductor. There is no regularity in the crystal orientation between different pellets. The defect level density is higher than that of AC-OS.

[0251] Next, the amorphous oxide semiconductor will be described.

[0252] Amorphous oxide semiconductors are oxides in which the atomic arrangement in the film is irregular and there are no crystalline parts. An example is an oxide semiconductor that has an amorphous state, such as quartz.

[0253] In amorphous oxide semiconductors, no crystalline parts can be observed in high-resolution TEM images.

[0254] When structural analysis is performed on amorphous oxide semiconductors using an XRD device, out-of-plane In the analysis by the ane method, no peaks indicating crystal planes are detected. When electron diffraction is performed on the amorphous oxide semiconductor, a halo pattern is observed. However, when nanobeam electron diffraction is performed, no spots are observed, and a halo pattern is observed. can be.

[0255] There are various views on amorphous structures. For example, A structure that does not have a crystal structure is called a completely amorphous structure. Also, the distance between the nearest neighboring atoms or the second nearest neighboring atoms is called A structure that has order but does not have long-range order is sometimes called an amorphous structure. Therefore, according to the strictest definition, an oxide semiconductor that has even a slight degree of order in its atomic arrangement is called an amorphous semiconductor. Furthermore, at least oxides with long-range order cannot be called semiconductors. The semiconductor cannot be called an amorphous oxide semiconductor. For example, CAAC-OS and nc-OS can be used as amorphous oxide semiconductors or completely amorphous oxides. It cannot be called a compound semiconductor.

[0256] Note that the oxide semiconductor has a structure exhibiting physical properties between those of the nc-OS and the amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor. (a-like OS:amorphous-like Oxide Semiconductor It is called a uctor.

[0257] In a-like OS, voids are observed in high-resolution TEM images. In addition, there are cases where crystals can be clearly seen in high-resolution TEM images. and regions where no crystalline portions can be identified.

[0258] The following describes how the influence of electron irradiation varies depending on the structure of the oxide semiconductor.

[0259] a-like OS, nc-OS, and CAAC-OS were prepared. -Ga-Zn oxide.

[0260] First, high-resolution cross-sectional TEM images of each sample are acquired. It can be seen that all of the samples have crystalline parts.

[0261] Furthermore, the size of the crystalline part of each sample is measured. Figure 37 shows the size of the crystalline part of each sample (from 22 points). This is an example of investigating the change in the average size of the 45 locations. It can be seen that the crystal part grows larger according to the cumulative amount of electron irradiation. As shown in (1) in 37, the size of the particles was about 1.2 nm in the initial stage of TEM observation. The crystal part (also called the initial nucleus) was exposed to a cumulative irradiation dose of 4.2 × 10 8 e - / nm 2 Smell On the other hand, the size of the nc-OS and C AAC-OS had a cumulative electron irradiation dose of 4.2 × 10 8 e - / nm 2 to It was found that the size of the crystals did not change regardless of the cumulative electron irradiation dose until the crystals reached the Specifically, as shown in (2) in Figure 37, regardless of the course of TEM observation, The size of the crystal part is about 1.4 nm. As shown above, the size of the crystals was approximately 2.1 nm regardless of the TEM observation process. You can see that.

[0262] In this way, a-like OS can be observed by irradiating it with a small amount of electrons, similar to the level observed by TEM. Crystallization may occur and the growth of crystals may be observed. On the other hand, high-quality nc-OS and In the case of CAAC-OS, crystallization due to minute electron irradiation, such as that observed by TEM, is hardly observed. You can see that it cannot be seen.

[0263] The size of the crystalline parts of a-like OS and nc-OS was measured using high-resolution TEM. For example, InGaZnO4 crystals have a layered structure, and In The unit cell of the InGaZnO4 crystal is: It has three In-O layers and six Ga-Zn-O layers, for a total of nine layers arranged in the c-axis direction. Therefore, the spacing between adjacent layers is determined by the lattice of the (009) plane. The value is approximately the same as the interplanar spacing (also called the d value), and is determined to be 0.29 nm from crystal structure analysis. Therefore, we focused on the lattice fringes in high-resolution TEM images and investigated the In the area where the thickness is between 0.28 nm and 0.30 nm, each lattice fringe is InGaZ. It corresponds to the ab plane of the nO4 crystal.

[0264] In addition, the density of oxide semiconductors may differ depending on the structure. For example, If the composition of a material is known, the density of that material can be determined by comparing it with the density of a single crystal of the same composition. The structure of the oxide semiconductor can be estimated. For example, the density of a single crystal is The density of the OS is 78.6% or more and less than 92.3%. In contrast, the density of the nc-OS and CAAC-OS was 92.3% or more and less than 100%. Note that an oxide semiconductor having a density of less than 78% of the density of a single crystal can be formed by film formation. The body is difficult.

[0265] The above will be explained using a specific example. For example, In:Ga:Zn=1:1:1 [atomic In oxide semiconductors that satisfy the numerical ratio, single crystal InGaZnO4 with a rhombohedral crystal structure Density is 6.357g / cm 3 Therefore, for example, In:Ga:Zn=1:1:1[ In oxide semiconductors that satisfy the atomic ratio, the density of the a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 For example, In:Ga:Zn=1:1:1 [ In oxide semiconductors that satisfy the [number of atoms / atoms ratio], the density of the nc-OS and the density of the CAAC-OS are is 5.9g / cm 3 More than 6.3g / cm 3 It will be less than.

[0266] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions at any ratio are used. By combining single crystals, it is possible to calculate the density corresponding to a single crystal of the desired composition. The density of a single crystal of a desired composition can be determined by the ratio of the single crystals of different compositions combined. However, the density should be calculated using as few types of single crystals as possible. It is preferable to calculate them in combination.

[0267] The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or a microcrystalline oxide semiconductor. The layer may be a laminated film containing two or more of a compound semiconductor and a CAAC-OS.

[0268] Oxide semiconductors with low impurity concentrations and low defect state densities (few oxygen vacancies) have carrier Therefore, such an oxide semiconductor can be used as a high-purity intrinsic or The CAAC-OS and nc-OS are essentially high-purity intrinsic oxide semiconductors. The impurity concentration is lower than that of OS-like and amorphous oxide semiconductors, and the density of defect states is lower. That is, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor is likely to be obtained. The transistors using the CAAC-OS or nc-OS have a negative threshold voltage. In addition, the high purity intrinsic or In reality, high-purity intrinsic oxide semiconductors have few carrier traps. Transistors using C-OS or nc-OS have small fluctuations in electrical characteristics and high reliability. The charge trapped in the carrier traps in the oxide semiconductor is It takes a long time to release the charge, and it can behave as if it were a fixed charge. Therefore, a transistor using an oxide semiconductor with a high impurity concentration and a high density of defect states has a low The electrical characteristics may become unstable.

[0269] <Film formation model> An example of a film formation model for CAAC-OS and nc-OS will be described below.

[0270] FIG. 38(A) shows how a CAAC-OS film is formed by sputtering. FIG.

[0271] The target 5130 is attached to a backing plate. A plurality of magnets are disposed at positions facing the target 5130. The magnetic field is generated by the magnet. The magnetic field of the magnet is used to increase the deposition rate. The sputtering method is called magnetron sputtering.

[0272] The target 5130 has a polycrystalline structure, and each grain contains a cleavage plane.

[0273] As an example, the cleavage surface of a target 5130 having In-Ga-Zn oxide is described. FIG. 39(A) shows the crystal structure of InGaZnO4 contained in the target 5130. In addition, in FIG. 39(A), the c-axis is directed upward, and the InGaZnO This is the structure of the crystal of 4.

[0274] As shown in Figure 39(A), in two adjacent Ga-Zn-O layers, the oxide in each layer It can be seen that the atoms are arranged close to each other. As a result, two adjacent Ga-Zn-O layers repel each other. The ZnO4 crystal has a cleavage plane between two adjacent Ga-Zn-O layers.

[0275] The substrate 5120 is disposed facing the target 5130, and the distance between them is d (target The target-substrate distance (TS distance) is preferably 0.01 m or more and 1 m or less. The thickness of the film deposition chamber is set to 0.02m or more and 0.5m or less. Most of the film deposition gas (e.g., oxygen) It is filled with a gas mixture containing hydrogen, argon, or oxygen at a ratio of 5% by volume or more, and The pressure is controlled to be in the range of 0.1 Pa to 100 Pa, preferably in the range of 0.1 Pa to 10 Pa. By applying a voltage above a certain level to the target 5130, discharge begins and plasma is generated. It is noted that a high density plasma region is formed near the target 5130 by the magnetic field. In the high density plasma region, the deposition gas is ionized, and ions 5101 The ions 5101 are, for example, positive ions of oxygen (O +) and argon cations (A r + ) etc.

[0276] The ions 5101 are accelerated toward the target 5130 by the electric field, and eventually reach the target 5130. At this time, flat or pellet-shaped sputter particles are ejected from the cleavage plane. The pellets 5100a and 5100b are separated and knocked out. 5100a and pellet 5100b are impacted by the impact of ion 5101. Distortion may occur.

[0277] The pellet 5100a is a flat or pellet-shaped pellet having a triangular, for example, equilateral triangular, plane. The pellet 5100b has a hexagonal, for example, regular hexagonal, plane. The sputtered particles are in the form of a plate or pellet. Pellet 5100b and other flat or pellet-shaped sputter particles are collectively referred to as pellet 5. The planar shape of the pellet 5100 is not limited to a triangle or a hexagon. For example, a triangle (e.g., an equilateral triangle) may have a shape that is made up of multiple triangles. In some cases, two squares (e.g., a diamond) are joined together to form a rectangle.

[0278] The thickness of the pellet 5100 is determined depending on the type of deposition gas, etc. The reason for this will be described later. It is preferable that the thickness of the pellet 5100 is uniform. Thin pellets are preferable to thick cubes. The thickness of the 5100 is 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. For example, the pellet 5100 has a width of 1 nm or more and 3 nm or less, preferably The pellet 5100 is (1) in FIG. For example, the target 51 having In-Ga-Zn oxide corresponds to the initial nucleus described in . When ions 5101 are bombarded onto the Ga-Zn-O layer 30, as shown in FIG. A pellet 5100 having three layers, an In-O layer, a Ga-Zn-O layer, and an In-O layer, emerges. FIG. 39(C) shows the structure of the pellet 5100 when observed from a direction parallel to the c-axis. Therefore, the pellet 5100 consists of two Ga-Zn-O layers (pans) and an In- It can also be called a nano-sized sandwich structure having a layer (filler) and a layer (filler).

[0279] The pellet 5100 receives an electrical charge as it passes through the plasma, causing the sides to become negative or positive. The pellet 5100 has oxygen atoms on the side, and the oxygen atoms are negatively charged. In this way, the sides can be charged with the same polarity, The repulsion between the particles occurs, allowing the particles to maintain their flat shape. However, in the case of In-Ga-Zn oxide, the oxygen atoms bonded to the indium atoms are negatively charged. Or, an acid bonded to an indium atom, a gallium atom, or a zinc atom may The atoms may become negatively charged. Also, the pellet 5100 may become It grows by bonding with indium atoms, gallium atoms, zinc atoms, oxygen atoms, etc. The difference in size between (2) and (1) in Figure 37 above is due to the amount of growth in the plasma. Here, when the substrate 5120 is at room temperature, the pellet 5100 is Since the film does not grow, it becomes nc-OS (see Figure 38(B)). Therefore, even if the substrate 5120 has a large area, the nc-OS film can be formed. In order to grow the pellet 5100 in plasma, the growth method in the sputtering method Increasing the film forming power is effective. By increasing the film forming power, the pellet 5100 structure This can stabilize the structure.

[0280] As shown in Figures 38(A) and 38(B), for example, pellet 5100 is a plasma It flies through the air like a kite and flutters up onto the substrate 5120. Pellet 51 Because 00 is electrically charged, it approaches an area where other pellets 5100 have already accumulated. Here, on the upper surface of the substrate 5120, a repulsive force is generated. In addition, the substrate 5120 and the target 51 Since a potential difference is applied between the substrate 5120 and the target 5130, Therefore, the pellet 5100 is disposed on the upper surface of the substrate 5120. The magnetic field and the electric current act on the object, creating a force (Lorentz force). This can be understood by the left-hand rule.

[0281] The pellet 5100 has a larger mass than a single atom. In order to move the object, it is important to apply some kind of force from the outside. It is possible that the force is generated by the action of the field and the electric current. In order to increase the The magnetic field is 10 G or more, preferably 20 G or more, more preferably 30 G or more, and more preferably It is preferable to provide an area where the resistance is 50 G or more. The magnetic field parallel to the top surface of the substrate 5120 is 1.5 times stronger than the magnetic field perpendicular to the top surface of the substrate 5120. times or more, preferably two times or more, more preferably three times or more, and even more preferably five times or more. It is a good idea to set up an area for this purpose.

[0282] At this time, the magnet and the substrate 5120 move or rotate relative to each other. Therefore, the direction of the horizontal magnetic field on the upper surface of the substrate 5120 continues to change. On the upper surface of 5120, the pellet 5100 is subjected to forces in various directions and It can be moved.

[0283] Also, when the substrate 5120 is heated as shown in FIG. 38(A), the pellet 5100 The resistance due to friction between the substrate 5120 and the pellets is small. The pellet 5100 glides over the top surface of the substrate 5120. The movement occurs with the flat surface facing the substrate 5120. When the particles reach the side of the pellet 5100, the sides are joined together. The oxygen atom on the side of 0 is released. The released oxygen atom Since the electron vacancies may be filled, the CAAC-OS has a low defect level density. The temperature of the upper surface of 5120 is, for example, 100°C or more and less than 500°C, 150°C or more and less than 450°C. or 170° C. or more and less than 400° C. That is, when the substrate 5120 has a large area, In this case, it is possible to form a CAAC-OS film.

[0284] Furthermore, when the pellet 5100 is heated on the substrate 5120, the atoms are rearranged, and the The structural distortion caused by the collision of the pellet 5101 is relaxed. Pellet 5100 becomes almost single crystal. Even if the 100 is heated after bonding, the pellet 5100 itself hardly expands or contracts. Therefore, the gaps between the pellets 5100 widen, causing defects such as grain boundaries. It does not form depressions or crevasse formation.

[0285] In addition, the CAAC-OS is not made of a single-crystal oxide semiconductor. The aggregates of pellet 5100 (nanocrystals) are arranged like piles of bricks or blocks. In addition, there are no grain boundaries between them. Even if deformation such as shrinkage occurs in CAAC-OS due to heating or bending, local stress Therefore, flexible semiconductors can be The structure of nc-OS is suitable for biomedical devices. The arrangement is like they are stacked in order.

[0286] When the target is sputtered with ions, not only pellets but also zinc oxide etc. fly out. Since zinc oxide is lighter than the pellets, it may reach the top surface of the substrate 5120 first. And, 0.1 nm to 10 nm, 0.2 nm to 5 nm, or 0.5 A zinc oxide layer 5102 having a thickness of 2 nm or more is formed. A cross-sectional schematic diagram is shown in FIG.

[0287] As shown in FIG. 40(A), a pellet 5105a and a pellet Here, the pellets 5105a and 5105b are piled up. The pellets 5105c are arranged so that their sides are in contact with each other. After being deposited on pellet 5105b, the particles slide on pellet 5105b. In another aspect of 5a, a plurality of particles 510 ejected from the target along with zinc oxide. 3 is crystallized by heating the substrate 5120, forming a region 5105a1. The atoms 5103 may include oxygen, zinc, indium, and gallium, among others.

[0288] Then, as shown in FIG. 40(B), the region 5105a1 is assimilated with the pellet 5105a. 5105a2. The pellet 5105c has a side surface similar to that of the pellet 5105a. Place it so that it touches the other side of 05b.

[0289] Next, as shown in FIG. 40(C), a pellet 5105d is further formed on the pellet 5105a2. and pellet 5105b, and then on pellet 5105a2 and pellet 51 It slides on the other side of the pellet 5105c. The pellet 5105e slides over the zinc oxide layer 5102.

[0290] As shown in FIG. 40(D), the pellet 5105d has a side surface similar to that of the pellet 510. The pellet 5105e is placed so that its side faces the pellet. Also, the other side of the pellet 5105d is arranged so as to be in contact with the other side of the pellet 5105c. In the process, a plurality of particles 5103 that fly out from the target together with zinc oxide are deposited on the substrate 512. 0, it crystallizes and forms a region 5105d1.

[0291] As described above, the piled pellets are arranged so that they come into contact with each other, and the pellets are bonded to each other on their side surfaces. Crystal growth occurs, forming a CAAC-OS on the substrate 5120. The individual pellets of AAC-OS are larger than those of nc-OS. This corresponds to the difference in size between (3) and (2) in 37.

[0292] In addition, the gaps between the pellets 5100 become extremely small, so that one large pellet is formed. The large pellets may have a single crystal structure. The size is 10 nm to 200 nm, 15 nm to 100 nm, or Therefore, the channel of the transistor may be When the formation region is smaller than a large pellet, it has a single crystal structure as the channel formation region. In addition, the pellet size is increased, so that the transistor chip size can be increased. Regions having a single crystal structure are used as the channel forming region, source region, and drain region. It may be possible.

[0293] In this way, the channel formation region of the transistor and the like are formed in a region having a single crystal structure. This may improve the frequency characteristics of the transistor.

[0294] Based on the above model, it is considered that the pellet 5100 accumulates on the substrate 5120. Therefore, unlike epitaxial growth, if the surface to be formed does not have a crystalline structure, For example, it is possible to form a CAAC-OS film on the substrate 5120. Even if the structure of the upper surface (surface to be formed) is amorphous (e.g., amorphous silicon oxide), It is possible to form a C-OS film.

[0295] In addition, even if the upper surface of the substrate 5120 on which the formation is to be performed is uneven, the CAAC-OS For example, the pellets 5100 are arranged along the shape of the upper surface of the substrate 5120. If the surface is atomically flat, the pellet 5100 will be placed with the flat surface, which is parallel to the ab plane, facing downwards. When the thickness of the pellet 5100 is uniform, the thickness is uniform, flat, and high. A layer with high crystallinity is formed. Then, the layer is stacked in n stages (n is a natural number). CAAC-OS can be obtained by

[0296] On the other hand, even if the upper surface of the substrate 5120 has unevenness, the CAAC-OS can be easily formed by the pellet 510 The structure is made up of n layers (n is a natural number) of layers in which 0s are arranged along the unevenness. Since the surface 20 has unevenness, gaps tend to occur between the pellets 5100. However, there is an intermolecular force between the pellets, so even if there are irregularities, the The gaps are arranged to be as small as possible. Therefore, even if there are irregularities, high crystallinity is maintained. It can be called CAAC-OS.

[0297] Therefore, CAAC-OS does not require laser crystallization and can be used on large-area glass substrates. Even if there is a problem, uniform film formation is possible.

[0298] Since the CAAC-OS film is formed using this model, the sputtered particles have a small thickness. It is preferable that the sputtered particles are in the form of pellets. However, the surface facing the substrate 5120 may not be uniform, and the thickness and crystal orientation may not be uniform. be.

[0299] The film formation model shown above allows for the formation of highly crystalline films even on a surface with an amorphous structure. A CAAC-OS having the formula:

[0300] (Embodiment 3) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention is shown in FIG. This will be explained with reference to the following.

[0301] [Circuit configuration example] In the configuration shown in Embodiment 1, the connection configuration of the transistors, wirings, and electrodes may be changed. By using the semiconductor device according to one embodiment of the present invention, various circuits can be configured. An example of a circuit configuration that can be realized by using the device will be described.

[0302] [CMOS Circuit] The circuit diagram shown in FIG. 21A includes a p-channel transistor 2200 and an n-channel transistor The transistors 2100 are connected in series and the gates of the transistors are connected together. The figure shows the configuration of an OS circuit. In addition, in the figure, a transistor using the second semiconductor material is are indicated with the symbol "OS."

[0303] [Analog Switch] The circuit diagram shown in FIG. 21B shows the transistors 2100 and 2200. The figure shows a configuration in which the source and drain of each are connected. It can function as a so-called analog switch.

[0304] [Example of storage device] By using a transistor according to one embodiment of the present invention, it is possible to keep the stored contents even when power is not supplied. An example of a semiconductor device (memory device) that can retain data and has no limit on the number of times it can be written is shown in Figure 2. 1(C).

[0305] The semiconductor device shown in FIG. 21C includes a transistor 3200 using a first semiconductor material and The semiconductor device includes a transistor 3300 and a capacitor 3400 made of a second semiconductor material. Note that the transistor 3300 is any of the transistors exemplified in the above embodiments. It is possible.

[0306] The transistor 3300 is a transistor in which a channel is formed in a semiconductor film including an oxide semiconductor. The transistor 3300 has a small off-state current, so that It is possible to retain the stored contents for a longer period of time, i.e., no refresh operation is required. A semiconductor memory device that does not require refresh operations or requires extremely low frequency of refresh operations. This makes it possible to sufficiently reduce power consumption.

[0307] In FIG. 21C, a first wiring 3001 is connected to a source electrode of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is connected to the source electrode of the transistor 3300 or The fourth wiring 3004 is electrically connected to one of the drain electrodes of the transistor 3300. The gate electrode of the transistor 3200 is electrically connected to the The other of the source electrode and the drain electrode of the transistor 3300 is connected to the capacitor 3400. The fifth wiring 3005 is electrically connected to one of the electrodes of the capacitor 3400. are electrically connected.

[0308] In the semiconductor device shown in FIG. 21C, the potential of the gate electrode of the transistor 3200 is maintained. By taking advantage of this feature, it is possible to write, store, and read information as follows: be.

[0309] Writing and holding of data will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and That is, the gate electrode of the transistor 3200 is supplied with a predetermined A constant charge is applied (write). Here, two different potential levels are applied ( Hereinafter, either the low-level charge or the high-level charge is given. After that, the potential of the fourth wiring 3004 is set to a potential that turns off the transistor 3300. By turning off the transistor 3300, the gate of the transistor 3200 The charge applied to the electrode is retained (retention).

[0310] Since the off-state current of the transistor 3300 is extremely small, the gate The charge on the electrode is maintained for a long period of time.

[0311] Next, reading of information will be described. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the transistor Depending on the amount of charge held in the gate electrode of the transistor 3200, the second wiring 3002 has different potentials. Generally, if the transistor 3200 is an n-channel type, the transistor 320 The apparent threshold voltage V when a high level charge is applied to the gate electrode of th_ H is the state when a low level charge is applied to the gate electrode of transistor 3200. Threshold Vth_L Here, the apparent threshold voltage is The potential of the fifth wiring 3005 required to turn on the transistor 3200 is Therefore, the potential of the fifth wiring 3005 is V th_H and V th_L Between By setting the potential V0 at the gate electrode of the transistor 3200, the charge applied to the gate electrode of the transistor 3200 can be determined. For example, if a high level charge is applied during writing, The potential of the fifth wiring 3005 is V0 (>V th_H ), then transistor 3200 is " When a low level charge is applied, the fifth wiring 3005 is in the "ON state." The potential is V0( <V th_L ), transistor 3200 remains in the "off state" Therefore, the stored data can be read by determining the potential of the second wiring 3002. It can be seen.

[0312] When memory cells are arranged in an array, only the information in the desired memory cell can be read. In this way, if the information is not read out, the state of the gate electrode The potential at which transistor 3200 is in the "off state" regardless of V th_ H A smaller potential may be applied to the fifth wiring 3005. Alternatively, depending on the state of the gate electrode, The potential at which transistor 3200 remains "on," i.e., V th_L Yo A potential larger than the potential at the fifth wiring 3005 may be applied to the fifth wiring 3005 .

[0313] 21(A) and the wiring 3001 in FIG. 21(C). A cross-sectional view of the structure in which the wiring 3003 is shared is shown in FIG. The cross-sectional view of Figure 21(A) is shown on the left side of the dotted line, and the cross-sectional view of the circuit diagram of Figure 21(C) is shown on the left side of the dotted line. show.

[0314] As shown in the figure, a transistor 3200 and a transistor located above the transistor 3200 3300, and by stacking these, the area occupied by the element can be reduced. Furthermore, since the capacitor element 3400 is located below the transistor 3300, By stacking these, the area occupied by the element can be reduced. Since the line 3005 has an overlapping area with the gate electrode of the transistor 3300, Furthermore, the area occupied by the element can be reduced.

[0315] Also, as shown in FIG. 23, the transistor 3300 and the transistor 2100 are fabricated in separate processes. It may be configured as follows.

[0316] The semiconductor device shown in FIG. 21D is different from the semiconductor device shown in FIG. 2 mainly in that the transistor 3200 is not provided. In this case, the same operations as above are performed to write and store information. It is possible to create

[0317] Next, the reading of information will be described. When the transistor 3300 is turned on, The third wiring 3003 in a floating state and the capacitor element 3400 are electrically connected to each other. As a result, the potential of the third wiring 3003 is The amount of change in the potential of the third wiring 3003 is the potential of one of the electrodes of the capacitor 3400. (or the charge stored in the capacitor 3400).

[0318] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, and the The capacitance component of the third wiring 3003 is CB, and the capacitance of the third wiring 3003 before the charge is redistributed is If the potential of the third wiring 3003 after the charge is redistributed is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB ×VB0+C×V) / (CB+C). Therefore, the state of the memory cell is If the potential of one of the electrodes of the element 3400 takes two states, V1 and V0 (V1>V0), then: The potential of the third wiring 3003 when the potential V1 is maintained (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is maintained (=( It can be seen that this is higher than (CB×VB0+C×V0) / (CB+C)).

[0319] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. This can be done.

[0320] In this case, the first semiconductor material is applied to a drive circuit for driving the memory cells. The transistor 3300 is a transistor in which a second semiconductor material is applied. The transistor may be stacked on the driver circuit.

[0321] In the semiconductor device described in this embodiment, an off-state current is generated by using an oxide semiconductor in a channel formation region. By applying transistors with extremely low current, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is not required or the refresh operation is Since it is possible to reduce the frequency of operation extremely, power consumption can be reduced significantly. In addition, even if there is no power supply (however, it is desirable that the potential is fixed), Even if there is a problem, it is possible to retain the stored contents for a long period of time.

[0322] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem of element degradation. For example, unlike conventional non-volatile memory, This eliminates the need to inject electrons into the floating gate or extract electrons from the floating gate. Therefore, the problem of deterioration of the gate insulating layer does not occur. In this device, there is no limit to the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and it is reliable. Furthermore, the on / off state of the transistor determines the writing and reading of information. Since the data is written into the memory, high speed operation can be easily achieved.

[0323] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0324] (Fourth embodiment) In this embodiment, the R The FID tag will be explained with reference to FIG.

[0325] The RFID tag in this embodiment has a memory circuit therein, and stores necessary information in the memory circuit. The information is stored in the memory and transmitted to and from the outside using a non-contact means, for example, wireless communication. Due to these characteristics, RFID tags can identify items by reading their individual information. It can be used for individual authentication systems that distinguish between people. To achieve this, extremely high reliability is required.

[0326] The structure of the RFID tag will be described with reference to Fig. 24. Fig. 24 shows the structure of the RFID tag. FIG. 1 is a block diagram illustrating an example.

[0327] As shown in FIG. 24, an RFID tag 800 includes a communicator 801 (such as an interrogator or reader / writer). 803 is transmitted from an antenna 802 connected to the The RFID tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, and a , a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that a reverse current is applied to a transistor having a rectifying effect included in the demodulation circuit 807. A material capable of sufficiently suppressing the above-mentioned problem, for example, an oxide semiconductor may be used. This prevents the degradation of rectification caused by reverse current and prevents the output of the demodulation circuit from saturating. In other words, the output of the demodulation circuit relative to the input of the demodulation circuit is made nearly linear. The data transmission format is a pair of coils arranged facing each other and transmitted by mutual induction. the electromagnetic coupling method, which communicates by electromagnetic induction, which communicates by electromagnetic induction, and the electromagnetic wave method, which communicates by electromagnetic induction. The RFID tag 800 shown in this embodiment is It is possible to use either of the above methods.

[0328] Next, the configuration of each circuit will be explained. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 805 adjusts the input AC signal generated by receiving a radio signal with the antenna 804. For example, half-wave double voltage rectification is performed, and the rectified signal is averaged by a capacitive element provided in the subsequent stage. The rectifier circuit 805 is a circuit for generating an input potential by smoothing the input voltage. A limiter circuit may be provided on the output side. When the internally generated voltage is large, power above a certain level is not input to the subsequent circuit. This is a circuit for controlling the

[0329] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the stable rise of the power supply voltage to reset the logic circuit 8. This is a circuit for generating the reset signal for 09.

[0330] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation in response to the

[0331] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. , a circuit that holds input information, such as a row decoder, a column decoder, a memory area, etc. The ROM 811 stores a unique number (ID) and outputs it according to the processing. This is a circuit for doing this.

[0332] The above-mentioned circuits can be selected or removed as needed.

[0333] Here, the memory device described in the above embodiment can be used as the memory circuit 810. The memory circuit of one embodiment of the present invention can retain data even when power is cut off. Furthermore, the memory circuit of one embodiment of the present invention can be suitably used for an RFID tag. The power (voltage) required to write data is significantly lower than that of conventional non-volatile memory. It is also possible to eliminate the difference in maximum communication distance when reading and writing data. Furthermore, it is possible to prevent malfunctions or erroneous writing due to a lack of power when writing data. It is possible.

[0334] The memory circuit of one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the manufacturer must A separate command is provided to write data, preventing users from freely rewriting it. It is preferable that the manufacturer writes the unique number on the product before shipping it. Therefore, instead of assigning a unique number to each RFID tag produced, This allows the allocation of unique numbers only to individual products, and the unique numbers of products will not be consecutive after shipment. This makes it easier to manage customers' accounts after products are shipped without having to worry about the need to return them to the supplier.

[0335] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0336] (Embodiment 5) In this embodiment, at least the transistors described in the embodiment can be used. Next, a CPU including the storage device described in the previous embodiment will be described.

[0337] FIG. 25 shows a CPU using the transistors described in the previous embodiments at least in part. FIG. 1 is a block diagram showing an example of a configuration.

[0338] The CPU shown in FIG. 25 includes an ALU 1191 (Arithmetic and logic unit) on a board 1190. tic logic unit, arithmetic circuit), ALU controller 1192, instruction Action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, an SOI substrate, The ROM 1199 and the ROM interface 1189 are It may be provided on a separate chip. Of course, the CPU shown in FIG. 25 is a simplified version of the configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their uses. For example, 25 is a core, and a configuration including a CPU or an arithmetic circuit shown in FIG. 25 is a core. Alternatively, each core may be configured to operate in parallel. The number of bits that can be handled by a circuit or data bus is, for example, 8 bits, 16 bits, 32 bits, 64 bits. It can be a cot, etc.

[0339] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, Interrupt controller 1194, register controller 1197, timing controller It is entered into La1195.

[0340] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to trigger the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it accordingly. Generates an address and reads or writes register 1196 depending on the CPU state. .

[0341] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal CLK1 based on the reference clock signal CLK1. The internal clock generating unit generates the internal clock signal CLK2. It is supplied to various circuits.

[0342] In the CPU shown in FIG. 25, a memory cell is provided in the register 1196. The transistor described in the above embodiment can be used as the memory cell of the memory cell 1196. Cut.

[0343] In the CPU shown in FIG. 25, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. If data retention in the capacitor is selected, rewriting data to the capacitor The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0344] FIG. 26 is a circuit diagram of an example of a storage element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A circuit 1202 in which memory data is not volatile, a switch 1203, a switch 1204, and a logic The circuit includes an element 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor element 1208, a transistor 1209, and a transistor 1210. The memory element 1200 may include a diode, a resistor, an inductor, etc., as needed. It may further include other elements such as a converter.

[0345] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of power supply voltage to the memory element 1200 is stopped, the transistor 12 The gate of 09 is supplied with ground potential (0V) or a potential that turns off transistor 1209. For example, the gate of the transistor 1209 is connected to the load such as a resistor. It is configured to be grounded.

[0346] The switch 1203 uses a transistor 1213 of one conductivity type (for example, n-channel type). The switch 1204 is configured with a conductivity type opposite to the one conductivity type (for example, a p-channel type). Here, the first transistor 1214 of the switch 1203 is used. The terminal corresponds to one of the source and drain of the transistor 1213, and the first terminal of the switch 1203. The terminal 2 corresponds to the other of the source and drain of the transistor 1213, and the terminal 3 corresponds to the other of the source and drain of the switch 1203. The first terminal and the second terminal are connected by a control signal RD input to the gate of the transistor 1213. Conduction or non-conduction between the terminals of the transistor 1213 (i.e., the on-state or off-state of the transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the transistor 1214. The switch 1204 is connected to the gate of the transistor 1214. The control signal RD input to the first terminal determines whether or not the first terminal is electrically connected to the second terminal. The on or off state of transistor 1214 is selected.

[0347] One of the source and drain of the transistor 1209 is connected to one of the pair of electrodes of the capacitor 1208. The connection point is electrically connected to one of the gate electrodes of the transistor 1210 and the gate of the transistor 1210. The node M2 ​​is connected to the source or drain of the transistor 1210. The other is electrically connected to a wiring (for example, a GND line) that can supply 1203 (one of the source and drain of the transistor 1213) The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the The other terminal of the switch 1204 (one of the source and drain terminals of the transistor 1214) The second terminal of the switch 1204 (the source of the transistor 1214) is electrically connected to the The other of the source and drain terminals is electrically connected to the wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) and the first terminal of the switch 1204 (one of the source and drain of the transistor 1214) ), an input terminal of the logic element 1206, and one of a pair of electrodes of the capacitor 1207. are electrically connected. Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a line that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a line (for example, a GND line). For example, a low power supply potential (such as GND) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitor element 120. The other of the pair of electrodes 8 is connected to a wiring (e.g., GND) that can supply a low power supply potential. The power supply is electrically connected to the power supply line.

[0348] The capacitors 1207 and 1208 are used to reduce the parasitic capacitance of transistors and wirings. It is possible to omit it by actively using it.

[0349] A control signal WE is input to the first gate (first gate electrode) of the transistor 1209. The switches 1203 and 1204 are connected to a control signal RD, which is different from the control signal WE. A conductive state or a non-conductive state between the first terminal and the second terminal is selected by When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the second terminal of the other switch are in a conductive state. There is no conduction between terminals 2.

[0350] The other of the source and drain of the transistor 1209 is connected to a data terminal of the circuit 1201. In FIG. 26, the signal output from the circuit 1201 is The example shown is input to the other of the source and drain of the transistor 1209. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and the inverted signal is output via the circuit 1220. and input to the circuit 1201.

[0351] In FIG. 26, the second terminal of the switch 1203 (the source of the transistor 1213) The signal output from the other drain is routed through logic element 1206 and circuit 1220. The example shown is an input to the circuit 1201, but is not limited to this. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the following may be included in the circuit 1201: When there is a node that holds a signal whose logical value is the inverse of the signal input from the input terminal The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the node can be input to the node.

[0352] In addition, in FIG. 26, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed on a layer or substrate 11 made of a semiconductor other than an oxide semiconductor. 90. For example, a silicon layer or The memory element may be a transistor in which a channel is formed in a silicon substrate. All the transistors used in the element 1200 are transistors whose channels are formed using oxide semiconductor films. Alternatively, the storage element 1200 may be a transistor 1209 or a In addition, a transistor in which a channel is formed using an oxide semiconductor film may be included. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It may also be a transistor formed by

[0353] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0354] In the semiconductor device according to one embodiment of the present invention, a power supply voltage is not supplied to the memory element 1200. During this time, the data stored in the circuit 1201 is transferred to the capacitor 12 It can be held by 08.

[0355] In addition, a transistor in which a channel is formed in an oxide semiconductor film has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor film varies depending on the crystallinity. The off-state current is significantly lower than that of a transistor having a channel formed in silicon. Therefore, by using the transistor as the transistor 1209, Even when the power supply voltage is not supplied to the capacitor 1200, the signal held in the capacitor 1208 is maintained for a long period of time. In this way, the memory element 1200 can maintain its stored contents ( It is possible to retain the data.

[0356] Furthermore, by providing the switches 1203 and 1204, the precharge operation Since the memory element is characterized by performing the above operation, after the power supply voltage is restarted, the circuit 1201 This reduces the time required to restore the original data.

[0357] In the circuit 1202, the signal held by the capacitor 1208 is transferred to the transistor. Therefore, the supply of the power supply voltage to the memory element 1200 is restarted. After the capacitor 1208 is opened, the signal held by the capacitor 1208 is transferred to the transistor 1210 (ON state or OFF state) and can be read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitor element 1208 fluctuates slightly, the original signal It is possible to read out the number accurately.

[0358] Such a storage element 1200 may be a register or cache memory of a processor. By using this in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one of the components of the processor, In addition, power can be stopped for a short period of time in multiple logic circuits, reducing power consumption. can be suppressed.

[0359] In this embodiment, the storage element 1200 is used as a CPU. The 1200 is equipped with a DSP (Digital Signal Processor), custom LSIs such as LSIs and PLDs (Programmable Logic Devices), Also compatible with RF-ID (Radio Frequency Identification) It is available.

[0360] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0361] (Embodiment 6) In this embodiment, a structural example of a display panel according to one embodiment of the present invention will be described.

[0362] [Configuration example] FIG. 27A is a top view of a display panel of one embodiment of the present invention, and FIG. 27B is a top view of a display panel of one embodiment of the present invention. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display panel according to one embodiment of the present invention. 27C is a circuit diagram illustrating a display panel according to one embodiment of the present invention. A circuit for explaining a pixel circuit that can be used when an organic EL element is applied to a pixel. Figure.

[0363] The transistors disposed in the pixel portion can be formed according to the above-described embodiment modes. In addition, since the transistor can be easily made into an n-channel type, the n-channel transistor in the driver circuit can be easily made into an n-channel type. A part of the driver circuit can be configured with a panel-type transistor, and the transistors in the pixel section can be In this way, the transistor shown in the above embodiment mode is formed in the pixel portion and the driver circuit. By using the capacitor, a highly reliable display device can be provided.

[0364] An example of a block diagram of an active matrix display device is shown in FIG. On this substrate 700, a pixel section 701, a first scanning line driving circuit 702, a second scanning line driving circuit 703, and a The pixel portion 701 has a signal line driver circuit 703 and a signal line driver circuit 704. A plurality of scanning lines are arranged extending from a first scanning line driving circuit 702 and a second scanning line driving circuit 704. The scanning lines are arranged extending from the second scanning line driving circuit 703. In the area, pixels each having a display element are arranged in a matrix. The substrate 700 of the device is a connection board such as an FPC (Flexible Printed Circuit). It is connected to a timing control circuit (also called a controller or control IC) via a connection. do.

[0365] In FIG. 27A, a first scanning line driver circuit 702, a second scanning line driver circuit 703, a signal The line driver circuit 704 is formed on the same substrate 700 as the pixel portion 701. The number of components such as drive circuits to be provided is reduced, which contributes to cost reduction. 700 If an external drive circuit is provided, it becomes necessary to extend the wiring, and the number of connections between the wiring increases. When a driver circuit is provided on the same substrate 700, the number of connections between the wirings can be reduced. This can improve reliability or yield.

[0366] [LCD panel] An example of the circuit configuration of a pixel is shown in Figure 27(B). 1 shows a pixel circuit that can be applied to the pixel of FIG.

[0367] This pixel circuit can be applied to a configuration in which one pixel has a plurality of pixel electrodes. The pixel electrodes are connected to different transistors, and each transistor can be driven by a different gate signal. This allows the individual pixel voltages of the multi-domain designed pixels to be The signals applied to the poles can be controlled independently.

[0368] The gate wiring 712 of the transistor 716 and the gate wiring 713 of the transistor 717 are separated so that different gate signals can be applied. The source or drain electrode 714, which functions as a transistor 716, is connected to the transistor The transistors 716 and 717 are used in common. The transistors described in the embodiments can be appropriately used. A display panel can be provided.

[0369] A first pixel electrode electrically connected to the transistor 716 and a second pixel electrode electrically connected to the transistor 717 The shape of the second pixel electrode that is electrically connected to the first pixel electrode and the second pixel electrode will be described. The first pixel electrode has a V-shaped configuration separated by a slit. The second pixel electrode is formed so as to surround the outside of the first pixel electrode.

[0370] The gate electrode of the transistor 716 is connected to the gate wiring 712, and the gate electrode of the transistor 717 is connected to the gate wiring 712. The gate electrode of the gate electrode 712 is connected to the gate wiring 713. 3, different gate signals are applied to transistors 716 and 717. By varying the voltage, the orientation of the liquid crystal can be controlled.

[0371] Also, a capacitance wiring 710, a gate insulating film functioning as a dielectric, and a first pixel electrode or A storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode.

[0372] The multi-domain structure has a first liquid crystal element 718 and a second liquid crystal element 719 in one pixel. The first liquid crystal element 718 is composed of a first pixel electrode, a counter electrode, and a liquid crystal layer therebetween. The second liquid crystal element 719 is composed of a second pixel electrode, a counter electrode, and a liquid crystal layer therebetween.

[0373] It should be noted that the pixel circuit shown in FIG. 27(B) is not limited to this. For example, The pixel shown has a new switch, resistor, capacitor, transistor, sensor, or logic circuit. You can also add roads etc.

[0374] [Organic EL panel] Another example of the circuit configuration of a pixel is shown in FIG. 27(C). 1 shows the pixel structure of the display panel.

[0375] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are emitted from one of the pair of electrodes. and holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The recombination of electrons and holes causes the light-emitting organic compound to form an excited state, which This mechanism is what causes this type of luminescence. The element is called a current-excited light-emitting element.

[0376] FIG. 27C is a diagram showing an example of an applicable pixel circuit. An example in which two transistors are used in one pixel is shown. can be used for the channel formation region of an n-channel transistor. The pixel circuit can be applied with digital time gray scale driving.

[0377] Regarding the configuration of applicable pixel circuits and pixel operation when digital time gray scale driving is applied, and explain.

[0378] The pixel 720 includes a switching transistor 721, a driving transistor 722, and a light emitting element. The switching transistor 721 has a gate element 724 and a capacitor element 723. The gate electrode is connected to the scanning line 726, and the first electrode (one of the source electrode and the drain electrode) is The second electrode (the other of the source electrode and the drain electrode) is connected to the signal line 725. The driving transistor 722 is connected to the gate electrode of the driving transistor 722. The first electrode is connected to a power supply line 727 via a capacitor element 723, and the second electrode is connected to the power supply line 727. The second electrode is connected to the first electrode (pixel electrode) of the light emitting element 724. The second electrode of 4 corresponds to the common electrode 728. The common electrode 728 is formed on the same substrate. It is electrically connected to the common potential line.

[0379] The switching transistor 721 and the driving transistor 722 are the same as those in the above embodiment. The transistors described below can be used as appropriate. This allows for a highly reliable organic EL display. A display panel can be provided.

[0380] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. The low power supply potential is a potential lower than the high power supply potential set to the power supply line 727, for example, GN The low power supply potential can be set to D, 0V, etc. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the light emitting element 72. By applying a voltage to the light emitting element 724, a current flows through the light emitting element 724, causing it to emit light. The forward voltage of 24 refers to the voltage required to achieve the desired brightness, and is at least Includes threshold voltage.

[0381] The capacitor 723 is substituted for the gate capacitance of the driving transistor 722. The gate capacitance of the driving transistor 722 can be omitted. A capacitance may be formed between the gate electrode and the electrode.

[0382] Next, a description will be given of the signal input to the driving transistor 722. Voltage input voltage driving In this method, the driving transistor 722 is in two states: fully on or off. A video signal that becomes a pixel value is input to the driving transistor 722. In order to operate the motor 722 in the linear region, a voltage higher than the voltage of the power supply line 727 is applied to the drive A signal line 725 is applied to the gate electrode of the transistor 722. A voltage equal to or greater than the threshold voltage Vth of the input transistor 722 is applied.

[0383] When analog gradation driving is performed, the gate electrode of the driving transistor 722 is connected to the light emitting element 72 A voltage equal to or greater than the sum of the forward voltage of the transistor 724 and the threshold voltage Vth of the driving transistor 722 is applied. In addition, a video signal is input so that the driving transistor 722 operates in the saturation region. A current flows through the light emitting element 724. In addition, the driving transistor 722 is operated in a saturation region. In order to achieve this, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By converting the video signal into an analog signal, a current corresponding to the video signal is passed through the light emitting element 724. , analog gray scale driving can be performed.

[0384] The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. The pixel circuit shown in 7(C) may include a switch, a resistor, a capacitor, a sensor, a transistor, or A logic circuit or the like may be added.

[0385] When the transistors exemplified in the above embodiments are applied to the circuit illustrated in FIG. The source electrode (first electrode) is on the low potential side, and the drain electrode (second electrode) is on the high potential side. Furthermore, the potential of the first gate electrode is controlled by a control circuit or the like. The second gate electrode is supplied with a potential lower than that applied to the source electrode by a wiring (not shown). Any of the above-mentioned potentials may be input.

[0386] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0387] (Embodiment 7) The semiconductor device according to one aspect of the present invention is used in a display device, a personal computer, a recording medium, and the like. Image playback device (typically DVD: Digital Versatile Disk) c) a device having a display that can play back a recording medium such as a In addition, electronic devices in which the semiconductor device according to one embodiment of the present invention can be used As mobile phones, handheld game consoles, portable data terminals, e-books, video cameras, Cameras such as digital still cameras, goggle-type displays (head-mounted displays) navigation systems, audio playback devices (car audio, digital audio players) Layers, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 28. .

[0388] FIG. 28A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display 904, microphone 905, speaker 906, operation keys 907, stylus 90 8. The portable game machine shown in FIG. 28(A) has two display units 903 and a display However, the number of display units that the portable game machine has is not limited to this. stomach.

[0389] FIG. 28(B) shows a portable data terminal, which includes a first housing 911, a second housing 912, a first display unit The first display unit 91 has a first display unit 913, a second display unit 914, a connection unit 915, an operation key 916, etc. 3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connecting portion 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. The display may be switched according to the angle between the first display unit 913 and the second display unit 912. and a display device to which a function as a position input device is added to at least one of the first display unit 911 and the second display unit 912. The function as a position input device may be realized by using a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a panel. It can also be added by providing a photoelectric conversion element, also called a photo sensor, in the pixel part of the display device. can be done.

[0390] FIG. 28C shows a notebook personal computer, which includes a housing 921, a display portion 922, It has a keyboard 923, a pointing device 924, and the like.

[0391] FIG. 28(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, a freezer compartment door 933, and a He has 33 etc.

[0392] FIG. 28(E) shows a video camera, which includes a first housing 941, a second housing 942, and a display unit 943. , an operation key 944, a lens 945, a connection part 946, etc. 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connecting portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 94 at the connection unit 946. 2.

[0393] FIG. 28(F) shows a standard automobile, which includes a body 951, wheels 952, a dashboard 953, It has Light 954 etc.

[0394] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0395] (Embodiment 8) In this embodiment, an example of use of an RFID according to one embodiment of the present invention will be described with reference to FIG. 29. RFID has a wide range of uses, including banknotes, coins, securities, and unregistered Bonds, certificates (driver's licenses, resident cards, etc., see Figure 29(A)), recording media (DVDs and videos) Deotape, etc., see Figure 29(B), packaging containers (wrapping paper, bottles, etc., see Figure 29(C) (See Figure 29(D)), vehicles (bicycles, etc., see Figure 29(D)), personal belongings (bags, glasses, etc.), food, Plants, animals, the human body, clothing, daily necessities, medical products including medicines and pharmaceuticals, or electronic devices ( LCD displays, EL displays, televisions, or mobile phones) or other items It can be attached to tags (see Figure 29(E) and Figure 29(F)) that are attached to each item. can.

[0396] The RFID 4000 according to one embodiment of the present invention can be attached to or embedded in a surface, It is fixed to the object. For example, if it is a book, it is embedded in the paper and the packaging is made of organic resin. If the RFI is used, it is embedded in the organic resin and fixed to each article. The D4000 is small, thin, and lightweight, so even after it is fixed to an object, it retains the device's original shape. It does not impair the design of banknotes, coins, securities, bearer bonds, or certificates. By providing an RFID 4000 according to one aspect of the present invention to a document or the like, an authentication function is provided. By utilizing this authentication function, it is possible to prevent counterfeiting. The present invention can be applied to vessels, recording media, personal belongings, food, clothing, household goods, electronic devices, etc. By attaching an RFID tag according to one aspect, the efficiency of a system such as an inspection system can be improved. Furthermore, even in the case of vehicles, the RFID tag according to one aspect of the present invention can be attached. This can improve security against theft and the like.

[0397] As described above, the RFID according to one aspect of the present invention can be used for the applications listed in this embodiment. This reduces the operating power consumption, including that for writing and reading information, thereby extending the maximum communication distance. It is also possible to keep the information for a very long time even when the power is cut off. Since it can be retained for a long period of time, it can be used suitably for applications where writing and reading are not performed frequently. can.

[0398] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. [Example]

[0399] In this example, cross-sectional observation was performed on an insulating film and an opening formed in an oxide semiconductor film. .

[0400] First, the method for preparing sample A, which was used for cross-sectional observation, will be described below.

[0401] First, a silicon wafer is thermally oxidized to form a 100 nm thermal oxide film on the surface of the silicon wafer. The thermal oxidation conditions were 950°C for 4 hours, and the thermal oxidation atmosphere was HCl in oxygen. The content was set to 3% by volume.

[0402] Next, the thermal oxide film 200 was etched by 100 nm.

[0403] Next, a tungsten target was used, and argon ( Ar) gas atmosphere, pressure 0.8 Pa, substrate temperature 230 °C, target and substrate The sputtering method was performed under the conditions of a distance of 60 mm and a power supply (DC) of 1.0 kW. Thus, a tungsten film 201 was formed to a thickness of 50 nm.

[0404] Next, tetraethoxysilane (TEOS) at a flow rate of 15 sccm and 750 sccm The substrate temperature was set at 300°C and a 27MHz high frequency power source was used. A silicon oxide film was deposited on the substrate by the CVD method, in which 300 W of high frequency power was supplied to parallel plate electrodes. A film of 00 nm was formed.

[0405] Next, an aluminum oxide target was used, and argon gas with a flow rate of 25 sccm was used as the deposition gas. Argon (Ar) gas and oxygen (O2) gas at a flow rate of 25 sccm were used, and the pressure was set at 0.4 Pa. The substrate temperature was set to 250°C, the distance between the target and the substrate was set to 60 mm, and the RF power was set to 2.5 kW. An aluminum oxide film was formed to a thickness of 20 nm by sputtering under conditions in which the temperature was increased.

[0406] Next, silane (SiH4) with a flow rate of 1 sccm and nitrous oxide ( N2O) was used as the source gas, the pressure in the reaction chamber was 200 Pa, the substrate temperature was 350 °C, and the frequency was 60 MHz. Using a high-frequency power supply, 150W of high-frequency power was supplied to parallel plate electrodes by the CVD method. A silicon oxynitride film was formed to a thickness of 50 nm.

[0407] Next, a 20 nm thick first oxide semiconductor film and a 15 nm thick second oxide semiconductor film were formed by sputtering. The first oxide semiconductor film was deposited under the conditions of In:Ga:Zn= A target with an atomic ratio of 1:3:4 was used, and argon (Ar) and In a mixed atmosphere of oxygen (O2) with a flow rate of 5 sccm, the pressure was 0.7 Pa and the power supply power ( DC 0.5kW was applied, the distance between the target and the substrate was 60mm, and the substrate temperature was 200℃. The second oxide semiconductor film was formed as follows: In:Ga:Zn=4:2:4.1 [atomic ratio] A target of 30 sccm argon (Ar) and 15 sccm acid were used. In a mixed atmosphere of oxygen (O2), a pressure of 0.7 Pa and a power supply (DC) of 0.5 kW were applied. The film was formed by applying a ion beam to the target, setting the distance between the target and the substrate to 60 mm, and setting the substrate temperature to 200°C.

[0408] Next, a tungsten target was used, and argon ( Ar) gas atmosphere, pressure 0.8 Pa, substrate temperature 230 °C, target and substrate The sputtering method was performed under the conditions of a distance of 60 mm and a power supply (DC) of 1.0 kW. This tungsten film was formed to a thickness of 30 nm. The oxide semiconductor film functions as a hard mask when the oxide semiconductor film and the second oxide semiconductor film are etched.

[0409] Next, a silicon nitride film was formed to a thickness of 100 nm by CVD.

[0410] Next, an organic resin film SWK-T7 (manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied to a thickness of 20 nm. Before applying -T7, the coating is heated at 200°C for 120 seconds to remove moisture, and then further ,1,3,3,3-Hexamethyldisilazane (HMDS) After applying lazane, the surface was heated at 110°C for 60 seconds to remove moisture. The mixture was heated at RT for 200 seconds to remove the solvent and water.

[0411] Next, a resist mask was formed, and a part of the organic resin film was etched. Chlorine (Cl2) gas was used.

[0412] Next, using the resist mask and the organic resin film as a mask, a part of the silicon nitride film is etched. The etching gas was trifluoromethane (CHF3) gas and helium (He). The silicon nitride film was processed in a mixed gas atmosphere.

[0413] Next, a tungsten film is formed using the resist mask, the organic resin film, and the silicon nitride film as a mask. The etching gas was chlorine (Cl2) gas, carbon tetrafluoride ( The tungsten film was processed under a mixed atmosphere of CF4 gas and oxygen (O2) gas. The tungsten film 207a and the tungsten film 207b were formed. In this process, the resist mask and the organic resin film are also etched and retreat.

[0414] Next, using the tungsten film 207a and the tungsten film 207b as a mask, a second oxide semiconductor film, first oxide semiconductor film, silicon oxynitride film, and aluminum oxide film The aluminum oxide film 203, the silicon oxynitride film 204, and the first The first oxide semiconductor film 205 and the second oxide semiconductor film 206 were formed. is a mixed atmosphere of trifluoromethane (CHF3) gas and helium (He) gas, Alternatively, hexafluoro-1,3-butadiene (C4F6) gas and argon (Ar) gas A mixed atmosphere was used.

[0415] Next, using the tungsten film 207a and the tungsten film 207b as a mask, an oxide film A part of the silicon film is etched to form an opening that reaches the tungsten film 201. The silicon film 202 was formed. The etching gas was hexafluoro-1,3-butadiene (C4 A mixed atmosphere of F6) gas and argon (Ar) gas was used.

[0416] Next, a titanium nitride film 208a was formed to a thickness of 5 nm by the CVD method.

[0417] Next, a tungsten film 208b was formed to a thickness of 200 nm by the CVD method.

[0418] Sample A was fabricated through the above steps.

[0419] In addition, Sample B was prepared. The method for preparing Sample B will be described below.

[0420] First, a silicon wafer is thermally oxidized to form a 100 nm thermal oxide film on the surface of the silicon wafer. The thermal oxidation conditions were 950°C for 4 hours, and the thermal oxidation atmosphere was HCl, which reacts with oxygen. The content was set to 3% by volume.

[0421] Next, the thermal oxide film was etched by 100 nm.

[0422] Next, a tungsten target was used, and argon ( Ar) gas atmosphere, pressure 0.8 Pa, substrate temperature 230 °C, target and substrate The sputtering method was performed under the conditions of a distance of 60 mm and a power supply (DC) of 1.0 kW. As a result, a tungsten film 211 was formed to a thickness of 150 nm.

[0423] Next, tetraethoxysilane (TEOS) at a flow rate of 15 sccm and 750 sccm The substrate temperature was set at 300°C and a 27MHz high frequency power source was used. A silicon oxide film was deposited on the substrate by the CVD method, in which 300 W of high frequency power was supplied to parallel plate electrodes. A film of 00 nm was formed.

[0424] Next, an aluminum oxide target was used, and argon gas with a flow rate of 25 sccm was used as the deposition gas. Argon (Ar) gas and oxygen (O2) gas at a flow rate of 25 sccm were used, and the pressure was set at 0.4 Pa. The substrate temperature was set to 250°C, the distance between the target and the substrate was set to 60 mm, and the RF power was set to 2.5 kW. An aluminum oxide film was formed to a thickness of 20 nm by sputtering under conditions in which the temperature was increased.

[0425] Next, silane (SiH4) with a flow rate of 1 sccm and nitrous oxide ( N2O) was used as the source gas, the pressure in the reaction chamber was 200 Pa, the substrate temperature was 350 °C, and the frequency was 60 MHz. Using a high-frequency power supply, 150W of high-frequency power was supplied to parallel plate electrodes by the CVD method. A silicon oxynitride film was formed to a thickness of 50 nm.

[0426] Next, a 10 nm thick first oxide semiconductor film and a 40 nm thick second oxide semiconductor film were formed by sputtering. The first oxide semiconductor film was deposited under the conditions of In:Ga:Zn= A target with an atomic ratio of 1:3:4 was used, and argon (Ar) and In a mixed atmosphere of oxygen (O2) with a flow rate of 5 sccm, the pressure was 0.4 Pa and the power supply power ( DC 0.5kW was applied, the distance between the target and the substrate was 60mm, and the substrate temperature was 200℃. The second oxide semiconductor film was formed as follows: In:Ga:Zn=1:1:1 [atomic ratio] The target was argon (Ar) with a flow rate of 30 sccm and oxygen ( In a mixed atmosphere of 0.4 Pa and 0.5 kW DC power, The film was formed with the distance between the target and the substrate set to 60 mm and the substrate temperature set to 300°C.

[0427] Next, a tungsten target was used, and argon ( Ar) gas atmosphere, pressure 0.8 Pa, substrate temperature 230 °C, target and substrate The sputtering method was performed under the conditions of a distance of 60 mm and a power supply (DC) of 1.0 kW. This tungsten film was formed to a thickness of 30 nm. The oxide semiconductor film functions as a hard mask when the oxide semiconductor film and the second oxide semiconductor film are etched.

[0428] Next, an organic resin film SWK-T7 was applied to a thickness of 20 nm. Before cooking, heat at 200°C for 120 seconds to remove moisture, then heat for 1,1,1,3,3, 3-Hexamethyldisilazane (HMDS) After applying, the film was heated at 110°C for 60 seconds to remove moisture. Then, it was heated at 200°C for 200 seconds. The solvent and water were removed.

[0429] Next, a resist mask was formed, and a part of the organic resin film was etched. Chlorine (Cl2) gas was used.

[0430] Next, using the resist mask and the organic resin film as a mask, a part of the tungsten film is etched. The etching gases were chlorine (Cl2) gas, carbon tetrafluoride (CF4) gas, and acid The tungsten film was processed in a mixed atmosphere of oxygen (O2) gas, and the tungsten film 217a and In the above etching process, the resist film 217a and the tungsten film 217b were formed. The mask and the organic resin film are also etched back.

[0431] Next, using the tungsten film 217a and the tungsten film 217b as a mask, a second oxide semiconductor film, first oxide semiconductor film, silicon oxynitride film, and aluminum oxide film The aluminum oxide film 213, the silicon oxynitride film 214, and the first The first oxide semiconductor film 215 and the second oxide semiconductor film 216 were formed. is a mixed atmosphere of trifluoromethane (CHF3) gas and helium (He) gas, Alternatively, hexafluoro-1,3-butadiene (C4F6) gas and argon (Ar) gas A mixed atmosphere was used.

[0432] Next, using the tungsten film 217a and the tungsten film 217b as a mask, an oxide film A part of the silicon film is etched to form an opening that reaches the tungsten film 211. The silicon film 212 was formed. The etching gas was hexafluoro-1,3-butadiene (C4 A mixed atmosphere of F6) gas and argon (Ar) gas was used.

[0433] Next, a titanium nitride film 218a was formed to a thickness of 10 nm by the CVD method.

[0434] Next, a tungsten film 218b was formed to a thickness of 200 nm by the CVD method.

[0435] Through the above steps, sample B was fabricated.

[0436] A cross-sectional STEM photograph of the prepared sample A is shown in Figure 30, and a cross-sectional STEM photograph of the prepared sample B is shown in Figure 31. The truth is shown in Figure 31.

[0437] From Figure 30, the width of the bottom of the opening of sample A was 51.5 nm. Also, from Figure 31, The width of the bottom of the opening in sample B was 99.2 nm.

[0438] From the above, silicon nitride is placed between the organic resin film and the tungsten film that functions as a hard mask. The silicon nitride film is placed in contact with the resist mask, and etching is performed under conditions where the selectivity of the silicon nitride film to the resist mask is large. Etching is performed to reduce the recession of the silicon nitride film, and the silicon nitride film is used as a mask to form an opening. By forming the resist mask, the length of the resist mask pattern is prevented from increasing, and the width of the bottom of the opening is reduced. (opening width) can be reduced. [Example]

[0439] In this embodiment, a first transistor (Si-FET) using single crystal silicon as a semiconductor film is and a second transistor (OS-FE) using an oxide semiconductor as a semiconductor film. The cross-sections of the semiconductor devices having Si-FETs and O-FETs were observed. The S-FET is fabricated by the method described in the first embodiment.

[0440] Figure 32 shows a cross-sectional STEM photograph of the semiconductor device.

[0441] As shown in Figure 32, the OS-FET was fabricated using a plug that was in direct contact with the Si-FET. The plug fabricated using the two-layer hard mask described above has a narrower bottom. In other words, the plug that is in direct contact with the Si-FET is buried in the opening, and the The opening of the plug fabricated using a hard mask was found to be more restricted in its expansion. It was confirmed that:

[0442] Also, the center O of the top surface of the gate electrode of the Si-FET shown in FIG. 32 and the oxide of the OS-FET The angle θ shown in FIG. 32 is 11° from the line segment C1-C2 on which the long side of the bottom surface of the nitride semiconductor film is located. It was 8.36°. [Explanation of symbols]

[0443] 100 transistors 101a Oxide semiconductor film 101b Oxide semiconductor film 101c Oxide semiconductor film 102a Oxide semiconductor film 102b Oxide semiconductor film 103 Conductive film 103a electrode 103a1 Conductive film 103a2 Island-shaped conductive film 103b electrode 103c electrode 104 Gate insulating film 105 gate electrode 106 insulating film 106a Insulating film 107 Insulating film 108 insulating film 109a Low resistance region 109b Low resistance region 110 Transistor 111 Semiconductor substrate 112 Semiconductor film 113a Low resistance layer 113b Low resistance layer 114 Gate insulating film 115 gate electrode 115a gate electrode 115b gate electrode 120 Barrier Film 121 insulating film 122 insulating film 123 insulating film 124 insulating film 125 insulating film 126 insulating film 127 insulating film 128 insulating film 130 Capacitive element 131a Oxide semiconductor film 131b Oxide semiconductor film 136 Electrode 137 Insulating Film 138 Electrode 140a Organic resin film 140b Organic resin film 141 Resist mask 141a Resist mask 146a Oxide semiconductor film 146b Oxide semiconductor film 147a layer 147b layer 160 transistors 161 Plug 162 Plug 163 Plug 164 plug 165 plug 166 Plug 167 Plug 168 Plug 169 Plug 170 plug 171 Plug 172 plug 173 Electrode 174 Electrode 175 Electrode 180 Wiring 181 Wiring 201 Tungsten film 202 Silicon oxide film 203 Aluminum oxide film 204 Silicon oxynitride film 205 Oxide semiconductor film 206 Oxide semiconductor film 207a Tungsten film 207b Tungsten film 208a Titanium nitride film 208b Tungsten film 211 Tungsten film 212 Silicon oxide film 213 Aluminum oxide film 214 Silicon oxynitride film 215 Oxide semiconductor film 216 Oxide semiconductor film 217a Tungsten film 217b Tungsten film 218a Titanium nitride film 218b Tungsten film 700 boards 701 Pixel section 702 Scanning line driving circuit 703 Scanning line driving circuit 704 Signal Line Driver Circuit 710 Capacitance wiring 712 Gate wiring 713 Gate wiring 714 Drain electrode 716 Transistor 717 Transistor 718 Liquid Crystal Devices 719 Liquid Crystal Devices 720 pixels 721 Switching Transistor 722 Drive transistor 723 Capacitor 724 Light-emitting element 725 signal line 726 scan lines 727 Power line 728 Common electrode 800 RFID tags 801 Communication Device 802 antenna 803 wireless signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 chassis 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 lens 946 Connection 951 body 952 wheels 953 Dashboard 954 Light 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic Elements 1207 Capacitor element 1208 Capacitor 1209 Transistor 1210 transistor 1213 Transistor 1214 transistor 1220 circuits 2100 transistors 2200 transistors 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 transistors 3300 transistors 3400 Capacitor 4000 RFID 5100 pellets 5100a pellets 5100b pellets 5101 AEON 5102 Zinc oxide layer 5103 particles 5105a Pellets 5105a1 area 5105a2 pellets 5105b Pellets 5105c Pellets 5105d Pellets 5105d1 area 5105e Pellets 5120 board 5130 Target 5161 Field

Claims

1. A first transistor having a first channel formation region containing silicon, A second transistor having a second channel formation region containing an oxide semiconductor, It has a capacitive element, One of the source and drain of the second transistor is electrically connected to the other of the source and drain of the first transistor. The source and drain of the second transistor are electrically connected to the gate of the first transistor and the capacitive element, in a semiconductor device. A first conductive layer having the function of one electrode of the capacitive element and being electrically connected to the gate electrode of the first transistor, A first insulating film having a region located above the first conductive layer, A second conductive layer is provided above the first conductive layer via the first insulating film and functions as the other electrode of the capacitive element, A second insulating film having a region located above the second conductive layer, A third insulating film having a region located above the second insulating film, The present invention comprises an oxide semiconductor layer having the second channel-forming region, located above the third insulating film, Each of the first conductive layer and the second conductive layer is provided in a position that overlaps with the first channel forming region. The length of the oxide semiconductor layer in the channel length direction of the second transistor is greater than the length of the first conductive layer in the channel length direction of the second transistor, and greater than the length of the second conductive layer in the channel length direction of the second transistor. The second insulating film comprises silicon nitride, The semiconductor device comprises a third insulating film having a region in contact with the lower surface of the oxide semiconductor layer and containing silicon oxide.

2. A first transistor having a first channel formation region containing silicon, A second transistor having a second channel formation region containing an oxide semiconductor, It has a capacitive element, One of the source and drain of the second transistor is electrically connected to the other of the source and drain of the first transistor. The source and drain of the second transistor are electrically connected to the gate of the first transistor and the capacitive element, in a semiconductor device. A first conductive layer having the function of one electrode of the capacitive element and being electrically connected to the gate electrode of the first transistor, A first insulating film having a region located above the first conductive layer, A second conductive layer is provided above the first conductive layer via the first insulating film and functions as the other electrode of the capacitive element, A second insulating film having a region located above the second conductive layer, A third insulating film having a region located above the second insulating film, An oxide semiconductor layer having the second channel-forming region, located above the third insulating film, A third conductive layer is provided above the oxide semiconductor layer and functions as the gate electrode of the second transistor, A fourth insulating film above the third conductive layer, A fourth conductive layer above the fourth insulating film, The fourth insulating film is further comprising a fifth conductive layer above it, Each of the first conductive layer and the second conductive layer is provided in a position that overlaps with the first channel forming region. The length of the oxide semiconductor layer in the channel length direction of the second transistor is greater than the length of the first conductive layer in the channel length direction of the second transistor, and greater than the length of the second conductive layer in the channel length direction of the second transistor. The second insulating film comprises silicon nitride, The third insulating film has a region in contact with the lower surface of the oxide semiconductor layer and has silicon oxide. Each of the fourth conductive layer and the fifth conductive layer has a region in contact with the upper surface of the fourth insulating film, The fourth conductive layer is electrically connected to one of the source and drain of the second transistor and to one of the source and drain of the first transistor. A semiconductor device wherein the fifth conductive layer is electrically connected to a low-resistance layer of a semiconductor film including the first channel-forming region.

3. In claim 1 or 2, The oxide semiconductor layer comprises In, Ga, and Zn, and is a semiconductor device.

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