Mother substrate and method for manufacturing mother substrate

Abstract

To provide a mother substrate and a method of manufacturing the mother substrate capable of efficiently performing inspection in manufacturing a display device.SOLUTION: A plurality of panel units each including a display region and a peripheral region around the display region, a margin region around the plurality of panel units, a lower electrode disposed in the display region, a rib layer having a pixel opening overlapping the lower electrode and disposed in the panel unit and the margin region, and a partition wall disposed in the margin region, the partition wall includes a bottom layer disposed on the rib layer, an axis layer disposed on the bottom layer and having conductivity, and an upper portion disposed on the axis layer, the bottom layer has a protruding portion protruding from a side surface of the axis layer, the upper portion has an eaves portion protruding from the side surface of the axis layer, the eaves portion has a notch overlapping the protruding portion in plan view, and the notch overlaps a boundary between the bottom layer and the axis layer in plan view.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] SUMMARY OF THE INVENTION Embodiments of the present invention relate to a motherboard and a method for manufacturing the motherboard. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have been put to practical use. When manufacturing this type of display device, inspections are carried out to confirm whether the elements on the substrate are formed as designed. Technology for efficiently carrying out such inspections is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a motherboard and a method for manufacturing the motherboard that enable efficient inspection during the manufacture of a display device. [Means for solving the problem]

[0005] A mother substrate according to one embodiment comprises a plurality of panel sections each including a display area and a peripheral area around the display area, a margin area around the plurality of panel sections, a lower electrode arranged in the display area, a rib layer having a pixel opening overlapping with the lower electrode and arranged in the panel section and the margin area, and a first partition arranged in the margin area, wherein the first partition includes a first bottom layer arranged on the rib layer, a first axial layer arranged on the first bottom layer and having conductivity, and a first upper portion arranged on the first axial layer, wherein the first bottom layer has a protrusion protruding from a side surface of the first axial layer, the first upper portion has an eave portion protruding from a side surface of the first axial layer, the eave portion has a notch that overlaps with the protrusion in a planar view, and the notch overlaps with the boundary between the first bottom layer and the first axial layer in a planar view.

[0006] A mother substrate according to another embodiment includes a plurality of panel sections each including a display area and a peripheral area around the display area, a margin area around the plurality of panel sections, a lower electrode arranged in the display area, a rib layer having a pixel opening overlapping the lower electrode and arranged in the panel section and the margin area, and a first partition wall arranged in the margin area, wherein the first partition wall includes a first bottom layer arranged on the rib layer, a first axial layer arranged on the first bottom layer and having conductivity, a first upper portion arranged on the first axial layer, a first partition wall opening, a second partition wall opening adjacent to the first partition wall opening, and a first portion located between the first partition wall opening and the second partition wall opening, wherein the first bottom layer has a protruding portion protruding from a side surface of the first axial layer, and the upper surface of the first axial layer is exposed in the first portion.

[0007] A method for manufacturing a motherboard according to one embodiment includes preparing a substrate including a panel portion including a display area and a peripheral area around the display area, and a margin area around the panel portion, forming a lower electrode in the display area, forming a rib layer covering the panel portion and the margin area, forming a first partition in the margin area including a first bottom layer formed on the rib layer, a first axial layer formed on the first bottom layer and having conductivity, and a first upper portion formed on the first axial layer, scanning a laser in a second direction inclined with respect to the first direction in which the first partition extends, removing a portion of the overhang portion of the first upper portion protruding from the side of the first axial layer, and measuring the length of the protruding portion of the first bottom layer protruding from the side of the first axial layer.

[0008] Another embodiment of a method for manufacturing a motherboard includes preparing a substrate including a panel portion including a display area and a peripheral area around the display area, and a margin area around the panel portion, forming a lower electrode in the display area, forming a rib layer covering the panel portion and the margin area, forming a first partition in the margin area including a first bottom layer formed on the rib layer, a first axial layer formed on the first bottom layer and having conductivity, and a first upper portion formed on the first axial layer, forming a resist covering the first partition, simultaneously removing a portion of the eave portion of the first upper portion protruding from the side of the first axial layer and a portion of the resist overlapping the eave portion with a laser, and measuring the length of the protrusion of the first bottom layer protruding from the side of the first axial layer.

[0009] A method for manufacturing a motherboard according to another embodiment includes preparing a substrate including a panel portion including a display area and a peripheral area around the display area, and a margin area around the panel portion, forming a lower electrode in the display area, forming a rib layer covering the panel portion and the margin area, forming a first partition in the margin area, the first partition including a first bottom layer formed on the rib layer, a first axial layer formed on the first bottom layer and having conductivity, a first upper portion formed on the first axial layer, a first partition opening, and a second partition opening adjacent to the first partition opening, forming a resist between the first partition opening and the second partition opening, exposing at least a portion of the first upper portion, removing the first upper portion exposed from the resist by etching, and measuring the length of the protruding portion of the first bottom layer protruding from the side of the first axial layer. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display panel taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic plan view of the motherboard according to the first embodiment. [Figure 5] FIG. 5 is a schematic plan view of a portion of the motherboard. [Figure 6] FIG. 6 is a schematic plan view showing an example of a configuration applicable to the test pattern of the motherboard according to the first embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view of the motherboard taken along line VII-VII in FIG. [Figure 8] FIG. 8 is an enlarged view of the area enclosed by the dashed line frame VIII in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view of the partition wall taken along line IX-IX in FIG. [Figure 10]FIG. 10 is a schematic cross-sectional view of the partition wall taken along line XX in FIG. [Figure 11] FIG. 11 is a flowchart showing an example of a method for manufacturing the display device according to the first embodiment. [Figure 12A] FIG. 12A is a schematic cross-sectional view showing a step of forming a panel unit on the motherboard according to the first embodiment. [Figure 12B] FIG. 12B is a schematic cross-sectional view showing a step subsequent to FIG. 12A. [Figure 12C] FIG. 12C is a schematic cross-sectional view showing a step subsequent to FIG. 12B. [Figure 12D] FIG. 12D is a schematic cross-sectional view showing a step subsequent to FIG. 12C. [Figure 12E] FIG. 12E is a schematic cross-sectional view showing a step subsequent to FIG. 12D. [Figure 12F] FIG. 12F is a schematic cross-sectional view showing a step subsequent to FIG. 12E. [Figure 12G] FIG. 12G is a schematic cross-sectional view showing a step subsequent to FIG. 12F. [Figure 12H] FIG. 12H is a schematic cross-sectional view showing a step subsequent to FIG. 12G. [Figure 12I] FIG. 12I is a schematic cross-sectional view showing a step subsequent to FIG. 12H. [Figure 12J] FIG. 12J is a schematic cross-sectional view showing a step subsequent to FIG. 12I. [Figure 13A] FIG. 13A is a schematic cross-sectional view showing a step of removing the rib layer in the terminal portion. [Figure 13B] FIG. 13B is a schematic cross-sectional view showing a step subsequent to FIG. 13A. [Figure 14A] FIG. 14A is a schematic cross-sectional view showing an example of a step of removing a part of the upper portion. [Figure 14B] FIG. 14B is a schematic plan view showing an example of a step of removing a part of the upper portion. [Figure 14C] FIG. 14C is a schematic cross-sectional view showing a step subsequent to FIG. 14A. [Figure 14D]FIG. 14D is a schematic plan view showing a step subsequent to FIG. 14B. [Figure 15] FIG. 15 is a schematic plan view showing an example of a configuration applicable to the test pattern of the motherboard according to the second embodiment. [Figure 16] FIG. 16 is an enlarged view of the area enclosed by the dashed line frame XVI in FIG. [Figure 17] FIG. 17 is a cross-sectional view showing an example of a step of removing a part of the upper portion. [Figure 18] FIG. 18 is a schematic plan view showing an example of a configuration applicable to the test pattern of the motherboard according to the third embodiment. [Figure 19] FIG. 19 is a schematic cross-sectional view of the motherboard taken along line XIX-XIX in FIG. [Figure 20A] FIG. 20A is a schematic cross-sectional view showing an example of a step of forming a first portion. [Figure 20B] FIG. 20B is a schematic cross-sectional view showing a step subsequent to FIG. 20A. [Figure 20C] FIG. 20C is a schematic cross-sectional view showing a step subsequent to FIG. 20B. [Figure 20D] FIG. 20D is a schematic cross-sectional view showing a step subsequent to FIG. 20C. [Figure 20E] FIG. 20E is a schematic cross-sectional view showing a step subsequent to FIG. 20D. DETAILED DESCRIPTION OF THE INVENTION

[0011] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0012] In the drawings, mutually perpendicular X-axis, Y-axis, and Z-axis are shown as necessary to facilitate understanding. The direction along the X-axis is referred to as the X-direction, the direction along the Y-axis is referred to as the Y-direction, and the direction along the Z-axis is referred to as the Z-direction. Viewing various elements parallel to the Z-direction is referred to as a planar view.

[0013] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0014] [First embodiment] 1 is a diagram showing an example of the configuration of a display device DSP according to the first embodiment. The display device DSP includes a display panel PNL including an insulating substrate 10. The display panel PNL has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a flexible resin film.

[0015] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.

[0016] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. However, the pixel PX may also include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0017] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0018] In the display area DA, there are arranged a plurality of scanning lines GL that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power supply lines PL. In the example of Fig. 1, the scanning lines GL and the power supply lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0019] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0020] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0021] The display device DSP further includes a terminal unit T arranged in the peripheral area SA. For example, a flexible circuit board is connected to the terminal unit T. Signals and voltages for driving the pixel circuits 1 are input to the display device DSP via the flexible circuit board and the terminal unit T.

[0022] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example of Fig. 2, subpixels SP2 and SP3 are aligned with subpixel SP1 in the X direction. Furthermore, subpixels SP2 and SP3 are aligned with subpixel SP1 in the Y direction.

[0023] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP2 and SP3 are alternately arranged in the Y direction, and columns in which multiple subpixels SP1 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG. 2.

[0024] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of FIG. 2, the pixel opening AP1 is larger than the pixel opening AP2, and the pixel opening AP2 is larger than the pixel opening AP3. That is, among the subpixels SP1, SP2, and SP3, the subpixel SP1 has the largest aperture ratio and the subpixel SP3 has the smallest aperture ratio. Note that the sizes and shapes of the pixel openings AP1, AP2, and AP3 are not limited to those shown in the example.

[0025] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap pixel aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap pixel aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap pixel aperture AP3.

[0026] The portions of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlap with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The portions of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlap with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The portions of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlap with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0027] In the display area DA, conductive partition walls 6 (second partition walls) are arranged above the rib layer 5. The partition walls 6 function as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3. The partition walls 6 entirely overlap the rib layer 5 and have the same planar shape as the rib layer 5.

[0028] Specifically, the partition wall 6 has a partition wall opening 601 in the subpixel SP1, a partition wall opening 602 in the subpixel SP2, and a partition wall opening 603 in the subpixel SP3. The partition wall openings 601, 602, and 603 are larger than the pixel openings AP1, AP2, and AP3, respectively, and surround the pixel openings AP1, AP2, and AP3, respectively. The partition wall openings 601, 602, and 603 overlap the entire display elements DE1, DE2, and DE3, respectively. That is, the partition wall 6 surrounds the display elements DE1, DE2, and DE3.

[0029] 3 is a schematic cross-sectional view of the display panel PNL taken along line III-III in FIG. 2. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines GL, signal lines SL, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0030] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross section of FIG. 3 , the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through a contact hole provided in the organic insulating layer 12.

[0031] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5, and an upper portion 62 (second upper portion) disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhanging shape.

[0032] In the example of FIG. 3, the lower part 61 has a bottom layer 63 (second bottom layer) arranged on the rib layer 5, and a conductive shaft layer 64 (second shaft layer) arranged on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. Also, in the example of FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0033] 3, the upper portion 62 has a first thin film 65 and a second thin film 66 disposed on the first thin film 65. For example, the width of the second thin film 66 is slightly smaller than the width of the first thin film 65. However, this is not limiting, and the first thin film 65 and the second thin film 66 may have the same width.

[0034] The organic layer OR1 is in contact with the lower electrode LE1 through a pixel opening AP1. The upper electrode UE1 is disposed on the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 is in contact with the lower electrode LE2 through a pixel opening AP2. The upper electrode UE2 is disposed on the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 is in contact with the lower electrode LE3 through a pixel opening AP3. The upper electrode UE3 is disposed on the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6.

[0035] Display element DE1 includes a cap layer CP1 disposed on an upper electrode UE1. Display element DE2 includes a cap layer CP2 disposed on an upper electrode UE2. Display element DE3 includes a cap layer CP3 disposed on an upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from organic layers OR1, OR2, and OR3, respectively.

[0036] In the following description, a multilayer structure including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as a laminate film FL1, a multilayer structure including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as a laminate film FL2, and a multilayer structure including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as a laminate film FL3. A partition wall 6 surrounds the laminate films FL1, FL2, and FL3.

[0037] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively, to cover the stacked films FL1, FL2, and FL3. The sealing layer SE11 continuously covers the display element DE1 and the partition wall 6 around it. The sealing layer SE12 continuously covers the display element DE2 and the partition wall 6 around it. The sealing layer SE13 continuously covers the display element DE3 and the partition wall 6 around it.

[0038] 3, the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP2 is spaced apart from the sealing layer SE12 on the partition wall 6. In addition, the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP3 is spaced apart from the sealing layer SE13 on the partition wall 6. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact with each other above the partition wall 6.

[0039] For example, gaps are formed between the sealing layers SE11, SE12, and SE13 and the upper portion 62 of the partition wall 6. The stacked films FL1, FL2, and FL3 may be disposed in at least a part of these gaps.

[0040] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0041] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0042] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0043] The lower electrodes LE1, LE2, and LE3 each include a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0044] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0045] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emissive layers.

[0046] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0047] The bottom layer 63 and the shaft layer 64 of the lower portion 61 of the partition wall 6 are formed of, for example, a metal material. Examples of the metal material for the bottom layer 63 include molybdenum (Mo), titanium (Ti), titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum (Al), an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). At least one of the bottom layer 63 and the shaft layer 64 may have a laminated structure of multiple layers. The shaft layer 64 may also include a layer formed of an insulating material.

[0048] The first thin film 65 of the partition wall 6 is formed of, for example, a metal material. The second thin film 66 of the partition wall 6 is formed of, for example, a conductive oxide. Examples of the metal material that can be used to form the first thin film 65 include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide that can be used to form the second thin film 66 include ITO or IZO. The upper portion 62 may include three or more layers, or may be formed of a single layer. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0049] A common voltage is supplied to the partition wall 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the lower portion 61. A pixel voltage corresponding to the video signal on the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0050] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0051] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0052] When manufacturing the display device DSP, a large motherboard is fabricated on which a plurality of regions (panel portions) each corresponding to a display panel PNL are formed. A configuration applicable to this motherboard will be described below.

[0053] 4 is a schematic plan view of the mother substrate MB (mother substrate for a display device) according to the first embodiment. The mother substrate MB has a rectangular shape as shown in the figure, but may have another shape such as a circle.

[0054] The mother substrate MB has a plurality of panel portions PP arranged in a matrix and blank areas BA around the panel portions PP. In the example of Fig. 4, the panel portions PP are lined up in the X and Y directions with blank areas BA between them. However, at least two of the plurality of panel portions PP on the mother substrate MB may be adjacent to each other without a blank area BA between them.

[0055] The motherboard MB further includes at least one test pattern TG. In the example of Fig. 4, multiple test patterns TG are arranged in the blank area BA. The positions and number of these test patterns TG are not particularly limited, but as an example, it is preferable that the test patterns TG are distributed in various places, such as near the edges and in the center of the motherboard MB.

[0056] 5 is a schematic plan view of a portion of the mother substrate MB. This drawing focuses on one panel portion PP. The outer shape of the panel portion PP corresponds to a cutting line CL1 along which the panel portion PP is cut out from the mother substrate MB.

[0057] Each panel unit PP has the above-mentioned display area DA and peripheral area SA. The peripheral area SA further includes an inspection area TA. In the inspection area TA, test pads and the like for inspecting the operation of the display panel PNL are arranged.

[0058] A cut line CL2 is formed on each panel portion PP, which divides the panel portion PP into a portion including a display area DA and a portion including an inspection area TA.

[0059] When manufacturing the display device DSP, first, the panel portion PP is cut out from the mother substrate MB along the cut line CL1. Then, the cut-out panel portion PP is inspected using the inspection pads. After this inspection, the inspection area TA is cut out from the panel portion PP along the cut line CL2.

[0060] The test pattern TG shown in Figure 4 may be placed not only in the margin area BA but also in the peripheral area SA. For example, the test pattern TG can be placed in the inspection area TA. In this case, the test pattern TG will not remain in the panel portion PP after the inspection area TA is separated along the cut line CL2. Even when the test pattern TG is placed in the margin area BA as shown in Figure 4, the test pattern TG will not remain in the panel portion PP after the inspection area TA is separated along the cut line CL2.

[0061] As another example, the test pattern TG may be arranged in a portion of the peripheral area SA excluding the inspection area TA. In this case, the test pattern TG remains in the panel unit PP after the inspection area TA is cut off along the cut line CL2.

[0062] Fig. 6 is a schematic plan view showing an example of a configuration applicable to the test pattern TG of the mother substrate MB according to the first embodiment. Fig. 7 is a schematic cross-sectional view of the mother substrate MB taken along line VII-VII in Fig. 6. Elements below the organic insulating layer 12 are omitted in Fig. 7.

[0063] As shown in FIG. 6, the test pattern TG is composed of a rib layer 5 and partition walls 7 (first partition walls). The rib layer 5 is arranged across the panel portion PP and the marginal area BA shown in FIG. 4. The partition walls 7 are arranged in the marginal area BA. The partition walls 7 may also be arranged in the peripheral area SA. The partition walls 7 extend in the X direction and the Y direction (first direction) and are formed in a lattice pattern. In the example of FIG. 6, the partition walls 7 have partition openings 701, 702, and 703.

[0064] For example, the shape and layout of the partition wall openings 701, 702, and 703 are similar to the shape and layout of the partition wall openings 601, 602, and 603 shown in Figure 2. However, the partition wall 7 may have one or more openings with shapes different from the partition wall openings 601, 602, and 603.

[0065] 6 and 7, the partition wall 7 includes a conductive lower portion 71 disposed on the rib layer 5, and an upper portion 72 (first upper portion) disposed on the lower portion 71. The upper portion 72 has a width greater than that of the lower portion 71. As a result, both ends of the upper portion 72 protrude beyond the side surfaces of the lower portion 71.

[0066] The lower portion 71 has a bottom layer 73 (first bottom layer) disposed on the rib layer 5, and a conductive shaft layer 74 (first shaft layer) disposed on the bottom layer 73. For example, the bottom layer 73 is formed thinner than the shaft layer 74.

[0067] The bottom layer 73 has a protruding portion 77 that protrudes from the side surface 74S of the shaft layer 74. The length of the protruding portion 77 in the X direction is defined as length L. Length L corresponds to the length along the X direction between the side surface 74S of the shaft layer 74 and the end of the bottom layer 73. More specifically, length L corresponds to the length along the X direction between the boundary 71B between the side surface 74S and the bottom layer 73 and the end of the bottom layer 73. In the example shown in FIG. 7, the side surface 74S is tapered. In FIG. 6, the portions of the outlines of the bottom layer 73 and the shaft layer 74 that overlap with the upper portion 72 are indicated by dashed lines.

[0068] The upper portion 72 has a first thin film 75 and a second thin film 76 disposed on the first thin film 75. For example, the width of the second thin film 76 is slightly smaller than the width of the first thin film 75. However, this is not limiting, and the first thin film 75 and the second thin film 76 may have the same width.

[0069] The thickness of the first thin film 75 is defined as thickness T. In the first embodiment, thickness T is, for example, 100 nm or less.

[0070] The upper portion 72 has an eave portion 78 that protrudes from the side surface 74S of the shaft layer 74. In the example shown in Fig. 7, the length of the eave portion 78 in the X direction is greater than the length L. That is, the protrusion 77 is completely covered by the eave portion 78 in a plan view.

[0071] The partition wall 7 can be formed in the same process as the partition wall 6. In this case, the bottom layer 73 is formed of the same material as the bottom layer 63, the shaft layer 74 is formed of the same material as the shaft layer 64, the first thin film 75 is formed of the same material as the first thin film 65, and the second thin film 76 is formed of the same material as the second thin film 66.

[0072] As shown in FIG. 6, the upper portion 72 has a groove portion 79 extending in a direction D1 (second direction) tilted at an angle θ1 counterclockwise with respect to the Y direction. The angle θ1 is, for example, an acute angle. In the example of FIG. 6, the groove portion 79 is disposed between the partition wall openings 701 and 702 (first partition wall opening, second partition wall opening). Note that the extending direction of the groove portion 79 is not limited to this example. For example, the groove portion 79 may extend in a direction tilted at an angle θ1 clockwise with respect to the Y direction. Also, the position of the groove portion 79 is not limited to the example shown.

[0073] The groove portion 79 has an end portion E1 that overlaps with the shaft layer 74 in a plan view. The end portion E1 is formed in an arc shape. The groove portion 79 reaches the partition wall opening 702. Between the groove portion 79 and the partition wall opening 702, a part of the top layer 72 is missing, and a part of the bottom layer 73 (the part with a diagonal line pattern) is exposed.

[0074] Although the details will be described later, the groove portion 79 is formed by irradiating the upper portion 72 with laser light. When the laser light is irradiated onto the overhang portion 78, a part of the overhang portion 78 is removed, and a part of the bottom layer 73 is exposed.

[0075] Fig. 8 is an enlarged view of the area surrounded by the dashed line frame VIII in Fig. 6. In Fig. 8, the portions of the bottom layer 73 and the axial layer 74 that do not overlap with the upper portion 72 are marked with diagonal lines.

[0076] The overhanging portion 78 has a notch 78N and a protruding portion 78V. The notch 78N corresponds to the portion removed from the overhanging portion 78 by the laser light described above. The notch 78N overlaps with the protruding portion 77 in a plan view and is adjacent to the groove portion 79 in the direction D1. The notch 78N also overlaps with the boundary 71B between the bottom layer 73 and the shaft layer 74 in a plan view.

[0077] The convex portion 78V is formed in a convex shape in the Y direction and is adjacent to the notch 78N in the Y direction. The convex portion 78V is spaced apart from the shaft layer 74, and a part of the notch 78N is disposed between the convex portion 78V and the shaft layer 74. In the example shown in FIG. 8, a part of the convex portion 78V overlaps with the groove portion 79. The convex portion 78V is formed by scanning the above-mentioned laser light in the direction D1.

[0078] 9 is a schematic cross-sectional view of the partition wall 7 taken along line IX-IX in FIG. 8. The groove portion 79 is formed concavely toward the lower portion 71. In the example of FIG. 9, the groove portion 79 is formed in the first thin film 75 and the second thin film 76. The groove portion 79 may reach the axial layer 74. The width and depth of the groove portion 79 vary depending on the output of the laser light that forms the groove portion 79, etc.

[0079] Fig. 10 is a schematic cross-sectional view of the partition wall 7 taken along line XX in Fig. 8. In Fig. 10, the groove portion 79 reaches the boundary between the lower surface of the upper portion 72 and the side surface 74S of the shaft layer 74. Therefore, in Fig. 10, the partition wall 7 does not have the overhang portion 78 on the side of the partition wall opening 702.

[0080] Next, an example of a manufacturing method of the display device DSP will be described. Fig. 11 is a flowchart showing an example of the manufacturing method of the display device DSP. Figs. 12A to 12J are schematic cross-sectional views showing the process of forming a panel section PP on a mother substrate MB. Figs. 12A to 12J mainly focus on the display area DA, and omit elements below the organic insulating layer 12.

[0081] In forming the panel portion PP, first, a circuit layer 11 and an organic insulating layer 12 are formed on a substrate 10 of a mother substrate MB (step PR1 in FIG. 11). Next, as shown in FIG. 12A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 (step PR2 in FIG. 11).

[0082] 12B, a rib layer 5 covering the lower electrodes LE1, LE2, and LE3 is formed over the entire mother substrate MB (step PR3 in FIG. 11). At this point, pixel openings AP1, AP2, and AP3 are not provided in the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0083] After the rib layer 5 is formed, steps for forming the partition walls 6 are performed (steps PR4 and PR5 in FIG. 11). In step PR4, as shown in FIG. 12C, a first layer L1 to be processed into the bottom layer 63, a second layer L2 to be processed into the shaft layer 64, a third layer L3 to be processed into the first thin film 65, and a fourth layer L4 to be processed into the second thin film 66 are sequentially formed over the entire mother substrate MB. Furthermore, a resist R1 is disposed on the fourth layer L4. The resist R1 is patterned into the shape of the partition walls 6. The first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 can be formed by, for example, sputtering.

[0084] In the subsequent step PR5, the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 are patterned using the resist R1 as a mask. In one example, the first layer L1 is formed of titanium nitride, the second layer L2 is formed of aluminum, the third layer L3 is formed of titanium, and the fourth layer L4 is formed of ITO. In this case, step PR5 may include wet etching to remove portions of the fourth layer L4 that are not covered by the resist R1, dry etching to remove portions of the first layer L1, the second layer L2, and the third layer L3 that are not covered by the resist R1, and wet etching to reduce the width of the second layer L2. The etching performed in step PR5 is appropriately selected depending on the structure and material of the partition wall 6.

[0085] After step PR5, as shown in FIG. 12D, the partition walls 6 are formed in the display area DA. After the partition walls 6 are formed, the resist R1 is removed (peeled off). In the wet etching that reduces the width of the second layer L2 described above, the second thin film 66 (fourth layer L4) may also be slightly eroded. When this erosion occurs, the width of the second thin film 66 becomes smaller than the width of the first thin film 65.

[0086] Next, a step for providing pixel openings AP1, AP2, and AP3 is performed (step PR6 in FIG. 11). In this step PR6, a resist R2 is formed to cover the partition wall 6, as shown in FIG. 12E. Furthermore, using the resist R2 as a mask, dry etching is performed on the rib layer 5. As a result, pixel openings AP1, AP2, and AP3 that expose the lower electrodes LE1, LE2, and LE3 are formed in the rib layer 5, as shown in FIG. 12F. After the dry etching, the resist R2 is removed (peeled off).

[0087] After step PR6, a step for removing the rib layer 5 in the terminal portion T shown in FIG. 1 is carried out (step PR7 in FIG. 11).

[0088] 13A and 13B are schematic cross-sectional views of the terminal portion T for explaining step PR7. As shown in these figures, the terminal portion T includes a conductive pad PD (conductive layer). The pad PD is disposed on an insulating layer 110 made of, for example, an inorganic insulating material. The pad PD and the insulating layer 110 are included in, for example, the circuit layer 11 shown in FIG. 3. For example, the peripheral edge of the pad PD is covered with an organic insulating layer 12.

[0089] The pads PD are formed in the peripheral region SA before step PR3, in which the rib layer 5 is formed. In step PR3, the pads PD are covered with the rib layer 5. Therefore, when step PR6 is completed, the pads PD are covered with the rib layer 5, as shown in FIG. 13A. In step PR7, a resist R3 having an opening above the pads PD is placed on the rib layer 5. Furthermore, using the resist R3 as a mask, dry etching is performed on the rib layer 5. As a result, terminal openings APt that overlap the pads PD and expose the pads PD are formed in the rib layer 5, as shown in FIG. 13B. After the dry etching, the resist R3 is removed (peeled off).

[0090] After step PR7, a step for forming the display element DE1 is performed (step PR8 in FIG. 11). To form the display element DE1, first, as shown in FIG. 12G, a stacked film FL1 and a sealing layer SE11 are formed. As shown in FIG. 3, the stacked film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed by, for example, vapor deposition. The sealing layer SE11 can be formed by, for example, CVD.

[0091] The laminated film FL1 and sealing layer SE11 are formed over the entire mother substrate MB, including not only the display area DA of each panel unit PP but also the peripheral area SA and marginal area BA. The laminated film FL1 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE11 continuously covers each divided part of the laminated film FL1 and the partition walls 6.

[0092] Next, the stacked film FL1 and the sealing layer SE11 are patterned. In this patterning, a resist R4 is disposed on the sealing layer SE11, as shown in FIG. 12G. The resist R4 covers the subpixel SP1 and part of the partition wall 6 around it.

[0093] Then, an etching process is performed using the resist R4 as a mask. As a result, as shown in FIG. 12H, the portions of the stacked film FL1 and the sealing layer SE11 exposed by the resist R4 are removed. In other words, the portions of the stacked film FL1 and the sealing layer SE11 that overlap the lower electrode LE1 are left, and the other portions are removed. This results in the formation of a display element DE1 in the subpixel SP1. For example, in the peripheral region SA and the marginal region BA, the stacked film FL1 and the sealing layer SE11 are removed by this etching process. This etching process may include wet etching or dry etching, which is performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching processes, the resist R4 is removed (peeled off).

[0094] In addition, when wet etching the stacked film FL1, the stacked film FL1 located above the partition wall 6 and below the sealing layer SE11 is also removed. As a result, a gap is formed between the sealing layer SE11 above the partition wall 6 and the partition wall 6. The stacked film FL1 that constitutes the display element DE1 is completely surrounded by the sealing layer SE11 and the partition wall 6, and is therefore not eroded by the wet etching.

[0095] After step PR8, a step for forming display element DE2 is performed (step PR9 in FIG. 11). Display element DE2 can be formed using the same procedure as display element DE1. That is, when forming display element DE2, a stacked film FL2 and a sealing layer SE12 are formed over the entire mother substrate MB. As shown in FIG. 3, stacked film FL2 includes an organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cap layer CP2 covering the upper electrode UE2.

[0096] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed by, for example, vapor deposition. The sealing layer SE12 can be formed by, for example, CVD. The stacked film FL2 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE12 continuously covers each divided part of the stacked film FL2 and the partition walls 6. By patterning the stacked film FL2 and the sealing layer SE2, a display element DE2 is formed in the subpixel SP2, as shown in FIG. 12I. For example, in the peripheral region SA and the marginal region BA, the stacked film FL2 and the sealing layer SE12 are removed by etching during the patterning process.

[0097] After step PR9, a step for forming display element DE3 is performed (step PR10 in FIG. 11). Display element DE3 can be formed using the same procedure as display elements DE1 and DE2. That is, when forming display element DE3, a stacked film FL3 and a sealing layer SE13 are formed over the entire mother substrate MB. As shown in FIG. 3, stacked film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3.

[0098] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed by, for example, vapor deposition. The sealing layer SE13 can be formed by, for example, CVD. The stacked film FL3 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE13 continuously covers each divided part of the stacked film FL3 and the partition walls 6. By patterning the stacked film FL3 and the sealing layer SE13, a display element DE3 is formed in the subpixel SP3, as shown in FIG. 12J. For example, in the peripheral region SA and the marginal region BA, the stacked film FL3 and the sealing layer SE13 are removed by etching during the patterning process.

[0099] Although it is assumed here that the display elements DE1, DE2, and DE3 are formed in this order, the display elements DE1, DE2, and DE3 may be formed in a different order.

[0100] After the display elements DE1, DE2, and DE3 are formed, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 shown in Figure 3 are formed in this order (step PR11 in Figure 11). Furthermore, each panel portion PP is cut out from the mother substrate MB along the cutting line CL1 (step PR12 in Figure 11).

[0101] Thereafter, each panel portion PP is inspected (step PR13 in FIG. 11). This inspection includes an inspection of the lighting of each display element DE1, DE2, DE3 using inspection pads arranged in the inspection area TA. After the inspection, the inspection area TA is cut along the cut line CL2 (step PR14 in FIG. 11). This completes the display panel PNL.

[0102] The partition walls 7 are formed in the peripheral region SA and the marginal region BA by steps PR4 and PR5, similarly to the partition walls 6. That is, by steps PR4 and PR5, a bottom layer 73 is formed on the rib layer 5, a shaft layer 74 is formed on the bottom layer 73, a first thin film 75 is formed on the shaft layer 74, and a second thin film 76 is formed on the first thin film 75. However, immediately after step PR5, no groove portion 79 is formed in the upper portion 72 of the partition wall 7. In the first embodiment, for example, the third layer L3 (first thin film 65) is formed to a thickness of 100 nm or less.

[0103] 14A to 14D are views showing an example of a step of removing a portion of the upper portion 72. FIGS. 14A and 14C are schematic cross-sectional views of the step, and FIGS. 14B and 14D are schematic plan views of the step. FIG. 14B is a cross-sectional view at the same time as FIG. 14A, and FIG. 14D is a cross-sectional view at the same time as FIG. 14C. Elements below the rib layer 5 are omitted in FIGS. 14A and 14C.

[0104] As shown in Fig. 14A, laser light LS is irradiated onto the upper portion 72 using the laser device 100. At this time, as shown in Fig. 14B, the starting point of processing by the laser light LS overlaps with the axial layer 74. Thereafter, the laser light LS is scanned in direction D1. That is, the laser light LS is scanned from the position where it overlaps with the axial layer 74 toward the overhanging portion 78 on the side of the partition opening 702. The laser device 100 is configured to emit laser light LS of, for example, an infrared wavelength.

[0105] By scanning the laser beam LS, a groove 79 is formed in the upper portion 72, as shown in FIGS. 14C and 14D. Furthermore, a portion of the overhanging portion 78 is removed by the laser beam LS, forming a notch 78N and a protrusion 78V in the overhanging portion 78. This allows the bottom layer 73 and the protrusion 77 to be visually recognized in a planar view. Thereafter, the length L of the protrusion 77 is measured using the measuring device 200. The length L can be measured, for example, by analyzing an image of the protrusion 77 taken in a planar view.

[0106] 14A to 14D may be performed, for example, after step PR7 of forming the terminal opening APt in the rib layer 5. However, without being limited to this, the steps shown in Fig. 14A to 14D may be performed, for example, after step PR6 of providing the pixel openings AP1, AP2, and AP3 in the rib layer 5.

[0107] The measurement process may be performed for each of the multiple test patterns TG distributed on the mother substrate MB as shown in Fig. 4. In this case, it is possible to suppress variations in measurement depending on the position on the mother substrate MB. As another example, the measurement process may be performed for some of the multiple test patterns TG.

[0108] As described above, in this embodiment, the step of measuring the length L of the protrusion 77 is carried out after removing a portion of the overhanging portion 78 with the laser light LS. If the overhanging portion 78 is not removed, it is necessary to measure the length L through a destructive test for observing the cross section of the partition wall 7. It is difficult to carry out a destructive test during the manufacturing process of the display device DSP, and the test takes time and effort.

[0109] In contrast to this, if a test pattern TG in which part of the overhanging portion 78 is removed by laser light LS is provided as in the present embodiment, it is possible to measure the length L of the protrusion 77 by observing from above the mother substrate MB without requiring destructive testing. Such a measurement can be easily carried out during the manufacture of the display device DSP, and if an inspection using the measurement results indicates a defect, the manufacture can be stopped without carrying out any subsequent processes.

[0110] Furthermore, in this embodiment, a part of the overhanging portion 78 is removed by scanning the laser light LS in a direction D1 inclined at an angle θ1 with respect to the extension direction (Y direction) of the partition wall 7. If the laser light LS were scanned parallel to the extension direction of the partition wall 7, it would be difficult to irradiate the laser light LS with the aim of targeting the base of the overhanging portion 78 (the boundary between the upper portion 72 and the axial layer 74) due to the influence of the processing accuracy and positioning accuracy of the laser device 100.

[0111] In contrast, according to this embodiment, the laser light LS reliably crosses the base of the overhanging portion 78. Therefore, high-precision processing and positioning are not required, which can reduce costs and improve yields.

[0112] Furthermore, in this embodiment, the laser light LS is scanned in direction D1 from the position overlapping with the shaft layer 74 toward the overhanging portion 78. If the laser light LS is scanned in the direction opposite to direction D1 from the overhanging portion 78 side toward the shaft layer 74, the laser light LS will first reach the end of the overhanging portion 78 of the partition wall 7. Therefore, the energy of the laser light LS is concentrated at the end of the overhanging portion 78, and the laser light LS may penetrate the overhanging portion 78 and process the bottom layer 73.

[0113] In contrast, according to this embodiment, the laser light LS is scanned from the position overlapping with the shaft layer 74 toward the partition opening 702. Therefore, the energy of the laser light LS is dispersed in the upper part 72, and the energy of the laser light LS is not concentrated on the overhanging portion 78. This makes it possible to prevent the laser light LS from processing the bottom layer 73, and makes it possible to accurately measure the length L of the protrusion 77.

[0114] As described above, according to this embodiment, it is possible to efficiently carry out inspections of the display device DSP during manufacturing. In addition to the effects described above, various other advantageous effects can be obtained from this embodiment.

[0115] [Second embodiment] Next, a second embodiment will be described. Fig. 15 is a schematic plan view showing an example of a configuration applicable to a test pattern TG of a motherboard MB according to the second embodiment. Elements that are the same as or similar to those in the first embodiment are given the same reference numerals, and duplicated explanations will be omitted as appropriate.

[0116] As shown in Fig. 15, the upper portion 72 has a groove portion 79 located on the side of the partition wall opening 702. In the example of Fig. 15, the groove portion 79 is disposed between the partition wall openings 701 and 702. Between the groove portion 79 and the partition wall opening 702, a part of the upper portion 72 is missing, and a part (the portion indicated by the diagonal lines) of the bottom layer 73 is exposed. The position of the groove portion 79 is not limited to the example shown in the figure. Furthermore, a plurality of groove portions 79 and exposed portions of the bottom layer 73 may be provided between the partition wall openings 701 and 702.

[0117] Although the details will be described later, the groove portion 79 is formed by irradiating the upper portion 72 with laser light. When the laser light is irradiated onto the overhang portion 78, a part of the overhang portion 78 is removed, and a part of the bottom layer 73 is exposed.

[0118] Figure 16 is an enlarged view of the area surrounded by the dashed line frame XVI in Figure 15. In Figure 16, the portions of the bottom layer 73 and the shaft layer 74 that do not overlap with the upper part 72 are marked with diagonal lines.

[0119] The overhanging portion 78 has a notch 78N. The notch 78N corresponds to a portion removed from the overhanging portion 78 by the laser beam that forms the groove 79. The boundary between the overhanging portion 78 and the notch 78N is rounded. The notch 78N overlaps with the boundary 71B between the bottom layer 73 and the shaft layer 74 in a plan view. The groove 79 is formed along the notch 78N.

[0120] The cross-sectional structure of the partition wall 7 including the notch 78N and the groove 79 is configured similarly to the cross section shown in Fig. 10. In addition, the thickness T of the first thin film 75 in this embodiment is, for example, greater than 100 nm.

[0121] Fig. 17 is a cross-sectional view showing an example of a step of removing a part of the upper portion 72. In Fig. 17, elements below the rib layer 5 are omitted.

[0122] As shown in FIG. 17, a resist R is formed to cover the partition wall 7. Then, dry etching is performed using the resist R as a mask. After the dry etching, a certain range including the overhanging portion 78 is irradiated with laser light LS using a laser device 100. This removes the overhanging portion 78 and the portion of the resist R irradiated with the laser light LS, and a notch 78N is formed in the overhanging portion 78. Then, the resist R is removed (peeled off). After the resist R is removed, the length L of the protrusion 77 is measured using a measuring device 200, similar to the process shown in FIG. 14C.

[0123] 17, a step PR7 for forming the terminal opening APt in the rib layer 5 can be used. In this case, the resist R corresponds to the resist R3 shown in FIGS. 13A and 13B. The dry etching performed before the irradiation with the laser light LS corresponds to the dry etching for forming the terminal opening APt in the rib layer 5.

[0124] 17, a step other than step PR7 may be used. As an example, step PR6 for providing pixel openings AP1, AP2, and AP3 in the rib layer 5 can be used as the step shown in FIG. 17. In this case, the resist R corresponds to the resist R2 shown in FIGS. 12E and 12F. Furthermore, the dry etching performed before irradiating with the laser light LS corresponds to the dry etching for forming the pixel openings AP1, AP2, and AP3 in the rib layer 5.

[0125] In this embodiment, the step of removing the overhanging portions 78 using the laser light LS is performed in a state in which the partition walls 7 are covered with the resist R. Therefore, part of the energy of the laser light LS is used to process the resist R. In this case, compared to the case in which the resist R is not present, it is possible to remove the overhanging portions 78 with almost no damage to the bottom layer 73.

[0126] Furthermore, in this embodiment, the process of removing the overhanging portion 78 using the laser light LS is performed after dry etching. Since the properties of the resist R change due to the dry etching, more energy of the laser light LS is used to process the resist R than when the laser light LS is irradiated before dry etching. Therefore, damage to the bottom layer 73 can be reduced.

[0127] Furthermore, while in the first embodiment the laser light LS is scanned in one direction, in this embodiment the laser light LS is irradiated over a fixed range. Therefore, in this embodiment, it is possible to remove the overhanging portion 78 even if the thickness T of the first thin film 75 is thicker than in the first embodiment. For example, in this embodiment, it is possible to remove the overhanging portion 78 even if the thickness T of the first thin film 75 is greater than 100 nm.

[0128] In addition, the mother substrate MB and the method for manufacturing the mother substrate MB according to the second embodiment have the same effects as the mother substrate MB and the method for manufacturing the mother substrate MB according to the first embodiment described above.

[0129] [Third embodiment] Next, a third embodiment will be described. Fig. 18 is a schematic plan view showing an example of a configuration applicable to a test pattern TG of a mother substrate MB according to the third embodiment. Fig. 19 is a schematic cross-sectional view of the mother substrate MB taken along line XIX-XIX in Fig. 18. Elements below the organic insulating layer 12 are omitted in Fig. 19.

[0130] The partition wall 7 has a first portion P1 (a portion with a diagonal line pattern) and a second portion P2 (a portion with a dot pattern). In the example of FIG. 18, the first portion P1 is located between the partition wall openings 701 and 702. The portion of the partition wall 7 excluding the first portion P1 corresponds to the second portion P2. Note that the position where the first portion P1 is provided is not limited to this example.

[0131] 18 and 19, the first portion P1 includes the lower portion 71 (the bottom layer 73 and the stem layer 74) similar to the partition wall 6. However, the first portion P1 does not include the upper portion 72 (the first thin film 75 and the second thin film 76). Therefore, the upper surface 74U of the stem layer 74 is exposed in the first portion P1.

[0132] 19, the second portion P2 includes a lower portion 71 (a bottom layer 73 and an axial layer 74) and an upper portion 72 (a first thin film 75 and a second thin film 76). Therefore, an upper surface 74U of the axial layer 74 is covered by the upper portion 72 in the second portion P2. The thickness T of the first thin film 75 in the second portion P2 is, for example, greater than 100 nm.

[0133] 18, the outlines of the bottom layer 73 and the shaft layer 74 of the second portion P2 are respectively indicated by dashed lines. For example, the bottom layer 73 of the second portion P2 is connected to the bottom layer 73 of the first portion P1. Similarly, the shaft layer 74 of the second portion P2 is connected to the shaft layer 74 of the first portion P1.

[0134] 19, the lower portions 71 of the first portion P1 and the second portion P2 are disposed on the rib layer 5. In the examples of FIGS. 18 and 19, the rib layer 5 is flat between the partition wall opening 701 and the first portion P1 and between the partition wall opening 702 and the first portion P1. However, for example, the rib layer 5 may have an opening located around the first portion P1.

[0135] 20A to 20E are schematic cross-sectional views showing one example of a process for forming the first portion P1. These cross-sectional views show the same portion as FIG. 19, and omit elements below the organic insulating layer 12. In the following description, the portion of the partition wall 7 where the first portion P1 is formed will be referred to as partition wall 7A, and the portion of the partition wall 7 where the second portion P2 is formed will be referred to as partition wall 7B.

[0136] To form the first portion P1, as shown in FIG. 20A, a resist R is formed to cover the partition walls 7A and 7B. Furthermore, as indicated by the arrows, the resist R is exposed using a mask MK. The mask MK has an opening MA above the partition wall 7A. The width W2 of the opening MA is smaller than the width W1 of the upper portion 72 (the width of the first thin film 75 in FIG. 20A). In one example, the width W2 is smaller than the width W1 by about 2 μm. In another example, the width W2 is approximately equal to the width W3 of the axial layer 74.

[0137] The resist R is, for example, a positive type. Therefore, as shown in Fig. 20B, the exposed portion of the resist R is removed in the development process. As a result, a part of the upper portion 72 of the partition 7A between the partition openings 701 and 702 is exposed from the resist R. The width of the portion removed in the development process is approximately equal to the width W2 of the opening MA of the mask MK.

[0138] 20B, the partition wall 7B is entirely covered with the resist R. Also, a part of the second thin film 76 of the partition wall 7A is exposed from the resist R. Furthermore, both ends of the upper part 72 of the partition wall 7A are covered with the resist R. In FIG. 20B, both ends of the first thin film 75 and the second thin film 76 of the partition wall 7A are covered with the resist R. The rib layer 5 around the partition wall 7A is not exposed from the resist R.

[0139] Next, an etching process is performed with the resist R in place. The etching process includes wet etching (first etching) shown in Fig. 20C and dry etching (second etching) shown in Fig. 20D.

[0140] 20C, the second thin film 76 of the partition wall 7A is removed by wet etching, and the upper surface of the first thin film 75 of the partition wall 7A is exposed. The upper portion 72 of the partition wall 7B is covered with the resist R and is therefore not removed by the wet etching.

[0141] After the wet etching, both ends of the first thin film 75 of the partition wall 7A may be covered with the resist R or may be exposed from the resist R, as shown in FIG. 20C.

[0142] After the wet etching, as shown in Fig. 20D, the first thin film 75 of the partition wall 7A is removed by dry etching. As a result, the upper portion 72 of the partition wall 7A is removed, and the upper surface of the axial layer 74 of the partition wall 7A is exposed. The upper portion 72 of the partition wall 7B is covered with the resist R and is therefore not removed by the dry etching.

[0143] After the etching step, the resist R is removed (peeled off) as shown in FIG. 20E. Through these steps, the first portion P1 and the second portion P2 are formed. The portion of the rib layer 5 surrounding the first portion P1 is flat because it was covered with the resist R. Specifically, the rib layer 5 is flat between the partition wall opening 701 and the first portion P1, and between the partition wall opening 702 and the first portion P1.

[0144] Using the first portion P1 thus formed, the length L of the protrusion 77 is measured in the same manner as in the first and second embodiments.

[0145] 20A to 20E, a step PR7 for forming the terminal opening APt in the rib layer 5 can be used. In this case, the resist R corresponds to the resist R3 shown in FIGS. 13A and 13B. The dry etching for removing the first thin film 75 of the partition wall 7A corresponds to the dry etching for forming the terminal opening APt in the rib layer 5. The dry etching for removing the first thin film 75 of the partition wall 7A and the dry etching for forming the terminal opening APt in the rib layer 5 may be performed simultaneously or separately. That is, the dry etching for forming the terminal opening APt in the rib layer 5 (third etching) may be performed after the dry etching for removing the first thin film 75 of the partition wall 7A. When the dry etchings are performed separately, the removal of the first thin film 75 and the formation of the terminal opening APt can be performed more accurately and with higher precision than when the dry etchings are performed simultaneously. On the other hand, when the dry etchings are performed simultaneously, an increase in the number of steps can be suppressed.

[0146] In this embodiment, the upper portion 72 of the first portion P1 is removed by performing an etching process. Therefore, it is possible to remove the upper portion 72 (eave portion 78) even when the thickness T of the first thin film 75 is large. For example, in this embodiment, it is possible to remove the upper portion 72 even when the thickness T of the first thin film 75 is greater than 100 nm.

[0147] Furthermore, in this embodiment, the width W2 of the opening MA of the mask MK is smaller than the width W1 of the upper portion 72. If the width W2 were larger than the width W1, the protruding portion 77 might be eroded by etching. Therefore, by making the width W2 smaller than the width W1, the erosion of the protruding portion 77 can be suppressed.

[0148] Furthermore, if the width W2 is too small compared to the width W1, the overhanging portion 78 may not be completely removed and may remain. If the remaining overhanging portion 78 separates from the mother substrate MB during the manufacturing process, it may adversely affect other products and equipment, resulting in a decrease in yield. In this embodiment, the width W2 is approximately 2 μm smaller than the width W1. In another example, the width W2 is approximately equal to the width W3 of the shaft layer 74. Under these conditions, the overhanging portion 78 can be completely removed by etching, making it possible to prevent a decrease in yield.

[0149] In addition, the mother substrate MB and the method for manufacturing the mother substrate MB according to the third embodiment have the same effects as the mother substrate MB and the method for manufacturing the mother substrate MB according to the first and second embodiments described above.

[0150] All motherboards and motherboard manufacturing methods that can be implemented by a person skilled in the art by making appropriate design modifications based on the motherboards and motherboard manufacturing methods described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0151] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0152] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0153] MB...motherboard, DSP...display device, DE1, DE2, DE3...display element, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, 5...rib layer, 6, 7...partition wall, 61, 71...lower part, 62, 72...upper part, 63, 73...bottom layer, 64, 74...axial layer, 65, 75...first thin film, 66, 76...second thin film, 77...protrusion, 78...eaves part.

Claims

1. a plurality of panel units each including a display area and a peripheral area around the display area; marginal areas around the plurality of panel portions; a lower electrode disposed in the display area; a rib layer having pixel openings overlapping the lower electrodes and disposed in the panel portion and the marginal area; a first partition wall disposed in the marginal region; Equipped with The first partition wall includes a first bottom layer disposed on the rib layer, a first axial layer disposed on the first bottom layer and having electrical conductivity, and a first upper portion disposed on the first axial layer, The first bottom layer has a protruding portion protruding from a side surface of the first axial layer, The first upper portion has an eave portion protruding from a side surface of the first axial layer, The eave portion has a notch that overlaps with the protrusion portion in a plan view, The notch overlaps with the boundary between the first bottom layer and the first shaft layer in a plan view. Motherboard.

2. the first upper portion further includes a groove portion extending in a second direction inclined with respect to a first direction in which the first partition wall extends, The notch is adjacent to the groove. The motherboard according to claim 1 .

3. The overhanging portion further includes a protrusion that is protruded in the first direction, The protrusion is adjacent to the notch. The motherboard according to claim 2 .

4. One end of the groove portion overlaps with the first axial layer in a plan view. The motherboard according to claim 2 .

5. The second direction is inclined at an acute angle with respect to the first direction. The motherboard according to claim 2 .

6. The first upper portion includes a first thin film disposed on the first axial layer and formed of a material containing titanium, and a second thin film disposed on the first thin film and formed of ITO, The thickness of the first thin film is 100 nm or less. The motherboard according to claim 2 .

7. The first upper portion further has a groove portion along the notch. The motherboard according to claim 1 .

8. The boundary between the eave portion and the notch is formed in a rounded shape. The motherboard according to claim 7 .

9. the first partition wall further includes a first partition wall opening and a second partition wall opening adjacent to the first partition wall opening, the groove portion is disposed between the first partition wall opening and the second partition wall opening. The motherboard according to claim 2 or 7.

10. a plurality of panel units each including a display area and a peripheral area around the display area; marginal areas around the plurality of panel portions; a lower electrode disposed in the display area; a rib layer having pixel openings overlapping the lower electrodes and disposed in the panel portion and the marginal area; a first partition wall disposed in the marginal region; Equipped with The first partition wall includes a first bottom layer disposed on the rib layer, a first axial layer disposed on the first bottom layer and having conductivity, a first upper portion disposed on the first axial layer, a first partition wall opening, a second partition wall opening adjacent to the first partition wall opening, and a first portion located between the first partition wall opening and the second partition wall opening, The first bottom layer has a protruding portion protruding from a side surface of the first axial layer, The upper surface of the first axial layer is exposed in the first portion. Motherboard.

11. the rib layer is flat between the first partition wall opening and the first portion and between the second partition wall opening and the first portion; The motherboard according to claim 10.

12. The first upper portion includes a first thin film disposed on the first axial layer and formed of a material containing titanium, and a second thin film disposed on the first thin film and formed of ITO, The thickness of the first thin film is greater than 100 nm; The motherboard according to claim 7 or 10.

13. a second partition wall disposed in the display region and surrounding the pixel opening; The second partition wall includes a second bottom layer disposed on the rib layer, a second axial layer disposed on the second bottom layer, and a second upper portion disposed on the second axial layer. The motherboard according to claim 1 or 10.

14. an organic layer in contact with the lower electrode through the pixel opening; an upper electrode disposed on the organic layer and in contact with the second axial layer; a cap layer disposed on the upper electrode; a sealing layer disposed on the cap layer, the second partition wall surrounds the lower electrode, the organic layer, the upper electrode, and the cap layer; The motherboard according to claim 13 .

15. A substrate is prepared, the substrate including a panel portion including a display area and a peripheral area around the display area, and a margin area around the panel portion; forming a lower electrode in the display area; forming a rib layer covering the panel portion and the marginal area; A first partition wall is formed in the blank area, the first partition wall including a first bottom layer formed on the rib layer, a first axial layer formed on the first bottom layer and having conductivity, and a first upper portion formed on the first axial layer; a laser is scanned in a second direction inclined with respect to a first direction in which the first partition wall extends, thereby removing a part of an overhang portion of the first upper portion that protrudes from a side surface of the first axial layer; measuring the length of a protruding portion of the first bottom layer protruding from a side surface of the first axial layer; Motherboard manufacturing method.

16. In the step of removing a portion of the overhang portion, the laser is scanned from a portion of the first upper portion that overlaps with the first axial layer toward the overhang portion. The method for manufacturing a motherboard according to claim 15.

17. forming a conductive layer in the peripheral region before the step of forming the rib layer; In the step of forming the rib layer, the rib layer is formed to cover the conductive layer, a terminal opening overlapping the conductive layer is formed in the rib layer between the step of forming the first partition wall and the step of removing a portion of the overhanging portion; The method for manufacturing a motherboard according to claim 15.

18. The step of forming the first upper portion includes the steps of: forming a first thin film made of a material containing titanium on the first axial layer; and forming a second thin film made of ITO on the first thin film; The first thin film is formed to a thickness of 100 nm or less. The method for manufacturing a motherboard according to claim 15.

19. A substrate is prepared, the substrate including a panel portion including a display area and a peripheral area around the display area, and a margin area around the panel portion; forming a lower electrode in the display area; forming a rib layer covering the panel portion and the marginal area; A first partition wall is formed in the blank area, the first partition wall including a first bottom layer formed on the rib layer, a first axial layer formed on the first bottom layer and having conductivity, and a first upper portion formed on the first axial layer; forming a resist to cover the first partition wall; A part of the overhanging portion of the first upper portion protruding from the side surface of the first axial layer and a part of the resist overlapping the overhanging portion are simultaneously removed by a laser; measuring the length of a protruding portion of the first bottom layer protruding from a side surface of the first axial layer; Motherboard manufacturing method.

20. forming a conductive layer in the peripheral region before the step of forming the rib layer; In the step of forming the rib layer, the rib layer is formed to cover the conductive layer, between the step of forming the resist and the step of removing the part of the overhanging portion, dry etching is performed to form a terminal opening in the rib layer that overlaps with the conductive layer. The method for manufacturing a motherboard according to claim 19.

21. The step of forming the first upper portion includes the steps of: forming a first thin film made of a material containing titanium on the first axial layer; and forming a second thin film made of ITO on the first thin film; The first thin film is formed to a thickness of greater than 100 nm. The method for manufacturing a motherboard according to claim 19.

22. A substrate is prepared, the substrate including a panel portion including a display area and a peripheral area around the display area, and a margin area around the panel portion; forming a lower electrode in the display area; forming a rib layer covering the panel portion and the marginal area; forming a first partition wall in the blank area, the first partition wall including a first bottom layer formed on the rib layer, a first axial layer formed on the first bottom layer and having conductivity, a first upper portion formed on the first axial layer, a first partition wall opening, and a second partition wall opening adjacent to the first partition wall opening; forming a resist between the first partition wall opening and the second partition wall opening, so that at least a part of the first upper portion is exposed; removing the first upper portion exposed from the resist by performing etching; measuring the length of a protruding portion of the first bottom layer protruding from a side surface of the first axial layer; Motherboard manufacturing method.

23. The step of forming the first upper portion includes the steps of: forming a first thin film made of a material containing titanium on the first axial layer; and forming a second thin film made of ITO on the first thin film; The first thin film is formed to a thickness of greater than 100 nm. The method for manufacturing a motherboard according to claim 22.

24. the step of removing the first upper portion includes the steps of: removing the second thin film exposed from the resist by performing a first etching; and removing the first thin film exposed from the resist by performing a second etching. The method for manufacturing a motherboard according to claim 23.

25. forming a conductive layer in the peripheral region before the step of forming the rib layer; In the step of forming the rib layer, the rib layer is formed to cover the conductive layer, performing the second etching to form a terminal opening in the rib layer that overlaps with the conductive layer; The method for manufacturing a motherboard according to claim 24.

26. the first etching is a wet etching; The second etching is a dry etching. The method for manufacturing a motherboard according to claim 24 or 25.

27. forming a conductive layer in the peripheral region before the step of forming the rib layer; In the step of forming the rib layer, the rib layer is formed to cover the conductive layer, After the second etching, a third etching is performed to form a terminal opening in the rib layer that overlaps with the conductive layer. The method for manufacturing a motherboard according to claim 24.

28. the first etching is a wet etching; the second etching is a dry etching, The third etching is a dry etching. The method for manufacturing a motherboard according to claim 27.

29. In the step of forming the resist, the resist is exposed using a mask having an opening with a width smaller than a width of the first upper portion. The method for manufacturing a motherboard according to claim 22.

30. In the step of forming the first partition wall, a second partition wall including a second bottom layer formed on the rib layer, a second axial layer formed on the second bottom layer and having conductivity, and a second upper portion formed on the second axial layer is formed in the display area.

23. The method for manufacturing a motherboard according to claim 15, 19 or 22.

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