Photoelectric conversion apparatus, photoelectric conversion system, apparatus, and signal processing method for photoelectric conversion apparatus

Abstract

To perform focus detection and image generation at high speed.SOLUTION: A photoelectric conversion apparatus including a plurality of pixels arranged in a matrix, the photoelectric conversion apparatus comprising: a first pixel and a second pixel arranged in a first row; a first microlens corresponding to the first pixel; and a second microlens corresponding to the second pixel, wherein a pair of a signal based on a first charge and a signal based on a fourth charge is output using a first control line to be used for focus detection and image generation.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device, a photoelectric conversion system, an apparatus, and a signal processing method for a photoelectric conversion device. [Background technology]

[0002] Patent Document 1 discloses an image sensor that has pixels including a plurality of photodiodes and outputs a signal for focus detection and a signal for image generation. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-98968 Summary of the Invention [Problem to be solved by the invention]

[0004] The image sensor disclosed in Patent Document 1 outputs a signal corresponding to one frame as a focus detection signal, while outputting signals corresponding to multiple frames as an image generation signal, which results in a lower frame rate during image generation.

[0005] SUMMARY OF THE INVENTION An object of the present invention is to provide a photoelectric conversion device that is capable of performing focus detection and image generation at high speed. [Means for solving the problem]

[0006] According to one disclosure of the present specification, there is provided a photoelectric conversion device having a plurality of pixels arranged in a matrix, the photoelectric conversion device including first and second pixels arranged in a first row, a first microlens corresponding to the first pixel, and a second microlens corresponding to the second pixel, the first pixel including a first photoelectric conversion element configured to photoelectrically convert light transmitted through the first microlens to generate a first charge, a second photoelectric conversion element configured to photoelectrically convert light transmitted through the first microlens to generate a second charge, a first floating diffusion configured to accumulate at least one of the first charge and the second charge, a first transfer transistor configured to transfer the first charge to the first floating diffusion, and a second transfer transistor configured to transfer the second charge to the first floating diffusion, the second pixel including a third photoelectric conversion element configured to photoelectrically convert light transmitted through the second microlens to generate a third charge, and a second transfer transistor configured to transfer the second charge to the first floating diffusion. a fourth photoelectric conversion element that generates a fourth charge by photoelectrically converting light that has passed through a lens, a second floating diffusion that accumulates at least one of the third charge and the fourth charge, a third transfer transistor that transfers the third charge to the second floating diffusion, and a fourth transfer transistor that transfers the fourth charge to the second floating diffusion, wherein the photoelectric conversion device has a first control line connected to the first transfer transistor and the fourth transfer transistor, and a second control line connected to the second transfer transistor and the third transfer transistor, the third photoelectric conversion element and the fourth photoelectric conversion element are arranged in this order in a direction from the first photoelectric conversion element to the second photoelectric conversion element, and the photoelectric conversion device outputs a set of a signal based on the first charge and a signal based on the fourth charge using the first control line for use in focus detection and image generation. [Effects of the Invention]

[0007] According to the present invention, focus detection and image generation can be performed at high speed. [Brief explanation of the drawings]

[0008] [Figure 1]FIG. 1 is a block diagram illustrating a photoelectric conversion device according to a first embodiment. [Figure 2] 1 is a circuit diagram illustrating a photoelectric conversion device according to a first embodiment; [Figure 3] FIG. 1 is a plan view illustrating a photoelectric conversion device according to a first embodiment; [Figure 4] FIG. 1 is a block diagram illustrating a photoelectric conversion device according to a first embodiment. [Figure 5] 1 is a driving timing chart illustrating a photoelectric conversion device according to a first embodiment; [Figure 6] FIG. 1 is a block diagram illustrating a photoelectric conversion device according to a first embodiment. [Figure 7] FIG. 10 is a block diagram illustrating a photoelectric conversion device according to a second embodiment. [Figure 8] FIG. 10 is a block diagram illustrating a photoelectric conversion device according to a second embodiment. [Figure 9] FIG. 10 is a circuit diagram illustrating a photoelectric conversion device according to a second embodiment. [Figure 10] FIG. 10 is a block diagram illustrating a photoelectric conversion device according to a third embodiment. [Figure 11] FIG. 10 is a circuit diagram illustrating a photoelectric conversion device according to a third embodiment. [Figure 12] 10 is a driving timing chart illustrating a photoelectric conversion device according to a third embodiment. [Figure 13] 10 is a driving timing chart illustrating a photoelectric conversion device according to a third embodiment. [Figure 14] 10 is a driving timing chart illustrating a photoelectric conversion device according to a third embodiment. [Figure 15] 10 is a driving timing chart illustrating a photoelectric conversion device according to a fourth embodiment. [Figure 16] Schematic diagram illustrating a device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Each embodiment will be described below with reference to the drawings. Note that the following embodiments do not limit the scope of the claimed invention. Although multiple features are described in the embodiments, not all of these features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same or similar components are given the same reference numerals, and redundant description will be omitted. Also, in the following embodiments, an imaging sensor will be mainly described as an example of a photoelectric conversion device. However, each embodiment is not limited to an imaging sensor and can be applied to other examples of photoelectric conversion devices. Examples include an imaging device, a range finder (a device for measuring distance using focus detection or TOF (Time Of Flight)), and a photometric device (a device for measuring the amount of incident light).

[0010] In this specification, terms indicating specific directions or positions (for example, "upper," "lower," "right," "left," and other terms including these terms) are used as necessary. The use of these terms is for the purpose of facilitating understanding of the embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention.

[0011] In this specification, the phrase "electrically connecting component A and component B" does not necessarily mean that component A and component B are directly connected. For example, even if another component C is connected between component A and component B, it is acceptable as long as they are electrically connected.

[0012] In this specification, "plane" refers to a surface parallel to the main surface of a substrate. The main surface of a substrate may be the light incident surface of a substrate including a photoelectric conversion element, a surface on which multiple AD (Analog-Digital) conversion circuits are repeatedly arranged, or a bonding surface between substrates in a stacked photoelectric conversion device. Furthermore, "plan view" refers to a view from a direction perpendicular to the main surface of the substrate. Furthermore, "cross section" refers to a surface perpendicular to the light incident surface of a semiconductor layer. Furthermore, "cross section" refers to a view from a direction parallel to the main surface of the substrate.

[0013] Metallic components such as wiring and pads described herein may be composed of a single metal element or a mixture (alloy). For example, wiring described as copper wiring may be composed of copper alone or may be composed primarily of copper with other components. Furthermore, for example, pads connected to external terminals may be composed of aluminum alone or may be composed primarily of aluminum with other components. The copper wiring and aluminum pads shown here are merely examples and can be replaced with various metals. Furthermore, the wiring and pads shown here are merely examples of metallic components used in photoelectric conversion devices and may also be applied to other metallic components.

[0014] In the following embodiments, a form of adding multiple signals will be described. This addition means mixing multiple signals. Therefore, the signal obtained by addition is not limited to the sum of multiple signals. For example, if two signals A and B are used as multiple signals, the "addition" in the following embodiments is not limited to A+B, which is the sum of signals A and B. For example, the "addition" may be a form of obtaining an average signal of signals A and B. Furthermore, the "addition" may be an addition process using a signal obtained by multiplying at least one of signals A and B by a coefficient. In other words, if the coefficients are α and β, a form of obtaining a signal of α×A+β×B is also included in the scope of adding signals A and B.

[0015] First Embodiment A photoelectric conversion device (a signal processing method for a photoelectric conversion device) according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 6. FIG.

[0016] FIG. 1 is an example of a block diagram of a photoelectric conversion device according to this embodiment.

[0017] As shown in FIG. 1, the photoelectric conversion device 1 includes a pixel array 11, a vertical scanning circuit 12, a timing signal output circuit 13, an AD (Analog-to-Digital) conversion unit 14, and a signal output circuit 15. The signal correction circuit 2 includes a focus detection circuit 20 and an image generation circuit 21, and performs signal processing on a signal output from the signal output circuit 15. Note that FIG. 1 illustrates a configuration in which the signal correction circuit 2 is arranged outside the photoelectric conversion device 1. Typically, the signal correction circuit 2 is provided on a chip separate from the chip on which the photoelectric conversion device 1 is formed. However, the present embodiment is not limited to this configuration, and the signal correction circuit 2 may be arranged inside the photoelectric conversion device 1.

[0018] The pixel array 11 has a plurality of pixels 10 arranged in a matrix across a plurality of rows and a plurality of columns. Each of the plurality of pixels 10 includes a photoelectric conversion element that generates and accumulates an electric charge according to the amount of light received, and outputs a pixel signal through photoelectric conversion. Note that in this specification, the horizontal direction in the drawings may be referred to as the row direction, and the vertical direction as the column direction. The number of rows and columns of the plurality of pixels 10 arranged in the pixel array 1 is not particularly limited. The plurality of pixels 10 may include effective pixels that output pixel signals according to the amount of incident light, as well as optical black pixels in which the photoelectric conversion element is shielded from light, dummy pixels that do not output a signal to an output line 108 (described later), and the like.

[0019] Also, color filters in a Bayer array are arranged corresponding to the plurality of pixels 10. For example, in the pixels 10 arranged in odd-numbered rows, red color filters are arranged corresponding to the pixels 10 arranged in odd-numbered columns, and green color filters are arranged corresponding to the pixels 10 arranged in even-numbered columns. Furthermore, in the pixels 10 arranged in even-numbered rows, green color filters are arranged corresponding to the pixels 10 arranged in odd-numbered columns, and blue color filters are arranged corresponding to the pixels 10 arranged in even-numbered columns. Note that the red color filter may be referred to as R, the green color filter as G, and the blue color filter as B, respectively.

[0020] The vertical scanning circuit 12 sequentially selects predetermined rows from among the multiple rows in which the pixels 10 are arranged, and supplies a drive signal to each row. The timing signal output circuit 13 supplies a vertical address signal, a control timing signal, and a drive signal for the pixels 10 to the vertical scanning circuit 12.

[0021] The timing signal output circuit 13 supplies a control timing signal and a horizontal scanning signal to the AD conversion unit 14. The timing signal output circuit 13 may be capable of setting a reference drive for the photoelectric conversion device through an external input and changing the settings of the photoelectric conversion device through communication. The signal output by the timing signal output circuit 13 may be generated by the timing signal output circuit 13 itself or by a circuit different from the timing signal output circuit 13.

[0022] The AD conversion unit 14 has an AD conversion circuit corresponding to each column in which the pixels 10 are arranged. The AD conversion unit 14 performs AD conversion on pixel signals, which are analog signals input from the pixels 10, and outputs digital signals. A plurality of AD conversion units 14 may be arranged in the vertical direction (up and down) of the pixel array 11. For example, pixel signals output from pixels 10 arranged in odd-numbered columns are input to the lower AD conversion unit 14, and pixel signals output from pixels 10 arranged in even-numbered columns are input to the upper AD conversion unit 14. The AD conversion method can be various, such as slope AD conversion, successive approximation AD conversion, or ΔΣ AD conversion.

[0023] The digital signal processed by the AD conversion unit 14 is temporarily stored, for example, in a memory included in the AD conversion unit 14. This stored digital signal is horizontally scanned, and the digital signal is input to the signal output circuit 15. The signal output circuit 15 outputs a signal conforming to the protocol within the system to the signal correction circuit 2 via the bus.

[0024] The focus detection circuit 20 is capable of performing focus detection by phase difference detection using the output signal of the photoelectric conversion device 1, which is based on the signal output by the pixel 10. The image generation circuit 21 is capable of generating an image by adding multiple signals using the same signal as that used for focus detection described above. In this way, by supplying the same signal to the focus detection circuit 20 and the image generation circuit 21, it is possible to perform focus detection and image generation in one frame.

[0025] 2 is an example of a circuit diagram of a pixel 10 included in the photoelectric conversion device according to this embodiment. Note that the present disclosure can be applied to both front-illuminated and back-illuminated sensors.

[0026] As shown in FIG. 2( a), the pixel 10 includes a first photoelectric conversion element 101, a second photoelectric conversion element 102, a first transfer transistor 103, a second transfer transistor 104, and a floating diffusion 109. Hereinafter, in this specification, the floating diffusion 109 may be referred to as FD109 (FD is an abbreviation for Floating Diffusion). The FD109 may also be referred to as a floating diffusion region 109. The pixel 10 further includes a reset transistor 105 for resetting the FD109, an amplification transistor 106 for amplifying a signal, and a selection transistor 107. The first photoelectric conversion element 101 and the second photoelectric conversion element 102 are electrically connected to a reference voltage node GND, and a reference voltage is supplied to them. The reset transistor 105 and the amplification transistor 106 are electrically connected to a power supply voltage node VDD, and a power supply voltage is supplied to them.

[0027] Here, the voltage of the power supply voltage node VDD is set to a voltage between 1 and 5V. Also, the voltage of the reference voltage node GND is set to 0V, but this is not limited to this. For example, the voltage of the reference voltage node GND may be a negative voltage, or a positive voltage smaller than the voltage of the power supply voltage node VDD. Also, the voltages of the power supply voltage node VDD and the reference voltage node GND may each be variable.

[0028] Note that the first transfer transistor 103, the second transfer transistor 104, the reset transistor 105, the amplification transistor 106, and the selection transistor 107 may each be an N-type MOS transistor or a P-type MOS transistor. In this embodiment, a case will be described in which, of the electron-hole pairs generated in the first photoelectric conversion element 101 and the second photoelectric conversion element 102 by incident light, electrons are used as signal charges. When electrons are used as signal charges, each transistor included in the pixel 10 may be configured as an N-type MOS transistor. However, the signal charges are not limited to electrons, and holes may also be used as signal charges. When holes are used as signal charges, each transistor included in the pixel 10 may be configured as a P-type MOS transistor different from that described in this embodiment.

[0029] The first photoelectric conversion element 101 and the second photoelectric conversion element 102 are, for example, photodiodes. The first photoelectric conversion element 101 and the second photoelectric conversion element 102 are not limited to photodiodes and may be, for example, photoelectric conversion films. The first photoelectric conversion element 101 and the second photoelectric conversion element 102 receive light incident on the pixel 10, generate charges corresponding to the incident light, and accumulate the charges. The reset transistor 105 is driven by a control signal res. When the reset transistor 105 is turned on (conductive), the FD 109 is reset to a voltage based on the power supply voltage. When the reset transistor 105 is turned off (non-conductive), the FD 109 is released from the reset state. The first transfer transistor 103 is driven by a control signal tx1. When the first transfer transistor 103 is turned on, charges generated in the first photoelectric conversion element 101 are transferred to the FD 109. The second transfer transistor 104 is driven by a control signal tx2. When the second transfer transistor 104 is turned on, the charge generated in the second photoelectric conversion element 102 is transferred to the FD unit 109. The FD 109 temporarily holds the charge input from at least one of the first photoelectric conversion element 101 and the second photoelectric conversion element 102 and functions as a charge-voltage conversion unit that converts the held charge into a voltage signal. The amplification transistor 106 amplifies the pixel signal (voltage signal) converted by the FD 109. The selection transistor 107 is driven by a control signal sel to connect the amplification transistor 106 to an output line 108 and output the pixel signal amplified by the amplification transistor 106 to the output line 108. Note that the pixel signal may include a reset level signal (noise signal) of the FD 109 and signals (photoelectric conversion signals) output from the first photoelectric conversion element 101 and the second photoelectric conversion element 102. The noise signal is a signal that mainly contains noise components possessed by the pixel 10.

[0030] The pixel 10 shown in FIG. 2(b) differs from the pixel 10 shown in FIG. 2(a) in the correspondence between the control signal and the transfer transistor (photoelectric conversion element). Specifically, in the pixel 10 shown in FIG. 2(b), the first transfer transistor 103 is driven by a control signal tx2, and the second transfer transistor 104 is driven by a control signal tx1. Note that the pixel 10 shown in FIG. 2(a) may be referred to as an A-type pixel 10, and the pixel 10 shown in FIG. 2(b) may be referred to as a B-type pixel 10. The pixel array 11 includes both the A-type pixels 10 and the B-type pixels 10, and a detailed configuration will be described later with reference to FIG. 4.

[0031] In this embodiment, a common amplification transistor 106 is provided corresponding to two photoelectric conversion elements, the first photoelectric conversion element 101 and the second photoelectric conversion element 102. Here, by driving the first transfer transistor 103 and the second transfer transistor 104 at the same timing, pixel signals are output from each of the first photoelectric conversion element 101 and the second photoelectric conversion element 102. Then, by adding the pixel signals output from each of the first photoelectric conversion element 101 and the second photoelectric conversion element 102 in the FD 109, a signal for image generation can be output. Meanwhile, by driving the first transfer transistor 103 and the second transfer transistor 104 at different timings, a phase difference signal for focus detection can be output.

[0032] The configuration of pixel 10 shown in FIG. 2 is merely an example, and pixel 10 may further include a transistor having a predetermined function. For example, a transistor for changing the capacitance value of FD 109 or a transistor for discharging charge from at least one of first photoelectric conversion element 101 and second photoelectric conversion element 102 may be further provided. Alternatively, pixel 10 may not include selection transistor 107, and the selected / unselected state of pixel 10 may be changed depending on the voltage input from reset transistor 105 to FD 109. When multiple output lines 108 are provided in one pixel column, one pixel 10 may include multiple selection transistors 107 connected to different output lines 108. Although pixel 10 shown in FIG. 2 shares FD 109 with first photoelectric conversion element 101 and second photoelectric conversion element 102, FD 109 may be provided for each of first photoelectric conversion element 101 and second photoelectric conversion element 102.

[0033] FIG. 3 is an example of a plan view of a pixel 10 included in the photoelectric conversion device according to this embodiment.

[0034] As shown in FIG. 3 , a microlens 110 is arranged corresponding to a pixel 10. The first photoelectric conversion element 101 is arranged corresponding to the left side of the microlens 110, and the second photoelectric conversion element 102 is arranged corresponding to the right side of the microlens 110. In other words, the first photoelectric conversion element 101 and the second photoelectric conversion element 102 are arranged so as to receive light passing through different regions of the pupil of the optical system. With this configuration, phase difference detection can be performed using different parallax signals on the left and right. Note that the first photoelectric conversion element 101 may be arranged corresponding to the upper side of the microlens 110, and the second photoelectric conversion element 102 may be arranged corresponding to the lower side of the microlens 110.

[0035] 4 is an example of a block diagram of a photoelectric conversion device according to this embodiment. Note that, as an example, FIG. 4 shows two pixels 10 in the vertical direction (first and second rows from the top) and 12 pixels 10 in the horizontal direction (first, second,..., twelfth columns from the left) of the multiple pixels 10 included in the pixel array 11. Furthermore, control signal tx1[0] and control signal tx2[0] indicate the control signal tx1 and control signal tx2 supplied to the pixel 10 arranged in the first row. Furthermore, control signal tx1[1] and control signal tx2[1] indicate the control signal tx1 and control signal tx2 supplied to the pixel 10 arranged in the second row.

[0036] As shown in FIG. 4, a first control line 134 that supplies a control signal tx1 to the pixel 10 and a second control line 135 that supplies a control signal tx2 to the pixel 10 are arranged. The connection relationship between the pixel 10 and the first control line 134 and the second control line 135 will be described using FIG. 4. A connection portion 120 indicates that the first control line 134 is connected to the gate of the first transfer transistor 103 corresponding to the first photoelectric conversion element 101 arranged on the left side of the pixel 10. A connection portion 121 indicates that the second control line 135 is connected to the gate of the second transfer transistor 104 corresponding to the second photoelectric conversion element 102 arranged on the right side of the pixel 10. A connection portion 122 indicates that the second control line 135 is connected to the gate of the first transfer transistor 103 corresponding to the first photoelectric conversion element 101 arranged on the left side of the pixel 10. Furthermore, the connection portion 123 indicates that the first control line 134 is connected to the second photoelectric conversion element 102 arranged to the right of the pixel 10. That is, among the pixels 10 arranged in the first row, the pixels 10 arranged in the first, second, fifth, sixth, ninth, and tenth columns are type A, and the pixels 10 arranged in the third, fourth, seventh, eighth, eleventh, and twelfth columns are type B. Furthermore, among the pixels 10 arranged in the second row, the pixels 10 arranged in the first, second, fifth, sixth, ninth, and tenth columns are type A, and the pixels 10 arranged in the third, fourth, seventh, eighth, eleventh, and twelfth columns are type B. Thus, in the present embodiment shown in FIG. 4, the pixels 10 arranged in different rows of the same column are of the same type, and the A-type pixels 10 and the B-type pixels 10 are alternately arranged every two columns. The pixels 10 arranged in the first row, first column, the first row, third column, the second row, first column, the second row, third column, and the first row, second column may be referred to as the first pixel, the second pixel, the third pixel, the fourth pixel, and the fifth pixel. The microlenses 110 arranged corresponding to the first to fifth pixels may be referred to as the first microlens, the second microlens, the third microlens, the fourth microlens, and the fifth microlens. The FDs 109 included in the first to third pixels may be referred to as the first floating diffusion, the second floating diffusion, and the third floating diffusion. The FDs 109 included in the fourth and fifth pixels may be referred to as the fourth floating diffusion and the fifth floating diffusion.The first photoelectric conversion element 101 that generates the first charge and the second photoelectric conversion element 102 that generates the second charge, which are included in the second pixel, may be referred to as the third photoelectric conversion element that generates the third charge and the fourth photoelectric conversion element that generates the fourth charge, respectively. The first transfer transistor 103 and the second transfer transistor 104 that the second pixel has may be referred to as the third transfer transistor and the fourth transfer transistor, respectively. The first photoelectric conversion element 101 that generates the first charge and the second photoelectric conversion element 102 that generates the second charge, which are included in the third pixel, may be referred to as the fifth photoelectric conversion element that generates the fifth charge and the sixth photoelectric conversion element that generates the sixth charge, respectively. The first transfer transistor 103 and the second transfer transistor 104 that the third pixel has may be referred to as the fifth transfer transistor and the sixth transfer transistor, respectively. The first photoelectric conversion element 101 that generates the first charge and the second photoelectric conversion element 102 that generates the second charge, which are included in the fourth pixel, may be referred to as the seventh photoelectric conversion element that generates the seventh charge and the eighth photoelectric conversion element that generates the eighth charge, respectively. The first transfer transistor 103 and the second transfer transistor 104 that are included in the fourth pixel may be referred to as the seventh transfer transistor and the eighth transfer transistor, respectively. The first photoelectric conversion element 101 that generates the first charge and the second photoelectric conversion element 102 that generates the second charge, which are included in the fifth pixel, may be referred to as the ninth photoelectric conversion element that generates the ninth charge and the tenth photoelectric conversion element that generates the tenth charge, respectively. The first transfer transistor 103 and the second transfer transistor 104 that are included in the fifth pixel may be referred to as the ninth transfer transistor and the tenth transfer transistor, respectively. The first control line 134 and the second control line 135 corresponding to the pixels 10 arranged in the second row may be referred to as the third control line and the fourth control line, respectively.

[0037] The AD conversion unit 14 will be described. Here, a form will be described in which the AD conversion unit 14 is a circuit that performs slope-type AD conversion. The AD conversion unit 14 has an AD conversion circuit 141 and a switch 142 corresponding to each column in which the pixels 10 are arranged. Pixel signals output from the pixels 10 are input to the AD conversion circuit 141 via output lines 108, and signals output from the AD conversion circuit 141 are input to the signal output circuit 15 via the switch 142. Pixel signals output from the pixels 10 arranged in odd-numbered columns are input to the AD conversion unit 14 arranged above the pixel array 11. Pixel signals output from the pixels 10 arranged in even-numbered columns are input to the AD conversion unit 14 arranged below the pixel array 11. For example, when the AD conversion circuit 141 performs slope-type AD conversion, the AD conversion circuit 141 includes a comparator and a counter (the comparator and counter are not shown). The comparator compares the pixel signal with the reference signal, and the counter holds a count value corresponding to the inversion timing of the comparator, thereby causing the AD conversion circuit 141 to perform AD conversion. Note that the AD conversion unit 14 arranged above the pixel array 11 has the same configuration as the AD conversion unit 14 arranged below the pixel array 11, and is therefore omitted from Figure 4.

[0038] The switches 142 corresponding to the first, fifth, and ninth columns are connected to a horizontal transfer line 143 (channel chA), and the switches 142 corresponding to the third, seventh, and eleventh columns are connected to a horizontal transfer line 144 (channel chB). The switches 142 are ON / OFF controlled by a control signal hadr, and are sequentially turned ON / OFF in the horizontal direction. When the switch 142 is ON, the digital signal output from the AD conversion circuit 141 is input to the signal output circuit 15 via the horizontal transfer line 143 or horizontal transfer line 144. The digital signals output from the AD conversion circuits 141 corresponding to the first, third, fifth, seventh, ninth, and eleventh columns are represented as signals ado(0) to ado(5), respectively. The control signals of the switches 142 corresponding to the first, third, fifth, seventh, ninth, and eleventh columns are represented as control signal hadr(0) to control signal hadr(5), respectively.

[0039] Fig. 5 is an example of a drive timing chart for the photoelectric conversion device according to this embodiment. Note that the first photoelectric conversion element 101 and the second photoelectric conversion element 102, which are indicated by diagonal lines in Fig. 4, are not read out in the drive timing chart shown in Fig. 5.

[0040] In Fig. 5, the horizontal axis represents time, and the timing of each drive pulse (each control signal), the digital value corresponding to each digital signal, and the digital value output to each channel are schematically shown. Each control signal shown in Fig. 5 corresponds to each control signal shown in Fig. 2 and Fig. 4.

[0041] At time t1, the vertical scanning circuit 12 sets the control signal VD (vertical synchronization signal) to low level, thereby starting one frame. At time t2, the vertical scanning circuit 12 sets the control signal HD (horizontal synchronization signal) to high level, thereby starting operation for one row. Furthermore, at time t2, the vertical scanning circuit 12 sets the control signal VD to low level, the control signal res[0] to low level, and the control signal sel[0] to high level.

[0042] During the period from time t3 to time t4, the vertical scanning circuit 12 sets the control signal tx1[0] to a high level and keeps the control signal tx2[0] at a low level. Here, [0] represents the row address indicating the first row, and the same control signal is supplied to the multiple pixels 10 arranged in the first row. As shown in FIG. 4, among the multiple pixels 10 arranged in the first row, the A-type pixels 10 arranged in columns 1, 2, 5, 6, 9, and 10 output pixel signals corresponding to the first photoelectric conversion elements 101 arranged on the left side. Furthermore, among the pixels 10 arranged in the first row, the B-type pixels 10 arranged in columns 3, 4, 7, 8, 11, and 12 output pixel signals corresponding to the second photoelectric conversion elements 102 arranged on the right side. Therefore, the pixels 10 arranged in the first row output pixel signals corresponding to either the photoelectric conversion elements arranged on the left or right side. At this time, the pixel signals output from the pixels 10 are switched between the pixel signals corresponding to the first photoelectric conversion elements 101 and the pixel signals corresponding to the second photoelectric conversion elements 102 every two columns.

[0043] At time t5, the AD conversion circuit 141 completes the AD conversion and holds the acquired digital values. Here, for signals ado(0) to ado(5), the digital values ​​corresponding to the photoelectric conversion elements driven by the control signal tx1[0] are set to values ​​d00 to d05, respectively.

[0044] At time t6, the timing signal output circuit 13 starts supplying the control signal hadr to the AD conversion unit 14, causing signals ado(0) to ado(5) to be output sequentially. In the first cycle, the control signal hadr(0) and the control signal hadr(1) are input to the switch 142. In the second cycle, the control signal hadr(2) and the control signal hadr(3) are input to the switch 142. In the third cycle, the control signal hadr(4) and the control signal hadr(5) are input to the switch 142. As a result, values ​​d00, d02, and d04 are output sequentially to the horizontal transfer line 143 (channel chA), and values ​​d01, d03, and d05 are output sequentially to the horizontal transfer line 144 (channel chB). Therefore, a signal corresponding to the first photoelectric conversion element 101 arranged on the left side of the pixel 10 is output to channel chA, and a signal corresponding to the second photoelectric conversion element 102 arranged on the right side of the pixel 10 is output to channel chB.

[0045] The driving performed on the pixels 10 arranged in the first row during the period from time t2 to time t6 is then performed on the pixels 10 arranged in the second row during the period from time t7 to time t11. Note that readout of the signals corresponding to the pixels 10 in the first row does not have to be completed at time t7, and readout of the signals corresponding to the pixels 10 in the first row and control of the pixels 10 in the second row may be processed in parallel. This is because readout of the signals corresponding to the pixels 10 in the first row is performed based on the information held in the AD conversion circuit 141, and therefore it is sufficient that readout of the signals corresponding to the pixels 10 in the first row is completed by the time the digital signals corresponding to the pixels 10 in the second row are held in the AD conversion circuit 141.

[0046] At time t7, the vertical scanning circuit 12 sets the control signal HD to high level, thereby starting operation for one row. Furthermore, at time t7, the vertical scanning circuit 12 sets the control signal res[0] to high level, the control signal sel[0] to low level, the control signal res[1] to low level, and the control signal sel[1] to high level.

[0047] During the period from time t8 to time t9, the vertical scanning circuit 12 sets the control signal tx1[1] to a high level and keeps the control signal tx2[1] at a low level. Here, [1] represents the row address indicating the second row, and the same control signal is supplied to the multiple pixels 10 arranged in the second row. As shown in FIG. 4, among the multiple pixels 10 arranged in the second row, the A-type pixels 10 arranged in columns 1, 2, 5, 6, 9, and 10 output pixel signals corresponding to the first photoelectric conversion elements 101 arranged on the left side. Furthermore, among the pixels 10 arranged in the second row, the B-type pixels 10 arranged in columns 3, 4, 7, 8, 11, and 12 output pixel signals corresponding to the second photoelectric conversion elements 102 arranged on the right side. Therefore, the pixels 10 arranged in the second row output pixel signals corresponding to either the photoelectric conversion elements arranged on the left or right side. At this time, the pixel signals output from the pixels 10 are switched between the pixel signals corresponding to the first photoelectric conversion elements 101 and the pixel signals corresponding to the second photoelectric conversion elements 102 every two columns.

[0048] At time t10, the AD conversion circuit 141 completes the AD conversion and holds the acquired digital values. Here, for signals ado(0) to ado(5), the digital values ​​corresponding to the photoelectric conversion elements driven by the control signal tx1[1] are set to values ​​d10 to d15, respectively. It is assumed that by time t10, reading of the digital signals corresponding to the pixels 10 arranged in the first row has been completed.

[0049] At time t11, the timing signal output circuit 13 starts supplying the control signal hadr to the AD conversion unit 14, causing signals ado(0) to ado(5) to be output sequentially. In the first cycle, the control signal hadr(0) and the control signal hadr(1) are input to the switch 142. In the second cycle, the control signal hadr(2) and the control signal hadr(3) are input to the switch 142. In the third cycle, the control signal hadr(4) and the control signal hadr(5) are input to the switch 142. As a result, values ​​d10, d12, and d14 are output sequentially to the horizontal transfer line 143 (channel chA), and values ​​d11, d13, and d15 are output sequentially to the horizontal transfer line 144 (channel chB). Therefore, a signal corresponding to the first photoelectric conversion element 101 arranged on the left side of the pixel 10 is output to channel chA, and a signal corresponding to the second photoelectric conversion element 102 arranged on the right side of the pixel 10 is output to channel chB.

[0050] The driving described above is performed row by row, and signals corresponding to all the pixels 10 are read out, thereby completing the driving for one frame.

[0051] FIG. 6 is an example of a block diagram of the signal correction circuit 2 according to this embodiment.

[0052] 6, the signal correction circuit 2 has a focus detection circuit 20 and an image generation circuit 21. Furthermore, a signal corresponding to the first photoelectric conversion element 101 input to channel chA and a signal corresponding to the second photoelectric conversion element 102 input to channel chB are input to the focus detection circuit 20 and the image generation circuit 21.

[0053] The focus detection circuit 20 has a peak detection circuit 201 and a phase difference detection circuit 202. The peak detection circuit 201 performs peak detection on signals sequentially input via channel chA. Furthermore, the peak detection circuit 201 performs peak detection on signals sequentially input via channel chB. The phase difference detection circuit 202 compares the peak positions of the signals sequentially input via channel chA detected by the peak detection circuit 201 with the peak positions of the signals sequentially input via channel chB. As a result, the phase difference detection circuit 202 detects whether the image is in focus, front-focused, or back-focused.

[0054] The image generation circuit 21 has an adder circuit 211 and a generation circuit 212. The adder circuit 211 adds signals input sequentially via channels chA and chB in the order of input. Thus, in FIG. 4, a signal corresponding to the first photoelectric conversion element 101 arranged to the left of the pixels 10 in the first column and a signal corresponding to the second photoelectric conversion element 102 arranged to the right of the pixels 10 in the third column are added (horizontal addition). The generation circuit 212 uses the signal added by the adder circuit 211 to perform noise removal, filtering, and other processing, and makes corrections suitable for the display system or recording system.

[0055] In this embodiment, it is possible to generate an image using signals output from multiple pixels 10 in one frame, and to perform focus detection using the same signals. This configuration is suitable for, for example, capturing video while measuring distances.

[0056] Although color filters are not shown here, consider a configuration in which color filters are arranged in a Bayer array. For example, among the pixels 10 arranged in the first row, red color filters are arranged corresponding to the pixels 10 arranged in the odd-numbered columns, and green color filters are arranged corresponding to the pixels 10 arranged in the even-numbered columns. Furthermore, among the pixels 10 arranged in the second row, green color filters are arranged corresponding to the pixels 10 arranged in the odd-numbered columns, and blue color filters are arranged corresponding to the pixels 10 arranged in the even-numbered columns. In this configuration, the signals added by the adder circuit 211 are those output from pixels 10 having color filters of the same color. Therefore, the adder circuit 211 can add signals from two pixels having color filters of the same color and arranged in the same row.

[0057] Although the present embodiment has been described with reference to an example in which vertical scanning is performed by selecting one row at a time, vertical scanning may also be performed by simultaneously selecting two rows, the first and third rows. In this case, by connecting the pixels 10 arranged in the first and third rows to a single output line 108, signals output from the pixels 10 arranged in the first and third rows can be added (vertical addition). With this configuration, signals output from two pixels 10 in each of the horizontal and vertical directions, i.e., a total of four pixels 10, can be added (horizontal and vertical addition). In the configuration in which the above-described Bayer array color filters are arranged, the four pixels 10 performing horizontal and vertical addition have color filters of the same color, so horizontal and vertical addition can be performed using signals corresponding to the same color.

[0058] Second Embodiment A photoelectric conversion device (signal processing method for a photoelectric conversion device) according to a second embodiment of the present invention will be described with reference to Figures 7 to 9. Note that components similar to those in the first embodiment are denoted by the same reference numerals, and descriptions of these components may be omitted or simplified.

[0059] The second embodiment differs from the first embodiment in that a processing circuit is provided Fig. 7 is an example of a block diagram of a photoelectric conversion device according to this embodiment.

[0060] As shown in FIG. 7, the photoelectric conversion device 1 includes a pixel array 11, a vertical scanning circuit 12, a timing signal output circuit 13, an AD conversion unit 14, a signal output circuit 15, and a processing circuit 16. The signal correction circuit 2 includes a focus detection circuit 20. Note that FIG. 7 illustrates a configuration in which the signal correction circuit 2 is arranged outside the photoelectric conversion device 1. Typically, the signal correction circuit 2 is provided on a chip separate from the chip on which the photoelectric conversion device 1 is formed. However, the present embodiment is not limited to this configuration, and the signal correction circuit 2 may be arranged inside the photoelectric conversion device 1.

[0061] The processing circuit 16 has a compression circuit 17 and an image generation circuit 21. The compression circuit 17 compresses the phase difference signal for focus detection. The digital signals held in the AD conversion unit 14 are sequentially transferred to the processing circuit 16 via channels chA and chB. The processing circuit 16 processes the signals sequentially input by horizontal scanning.

[0062] The signal correction circuit 2 performs focus detection by changing the processing in accordance with the signal compressed by the compression circuit 17. Furthermore, the signal correction circuit 2 performs noise removal, filtering, etc. using the signal output from the image generation circuit 21, and makes corrections suitable for the display system or the recording system. In this embodiment, the photoelectric conversion device 1 has the image generation circuit 21, not the signal correction circuit 2.

[0063] FIG. 8 is an example of a block diagram of the processing circuit 16 included in the photoelectric conversion device 1 according to this embodiment.

[0064] As shown in FIG. 8, the image generation circuit 21 has an adder circuit 211 and a generation circuit 212. The adder circuit 211 adds signals input sequentially via channel chA and channel chB in the order of input. The generation circuit 212 performs gain processing, clamping processing, and the like using the signal added by the adder circuit 211. In this embodiment, the signal correction circuit 2 performs correction processing suitable for the display system or recording system. Therefore, the generation circuit 212 performs preprocessing necessary for the signal correction circuit 2 in the subsequent stage to perform correction processing. The compression circuit 17 included in the processing circuit 16 shown in FIG. 8 will be described later using FIG. 9.

[0065] 9 is an example of a circuit diagram of the compression circuit 17 included in the photoelectric conversion device 1 according to this embodiment. Note that a signal corresponding to channel chA is input to the compression circuit 17 of this embodiment, but a signal corresponding to channel chB is not input. FIGS. 9(a), 9(b), and 9(c) show different driving operations using the same circuit configuration.

[0066] 9(a) shows a driving method in which one pixel's worth of signals is thinned out from two pixels' worth of signals of channel chA that are sequentially input. As shown in FIG. 9(a), the input signal of channel chA is delayed by one cycle in D latch circuit 171 and then input to flip-flop circuit 174 via multiplexer circuits 172 and 173. Here, clock signal 1 / 2clkA is input to flip-flop circuit 174 via multiplexer circuit 175. Clock signal 1 / 2clkA is a clock signal corresponding to the 1 / 2-cycle clock signal clkA. By this driving method, one pixel's worth of signals of two pixels' worth of signals of channel chA that are sequentially input is output as signal FOUTA.

[0067] 9(b) shows a driving method for adding and outputting signals for two pixels of channel chA that are input sequentially. As shown in FIG. 9(b), an adder 176 adds signals from the previous and subsequent stages of the D latch circuit 171. A multiplexer circuit 172 outputs the signal added by the adder 176. The driving of the circuit subsequent to the multiplexer circuit 172 is the same as in FIG. 9(a). By this driving method, a signal obtained by adding signals for two pixels of channel chA that are input sequentially is output as signal FOUTA.

[0068] FIG. 9(c) shows a driving method that not only adds signals for two pixels shown in FIG. 9(b) but also deletes the least significant bits of the added signal (digital signal) (bit number reduction processing). As shown in FIG. 9(c), a bit deletion circuit 177 deletes the least significant bits of the signal output from the multiplexer circuit 172. The signal output from the bit deletion circuit 177 is input to a flip-flop circuit 174 via a multiplexer circuit 173. The driving of the circuit downstream of the multiplexer circuit 173 is the same as in FIG. 9(a). The driving of the circuit upstream of the multiplexer circuit 172 is the same as in FIG. 9(b). By this driving method, a signal obtained by adding signals for two pixels of channel chA that are input sequentially is output as a signal FOUTA with the least significant bits deleted.

[0069] The compression circuit 17 of this embodiment has, for example, the circuit configuration and drive shown in FIG. 9 and compresses the phase difference signal for focus detection. The circuit configuration shown in FIG. 9 may switch between the drive modes shown in FIGS. 9(a), 9(b), and 9(c) depending on the operating mode. When the compression circuit 17 drives as shown in FIG. 9(a), the compression circuit 17 may not include components that are not necessarily required for the drive described using FIG. 9(a). When the compression circuit 17 drives as shown in FIG. 9(b), the compression circuit 17 may not include components that are not necessarily required for the drive described using FIG. 9(b). Various data compression methods are not limited to the circuit configuration and drive shown in FIGS. 9(a), 9(b), and 9(c), and various data compression methods can be applied only to the phase difference signal. Data compression can be applied not only to the phase difference signal for focus detection but also to the signal for image generation. In this case, it is preferable to set the compression rate of the phase difference signal higher than that of the signal for image generation.

[0070] The signal correction circuit 2 subtracts the signal corresponding to channel chA output from the compression circuit 17 from the signals corresponding to channel chA and channel chB output from the image generation circuit 21. Through this subtraction process, the signal correction circuit 2 generates a signal corresponding to channel chB. Then, the signal correction circuit 2 performs peak detection and phase difference detection to perform focus detection using the signal corresponding to channel chA and the signal corresponding to channel chB.

[0071] In this embodiment, it is possible to generate an image using signals output from multiple pixels 10 in one frame, and to perform focus detection using the same signals. This configuration is suitable for, for example, capturing video while measuring distances.

[0072] Furthermore, in this embodiment, by using the compression circuit 17, the data bandwidth of the photoelectric conversion device 1 and the photoelectric conversion system including the photoelectric conversion device 1 can be reduced, and the load on the signal correction circuit 2 can be reduced.

[0073] Third Embodiment A photoelectric conversion device (signal processing method for a photoelectric conversion device) according to a third embodiment of the present invention will be described with reference to Figures 10 to 14. Note that components similar to those in the first and second embodiments are denoted by the same reference numerals, and descriptions of these components may be omitted or simplified.

[0074] The third embodiment differs from the first embodiment in that it includes a processing circuit 16, and the configuration of the processing circuit 16 differs from that of the second embodiment. Fig. 10 is an example of a block diagram of the processing circuit 16 included in the photoelectric conversion device 1 according to this embodiment.

[0075] As shown in FIG. 10, the processing circuit 16 has a compression circuit 17 and an image generation circuit 21. The image generation circuit 21 also has an adder circuit 211 and a generation circuit 212. The adder circuit 211 adds signals input sequentially via channel chA and channel chB in the order of input. The generation circuit 212 performs gain processing, clamp processing, etc. using the signal added by the adder circuit 211. The compression circuit 17 receives the signal output from the adder circuit 211. The adder circuit 211 included in the image generation circuit 21 shown in FIG. 10 will be described later with reference to FIG. 11.

[0076] Fig. 11 is an example of a circuit diagram of the adder circuit 211 included in the photoelectric conversion device 1 according to this embodiment. Fig. 11(a), Fig. 11(b), and Fig. 11(c) show different driving operations for the same circuit configuration.

[0077] FIG. 11(a) shows a driving method in which pixel signals output from two pixels 10 arranged in the same row are added (horizontal addition).

[0078] As shown in FIG. 11(a), the input signal corresponding to channel chA is delayed by two clocks in D latch circuit 311 and D latch circuit 312, and then input to adder 317 via multiplexer circuit 316. Furthermore, the signal corresponding to channel chA that has passed through multiplexer circuit 316 is input to flip-flop circuit 321 in addition to adder 317. Furthermore, the input signal corresponding to channel chB is delayed by two clocks in D latch circuit 318 and D latch circuit 319, and then input to adder 317 via multiplexer circuit 320. Here, the signal corresponding to channel chA and the signal corresponding to channel chB that are input at the same timing are added by adder 317, and then input to flip-flop circuit 322. The signals input to flip-flop circuit 321 and flip-flop circuit 322, respectively, as described above, are output as signal fouta and signal pout1, respectively, using clock signal clka. By such driving, a signal for one pixel corresponding to channel chA is output as signal fouta. Also, a signal obtained by adding the signal for one pixel corresponding to channel chA and the signal for one pixel corresponding to channel chB is output as signal pout1.

[0079] During the addition drive shown in FIG. 11(a), adders 315, 326, and 329 are controlled to output 0. At this time, since adders 315, 326, and 329 output 0, multiplexer circuits 313, 314, 323, 324, 327, and 328 are controlled to output the input 0. With this drive, the signals output from adders 315, 326, and 329 remain 0 and do not fluctuate, thereby reducing power consumption. Note that the clock signal clkb input to flip-flop circuits 330 and 331 may be fixed to a low level. In this case, power consumption can be further reduced by flip-flop circuits 330 and 331.

[0080] Fig. 11(b) shows a drive that adds (horizontal addition) pixel signals output from three pixels 10 arranged in the same row. Fig. 11(b) differs from Fig. 11(a) in that each multiplexer circuit does not output an input 0.

[0081] As shown in FIG. 11(b), the multiplexer circuit 313 is controlled to output the signal douta_dd, the multiplexer circuit 314 is controlled to output the signal douta_d, and the multiplexer circuit 328 is controlled to output a signal corresponding to channel chA. The multiplexer circuit 323 is controlled to output the signal doutb_d, the multiplexer circuit 324 is controlled to output a signal corresponding to channel chB, and the multiplexer circuit 327 is controlled to output the signal add_b1. Through this driving, a signal obtained by adding together two sequentially input signals corresponding to channel chA is output as the signal fouta. A signal obtained by adding together two sequentially input signals corresponding to channel chB is output as the signal foutb. A signal obtained by adding together two sequentially input signals corresponding to channel chA and one pixel corresponding to channel chB is output as the signal pout1. A signal obtained by adding together two sequentially input signals corresponding to channel chB and one pixel corresponding to channel chA is output as the signal pout2.

[0082] During the addition drive shown in Fig. 11(b), the adders 315, 326, and 329, whose outputs were fixed in Fig. 11(a), can output signals that vary in accordance with the results of the addition process. Also, the clock signal clkb, which was fixed at a low level in Fig. 11(a), operates at the same frequency as the clock signal clka.

[0083] Fig. 11(c) shows a drive for adding (horizontal adding) pixel signals output from four pixels 10 arranged in the same row. Fig. 11(c) differs from Fig. 11(b) in the control of multiplexer circuits 320, 325, 327, and 328. Note that multiplexer circuits 327 and 328 are controlled to output 0, similar to Fig. 11(a).

[0084] As shown in FIG. 11(c), multiplexer circuit 320 outputs signal add_b1, and multiplexer circuit 325 outputs signal doutb_dd. Also, adder 326 adds signals doutb_d and doutb_dd, and adder 317 adds signals add_a1 and add_b1. Then, flip-flop circuit 321 outputs signal add_a1 as signal fouta, and flip-flop circuit 322 outputs signal add_out1 as signal pout1. Driven in this manner, a signal for two pixels corresponding to channel chA is output as signal fouta. Also, a signal obtained by adding together signals for two pixels corresponding to channel chA and signals for two pixels corresponding to channel chB is output as signal pout1.

[0085] During the addition drive shown in FIG. 11(c), the signal output from the adder 329 is controlled to remain unchanged at 0. This type of drive reduces power consumption. The clock signal clkb input to the flip-flop circuits 330 and 331 may be fixed to a low level. In this case, the flip-flop circuits 330 and 331 can further reduce power consumption.

[0086] Fig. 12 is an example of a drive timing chart for the photoelectric conversion device according to this embodiment. Fig. 12 illustrates the driving of adding (horizontal addition) pixel signals output from two pixels 10 arranged in the same row, as described with reference to Fig. 11(a).

[0087] In Fig. 12, the horizontal axis represents time, and the timing of each drive pulse (each control signal), the digital value corresponding to each digital signal, and the digital value output to each channel are schematically shown. Each control signal shown in Fig. 12 corresponds to each control signal shown in Fig. 2, Fig. 4, and Fig. 11(a).

[0088] At time t20, the leading signals corresponding to channels chA and chB are input to the adder circuit 211. Here, the leading signal corresponding to channel chA has a value d00, and the leading signal corresponding to channel chB has a value d01.

[0089] At time t21, the signal douta_d output from the D latch circuit 311 becomes a value d00, and the signal doutb_d output from the D latch circuit 311 becomes a value d01.

[0090] At time t22, the signal douta_dd output from the D latch circuit 312 becomes a value d00, and the signal doutb_dd output from the D latch circuit 319 becomes a value d01. Also, at time t22, as shown in FIG. 11(a), the signal douta_dd is input to the adder 317 via the multiplexer circuit 316, and the signal doutb_dd is input to the adder 317 via the multiplexer circuit 320. The adder 317 adds the signals douta_dd and doutb_dd, and the adder 317 outputs the value d00+value d01 as the signal add_out1.

[0091] At time t23, the signal douta_dd is output as the signal fouta from the flip-flop circuit 321. That is, at time t23, the flip-flop circuit 321 outputs a value d00 as the signal fouta. Also, at time t23, the signal add_out1 is output as the signal pout1 from the flip-flop circuit 322. That is, at time t23, the flip-flop circuit 322 outputs a value d00+a value d01 as the signal pout1.

[0092] Note that the same processing as that executed from time t20 to time t23 described above is also executed from time t21 to time t24 using different signals input to the adder circuit 211 via channel chA and channel chB. Furthermore, similar processing is executed sequentially from time t22 onwards.

[0093] The two signals input to the adders 315, 326, and 329 are fixed to 0. Therefore, the signals add_a1, add_b1, and add_out2 output from the adders 315, 326, and 329 are fixed to 0. Furthermore, since the clock signal clkb is fixed to a low level, the signal pout2 output from the flip-flop circuit 730 and the signal foutb output from the flip-flop circuit 731 are also fixed to a low level.

[0094] Fig. 13 is an example of a drive timing chart for the photoelectric conversion device according to this embodiment. Fig. 13 illustrates the driving of adding (horizontal addition) pixel signals output from three pixels 10 arranged in the same row, as described with reference to Fig. 11(b).

[0095] In Fig. 13, the horizontal axis represents time, and the timing of each drive pulse (each control signal), the digital value corresponding to each digital signal, and the digital value output to each channel are schematically shown. Each control signal shown in Fig. 13 corresponds to each control signal shown in Fig. 2, Fig. 4, and Fig. 11(b).

[0096] At time t20, the leading signals corresponding to channels chA and chB are input to the adder circuit 211. Here, the leading signal corresponding to channel chA has a value d00, and the leading signal corresponding to channel chB has a value d01.

[0097] At time t21, the signal douta_d output from the D latch circuit 311 becomes a value d00, and the signal doutb_d output from the D latch circuit 311 becomes a value d01.

[0098] At time t22, the signal douta_dd output from the D latch circuit 312 becomes a value d00, and the signal doutb_dd output from the D latch circuit 319 becomes a value d01.

[0099] 11(b), at time t22, signal douta_d is input to adder 315 via multiplexer circuit 314, and signal douta_dd is input to adder 315 via multiplexer circuit 313. Adder 315 adds signals douta_d and douta_dd, and the adder 315 outputs a value d00+value d02 as signal add_a1. Also, at time t22, as shown in FIG. 11(b), signal doutb_d is input to adder 326 via multiplexer circuit 323, and the signal input from channel chB is input to adder 326 via multiplexer circuit 324. Adder 326 adds signal doutb_d and the signal input from channel chB, and the adder 326 outputs a value d03+value d05 as signal add_b1.

[0100] Also, at time t22, adder 317 adds signal add_a1 and signal doutb_dd, and outputs value d00+value d01+value d02 as signal add_out1 from adder 317. Also, at time t22, adder 329 adds signal add_b1 and the signal input from channel chA, and outputs value d03+value d04+value d05 as signal add_out2 from adder 329.

[0101] At time t23, the flip-flop circuit 321 outputs a signal add_a1 as the signal fouta. That is, at time t23, the flip-flop circuit 321 outputs a value d00+a value d02 as the signal fouta. Also, at time t23, the flip-flop circuit 322 outputs a signal add_out1 as the signal pout1. That is, at time t23, the flip-flop circuit 322 outputs a value d00+a value d01+a value d02 as the signal pout1. Also, at time t23, the flip-flop circuit 330 outputs a signal add_out2 as the signal pout2. That is, at time t23, the flip-flop circuit 330 outputs a value d03+a value d04+a value d05 as the signal pout2. Also, at time t23, the flip-flop circuit 331 outputs a signal add_b1 as the signal foutb. That is, at time t23, the flip-flop circuit 330 outputs the value d03+value d05 as the signal foutb.

[0102] Here, the signals output as signals fouta and foutb are the sum of signals output from two pixels, not three pixels. This is because signals fouta and foutb are used as focus detection signals in subsequent processing, and it is not desirable to add outputs from photoelectric conversion elements on different sides. In other words, signals fouta and foutb are not the sum of signals corresponding to channel chA and channel chB.

[0103] 13, clock signals clka and clkb transition from low to high at times t23 and t26. That is, clock signals clka and clkb are driven at one-third the frequency of clock signal clka in FIG. 12. This allows three cycles of signal accumulation, and ultimately adds three pixel signals together in adder 317. Therefore, clock signals clka and clkb are driven at one-third the frequency of the input clock, which transitions from low to high at times t20, t21, t22, t23, etc.

[0104] Fig. 14 is an example of a drive timing chart for the photoelectric conversion device according to this embodiment. Fig. 14 illustrates the driving of adding (horizontal adding) pixel signals output from four pixels 10 arranged in the same row, as described with reference to Fig. 11(c).

[0105] In Fig. 14, the horizontal axis represents time, and the timing of each drive pulse (each control signal), the digital value corresponding to each digital signal, and the digital value output to each channel are schematically shown. Each control signal shown in Fig. 14 corresponds to each control signal shown in Fig. 2, Fig. 4, and Fig. 11(c).

[0106] At time t20, the leading signals corresponding to channels chA and chB are input to the adder circuit 211. Here, the leading signal corresponding to channel chA has a value d00, and the leading signal corresponding to channel chB has a value d01.

[0107] At time t21, the signal douta_d output from the D latch circuit 311 becomes a value d00, and the signal doutb_d output from the D latch circuit 311 becomes a value d01.

[0108] At time t22, the signal douta_dd output from the D latch circuit 312 becomes a value d00, and the signal doutb_dd output from the D latch circuit 319 becomes a value d01.

[0109] 11(c), at time t22, signal douta_d is input to adder 315 via multiplexer circuit 314, and signal douta_dd is input to adder 315 via multiplexer circuit 313. Adder 315 adds signals douta_d and douta_dd, and the adder 315 outputs a value d00+value d02 as signal add_a1. Also, at time t22, as shown in FIG. 11(c), signal doutb_d is input to adder 326 via multiplexer circuit 323, and signal doutb_dd is input to adder 326 via multiplexer circuit 325. Adder 326 adds signals doutb_d and doutb_dd, and the adder 326 outputs a value d01+value d03 as signal add_b1.

[0110] Also, at time t22, the adder 317 adds the signals add_a1 and add_b1, and outputs the value d00+value d01+value d02+value d03 as the signal add_out1.

[0111] At time t23, the signal add_a1 is output from the flip-flop circuit 321 as the signal fouta. That is, at time t23, the flip-flop circuit 321 outputs the value d00+value d02 as the signal fouta. Also, at time t23, the signal add_out1 is output from the flip-flop circuit 322 as the signal pout1. That is, at time t23, the flip-flop circuit 322 outputs the value d00+value d01+value d02+value d03 as the signal pout1.

[0112] Since the clock signal clkb is fixed to a low level, the signal pout2 output from the flip-flop circuit 730 and the signal foutb output from the flip-flop circuit 731 are also fixed to a low level.

[0113] 14, the clock signal clka transitions from low to high at times t23, t25, and t27, driving the flip-flop circuits 321 and 322. That is, the clock signal clka is driven at half the frequency of the clock signal clka in FIG. 12. As a result, two cycles of signals are accumulated in each of the two systems, channel chA and channel chB, and the signals for four pixels are finally added in the adder 317. Therefore, the clock signal clka is driven at half the frequency of the input clock that transitions from low to high at times t20, t21, t22, t23, etc.

[0114] As described above, two-pixel addition, three-pixel addition, and four-pixel addition can be realized by the circuit configuration of the adder circuit 211 shown in Fig. 11. Furthermore, the multiplexer circuit included in the adder circuit 211 can be switched by a signal output from the timing signal output circuit 13. Note that the driving of two-pixel addition, three-pixel addition, and four-pixel addition may be switched according to the multiple operation modes of the photoelectric conversion device.

[0115] Furthermore, the signals fouta and foutb used for phase difference detection output from the adder circuit 211 may be compressed by the compressor circuit 17 as shown in the second embodiment. In this case, it is possible to reduce the load on the signal correction circuit 2.

[0116] As shown in the second embodiment, the signals pout1 and pout2 used for image generation output from the addition circuit 211 may be subjected to only necessary processing such as gain processing and clamping processing in the generation circuit 212 as preprocessing for the subsequent signal correction circuit 2. In this case, corrections suitable for the display system and recording system are performed in the signal correction circuit 2.

[0117] In this embodiment, two to four horizontal pixel additions have been shown, but as in the first embodiment, two-pixel addition, three-pixel addition, or four-pixel addition can also be performed vertically by changing the number of rows selected simultaneously by the vertical scanning circuit 12 that performs vertical scanning. In this case, multiple pixels 10 arranged in multiple rows are simultaneously connected to one output line 108, resulting in pseudo-vertical addition. This makes it possible to achieve two-pixel addition, three-pixel addition, or four-pixel addition operations in both the vertical and horizontal directions.

[0118] As described above, by switching between two-pixel addition, three-pixel addition, and four-pixel addition of the same color during one frame of driving, it is possible to perform focus detection using the same signal as that used for image generation. This makes it possible to optimally perform video shooting while measuring the distance, for example.

[0119] Furthermore, the focus detection signals can be compressed by the compression circuit 17, and the number of image generation signals can be reduced by adding together signals for multiple pixels. This makes it possible to reduce the data bandwidth within the photoelectric conversion system and lighten the load on the signal correction circuit 2.

[0120] Fourth Embodiment A photoelectric conversion device (signal processing method for a photoelectric conversion device) according to a fourth embodiment of the present invention will be described with reference to Fig. 15. Note that the same components as those in the first, second, and third embodiments are denoted by the same reference numerals, and descriptions of these components may be omitted or simplified.

[0121] The fourth embodiment differs from the first, second, and third embodiments in that it does not add (horizontal addition, vertical addition, horizontal-vertical addition, etc.) signals output from multiple pixels 10. Fig. 15 is an example of a drive timing chart for the photoelectric conversion device according to this embodiment.

[0122] In Figure 15, the horizontal axis represents time, and the timing of each drive pulse (each control signal), the digital value corresponding to each digital signal, and the digital value output to each channel are schematically shown. The control signals shown in Figure 15 correspond to the control signals shown in Figures 2 and 4. Note that the operation from time t1 to time t4 is the same as that shown in Figure 5 described above, and therefore a description thereof will be omitted. Note that the period from time t1 to time t7 and the period from time t7 to time t44 may be referred to as the first period and the second period, respectively.

[0123] At time t5, the AD conversion circuit 141 completes the AD conversion and holds the acquired digital values. Here, signals ado(0), ado(2), and ado(4) are assumed to be values ​​Da00, Da02, and Da04, respectively, which are digital values ​​corresponding to the first photoelectric conversion element 101 driven by the control signal tx1[0]. Here, signals ado(1), ado(3), and ado(5) are assumed to be values ​​Db01, Db03, and Db05, respectively, which are digital values ​​corresponding to the second photoelectric conversion element 102 driven by the control signal tx1[0].

[0124] At time t6, the timing signal output circuit 13 starts supplying the control signal hadr to the AD conversion unit 14, causing signals ado(0) to ado(5) to be output sequentially. In the first cycle, the control signal hadr(0) and the control signal hadr(1) are input to the switch 142. In the second cycle, the control signal hadr(2) and the control signal hadr(3) are input to the switch 142. In the third cycle, the control signal hadr(4) and the control signal hadr(5) are input to the switch 142. As a result, values ​​Da00, Da02, and Da04 are output sequentially to the horizontal transfer line 143 (channel chA), and values ​​Db01, Db03, and Db05 are output sequentially to the horizontal transfer line 144 (channel chB). Therefore, a signal corresponding to the first photoelectric conversion element 101 arranged on the left side of pixel 10 is output to channel chA, and a signal corresponding to the second photoelectric conversion element 102 arranged on the right side of pixel 10 is output to channel chB.

[0125] At time t7, the vertical scanning circuit 12 sets the control signal HD to high level, thereby starting operation for one row. In the driving of the first embodiment shown in FIG. 5, at time t7, control shifts to control of the pixels 10 arranged in the next row. However, in this embodiment, control does not shift to control of the pixels 10 arranged in the next row at time t7, but rather maintains the state at time t7 and continues control of the pixels 10 arranged in the row that was controlled before time t7.

[0126] During the period from time t40 to time t41, the control signal tx1[0] and the control signal tx2[0] become high level. This turns on the first transfer transistor 103 and the second transfer transistor 104, and the charges output from the first photoelectric conversion element 101 and the second photoelectric conversion element 102 are added together in the FD 109. At time t42, this added signal is AD converted by the AD conversion circuit 141, and the signals ado(0) to ado(5) output from the AD conversion circuit 141 are set to values ​​Dab00 to Dab05, respectively.

[0127] At time t43, the timing signal output circuit 13 starts supplying the control signal hadr to the AD conversion unit 14, causing signals ado(0) to ado(5) to be output sequentially. In the first cycle, the control signal hadr(0) and the control signal hadr(1) are input to the switch 142. In the second cycle, the control signal hadr(2) and the control signal hadr(3) are input to the switch 142. In the third cycle, the control signal hadr(4) and the control signal hadr(5) are input to the switch 142. As a result, the values ​​Dab00, Dab02, and Dab04 are output sequentially to the horizontal transfer line 143 (channel chA), and the values ​​Dab01, Dab03, and Dab05 are output sequentially to the horizontal transfer line 144 (channel chB). Therefore, a signal obtained by adding together the signal corresponding to the first photoelectric conversion element 101 and the signal corresponding to the second photoelectric conversion element 102 is output to channels chA and chB.

[0128] Here, the signal correction circuit 2 temporarily holds the signals of values ​​Da00, Da02, and Da04 corresponding to channel chA that are output during the period from time t2 to time t7. The temporarily held signals are then subtracted from the signals of values ​​Dab00, Dab02, and Dab04 corresponding to channel chA that are output from time t43. The signal correction circuit 2 also temporarily holds the signals of values ​​Db01, Db03, and Db05 corresponding to channel chB that are output during the period from time t2 to time t7. The temporarily held signals are then subtracted from the signals of values ​​Dab01, Dab03, and Dab05 corresponding to channel chB that are output from time t43. That is, the signal correction circuit 2 performs the arithmetic operations of (value Dab00) - (value Da00), (value Dab02) - (value Da02), and (value Dab04) - (value Da04) for channel chA, respectively. Furthermore, the signal correction circuit 2 executes the calculation processes of (value Dab01)-(value Db01), (value Dab03)-(value Db03), and (value Dab05)-(value Db05) for channel chB.

[0129] From the above, (value Dab00)-(value Da00) can obtain a signal corresponding to the second photoelectric conversion element 102. Also, (value Dab01)-(value Db01) can obtain a signal corresponding to the first photoelectric conversion element 101.

[0130] In this way, by the control signal HD going high twice, signals are read out twice from the pixels 10 arranged in any row. Then, the signals sequentially output from channels chA and chB are subjected to a process of subtracting the signal read out the first time from the signal read out the second time. This driving process makes it possible to obtain signals corresponding to the first photoelectric conversion elements 101 of the pixels 10 arranged in any row and signals corresponding to the second photoelectric conversion elements 102 of the pixels 10 arranged in any row. Furthermore, the focus detection circuit 20 of the signal correction circuit 2 uses these signals to detect their respective peaks, thereby enabling phase difference detection.

[0131] The signals corresponding to values ​​Dab00 to Dab05 output sequentially from channels chA and chB after time t43 are used for image generation, and are appropriately corrected in the signal correction circuit 2.

[0132] After time t44, the operation from time t2 to time t44 is repeated. However, after time t44, rows different from those read from time t2 to time t44 are read. That is, the control signal res[0] becomes high, the control signal sel[0] becomes low, the control signal res[1] becomes low, and the control signal sel[1] becomes high.

[0133] In this embodiment, it is possible to generate an image using signals output from multiple pixels 10 in one frame, and to perform focus detection using the same signals. This configuration is suitable for, for example, capturing video while measuring distances.

[0134] Furthermore, by combining the non-addition drive (non-addition mode) of this embodiment shown in Fig. 15 with the addition drive (addition mode) of the first embodiment shown in Fig. 5, the operation mode can be optimally switched. For example, it is possible to switch between using the non-addition mode when shooting still images and the addition mode when shooting moving images.

[0135] Here, the period from time t2 to time t7 shown in Fig. 15 can be regarded as the same period as the period from time t2 to time t7 shown in Fig. 5, and the pulse positions can be made the same. By doing so, when changing the operating mode, the operating mode can be changed without changing the timing at which the control signal HD goes high or the pulse positions.

[0136] Fifth Embodiment The fifth embodiment is applicable to any of the first to fourth embodiments. FIG. 16(a) is a schematic diagram illustrating an apparatus 9191 including a semiconductor device 930 according to this embodiment. The photoelectric conversion device according to any of the above-described embodiments can be used for the semiconductor device 930. The apparatus 9191 including the semiconductor device 930 will be described in detail. The semiconductor device 930 may include a semiconductor device 910. The semiconductor device 930 may include, in addition to the semiconductor device 910, a package 920 that houses the semiconductor device 910. The package 920 may include a base to which the semiconductor device 910 is fixed and a lid such as glass that faces the semiconductor device 910. The package 920 may further include bonding members such as bonding wires or bumps that connect terminals provided on the base to terminals provided on the semiconductor device 910.

[0137] The equipment 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror, and includes an optical system that guides light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0138] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0139] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit provided in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0140] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operations.

[0141] Furthermore, the device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 990 in the transportation equipment may be used as a moving device. The device 9191 as transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) using an imaging function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0142] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental impact, reducing costs, reducing size, and reducing weight.

[0143] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can also be improved. For example, by installing the semiconductor device 930 in a transport equipment, excellent performance can be obtained when photographing the exterior of the transport equipment or measuring the external environment. Therefore, when manufacturing and selling transport equipment, deciding to install the semiconductor device according to this embodiment in the transport equipment is advantageous in terms of improving the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0144] The photoelectric conversion system and the moving object of this embodiment will be described with reference to FIGS. 16(b) and 16(c).

[0145] FIG. 16(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 80 includes a photoelectric conversion device 1. The photoelectric conversion device 1 is the photoelectric conversion device (imaging device) described in any of the above embodiments. The photoelectric conversion system 80 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the photoelectric conversion device 1, and a parallax acquisition unit 802 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 80. Here, the photoelectric conversion system 80 may include an optical system (not shown) that guides light to the photoelectric conversion device 1, such as a lens, shutter, or mirror. The multiple photoelectric conversion elements receive light beams that have passed through different positions of a pupil of the optical system, and the photoelectric conversion device 1 outputs image data corresponding to the light beams that have passed through the different positions. The parallax acquisition unit 802 may then calculate parallax using the output image data. The photoelectric conversion system 80 also includes a distance acquisition unit 803 that calculates the distance to the object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information is information about the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 804 may determine the possibility of collision using any of this distance information. The distance information may be acquired using ToF (Time of Flight). The distance information acquisition means may be realized by dedicated hardware or a software module. It may also be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or the like, or a combination thereof.

[0146] The photoelectric conversion system 80 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 80 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The photoelectric conversion system 80 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high possibility of a collision, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0147] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 80. Fig. 16(c) shows the photoelectric conversion system 80 when imaging the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 80 or the photoelectric conversion device 1. This configuration can further improve the accuracy of distance measurement.

[0148] While the above describes an example of control to prevent collisions with other vehicles, the present invention can also be applied to other applications, such as autonomous driving control to follow other vehicles and autonomous driving control to prevent vehicles from drifting out of their lanes. Furthermore, the photoelectric conversion system 80 can be applied not only to automobiles and other vehicles, but also to moving objects (mobile devices) such as ships, aircraft, and industrial robots. The moving object includes one or both of a driving force generator that generates a driving force primarily used to move the moving object and a rotating object primarily used to move the moving object. The driving force generator can be an engine, a motor, or the like. The rotating object can be a tire, a wheel, a ship's screw, an aircraft's propeller, or the like. In addition to moving objects, the present invention can be applied to a wide range of devices that utilize object recognition, such as intelligent transport systems (ITS).

[0149] As used herein, expressions such as "A or B," "at least one of A and B," "at least one of A or / and B," "one or more of A or / and B," and the like, include all possible combinations of the listed items unless expressly defined otherwise. That is, the above expressions are understood to disclose all cases, including cases containing at least one A, cases containing at least one B, and cases containing both at least one A and at least one B. This applies equally to combinations of three or more elements.

[0150] The above-described embodiments can be modified as appropriate without departing from the spirit of the present invention. The disclosure of this specification includes not only what is described herein but also all matters that can be understood from the specification and the accompanying drawings. The disclosure of this specification also includes the complement of the concepts described herein. In other words, if the specification contains a statement that "A is greater than B," even if the statement that "A is not greater than B" is omitted, the specification can still be said to disclose that "A is not greater than B." This is because the statement that "A is greater than B" presupposes that the case in which "A is not greater than B" is taken into consideration.

[0151] The disclosure of this embodiment includes the following configurations.

[0152] (Configuration 1) A photoelectric conversion device having a plurality of pixels arranged in a matrix, the photoelectric conversion device including first and second pixels arranged in a first row, a first microlens corresponding to the first pixel, and a second microlens corresponding to the second pixel, wherein the first pixel includes a first photoelectric conversion element that photoelectrically converts light transmitted through the first microlens to generate a first charge, a second photoelectric conversion element that photoelectrically converts light transmitted through the first microlens to generate a second charge, a first floating diffusion that accumulates at least one of the first charge and the second charge, a first transfer transistor that transfers the first charge to the first floating diffusion, and a second transfer transistor that transfers the second charge to the first floating diffusion, and the second pixel includes a third photoelectric conversion element that photoelectrically converts light transmitted through the second microlens to generate a third charge, and a second photoelectric conversion element that photoelectrically converts light transmitted through the second microlens to generate a third charge. a fourth photoelectric conversion element that generates a fourth charge by photoelectrically converting light that has passed through a lens, a second floating diffusion that accumulates at least one of the third charge and the fourth charge, a third transfer transistor that transfers the third charge to the second floating diffusion, and a fourth transfer transistor that transfers the fourth charge to the second floating diffusion, wherein the photoelectric conversion device has a first control line connected to the first transfer transistor and the fourth transfer transistor, and a second control line connected to the second transfer transistor and the third transfer transistor, the third photoelectric conversion element and the fourth photoelectric conversion element being arranged in this order in a direction from the first photoelectric conversion element to the second photoelectric conversion element, and wherein the photoelectric conversion device outputs a set of a signal based on the first charge and a signal based on the fourth charge using the first control line for use in focus detection and image generation.

[0153] (Configuration 2) The photoelectric conversion device described in configuration 1, characterized in that the second control line is used to output a set of signals based on the second charge and the third charge for use in focus detection and image generation.

[0154] (Configuration 3) A photoelectric conversion device described in configuration 1 or 2, characterized in that it uses the first control line and the second control line to output a set of a signal based on the first charge and a signal based on the second charge for use in focus detection and image generation.

[0155] (Configuration 4) A pixel includes a third pixel and a fourth pixel arranged in a second row, a third microlens corresponding to the third pixel, and a fourth microlens corresponding to the fourth pixel, wherein the first pixel and the third pixel are arranged in the same column, and the second pixel and the fourth pixel are arranged in the same column, the third pixel includes a fifth photoelectric conversion element that performs photoelectric conversion on light that has passed through the third microlens to generate a fifth charge, a sixth photoelectric conversion element that performs photoelectric conversion on light that has passed through the third microlens to generate a sixth charge, a third floating diffusion that accumulates at least one of the fifth charge and the sixth charge, a fifth transfer transistor that transfers the fifth charge to the third floating diffusion, and a sixth transfer transistor that transfers the sixth charge to the third floating diffusion, and the fourth pixel includes a seventh photoelectric conversion element that performs photoelectric conversion on light that has passed through the fourth microlens to generate a seventh charge, and an eighth photoelectric conversion element that performs photoelectric conversion on light that has passed through the fourth microlens to generate an eighth charge. a fourth floating diffusion configured to store at least one of the seventh charge and the eighth charge, a seventh transfer transistor configured to transfer the seventh charge to the fourth floating diffusion, and an eighth transfer transistor configured to transfer the eighth charge to the fourth floating diffusion; a third control line connected to the fifth transfer transistor and the eighth transfer transistor, and a fourth control line connected to the sixth transfer transistor and the seventh transfer transistor; the fifth photoelectric conversion element and the sixth photoelectric conversion element are arranged in order in a direction from the first photoelectric conversion element to the second photoelectric conversion element, and the seventh photoelectric conversion element and the eighth photoelectric conversion element are arranged in order in a direction from the first photoelectric conversion element to the second photoelectric conversion element; and the photoelectric conversion device according to any one of configurations 1 to 3, characterized in that the photoelectric conversion device uses the third control line to output a set of a signal based on the fifth charge and a signal based on the eighth charge for use in focus detection and image generation.

[0156] (Configuration 5) The photoelectric conversion device according to any one of configurations 1 to 4, wherein after the first control line is used, the third control line is used without using the second control line.

[0157] (Configuration 6) The photoelectric conversion device according to any one of configurations 1 to 5, further comprising color filters, the color filters corresponding to the first pixel and the second pixel being the same color.

[0158] (Structure 7) The photoelectric conversion device according to any one of structures 1 to 6, comprising: a fifth pixel arranged in the first row; and a fifth microlens corresponding to the fifth pixel, the fifth pixel being arranged between the first pixel and the second pixel; the fifth pixel comprising: a ninth photoelectric conversion element that photoelectrically converts light that has passed through the fifth microlens to generate a ninth charge; a tenth photoelectric conversion element that photoelectrically converts light that has passed through the fifth microlens to generate a tenth charge; a fifth floating diffusion that accumulates at least one of the ninth charge and the tenth charge; a ninth transfer transistor that transfers the ninth charge to the fifth floating diffusion; and a tenth transfer transistor that transfers the tenth charge to the fifth floating diffusion; the ninth photoelectric conversion element and the tenth photoelectric conversion element are arranged in this order in a direction from the first photoelectric conversion element to the second photoelectric conversion element; the first control line is connected to the ninth transfer transistor; and the second control line is connected to the tenth transfer transistor.

[0159] (Structure 8) A photoelectric conversion device described in any one of structures 1 to 7, further comprising a color filter, wherein the color filter corresponding to the first pixel and the color filter corresponding to the second pixel are the same color, and the color filter corresponding to the first pixel and the color filter corresponding to the fifth pixel are different colors.

[0160] (Configuration 9) A photoelectric conversion device according to any one of configurations 1 to 8, further comprising a compression circuit, wherein the compression circuit performs at least one of thinning processing, addition processing, and bit number reduction processing on a signal output for use in focus detection.

[0161] (Configuration 10) A photoelectric conversion device described in any one of configurations 1 to 9, characterized in that a set of a signal based on the first charge and a signal based on the fourth charge is output during one frame for use in focus detection and image generation.

[0162] (Configuration 11) The photoelectric conversion device according to any one of configurations 1 to 10, wherein the first floating diffusion is shared by the first photoelectric conversion element and the second photoelectric conversion element.

[0163] (Configuration 12) The photoelectric conversion device according to any one of configurations 1 to 11, wherein the first control line is driven in a first period, and the first control line and the second control line are driven in a second period.

[0164] (Configuration 13) The photoelectric conversion device according to any one of configurations 1 to 12, characterized in that focus detection is performed by subtracting the signal output during the first period from the signal output during the second period.

[0165] (Configuration 14) A photoelectric conversion device described in any one of configurations 1 to 13, further comprising a focus detection circuit, wherein the focus detection circuit performs focus detection using a pair of a signal based on the first charge and a signal based on the fourth charge.

[0166] (Configuration 15) A photoelectric conversion device described in any one of configurations 1 to 14, further comprising an image generation circuit, wherein the image generation circuit generates an image using a set of a signal based on the first charge and a signal based on the fourth charge.

[0167] (Configuration 16) A photoelectric conversion device described in any one of configurations 1 to 15, characterized in that the image generation circuit has an addition circuit that performs addition processing on signals output from the multiple pixels, and the addition circuit changes the number of signals to be added depending on multiple operating modes of the photoelectric conversion device.

[0168] (Configuration 17) A photoelectric conversion system comprising the photoelectric conversion device described in any one of configurations 1 to 13, further comprising a focus detection circuit, wherein the focus detection circuit performs focus detection using a set of a signal based on the first charge and a signal based on the fourth charge.

[0169] (Configuration 18) A photoelectric conversion system comprising the photoelectric conversion device described in any one of configurations 1 to 13, further comprising an image generation circuit, wherein the image generation circuit generates an image using a set of a signal based on the first charge and a signal based on the fourth charge.

[0170] (Configuration 19) An apparatus comprising a photoelectric conversion device according to any one of configurations 1 to 18, further comprising at least one of an optical device that guides light to the photoelectric conversion device, a control device that controls the photoelectric conversion device, a processing device that processes signals output from the photoelectric conversion device, a display device that displays information obtained by the photoelectric conversion device, a memory device that stores information obtained by the photoelectric conversion device, and a mechanical device that operates based on information obtained by the photoelectric conversion device.

[0171] (Method 1) A pixel array includes a plurality of pixels arranged in a matrix, the pixel array including a first pixel and a second pixel arranged in a first row, a first microlens corresponding to the first pixel, and a second microlens corresponding to the second pixel, the first pixel including a first photoelectric conversion element configured to photoelectrically convert light transmitted through the first microlens to generate a first charge, a second photoelectric conversion element configured to photoelectrically convert light transmitted through the first microlens to generate a second charge, a first floating diffusion configured to accumulate at least one of the first charge and the second charge, a first transfer transistor configured to transfer the first charge to the first floating diffusion, and a second transfer transistor configured to transfer the second charge to the first floating diffusion, the second pixel including a third photoelectric conversion element configured to photoelectrically convert light transmitted through the second microlens to generate a third charge, a fourth photoelectric conversion element configured to photoelectrically convert light transmitted through the second microlens to generate a fourth charge, and a fourth transfer transistor configured to transfer the third charge and a second floating diffusion that accumulates at least one of the first charge and the fourth charge, a third transfer transistor that transfers the third charge to the second floating diffusion, and a fourth transfer transistor that transfers the fourth charge to the second floating diffusion, wherein the third photoelectric conversion element and the fourth photoelectric conversion element are arranged in order in a direction from the first photoelectric conversion element to the second photoelectric conversion element, and the signal processing method for outputting a set of a signal based on the first charge and a signal based on the fourth charge using the first control line, the signal processing method for a photoelectric conversion device comprising: a first control line connected to the first transfer transistor and the fourth transfer transistor; [Explanation of symbols]

[0172] 1 Photoelectric conversion device 10 pixels 110 Micro Lens 101 first photoelectric conversion element 102 Second photoelectric conversion element 109 Floating Diffusion 103 first transfer transistor 104 second transfer transistor 134 First Control Line 135 Second Control Line

Claims

1. A photoelectric conversion device including a plurality of pixels arranged in a matrix, a first pixel and a second pixel arranged in a first row; a first microlens corresponding to the first pixel; a second microlens corresponding to the second pixel; the first pixel includes a first photoelectric conversion element that photoelectrically converts light that has passed through the first microlens to generate a first charge, a second photoelectric conversion element that photoelectrically converts light that has passed through the first microlens to generate a second charge, a first floating diffusion that accumulates at least one of the first charge and the second charge, a first transfer transistor that transfers the first charge to the first floating diffusion, and a second transfer transistor that transfers the second charge to the first floating diffusion; the second pixel includes a third photoelectric conversion element that photoelectrically converts light that has passed through the second microlens to generate a third charge, a fourth photoelectric conversion element that photoelectrically converts light that has passed through the second microlens to generate a fourth charge, a second floating diffusion that accumulates at least one of the third charge and the fourth charge, a third transfer transistor that transfers the third charge to the second floating diffusion, and a fourth transfer transistor that transfers the fourth charge to the second floating diffusion; a first control line connected to the first transfer transistor and the fourth transfer transistor, and a second control line connected to the second transfer transistor and the third transfer transistor; the third photoelectric conversion element and the fourth photoelectric conversion element are arranged in this order in a direction from the first photoelectric conversion element to the second photoelectric conversion element, Using the first control line, a set of signals based on the first charge and the fourth charge are output for use in focus detection and image generation. A photoelectric conversion device characterized by:

2. 2. The photoelectric conversion device according to claim 1, wherein the second control line is used to output a set of signals based on the second charge and the third charge for use in focus detection and image generation.

3. The photoelectric conversion device according to claim 1, characterized in that the first control line and the second control line are used to output a set of signals based on the first charge and signals based on the second charge for use in focus detection and image generation.

4. a third pixel and a fourth pixel arranged in a second row; a third microlens corresponding to the third pixel; a fourth microlens corresponding to the fourth pixel, the first pixel and the third pixel are arranged in the same column, and the second pixel and the fourth pixel are arranged in the same column; the third pixel includes a fifth photoelectric conversion element that photoelectrically converts light that has passed through the third microlens to generate a fifth charge, a sixth photoelectric conversion element that photoelectrically converts light that has passed through the third microlens to generate a sixth charge, a third floating diffusion that accumulates at least one of the fifth charge and the sixth charge, a fifth transfer transistor that transfers the fifth charge to the third floating diffusion, and a sixth transfer transistor that transfers the sixth charge to the third floating diffusion; the fourth pixel includes: a seventh photoelectric conversion element that performs photoelectric conversion on light that has passed through the fourth microlens to generate a seventh charge; an eighth photoelectric conversion element that performs photoelectric conversion on light that has passed through the fourth microlens to generate an eighth charge; a fourth floating diffusion that accumulates at least one of the seventh charge and the eighth charge; a seventh transfer transistor that transfers the seventh charge to the fourth floating diffusion; and an eighth transfer transistor that transfers the eighth charge to the fourth floating diffusion; a third control line connected to the fifth transfer transistor and the eighth transfer transistor, and a fourth control line connected to the sixth transfer transistor and the seventh transfer transistor; the fifth photoelectric conversion element and the sixth photoelectric conversion element are arranged in this order in a direction from the first photoelectric conversion element to the second photoelectric conversion element, the seventh photoelectric conversion element and the eighth photoelectric conversion element are arranged in this order in a direction from the first photoelectric conversion element toward the second photoelectric conversion element, 2. The photoelectric conversion device according to claim 1, wherein the third control line is used to output a set of signals based on the fifth charge and the eighth charge for use in focus detection and image generation.

5. 5. The photoelectric conversion device according to claim 4, wherein after the first control line is used, the third control line is used without using the second control line.

6. 2. The photoelectric conversion device according to claim 1, further comprising color filters, the color filters corresponding to the first pixel and the second pixel being the same color.

7. a fifth pixel arranged in the first row; a fifth microlens corresponding to the fifth pixel, the fifth pixel is disposed between the first pixel and the second pixel, the fifth pixel includes a ninth photoelectric conversion element that photoelectrically converts light that has passed through the fifth microlens to generate a ninth charge, a tenth photoelectric conversion element that photoelectrically converts light that has passed through the fifth microlens to generate a tenth charge, a fifth floating diffusion that accumulates at least one of the ninth charge and the tenth charge, a ninth transfer transistor that transfers the ninth charge to the fifth floating diffusion, and a tenth transfer transistor that transfers the tenth charge to the fifth floating diffusion; the ninth photoelectric conversion element and the tenth photoelectric conversion element are arranged in this order in a direction from the first photoelectric conversion element toward the second photoelectric conversion element, 2. The photoelectric conversion device according to claim 1, wherein the first control line is connected to the ninth transfer transistor, and the second control line is connected to the tenth transfer transistor.

8. The photoelectric conversion device of claim 7, further comprising a color filter, wherein the color filter corresponding to the first pixel and the color filter corresponding to the second pixel are the same color, and the color filter corresponding to the first pixel and the color filter corresponding to the fifth pixel are different colors.

9. 2. The photoelectric conversion device according to claim 1, further comprising a compression circuit, wherein the compression circuit performs at least one of thinning processing, addition processing, and bit number reduction processing on the signal output for use in focus detection.

10. 2. The photoelectric conversion device according to claim 1, wherein a set of a signal based on the first charge and a signal based on the fourth charge is output during one frame for use in focus detection and image generation.

11. The photoelectric conversion device according to claim 1 , wherein the first floating diffusion is shared by the first photoelectric conversion element and the second photoelectric conversion element.

12. 2. The photoelectric conversion device according to claim 1, wherein the first control line is used in a first period, and the first control line and the second control line are used in a second period.

13. 13. The photoelectric conversion device according to claim 12, wherein focus detection is performed by subtracting the signal output during the first period from the signal output during the second period.

14. 2. The photoelectric conversion device according to claim 1, further comprising a focus detection circuit, wherein the focus detection circuit performs focus detection using a set of a signal based on the first charge and a signal based on the fourth charge.

15. 2. The photoelectric conversion device according to claim 1, further comprising an image generation circuit, wherein the image generation circuit generates an image using a set of a signal based on the first charge and a signal based on the fourth charge.

16. The photoelectric conversion device according to claim 15, wherein the image generation circuit has an adder circuit that performs an addition process on signals output from the plurality of pixels, and the adder circuit changes the number of signals to be added depending on a plurality of operation modes of the photoelectric conversion device.

17. A photoelectric conversion system comprising the photoelectric conversion device according to any one of claims 1 to 13, A photoelectric conversion system further comprising a focus detection circuit, wherein the focus detection circuit performs focus detection using a set of a signal based on the first charge and a signal based on the fourth charge.

18. A photoelectric conversion system comprising the photoelectric conversion device according to any one of claims 1 to 13, A photoelectric conversion system further comprising an image generation circuit, wherein the image generation circuit generates an image using a set of a signal based on the first charge and a signal based on the fourth charge.

19. An apparatus comprising the photoelectric conversion device according to any one of claims 1 to 16, an optical device that guides light to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

20. A plurality of pixels arranged in a matrix, a first pixel and a second pixel arranged in a first row; a first microlens corresponding to the first pixel; a second microlens corresponding to the second pixel; the first pixel includes a first photoelectric conversion element that photoelectrically converts light that has passed through the first microlens to generate a first charge, a second photoelectric conversion element that photoelectrically converts light that has passed through the first microlens to generate a second charge, a first floating diffusion that accumulates at least one of the first charge and the second charge, a first transfer transistor that transfers the first charge to the first floating diffusion, and a second transfer transistor that transfers the second charge to the first floating diffusion; the second pixel includes a third photoelectric conversion element that photoelectrically converts light that has passed through the second microlens to generate a third charge, a fourth photoelectric conversion element that photoelectrically converts light that has passed through the second microlens to generate a fourth charge, a second floating diffusion that accumulates at least one of the third charge and the fourth charge, a third transfer transistor that transfers the third charge to the second floating diffusion, and a fourth transfer transistor that transfers the fourth charge to the second floating diffusion; a first control line connected to the first transfer transistor and the fourth transfer transistor, and a second control line connected to the second transfer transistor and the third transfer transistor; the third photoelectric conversion element and the fourth photoelectric conversion element are arranged in this order in a direction from the first photoelectric conversion element to the second photoelectric conversion element, a signal processing method for a photoelectric conversion device that outputs a set of a signal based on the first charge and a signal based on the fourth charge using the first control line, the method comprising: A set of a signal based on the first charge and a signal based on the fourth charge output from the photoelectric conversion device is used to perform focus detection and image generation. A signal processing method for a photoelectric conversion device comprising:

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