Semiconductor device

Abstract

To provide a semiconductor device which suppresses growth of a lamination defect and improves reliability.SOLUTION: A semiconductor device of an embodiment includes an element region, a termination region surrounding the element region, and an intermediate region provided between the element region and the termination region. The element region includes a silicon carbide region of a first conductivity type, a silicon carbide layer having a plurality of silicon carbide regions of a second conductivity type, and a gate electrode, and the intermediate region includes a silicon carbide layer having a silicon carbide region of the second conductivity type outside the plurality of silicon carbide regions of the second conductivity type. A width of the silicon carbide region of the second conductivity type in the intermediate region is not less than 0.5 times and not more than 3 times a width of the silicon carbide region of the second conductivity type in the element region. A distance between the silicon carbide region of the second conductivity type in the intermediate region and an outermost silicon carbide region among the plurality of silicon carbide regions of the second conductivity type in the element region is 0.5 times or more and 3 times or less a distance between the silicon carbide regions of the second conductivity type in the element region.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Silicon carbide is expected to be a promising material for semiconductor devices. Compared to silicon, silicon carbide has excellent physical properties, such as a band gap three times larger, a breakdown field strength approximately ten times larger, and a thermal conductivity approximately three times larger. Utilizing these properties, for example, can realize a metal oxide semiconductor field effect transistor (MOSFET) that can withstand high voltages, have low loss, and operate at high temperatures.

[0003] Vertical MOSFETs using silicon carbide have a built-in pn junction diode. For example, MOSFETs are used as switching elements connected to inductive loads. In this case, the pn junction diode allows a freewheeling current to flow even when the MOSFET is off.

[0004] However, when a return current is passed through a bipolar pn junction diode, stacking faults grow in the silicon carbide layer due to the carrier recombination energy. The growth of stacking faults in the silicon carbide layer causes a problem: the on-resistance of the MOSFET increases. The increase in the on-resistance of the MOSFET reduces the reliability of the MOSFET. For example, by providing a unipolar Schottky Barrier Diode (SBD) as an internal diode in the MOSFET, it is possible to suppress the growth of stacking faults in the silicon carbide layer. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 6976489 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a semiconductor device that suppresses the growth of stacking faults and improves reliability. [Means for solving the problem]

[0007] The semiconductor device of the embodiment includes an element region, a termination region surrounding the element region, and an intermediate region provided between the element region and the termination region and surrounding the element region, the element region including a first electrode, a second electrode, a gate electrode, a first surface provided between the first electrode and the second electrode and on the side of the first electrode, and a second surface provided on the side of the second electrode, the first region, a second region provided between the first region and the first surface and having a first conductivity type impurity concentration higher than that of the first region, and a second region in contact with the first surface. a first silicon carbide region of a first conductivity type having a first portion facing a gate electrode and a second portion in contact with the first surface and in contact with the first electrode; a second silicon carbide region of a second conductivity type provided between the second region and the first surface and electrically connected to the first electrode; a third silicon carbide region of a second conductivity type provided between the second region and the first surface, on the side of the intermediate region of the second silicon carbide region, and electrically connected to the first electrode; a fourth silicon carbide region of the second conductivity type provided between the second region and the first surface, between the second silicon carbide region and the fourth silicon carbide region, facing the gate electrode and electrically connected to the first electrode; a fifth silicon carbide region of the second conductivity type provided between the second region and the first surface, between the second silicon carbide region and the fourth silicon carbide region, facing the gate electrode and electrically connected to the first electrode; a silicon carbide layer including: a sixth silicon carbide region of a second conductivity type having a depth shallower than a depth of the silicon region; and a seventh silicon carbide region of a first conductivity type provided between the fifth silicon carbide region and the first surface and electrically connected to the first electrode; and a gate insulating layer provided between the gate electrode and the fifth silicon carbide region and between the gate electrode and the first portion, wherein the termination region includes: a wiring layer electrically connected to the first electrode, the second electrode, and the first silicon carbide region having a third portion in contact with the first surface and in contact with the wiring layer;the silicon carbide layer including an eighth silicon carbide region of a second conductivity type that is provided between the first silicon carbide region and the first surface and electrically connected to the wiring layer and has a depth shallower than the third silicon carbide region, and the intermediate region is in contact with the second electrode, the first silicon carbide region, and the third silicon carbide region and the eighth silicon carbide region of the second conductivity type that is provided between the first silicon carbide region and the first surface and electrically connected to the first electrode, and is in contact with the third silicon carbide region and the eighth silicon carbide region, and has a depth shallower than the third silicon carbide region. the silicon carbide layer including: a ninth silicon carbide region; and a tenth silicon carbide region of the second conductivity type provided between the first silicon carbide region and the ninth silicon carbide region, the tenth silicon carbide region having a first width in a first direction parallel to the first surface that is 0.5 to 3 times the second width in the first direction of the fourth silicon carbide region, and a first distance in the first direction between the fourth silicon carbide region and the third silicon carbide region that is 0.5 to 3 times the second distance in the first direction between the fourth silicon carbide region and the fifth silicon carbide region. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic top view of a semiconductor device according to a first embodiment. [Figure 2] 1 is a schematic top view of a semiconductor device according to a first embodiment. [Figure 3] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 4] FIG. 2 is an equivalent circuit diagram of the semiconductor device according to the first embodiment. [Figure 5] FIG. 10 is a schematic cross-sectional view of a semiconductor device of a comparative example. [Figure 6] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 7] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 8] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described may be omitted as appropriate.

[0010] In the following description, n + , n, n - and p + , p, p - When the notation is used, it indicates the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The type is simply n-type, p + type, p - The type is sometimes simply referred to as p-type.

[0011] In this specification, unless otherwise specified, "impurity concentration" refers to a concentration compensated for the concentration of impurities of the opposite conductivity type. That is, the n-type impurity concentration in an n-type silicon carbide region refers to the concentration obtained by subtracting the concentration of p-type impurities from the concentration of n-type impurities. Furthermore, the p-type impurity concentration in a p-type silicon carbide region refers to the concentration obtained by subtracting the concentration of n-type impurities from the concentration of p-type impurities. In this specification, unless otherwise specified, "impurity concentration in a silicon carbide region" refers to the maximum impurity concentration in the corresponding silicon carbide region.

[0012] The impurity concentration can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS). The relative level of the impurity concentration can also be determined from the carrier concentration determined by, for example, Scanning Capacitance Microscopy (SCM). Distances such as the depth and thickness of the impurity region can be determined by, for example, SIMS or Scanning Electron Microscope (SEM). Distances such as the depth, thickness, width, and spacing of the impurity region can also be determined from a composite image of, for example, an SCM image and an Atomic Force Microscope (AFM) image.

[0013] (First embodiment) The semiconductor device of the first embodiment includes an element region, a termination region surrounding the element region, and an intermediate region provided between the element region and the termination region and surrounding the element region. The element region is a silicon carbide layer having a first surface on the first electrode side and a second surface on the second electrode side, the element region including a first electrode, a second electrode, a gate electrode, and a second region provided between the first electrode and the second electrode and having a higher first conductivity type impurity concentration than the first region, a first portion in contact with the first surface and facing the gate electrode, and a second portion in contact with the first surface and in contact with the first electrode. a first silicon carbide region of a first conductivity type having a second portion; a second silicon carbide region of a second conductivity type provided between the second region and the first surface and electrically connected to the first electrode; a third silicon carbide region of the second conductivity type provided between the second region and the first surface and on the side of an intermediate region of the second silicon carbide region and electrically connected to the first electrode; a fourth silicon carbide region of the second conductivity type provided between the second region and the first surface, between the third silicon carbide region and the fourth silicon carbide region, facing the gate electrode and electrically connected to the first electrode; a fifth silicon carbide region of the second conductivity type provided between the second region and the first surface, between the second silicon carbide region and the fourth silicon carbide region, facing the gate electrode and electrically connected to the first electrode; a sixth silicon carbide region of the second conductivity type provided between the second region and the first surface, between the third silicon carbide region and the fourth silicon carbide region, and having a depth shallower than a depth of the third silicon carbide region and a depth of the fourth silicon carbide region; and a seventh silicon carbide region of the first conductivity type provided between the fifth silicon carbide region and the first surface and electrically connected to the first electrode; and a gate insulating layer provided between the gate electrode and the fifth silicon carbide region and between the gate electrode and the first portion. The termination region includes a silicon carbide layer including: a wiring layer electrically connected to the first electrode; a second electrode; a first silicon carbide region having a third portion in contact with the first surface and in contact with the wiring layer; and an eighth silicon carbide region of the second conductivity type provided between the first silicon carbide region and the first surface, electrically connected to the wiring layer, and shallower in depth than the third silicon carbide region.the intermediate region includes a silicon carbide layer including: a second electrode; a first silicon carbide region; a ninth silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface and electrically connected to the first electrode, in contact with the third silicon carbide region and the eighth silicon carbide region, and shallower than the third silicon carbide region; and a tenth silicon carbide region of the second conductivity type provided between the first silicon carbide region and the ninth silicon carbide region, having a first width in a first direction parallel to the first surface that is 0.5 to 3 times the second width in the first direction of the fourth silicon carbide region, and a first distance in the first direction between the third silicon carbide region and the tenth silicon carbide region that is 0.5 to 3 times the second distance in the first direction between the fourth silicon carbide region and the fifth silicon carbide region.

[0014] 1(a) and 1(b) are schematic top views of a semiconductor device according to a first embodiment. Fig. 1(a) shows the layout patterns of an element region, a termination region, and an intermediate region. Fig. 1(b) shows the layout patterns of a source electrode, a source electrode wiring layer, a gate pad electrode, and a gate electrode wiring layer.

[0015] 2(a) and 2(b) are schematic top views of the semiconductor device of the first embodiment. Fig. 2(a) shows the layout patterns of the element region, termination region, and intermediate region. Fig. 2(b) shows the layout patterns of the gate electrode, gate connection layer, and gate pad layer.

[0016] 3 is a schematic cross-sectional view of the semiconductor device of the first embodiment, taken along the line AA' shown in FIGS.

[0017] The semiconductor device of the first embodiment is a planar-gate vertical MOSFET 100 using silicon carbide. The MOSFET 100 is, for example, a double implantation MOSFET (DIMOSFET) in which a base region and a source region are formed by ion implantation. The semiconductor device of the first embodiment also includes an SBD as a built-in diode.

[0018] The following description will be given taking as an example a case where the first conductivity type is n-type and the second conductivity type is p-type. The MOSFET 100 is a vertical n-channel MOSFET that uses electrons as carriers.

[0019] The MOSFET 100 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a source electrode wiring layer 13 (wiring layer), a silicide layer 14, a drain electrode 15 (second electrode), a gate insulating layer 16, a gate electrode 18, a gate connection layer 20, a gate pad layer 21, a gate electrode pad 22, a gate electrode wiring layer 23, a field insulating layer 24, and an interlayer insulating layer 26.

[0020] The silicon carbide layer 10 is n + n-type drain region 30, n-type drift region 31 (first silicon carbide region), p-type outer peripheral p-region 32 (third silicon carbide region), p-type first base region 33a (fourth silicon carbide region), p-type second base region 33b (fifth silicon carbide region), p-type third base region 33c (second silicon carbide region), p-type first p-region 34 (sixth silicon carbide region), n + The n-type drift region 31 (first silicon carbide region) includes an n-type source region 35 (seventh silicon carbide region), a p-type second p-region 36 (eighth silicon carbide region), a p-type third p-region 37 (ninth silicon carbide region), and a p-type fourth p-region 38 (tenth silicon carbide region). - The n-type drift region 31 has a first portion 31x, a second portion 31y, and a third portion 31z.

[0021] Hereinafter, the first base region 33a (fourth silicon carbide region), the second base region 33b (fifth silicon carbide region), and the third base region 33c (second silicon carbide region) may be individually or collectively referred to simply as base region 33.

[0022] The MOSFET 100 includes a device region 101 , a termination region 102 , and an intermediate region 103 .

[0023] The termination region 102 surrounds the element region 101. The intermediate region 103 is provided between the element region 101 and the termination region 102. The termination region 102 surrounds the intermediate region 103. The intermediate region 103 surrounds the element region 101.

[0024] The device region 101 includes a plurality of MOSFETs and a plurality of SBDs, and the termination region 102 includes an SBD.

[0025] When the MOSFET 100 is in an off state, the termination region 102 and the intermediate region 103 reduce the strength of the electric field applied to the termination portion of the pn junction in the element region 101. The termination region 102 and the intermediate region 103 have the function of improving the dielectric breakdown voltage of the MOSFET 100.

[0026] The device region 101 includes a silicon carbide layer 10, a source electrode 12, a silicide layer 14, a drain electrode 15, a gate insulating layer 16, a gate electrode 18, a field insulating layer 24, and an interlayer insulating layer 26.

[0027] The silicon carbide layer 10 in the element region 101 is n + n-type drain region 30, n-type drift region 31 (first silicon carbide region), p-type outer peripheral p-region 32 (third silicon carbide region), p-type first base region 33a (fourth silicon carbide region), p-type second base region 33b (fifth silicon carbide region), p-type third base region 33c (second silicon carbide region), p-type first p-region 34 (sixth silicon carbide region), n + The drift region 31 of the element region 101 includes an n-type source region 35 (seventh silicon carbide region). - The drift region 31 of the element region 101 has a first portion 31x and a second portion 31y.

[0028] Termination region 102 includes silicon carbide layer 10, source electrode wiring layer 13, silicide layer 14, drain electrode 15, and interlayer insulating layer .

[0029] The silicon carbide layer 10 in the termination region 102 is n +The termination region 102 includes an n-type drain region 30, an n-type drift region 31 (first silicon carbide region), and a p-type second p-region 36 (eighth silicon carbide region). The drift region 31 of the termination region 102 has a third portion 31z.

[0030] The intermediate region 103 includes a silicon carbide layer 10, a silicide layer 14, a drain electrode 15, a gate insulating layer 16, a gate connection layer 20, a gate pad layer 21, a gate electrode pad 22, a gate electrode wiring layer 23, a field insulating layer 24, and an interlayer insulating layer 26.

[0031] The silicon carbide layer 10 in the intermediate region 103 is n + The n-type drain region 30, the n-type drift region 31, the p-type third p-region 37, and the p-type fourth p-region 38 are included.

[0032] The silicon carbide layer 10 is provided between the source electrode 12 and the drain electrode 15. The silicon carbide layer 10 is made of single-crystal SiC. The silicon carbide layer 10 is, for example, 4H—SiC.

[0033] The silicon carbide layer 10 has a first surface ("F1" in FIG. 3) and a second surface ("F2" in FIG. 3). Hereinafter, the first surface F1 may be referred to as the front surface, and the second surface F2 may be referred to as the back surface. The first surface F1 is located on the source electrode 12 side of the silicon carbide layer 10. The second surface F2 is located on the drain electrode 15 side of the silicon carbide layer 10. The first surface F1 and the second surface F2 face each other. Hereinafter, "depth" refers to the depth from the first surface toward the second surface.

[0034] The first surface is parallel to a first direction and a second direction, and the second direction is perpendicular to the first direction.

[0035] The first face F1 is, for example, a face inclined at an angle of 0 to 8 degrees with respect to the (0001) face. The second face F2 is, for example, a face inclined at an angle of 0 to 8 degrees with respect to the (000-1) face. The (0001) face is called a silicon face. The (000-1) face is called a carbon face.

[0036] The silicon carbide layer 10 has a thickness of, for example, not less than 5 μm and not more than 350 μm.

[0037] n + The n-type drain region 30 is provided on the back surface side of the silicon carbide layer 10. The drain region 30 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 30 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0038] The n-type drift region 31 is provided between the drain region 30 and the first face F1. The n-type drift region 31 is provided between the source electrode 12 and the drain electrode 15. The n-type drift region 31 is provided between the gate electrode 18 and the drain electrode 15. The n-type drift region 31 is provided on the drain region 30.

[0039] The drift region 31 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 31 is lower than the n-type impurity concentration of the drain region 30. The n-type impurity concentration of the drift region 31 is, for example, 4×10 14 cm -3 5x10 or more 17 cm -3 The thickness of the drift region 31 is, for example, not less than 3 μm and not more than 100 μm.

[0040] The drift region 31 is formed in the element region 101 as follows: - The semiconductor device has an n-type low concentration region 31a and an n-type high concentration region 31b. The high concentration region 31b is provided between the low concentration region 31a and the first face F1.

[0041] The drift region 31 includes a first portion 31x and a second portion 31y in the element region 101. The first portion 31x and the second portion 31y are included in the high-concentration region 31b.

[0042] The first portion 31x contacts the first face F1 and faces the gate electrode 18 with the gate insulating layer 16 interposed therebetween. The first portion 31x functions as a current path for the MOSFET in the element region 101, for example.

[0043] The second portion 31y is in contact with the first face F1 and the source electrode 12. The second portion 31y functions, for example, as a current path of the SBD in the element region 101. For example, a silicide layer 14 is provided in the second direction of the second portion 31y.

[0044] The p-type base region 33 is provided between the drift region 31 and the first face F1. The base region 33 is provided between the high concentration region 31b and the first face F1.

[0045] The base region 33 extends, for example, in the second direction. For example, a plurality of base regions 33 are repeatedly arranged in the first direction.

[0046] The base region 33 includes, for example, a first base region 33a, a second base region 33b, and a p-type third base region 33c. The first base region 33a is provided between the third base region 33c and the outer periphery p-type region 32. The second base region 33b is provided between the third base region 33c and the first base region 33a.

[0047] The base region 33 functions as the channel region of the MOSFET 100 .

[0048] The width of the base region 33 in the first direction is, for example, not less than 0.5 μm and not more than 2.0 μm. The second width (w2 in FIG. 3) of the first base region 33a in the first direction is, for example, not less than 0.5 μm and not more than 2.0 μm.

[0049] The distance in the first direction between two adjacent base regions 33 in the first direction is, for example, not less than 0.5 μm and not more than 2.0 μm. The second distance in the first direction (s2 in FIG. 3) between the first base region 33 a and the second base region 33 b is, for example, not less than 0.5 μm and not more than 2.0 μm.

[0050] The depth of the base region 33 is, for example, not less than 1.0 μm and not more than 2.0 μm.

[0051] The base region 33 is electrically connected to the source electrode 12. The base region 33 is fixed to the potential of the source electrode 12.

[0052] A portion of the base region 33 is in contact with the first face F1. A portion of the base region 33 faces the gate electrode 18. For example, a portion of the first base region 33a faces the gate electrode 18. For example, a portion of the second base region 33b faces the gate electrode 18. A gate insulating layer 16 is sandwiched between the portion of the base region 33 and the gate electrode 18.

[0053] The base region 33 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the base region 33 is, for example, 5×10 17 cm -3 More than 1×10 20 cm -3 The following is the result.

[0054] The p-type outer peripheral p-region 32 is provided between the drift region 31 and the first face F1. The outer peripheral p-region 32 is provided between the high-concentration region 31b and the first face F1.

[0055] The outer circumferential p region 32 is provided on the outer periphery of the base region 33. The outer circumferential p region 32 is provided on the intermediate region 103 side of the base region 33. The outer circumferential p region 32 is provided on the intermediate region 103 side of the third base region 33c. For example, the outer circumferential p region 32 surrounds the base region 33 on the first face F1.

[0056] The width of the outer periphery p-type region 32 in the first direction is, for example, not less than 0.5 μm and not more than 2.0 μm, and is, for example, substantially the same as the width of the base region 33 in the first direction.

[0057] The distance in the first direction between the outer periphery p-type region 32 and the first base region 33a is, for example, 0.5 μm or more and 2.0 μm or less. For example, the distance in the first direction between the outer periphery p-type region 32 and the first base region 33a is substantially equal to the distance in the first direction between two base regions 33 adjacent in the first direction.

[0058] The second depth (d2 in FIG. 3) of the outer periphery p-type region 32 is, for example, 1.0 μm or more and 2.0 μm or less. The second depth d2 of the outer periphery p-type region 32 is, for example, substantially the same as the depth of the base region 33.

[0059] The peripheral p-type region 32 is electrically connected to the source electrode 12. The peripheral p-type region 32 is fixed to the potential of the source electrode 12.

[0060] The peripheral p-type region 32 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the peripheral p-type region 32 is, for example, 5×10 17 cm -3 More than 1×10 20 cm -3 The p-type impurity concentration of the peripheral p-region 32 is, for example, substantially the same as the p-type impurity concentration of the base region 33.

[0061] The peripheral p-type region 32 is formed in the same manufacturing process as the base region 33 using the same mask pattern, for example.

[0062] The p-type first p region 34 is provided between the drift region 31 and the first face F1. The first p region 34 is provided between the high concentration region 31b and the first face F1.

[0063] The first p region 34 is provided, for example, between two base regions 33 adjacent in the first direction. The first p region 34 is provided between the outer periphery p region 32 and the first base region 33a. The first p region 34 is provided between the silicide layer 14 and the high concentration region 31b.

[0064] The depth of the first p region 34 is shallower than the second depth d2 of the peripheral p region 32 and the depth of the base region 33. The depth of the first p region 34 is shallower than the depth of the first base region 33a, for example. The depth of the first p region 34 is not less than 0.5 μm and not more than 1 μm, for example.

[0065] The first p-region 34 is electrically connected to the source electrode 12. The first p-region 34 is fixed to the potential of the source electrode 12.

[0066] The first p-type region 34 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the first p-type region 34 is, for example, 5×10 17 cm -3 More than 1×10 20 cm -3 The following is the result.

[0067] The drift region 31 includes a third portion 31z in the termination region 102. The third portion 31z contacts the first face F1 and the source electrode wiring layer 13. The third portion 31z functions as, for example, a current path for the SBD in the termination region 102.

[0068] The p-type second p region 36 is provided between the drift region 31 and the first face F1. The second p region 36 is provided between the low concentration region 31a and the first face F1.

[0069] The depth of the second p region 36 is shallower than the depth of the peripheral p region 32 and the depth of the base region 33. The depth of the second p region 36 is, for example, shallower than the depth of the first base region 33a. The depth of the second p region 36 is, for example, not less than 0.5 μm and not more than 1 μm.

[0070] The depth of the second p region 36 is, for example, substantially the same as the depth of the first p region 34 .

[0071] The second p region 36 is electrically connected to the source electrode wiring layer 13. The second p region 36 is fixed to the potential of the source electrode wiring layer 13. The second p region 36 is fixed to the potential of the source electrode 12.

[0072] The second p-type region 36 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the second p-type region 36 is, for example, 5×10 17 cm -3 More than 1×10 20 cm -3 The p-type impurity concentration of the second p-region 36 is, for example, substantially the same as the p-type impurity concentration of the first p-region 34.

[0073] The second p-region 36 is formed, for example, in the same manufacturing process as the first p-region 34 using the same mask pattern.

[0074] The p-type third p region 37 is provided between the drift region 31 and the first face F1. The third p region 37 is provided between the low-concentration region 31a and the first face F1. The third p region 37 contacts the outer periphery p region 32 and the second p region 36.

[0075] The depth of the third p region 37 is shallower than the depth of the peripheral p region 32 and the depth of the base region 33. The depth of the third p region 37 is, for example, shallower than the depth of the first base region 33a. The depth of the third p region 37 is, for example, not less than 0.5 μm and not more than 1 μm.

[0076] The depth of the third p region 37 is, for example, substantially the same as the depth of the first p region 34 and the depth of the second p region 36 .

[0077] The third p region 37 is electrically connected to the source electrode 12. The third p region 37 is fixed to the potential of the source electrode 12.

[0078] The third p-type region 37 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the third p-type region 37 is, for example, 5×10 17 cm -3 More than 1×10 20 cm -3The p-type impurity concentration of the third p-region 37 is, for example, substantially the same as the p-type impurity concentration of the first p-region 34 and the p-type impurity concentration of the second p-region 36.

[0079] The third p region 37 is formed in the same manufacturing process as the first p region 34 and the second p region 36 using the same mask pattern, for example.

[0080] The p-type fourth p region 38 is provided between the drift region 31 and the first face F1. The fourth p region 38 is provided between the drift region 31 and the third p region 37.

[0081] The fourth p region 38 is provided, for example, between the low concentration region 31a and the first face F1. The fourth p region 38 is provided, for example, between the low concentration region 31a and the third p region 37. The fourth p region 38 is in contact with the low concentration region 31a, for example.

[0082] The fourth p region 38 is provided on the outer periphery of the outer p region 32. The fourth p region 38 is provided on the termination region 102 side of the outer p region 32. For example, the fourth p region 38 surrounds the outer p region 32 on the first face F1.

[0083] The first width (w1 in FIG. 3) of the fourth p region 38 in the first direction is, for example, 0.5 to 3 times the width of the base region 33 in the first direction. The first width w1 of the fourth p region 38 is 0.5 to 3 times the second width (w2 in FIG. 3) of the first base region 33a in the first direction. The first width w1 of the fourth p region 38 is, for example, 0.5 μm to 10 μm. The first width w1 of the fourth p region 38 is, for example, substantially the same as the width of the base region 33 in the first direction.

[0084] The first distance (s1 in FIG. 3) in the first direction between the fourth p region 38 and the outer periphery p region 32 is 0.5 to 3 times the second distance (s2 in FIG. 3) between the first base region 33a and the second base region 33b. The first distance s1 between the fourth p region 38 and the outer periphery p region 32 is, for example, 0.5 μm to 2.0 μm.

[0085] The fourth p-region 38 is provided, for example, on the element region 101 side of the end of the field insulating layer 24 of the intermediate region 103 on the element region 101 side.

[0086] The first depth (d1 in FIG. 3) of the fourth p region 38 is deeper than the depth of the third p region 37. The first depth d1 of the fourth p region 38 is, for example, not less than 1.0 μm and not more than 2.0 μm. The first depth d1 of the fourth p region 38 is, for example, not less than 1.5 and not more than 5 times the depth of the third p region 37.

[0087] The first depth d1 of the fourth p region 38 is, for example, 0.5 to 2 times the depth of the base region 33. The first depth d1 of the fourth p region 38 is, for example, equal to or greater than the depth of the base region 33. The first depth d1 of the fourth p region 38 is, for example, deeper than the depth of the base region 33.

[0088] The first depth d1 of the fourth p region 38 is, for example, 0.5 to 2 times the depth of the first base region 33a. The first depth d1 of the fourth p region 38 is, for example, equal to or greater than the depth of the first base region 33a. The first depth d1 of the fourth p region 38 is, for example, deeper than the depth of the first base region 33a.

[0089] The first depth d1 of the fourth p region 38 is, for example, 0.5 to 2 times the second depth (d2 in FIG. 3 ) of the peripheral p region 32. The first depth d1 of the fourth p region 38 is, for example, greater than or equal to the second depth d2 of the peripheral p region 32. The first depth d1 of the fourth p region 38 is, for example, deeper than the second depth d2 of the peripheral p region 32.

[0090] The fourth p-region 38 is electrically connected to the source electrode 12. The fourth p-region 38 is fixed to the potential of the source electrode 12.

[0091] The fourth p-type region 38 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the fourth p-type region 38 is, for example, 1×10 17 cm -3 More than 1×10 20 cm -3 The following is the result.

[0092] The p-type impurity concentration of the fourth p region 38 is, for example, 0.1 to 2 times the p-type impurity concentration of the base region 33. The p-type impurity concentration of the fourth p region 38 is, for example, 0.1 to 2 times the p-type impurity concentration of the first base region 33a. The p-type impurity concentration of the fourth p region 38 is, for example, substantially the same as the p-type impurity concentration of the first base region 33a.

[0093] The p-type impurity concentration of the fourth p region 38 is, for example, 0.1 to 2 times the p-type impurity concentration of the peripheral p region 32. The p-type impurity concentration of the fourth p region 38 is, for example, substantially the same as the p-type impurity concentration of the peripheral p region 32.

[0094] The fourth p-type region 38 is formed in the same manufacturing process as the base region 33 and the peripheral p-type region 32 using the same mask pattern, for example.

[0095] The third distance in the first direction (s3 in FIG. 3) between the high concentration region 31b and the third portion 31z is greater than the third distance in the first direction (s4 in FIG. 3) between the fourth p region 38 and the third portion 31z.

[0096] A third distance s3 in the first direction between the high-concentration region 31b and the third portion 31z is, for example, not less than 50 μm and not more than 200 μm.

[0097] The first width w1 of the fourth p region 38 is, for example, not more than one-tenth of the fourth distance (s4 in FIG. 3) in the first direction between the fourth p region 38 and the third portion 31z.

[0098] n + The source region 35 is provided between the base region 33 and the first face F1. The source region 35 is provided, for example, between the second base region 33b and the first face F1. The source region 35 extends, for example, in the first direction.

[0099] The source region 35 contains, for example, phosphorus (P) or nitrogen (N) as an n-type impurity. The n-type impurity concentration of the source region 35 is higher than the n-type impurity concentration of the drift region 31.

[0100] The n-type impurity concentration of the source region 35 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The depth of the source region 35 is shallower than the depth of the first p-region 34. The depth of the source region 35 is, for example, not less than 0.05 μm and not more than 0.2 μm.

[0101] The source region 35 is electrically connected to the source electrode 12. The source region 35 is in contact with the silicide layer 14. The contact between the source region 35 and the source electrode 12 is, for example, an ohmic contact. The source region 35 is fixed to the potential of the source electrode 12.

[0102] The gate electrode 18 is provided on the first face F1 side of the silicon carbide layer 10. The gate electrode 18 extends, for example, in the second direction. The multiple gate electrodes 18 are arranged, for example, parallel to one another in the first direction. The gate electrodes 18 have, for example, a stripe shape.

[0103] The gate electrode 18 is a conductive layer, and is, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

[0104] The gate electrode 18 faces the base region 33. The gate electrode 18 faces the first portion 31x.

[0105] The gate connection layer 20 is provided on the first face F1 side of the silicon carbide layer 10. The gate connection layer 20 is provided on the gate insulating layer 16 or the field insulating layer 24.

[0106] A portion of the gate connection layer 20 extends, for example, in a direction perpendicular to the gate electrode 18. The gate connection layer 20 has a function of electrically connecting the gate electrode 18 and the gate electrode pad 22.

[0107] The gate connection layer 20 is formed of, for example, the same material as the gate electrode 18 .

[0108] The gate pad layer 21 is provided on the first face F1 side of the silicon carbide layer 10. The gate pad layer 21 is provided on the field insulating layer 24.

[0109] The gate pad layer 21 is physically and electrically connected to the gate connection layer 20. The gate pad layer 21 has a function of electrically connecting the gate electrode 18 and the gate electrode pad 22.

[0110] The gate pad layer 21 is formed of, for example, the same material as the gate electrode 18 and the gate connection layer 20 .

[0111] The gate insulating layer 16 is provided between the gate electrode 18 and the base region 33. The gate insulating layer 16 is provided between the gate electrode 18 and the first portion 31x. The gate insulating layer 16 is provided between the gate electrode 18 and the source region 35.

[0112] The gate insulating layer 16 is made of, for example, silicon oxide. For example, a high-k insulating material (high dielectric constant insulating material) can be used for the gate insulating layer 16.

[0113] A field insulating layer 24 is provided on the silicon carbide layer 10 in the intermediate region 103. The field insulating layer 24 is, for example, silicon oxide.

[0114] The interlayer insulating layer 26 is provided on the gate electrode 18 and the silicon carbide layer 10. The interlayer insulating layer 26 is, for example, silicon oxide.

[0115] The source electrode 12 is provided on the first face F1 side of the silicon carbide layer 10 in the element region 101. The source electrode 12 is provided on the interlayer insulating layer .

[0116] The source electrode 12 is in contact with the silicon carbide layer 10 in the element region 101. The source electrode 12 is in contact with the silicide layer 14. The source electrode 12 is in contact with the second portion 31y.

[0117] The silicide layer 14 includes a silicide, such as nickel silicide or titanium silicide.

[0118] The contact between the source electrode 12 and the source region 35 becomes an ohmic contact by sandwiching the silicide layer 14 therebetween. The contact between the source electrode 12 and the base region 33 becomes an ohmic contact by sandwiching the silicide layer 14 therebetween. The contact between the source electrode 12 and the first p region 34 becomes an ohmic contact by sandwiching the silicide layer 14 therebetween.

[0119] The source electrode 12 includes a metal and has, for example, a laminated structure of titanium (Ti) and aluminum (Al).

[0120] The source electrode 12 is in contact with the second portion 31y, and the contact between the source electrode 12 and the second portion 31y is a Schottky contact.

[0121] The source electrode wiring layer 13 is provided on the first face F1 side of the silicon carbide layer 10 in the termination region 102. The source electrode wiring layer 13 is provided on the interlayer insulating layer .

[0122] The source electrode wiring layer 13 is physically and electrically connected to the source electrode 12. The source electrode wiring layer 13 surrounds the source electrode 12, for example.

[0123] The source electrode wiring layer 13 is in contact with the silicon carbide layer 10 in the termination region 102. The source electrode wiring layer 13 is in contact with the silicide layer 14. The source electrode wiring layer 13 is in contact with the third portion 31z.

[0124] The contact between the source electrode wiring layer 13 and the second p-region 36 is an ohmic contact by sandwiching the silicide layer 14 therebetween.

[0125] The source electrode wiring layer 13 contains a metal. The source electrode 12 has a laminated structure of, for example, titanium (Ti) and aluminum (Al).

[0126] The source electrode wiring layer 13 is in contact with the third portion 31z, and the contact between the source electrode wiring layer 13 and the third portion 31z is a Schottky contact.

[0127] The gate electrode pad 22 is provided on the first face F1 side of the silicon carbide layer in the intermediate region 103. The gate electrode pad 22 is provided on the interlayer insulating layer .

[0128] The gate electrode pad 22 includes a metal. The gate electrode pad 22 has a laminated structure of, for example, titanium (Ti) and aluminum (Al). The gate electrode pad 22 is formed of, for example, the same material as the source electrode 12 and the source electrode wiring layer 13.

[0129] The gate electrode wiring layer is provided on the first face F1 side of the silicon carbide layer in the intermediate region 103. The gate electrode wiring layer is provided on the interlayer insulating layer .

[0130] The gate electrode wiring layer 23 is physically and electrically connected to the gate electrode pad 22. The gate electrode wiring layer 23 is physically and electrically connected to the gate connection layer 20.

[0131] The gate electrode wiring layer 23 includes a metal. The source electrode 12 has, for example, a laminated structure of titanium (Ti) and aluminum (Al). The gate electrode wiring layer 23 is formed of, for example, the same material as the source electrode 12, the source electrode wiring layer 13, and the gate electrode pad 22.

[0132] The drain electrode 15 is provided on the back surface of the silicon carbide layer 10. The drain electrode 15 is in contact with the drain region 30.

[0133] The drain electrode 15 is, for example, a metal or a metal-semiconductor compound, and includes at least one material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0134] In the element region 101, the gate electrode 18, the gate insulating layer 16, the base region 33, the source region 35, the first portion 31x of the drift region 31, the drain region 30, the source electrode 12, and the drain electrode 15 form a MOSFET. When the MOSFET 100 is in an on-state, a current flows from the drain electrode 15 to the source electrode 12 through the MOSFET in the element region 101.

[0135] In the element region 101, the source electrode 12, the second portion 31y of the drift region 31, the drain region 30, and the drain electrode 15 form an SBD. When the MOSFET 100 is in an off state and a positive voltage is applied to the source electrode 12 with respect to the drain electrode 15, the SBD in the element region 101 allows a current to flow from the source electrode 12 to the drain electrode 15.

[0136] In the termination region 102, the source electrode wiring layer 13, the third portion 31z of the drift region 31, the drain region 30, and the drain electrode 15 form an SBD. When the MOSFET 100 is in an off state and a positive voltage is applied to the source electrode 12 with respect to the drain electrode 15, the SBD in the termination region 102 allows a current to flow from the source electrode wiring layer 13 to the drain electrode 15.

[0137] Next, the operation and effects of the MOSFET 100 of the first embodiment will be described.

[0138] 4 is an equivalent circuit diagram of the semiconductor device of the first embodiment. In the MOSFET 100, a pn junction diode and an SBD are connected in parallel to the transistor as built-in diodes between the source electrode 12 and the drain electrode 15 of the element region 101. The base region 33 is the anode side of the pn junction diode, and the drift region 31 is the cathode side of the pn junction diode. The source electrode 12 is the anode of the SBD, and the drain electrode 15 is the cathode of the SBD.

[0139] For example, consider a case where MOSFET 100 is used as a switching element connected to an inductive load. When MOSFET 100 is off, an induced current caused by the inductive load may apply a voltage to source electrode 12 that is positive with respect to drain electrode 15. In this case, a forward current flows through the built-in diode. This state is also called a reverse conduction state.

[0140] If a MOSFET does not have an SBD, a forward current flows through the pn junction diode. The pn junction diode operates in bipolar mode. When a return current flows through a bipolar pn junction diode, stacking faults grow in the silicon carbide layer due to the carrier recombination energy. When stacking faults grow in the silicon carbide layer, the on-resistance of the MOSFET increases. This increase in the on-resistance of the MOSFET reduces the reliability of the MOSFET.

[0141] The MOSFET 100 includes an SBD. The forward voltage (Vf) at which a forward current begins to flow through the SBD is lower than the forward voltage (Vf) of a pn junction diode. Therefore, a forward current flows through the SBD before the pn junction diode.

[0142] The forward voltage (Vf) of the SBD is, for example, not less than 1.0 V and not more than 2.0 V. The forward voltage (Vf) of the pn junction diode is, for example, not less than 2.0 V and not more than 3.0 V.

[0143] The SBD operates in a unipolar manner. Therefore, even if a forward current flows, stacking faults do not grow in the silicon carbide layer 10 due to carrier recombination energy. This prevents an increase in the on-resistance of the MOSFET 100, thereby improving the reliability of the MOSFET 100.

[0144] Furthermore, when a forward current flows through the SBD, the voltage on the N-side of the pn junction diode increases, effectively reducing the voltage applied to the pn junction near the SBD. Therefore, by providing the SBD, the forward voltage (Vf) of the pn junction diode near the SBD can be effectively increased. This prevents a forward current from flowing through the pn junction diode. In other words, the operation start voltage of the pn junction diode can be increased. This improves the reliability of the MOSFET 100.

[0145] Fig. 5 is a schematic cross-sectional view of a semiconductor device of a comparative example, which is a MOSFET 900. Fig. 5 is a view corresponding to Fig. 3 of the first embodiment.

[0146] The MOSFET 900 of the comparative example differs from the MOSFET 100 of the first embodiment in that the first width (w1 in FIG. 5) in the first direction of the fourth p region 38 provided in the intermediate region 103 is greater than three times the second width (w2 in FIG. 5) in the first direction of the first base region 33a.

[0147] The MOSFET 900 of the comparative example has a third p-type region 37 and a fourth p-type region 38 deeper than the third p-type region 37, provided outside the n-type heavily doped region 31b provided in the element region 101. This configuration reduces the strength of the electric field applied to the end of the pn junction in the element region 101 when the MOSFET 900 is in the off state. This improves the breakdown voltage of the MOSFET 900.

[0148] Fig. 6 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment, Fig. 6 is a schematic cross-sectional view of a semiconductor device of a comparative example, and Fig. 6 is a diagram corresponding to Fig. 5.

[0149] 6 shows, by circuit symbols, the pn junction diode and SBD present in the MOSFET 900. In addition, in FIG. 6, arrows indicate the current flowing through the MOSFET 900 when a voltage that is positive with respect to the drain electrode 15 is applied to the source electrode 12 of the MOSFET 900.

[0150] As shown in FIG. 6, in the element region 101, a forward current flows through the SBD, which includes the source electrode 12 and the second portion 31y of the drift region 31. The forward current passes between the base regions 33 and flows around to the bottom of the base region 33. The forward current that flows around to the bottom of the base region 33 increases the voltage on the N-side of the pn junction diode formed by the base region 33 and the drift region 31, effectively reducing the voltage applied to the pn junction near the SBD. This effectively increases the forward voltage (Vf) of the pn junction diode in the element region 101. This prevents the forward current from flowing through the pn junction diode in the element region 101.

[0151] 6, in the termination region 102, a forward current flows through the SBD including the source electrode wiring layer 13 and the third portion 31z of the drift region 31. The forward current passes between the second p region 36 and flows around to the bottoms of the second p region 36, the third p region 37, and the fourth p region 38. However, because there is a distance from the SBD in the termination region 102 to the fourth p region 38 close to the element region 101, the current is prevented from flowing around to the bottom of the fourth p region 38 close to the element region 101.

[0152] Therefore, in the portion close to the element region 101, an increase in the voltage on the N side of the pn junction diode formed by the fourth p region 38 and the drift region 31 is unlikely to occur. That is, a decrease in the voltage applied to the pn junction due to a forward current is suppressed. As a result, the pn junction diode in the element region 101 operates, and a bipolar current easily flows in the drift region 31. This raises concerns about a decrease in the reliability of the MOSFET 900 due to an increase in on-resistance.

[0153] Fig. 7 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment, Fig. 7 is a schematic cross-sectional view of the semiconductor device of the first embodiment, Fig. 7 is a diagram corresponding to Fig. 3.

[0154] 7 shows, by circuit symbols, the pn junction diode and SBD present in the MOSFET 100. In addition, in FIG. 7, arrows indicate the current flowing through the MOSFET 100 when a voltage that is positive with respect to the drain electrode 15 of the MOSFET 100 is applied to the source electrode 12 of the MOSFET 100.

[0155] 7, similar to the MOSFET 900 of the comparative example shown in FIG. 6, in the element region 101, a forward current flows through the SBD including the source electrode 12 and the second portion 31y of the drift region 31. Therefore, similar to the MOSFET 900 of the comparative example, a forward current is prevented from flowing through the pn junction diode in the element region 101.

[0156] 7, in the MOSFET 100 of the first embodiment, the first width (w1 in FIG. 7) in the first direction of the fourth p region 38 provided in the intermediate region 103 is three times or less the second width (w2 in FIG. 7) in the first direction of the first base region 33a. The first width w1 of the fourth p region 38 is smaller than that of the MOSFET 900 of the comparative example.

[0157] The reduction in the first width w1 of the fourth p region 38 reduces the proportion of the deep p-type region in the intermediate region 103. This promotes the current flowing from the SBD in the termination region 102 to the bottom of the fourth p region 38 near the element region 101.

[0158] Therefore, in the portion close to the element region 101, an increase in the voltage on the N side of the pn junction diode formed by the fourth p region 38 and the drift region 31 is likely to occur. This promotes a decrease in the voltage applied to the pn junction due to the forward current. This makes it difficult for the pn junction diode in the element region 101 to operate, making it difficult for bipolar current to flow in the drift region 31. This suppresses the generation of stacking faults and improves the reliability of the MOSFET 100.

[0159] From the viewpoint of promoting penetration of the fourth p region 38 into the bottom and improving the reliability of the MOSFET 100, the first width w1 of the fourth p region 38 is preferably equal to or less than twice the second width w2 in the first direction of the first base region 33a, more preferably equal to or less than 1.5 times, and even more preferably equal to or less than 1 time.

[0160] From the viewpoint of reducing the strength of the electric field applied to the terminal end of the pn junction of the element region 101 and improving the dielectric breakdown voltage of the MOSFET 100, the first width w1 of the fourth p region 38 is preferably at least 0.75 times the width w2 of the first base region 33a in the first direction, and more preferably at least 1 time.

[0161] From the viewpoint of promoting penetration of the fourth p region 38 to the bottom and improving the reliability of the MOSFET 100, the first width w1 of the fourth p region 38 is preferably 10 μm or less, more preferably 5 μm or less, even more preferably 3 μm or less, and most preferably 1.5 μm or less.

[0162] From the viewpoint of reducing the strength of the electric field applied to the terminal end of the pn junction in the element region 101 and improving the dielectric breakdown voltage of the MOSFET 100, the first width w1 of the fourth p region 38 is preferably 0.5 μm or more, and more preferably 1.0 μm or more.

[0163] From the viewpoint of reducing the strength of the electric field applied to the terminal end of the pn junction in the element region 101 and improving the dielectric breakdown voltage of the MOSFET 100, it is preferable that the p-type impurity concentration of the fourth p region 38 be 0.1 to 2 times the p-type impurity concentration of the first base region 33a.

[0164] From the viewpoint of reducing the strength of the electric field applied to the terminal end of the pn junction in the element region 101 and improving the dielectric breakdown voltage of the MOSFET 100, it is preferable that the p-type impurity concentration of the fourth p region 38 be 0.1 to 2 times the p-type impurity concentration of the peripheral p region 32.

[0165] From the viewpoint of reducing the strength of the electric field applied to the terminal end of the pn junction in the element region 101 and improving the dielectric breakdown voltage of the MOSFET 100, it is preferable that the depth of the fourth p region 38 is deeper than the depths of the base region 33 and the peripheral p region 32.

[0166] From the viewpoint of reducing the strength of the electric field applied to the terminal end of the pn junction in the element region 101 and improving the dielectric breakdown voltage of the MOSFET 100, it is preferable that the first distance s1 in the first direction between the fourth p region 38 and the peripheral p region 32 be 0.75 to 2 times the second distance (s2 in FIG. 3) between the first base region 33a and the second base region 33b.

[0167] From the viewpoint of reducing the strength of the electric field applied to the terminal end of the pn junction of the element region 101 and improving the dielectric breakdown voltage of the MOSFET 100, it is preferable that the third distance in the first direction (s3 in FIG. 3) between the high-concentration region 31b and the third portion 31z is greater than the fourth distance in the first direction (s4 in FIG. 3) between the fourth p region 38 and the third portion 31z.

[0168] From the viewpoint of promoting penetration of the fourth p region 38 into the bottom and improving the reliability of the MOSFET 100, the first width w1 of the fourth p region 38 in the first direction is preferably not more than one-tenth, more preferably not more than one-twentieth, and even more preferably not more than one-fiftieth of the fourth distance (s4 in FIG. 3) in the first direction between the fourth p region 38 and the third portion 31z.

[0169] As described above, according to the first embodiment, a MOSFET is realized in which the forward current is prevented from flowing through the pn junction diode and the reliability is improved.

[0170] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that it further includes an eleventh silicon carbide region of the first conductivity type provided between the tenth silicon carbide region and the first surface. Hereinafter, some description of content that overlaps with the first embodiment may be omitted.

[0171] Fig. 8 is a schematic cross-sectional view of a semiconductor device according to the second embodiment, which corresponds to Fig. 3 of the first embodiment.

[0172] The semiconductor device of the second embodiment is a planar-gate vertical MOSFET 200 using silicon carbide. The MOSFET 200 is, for example, a DIMOSFET in which the base region and the source region are formed by ion implantation. The semiconductor device of the second embodiment also includes an SBD as a built-in diode.

[0173] The following description will be given taking as an example a case where the first conductivity type is n-type and the second conductivity type is p-type. The MOSFET 200 is a vertical n-channel MOSFET that uses electrons as carriers.

[0174] The MOSFET 200 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a source electrode wiring layer 13 (wiring layer), a silicide layer 14, a drain electrode 15 (second electrode), a gate insulating layer 16, a gate electrode 18, a gate connection layer 20, a gate pad layer 21, a gate electrode pad 22, a gate electrode wiring layer 23, a field insulating layer 24, and an interlayer insulating layer 26.

[0175] The silicon carbide layer 10 is n + n-type drain region 30, n-type drift region 31 (first silicon carbide region), p-type outer peripheral p-region 32 (third silicon carbide region), p-type first base region 33a (fourth silicon carbide region), p-type second base region 33b (fifth silicon carbide region), p-type third base region 33c (second silicon carbide region), p-type first p-region 34 (sixth silicon carbide region), n + a second p-type region 36 (eighth silicon carbide region), a third p-type region 37 (ninth silicon carbide region), a fourth p-type region 38 (tenth silicon carbide region), an n + The n-type drift region 31 (first silicon carbide region) includes an n-type floating region 39 (eleventh silicon carbide region). - The n-type drift region 31 has a first portion 31x, a second portion 31y, and a third portion 31z.

[0176] n + A floating region 39 is provided between the fourth p region 38 and the first face F1. The floating region 39 is provided directly above the fourth p region 38. The floating region 39 contacts the first face F1. The floating region 39 is provided within the third p region 37.

[0177] The floating region 39 is electrically floating and is not electrically connected to any of the source electrode 12, the drain electrode 15, and the gate electrode 18.

[0178] The fourth p region 38 and the floating region 39 are formed, for example, in the same manufacturing process using the same mask pattern as the base region 33 and the source region 35. By forming the fourth p region 38 and the floating region 39 in the same manufacturing process using the same mask pattern as the base region 33 and the source region 35, it is possible to shorten the manufacturing process of the MOSFET 200 and reduce manufacturing costs, for example.

[0179] As described above, according to the second embodiment, similarly to the first embodiment, a forward current is prevented from flowing through the pn junction diode, and a MOSFET with improved reliability is realized.

[0180] In the first and second embodiments, the case where the crystal structure of SiC is 4H—SiC has been described as an example, but the present invention can also be applied to devices using SiC with other crystal structures such as 6H—SiC, 3C—SiC, etc. Furthermore, it is also possible to apply a plane other than the (0001) plane to the surface of the silicon carbide layer 10.

[0181] In the first and second embodiments, an example is described in which the first conductivity type is n-type and the second conductivity type is p-type, but it is also possible for the first conductivity type to be p-type and the second conductivity type to be n-type.

[0182] In the first and second embodiments, aluminum (Al) is used as an example of the p-type impurity, but boron (B) can also be used. Furthermore, nitrogen (N) and phosphorus (P) are used as examples of the n-type impurity, but arsenic (As), antimony (Sb), etc. can also be used.

[0183] In the first or second embodiment, the gate electrode 18 has a stripe shape in the element region 101, but it is also possible to use a structure in which the gate electrode 18 has a mesh shape, for example.

[0184] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0185] 10 Silicon carbide layer 12 Source electrode (first electrode) 13 Source electrode wiring layer (wiring layer) 15 Drain electrode (second electrode) 16 Gate insulating layer 18 gate electrode 31 n-type drift region (first silicon carbide region) 31a n - Low concentration region of the shape (first region) 31b n-type high concentration region (second region) 31x First part 31y second part 31z Third Part 32 p-type outer p region (third silicon carbide region) 33a: p-type first base region (fourth silicon carbide region) 33b p-type second base region (fifth silicon carbide region) 33c p-type third base region (second silicon carbide region) 34 p-type first p region (sixth silicon carbide region) 35n + Type source region (seventh silicon carbide region) 36 p-type second p region (eighth silicon carbide region) 37 p-type third p region (ninth silicon carbide region) 38 p-type fourth p region (tenth silicon carbide region) 39n+ Mold floating region (11th silicon carbide region) 100 MOSFET (semiconductor device) 101 Element Area 102 Termination area 103 Intermediate area 200 MOSFET (semiconductor device) F1 First Side F2 Second side d1 First depth d2 Second depth s1 First distance s2 Second distance s3 Third distance s4 fourth distance w1 First width w2 Second width

Claims

1. an element region; a termination region surrounding the element region; an intermediate region provided between the element region and the termination region and surrounding the element region; Equipped with The element region is a first electrode; a second electrode; and a gate electrode; a silicon carbide layer provided between the first electrode and the second electrode, the silicon carbide layer having a first surface on the first electrode side and a second surface on the second electrode side, a first silicon carbide region of a first conductivity type, the first silicon carbide region having: a first region; a second region provided between the first region and the first surface and having a first conductivity type impurity concentration higher than that of the first region; a first portion in contact with the first surface and facing the gate electrode; and a second portion in contact with the first surface and in contact with the first electrode; a second silicon carbide region of a second conductivity type provided between the second region and the first surface and electrically connected to the first electrode; a third silicon carbide region of the second conductivity type provided between the second region and the first surface, on the side of the intermediate region of the second silicon carbide region, and electrically connected to the first electrode; a fourth silicon carbide region of the second conductivity type provided between the second region and the first surface, between the second silicon carbide region and the third silicon carbide region, facing the gate electrode and electrically connected to the first electrode; a fifth silicon carbide region of the second conductivity type provided between the second region and the first surface, between the second silicon carbide region and the fourth silicon carbide region, facing the gate electrode and electrically connected to the first electrode; a sixth silicon carbide region of the second conductivity type provided between the second region and the first surface, between the third silicon carbide region and the fourth silicon carbide region, and having a depth shallower than a depth of the third silicon carbide region and a depth of the fourth silicon carbide region; a seventh silicon carbide region of the first conductivity type provided between the fifth silicon carbide region and the first surface and electrically connected to the first electrode; a silicon carbide layer comprising: a gate insulating layer provided between the gate electrode and the fifth silicon carbide region and between the gate electrode and the first portion; Including, The termination region is a wiring layer electrically connected to the first electrode; the second electrode; the silicon carbide layer including: the first silicon carbide region having a third portion in contact with the first surface and in contact with the wiring layer; and an eighth silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface, electrically connected to the wiring layer, and having a depth shallower than that of the third silicon carbide region; Including, The intermediate region is the second electrode; the first silicon carbide region; and a ninth silicon carbide region of the second conductivity type, the ninth silicon carbide region being provided between the first silicon carbide region and the first surface, electrically connected to the first electrode, in contact with the third silicon carbide region and the eighth silicon carbide region, and having a depth shallower than that of the third silicon carbide region; a tenth silicon carbide region of a second conductivity type provided between the first silicon carbide region and the ninth silicon carbide region, the tenth silicon carbide region having a first width in a first direction parallel to the first surface that is 0.5 to 3 times a second width in the first direction of the fourth silicon carbide region, and a first distance in the first direction between the tenth silicon carbide region and the third silicon carbide region that is 0.5 to 3 times a second distance in the first direction between the fourth silicon carbide region and the fifth silicon carbide region.

2. 2. The semiconductor device according to claim 1, wherein the first width is equal to or smaller than twice the second width.

3. 2. The semiconductor device according to claim 1, wherein the first width is not less than 0.5 [mu]m and not more than 10 [mu]m.

4. 2. The semiconductor device according to claim 1, wherein the concentration of the second conductivity type impurity in the tenth silicon carbide region is 0.1 to 2 times the concentration of the second conductivity type impurity in the third silicon carbide region.

5. The semiconductor device according to claim 1 , wherein the first depth of the tenth silicon carbide region is greater than the second depth of the third silicon carbide region.

6. The semiconductor device according to claim 1 , wherein the tenth silicon carbide region is in contact with the first region.

7. 2. The semiconductor device of claim 1, wherein a third distance in the first direction between the second region and the third portion is greater than a fourth distance in the first direction between the tenth silicon carbide region and the third portion.

8. 2 . The semiconductor device according to claim 1 , wherein the first width is equal to or less than one-tenth of a fourth distance in the first direction between the tenth silicon carbide region and the third portion.

9. The semiconductor device according to claim 1 , further comprising: an eleventh silicon carbide region of the first conductivity type provided between the tenth silicon carbide region and the first surface.

10. The semiconductor device according to claim 9 , wherein the eleventh silicon carbide region is electrically floating.

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