Image pickup device

Abstract

To suppress distortion caused by a rolling shutter.SOLUTION: An imaging element includes a first semiconductor substrate having a plurality of pixels, and a second semiconductor substrate having a control circuit unit and a peripheral circuit unit arranged outside the control circuit unit. The pixel includes a photoelectric conversion unit configured to convert light into a charge, a holding unit configured to hold the charge of the photoelectric conversion unit, a first transfer unit configured to transfer the charge from the photoelectric conversion unit to the holding unit, an accumulation unit configured to accumulate the charge of the holding unit, a second transfer unit configured to transfer the charge from the holding unit to the accumulation unit, and an output unit configured to output a signal based on the charge of the accumulation unit, the control circuit unit includes a first pixel control unit that controls the first transfer unit of a first pixel among the plurality of pixels, and a second pixel control unit that controls the first transfer unit of a second pixel among the plurality of pixels, and the peripheral circuit unit controls the output unit of the first pixel and the output unit of the second pixel.SELECTED DRAWING: Figure 1

Description

Incorporation by Reference

[0001] This application claims priority from Japanese Patent Application No. 2021-137586, filed on August 25, 2021, the contents of which are incorporated herein by reference. [Technical Field]

[0002] The present invention relates to an imaging element and an imaging device. [Background technology]

[0003] An image sensor having a pixel array in which a plurality of pixels are arranged is known (for example, Patent Document 1). Conventionally, when an image signal is read using a rolling shutter method, there has been a problem in that distortion occurs in the captured image of the subject. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-72779 Summary of the Invention

[0005] The imaging element of the first disclosed technique includes a first photoelectric conversion unit that converts light into electric charges, a second photoelectric conversion unit that converts light into electric charges and is arranged alongside the first photoelectric conversion unit in the row direction, a first transfer unit that transfers electric charges converted by the first photoelectric conversion unit, a second transfer unit that transfers electric charges converted by the second photoelectric conversion unit, a first holding unit that holds electric charges transferred from the first photoelectric conversion unit by the first transfer unit, a second holding unit that holds electric charges transferred from the second photoelectric conversion unit by the second transfer unit, a first accumulation unit to which the electric charges held in the first holding unit are transferred, a second accumulation unit to which the electric charges held in the second holding unit are transferred, a first output unit that outputs a first signal based on the electric charges transferred from the first holding unit to the first accumulation unit, the first output unit having a first selection unit electrically connected to the first signal line, and a first selection unit that selects an electric charge based on the electric charges transferred from the second holding unit to the second accumulation unit. a first semiconductor substrate having a pixel portion including a second output portion that outputs a second signal to a second signal line, the second output portion having a second selection portion electrically connected to the second signal line; a semiconductor substrate stacked on the first semiconductor substrate, the first circuit portion including a first control block that outputs a first transfer control signal to control the first transfer portion and a second control block that outputs a second transfer control signal to control the second transfer portion; and a second semiconductor substrate arranged outside the first circuit portion, the second circuit portion outputting a selection control signal to control the first selection portion and the second selection portion, wherein the first transfer portion is electrically connected to a first transfer control line through which the first transfer control signal is output, the second transfer portion is electrically connected to a second transfer control line through which the second transfer control signal is output, and the first selection portion and the second selection portion are electrically connected to the selection control line through which the selection control signal is output.

[0006] The imaging device of the second disclosed technique includes the imaging element of the first disclosed technique. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is an exploded perspective view showing an example of an imaging element. [Figure 2]FIG. 2 is an explanatory diagram showing an example of a specific configuration of a pixel unit. [Figure 3] FIG. 3 is a circuit diagram showing an example of a circuit configuration of a pixel. [Figure 4] FIG. 4 is an explanatory diagram showing an example of a specific configuration of the control circuit unit. [Figure 5] FIG. 5 is an explanatory diagram showing an example of the internal configuration of the control block. [Figure 6] FIG. 6 is an explanatory diagram showing an example of signal transmission between a first semiconductor substrate and a second semiconductor substrate in an imaging element. [Figure 7] FIG. 7 is an explanatory diagram showing an example of an XZ direction cross section of the imaging element according to this embodiment. [Figure 8] FIG. 8 is a timing chart showing an example 1 of the imaging operation of the imaging element. [Figure 9] FIG. 9 is a timing chart showing a second example of the imaging operation of the imaging element. [Figure 10] FIG. 10 is a timing chart showing the imaging operation of the imaging element according to the comparative example. [Figure 11] FIG. 11 is an explanatory diagram showing an example of a subject imaged by an imaging element. [Figure 12] FIG. 12 is a timing chart showing the exposure time for each of the regions 1 to 5 shown in FIG. [Figure 13] FIG. 13 is a plan view showing an example of the layout of a plurality of control blocks. [Figure 14] FIG. 14 is a circuit diagram showing another example of the circuit configuration of a pixel. [Figure 15] FIG. 15 is a timing chart showing a third example of an imaging operation of the imaging element. [Figure 16] FIG. 16 is an exploded perspective view showing another example of the imaging element. [Figure 17] FIG. 17 is an explanatory diagram showing another example of the specific configuration of the control circuit section. [Figure 18] FIG. 18 is an explanatory diagram showing the connection relationship between the first semiconductor substrate and the second semiconductor substrate in the imaging element. [Figure 19]FIG. 19 is an explanatory diagram showing an example of signal transmission between a first semiconductor substrate and a second semiconductor substrate in an imaging element. [Figure 20] FIG. 20 is an explanatory diagram showing the connection relationship between the ADC unit and the pixel block. [Figure 21] FIG. 21 is a timing chart showing the imaging operation in a pixel block of the imaging element. [Figure 22] FIG. 22 is an explanatory diagram showing an example of exposure timing for each pixel block. [Figure 23] FIG. 23 is a block diagram showing an example of the configuration of the autonomous exposure control system 1. As shown in FIG. [Figure 24] FIG. 24 is a block diagram showing an example of the configuration of the autonomous exposure control system 2. In FIG. [Figure 25] FIG. 25 is a block diagram showing an example of the configuration of the autonomous exposure control system 3. [Figure 26] FIG. 26 is an explanatory diagram showing local control and global control. [Figure 27] FIG. 27 is an explanatory diagram showing an example of a control method based on an autonomous exposure control system using an image sensor including pixels with a 6Tr configuration. [Figure 28] FIG. 28 is a pulse chart of control method 1-1. [Figure 29] FIG. 29 is a pulse chart of control method 1-2. [Figure 30] FIG. 30 is an explanatory diagram showing an example of a control method based on an autonomous exposure control system using an image sensor including pixels with a 5Tr configuration. [Figure 31] FIG. 31 is a pulse chart of control method 2-1. [Figure 32] FIG. 32 is a pulse chart of control method 2-2. [Figure 33] FIG. 33 is an explanatory diagram showing an example of a control method based on an autonomous exposure control system using an image sensor including pixels with a 6Tr configuration. [Figure 34] FIG. 34 is a pulse chart of control method 3-1. [Figure 35] FIG. 35 is a pulse chart of control method 3-2. [Figure 36]FIG. 36 is an explanatory diagram showing an example of a control method based on an autonomous exposure control system using an image sensor including pixels with a 5Tr configuration. [Figure 37] FIG. 37 is a pulse chart of control method 4-1. [Figure 38] FIG. 38 is a pulse chart of control method 4-2. [Figure 39] FIG. 39 is an explanatory diagram showing frame-straddling exposure. [Figure 40] FIG. 40 is an explanatory diagram showing an example of flicker reduction control. [Figure 41] FIG. 41 is an explanatory diagram showing Example 1 of pixel group unit exposure control. [Figure 42] FIG. 42 is an explanatory diagram showing an example of wiring in pixel group unit exposure control. [Figure 43] FIG. 43 is an explanatory diagram showing a second example of pixel group unit exposure control. [Figure 44] FIG. 44 is an explanatory diagram showing pixel group unit exposure control example 3. In FIG. [Figure 45] FIG. 45 is an explanatory diagram showing Example 3 of pixel group unit exposure control. [Figure 46] FIG. 46 is a circuit diagram showing a first example of circuit configuration for autonomous exposure control 2 with additional memory. [Figure 47] FIG. 47 is an explanatory diagram showing an example of the operation of autonomous exposure control in pixel block units in the circuit configuration example 1 shown in FIG. [Figure 48] FIG. 48 is a pulse chart showing an example of the operation of autonomous exposure control in pixel block units in the circuit configuration example 1 shown in FIG. [Figure 49] FIG. 49 is a circuit diagram showing a second circuit configuration example of autonomous exposure control 2 with additional memory. [Figure 50] FIG. 50 is a pulse chart showing an example of the operation of autonomous exposure control in pixel block units in the circuit configuration example 2 shown in FIG. [Figure 51] FIG. 51 is a block diagram illustrating an example of the configuration of an imaging device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0009] In this specification, the X-axis and Y-axis are perpendicular to each other, and the Z-axis is perpendicular to the XY plane. The XYZ-axes form a right-handed system. The direction parallel to the Z-axis may be referred to as the stacking direction of the image sensor 100. In this specification, the terms "up" and "down" are not limited to the up and down directions in the direction of gravity. These terms merely refer to relative directions in the Z-axis direction. Note that in this specification, the arrangement in the X-axis direction will be described as a "row" and the arrangement in the Y-axis direction as a "column," but the matrix direction is not limited to this.

[0010] <Image sensor configuration> First, the configuration of the imaging element will be described with reference to Figures 1 to 22. The imaging element may have a back-illuminated or front-illuminated structure.

[0011] FIG. 1 is an exploded perspective view showing an example of an image sensor 100A. The image sensor 100A captures an image of a subject. The image sensor 100A generates image data of the captured subject. The image sensor 100A includes a first semiconductor substrate 110, a second semiconductor substrate 120, and a third semiconductor substrate 130. As shown in FIG. 1, the first semiconductor substrate 110 is stacked on the second semiconductor substrate 120, and the second semiconductor substrate 120 is stacked on the third semiconductor substrate 130.

[0012] The first semiconductor substrate 110 has a pixel section 101. The pixel section 101 outputs a pixel signal based on incident light.

[0013] The second semiconductor substrate 120 has a control circuit section 102 and a peripheral circuit section 121 .

[0014] The control circuit unit 102 receives pixel signals output from the first semiconductor substrate 110. The control circuit unit 102 processes the received pixel signals. The control circuit unit 102 is disposed on the second semiconductor substrate 120 at a position facing the pixel unit 101. For example, the control circuit unit 102 is disposed so as to overlap with the pixel unit 101 in the direction in which the first semiconductor substrate 110 and the second semiconductor substrate 120 are stacked. The control circuit unit 102 may output a control signal to the pixel unit 101 for controlling the driving of the pixel unit 101.

[0015] The peripheral circuit unit 121 controls the driving of the control circuit unit 102. The peripheral circuit unit 121 is arranged around the control circuit unit 102 on the second semiconductor substrate 120. Specifically, the peripheral circuit unit 121 is arranged in an area on the second semiconductor substrate 120 that is arranged outside the area in which the control circuit unit 102 is arranged. The peripheral circuit unit 121 may also be electrically connected to the first semiconductor substrate 110 and control the driving of the pixel unit 101. The peripheral circuit unit 121 is arranged along two sides of the second semiconductor substrate 120, but the arrangement of the peripheral circuit unit 121 is not limited to this example.

[0016] The third semiconductor substrate 130 has a data processing unit 103. The data processing unit 103 uses the digital data output from the second semiconductor substrate 120 to perform addition processing, thinning processing, and other image processing.

[0017] 2 is an explanatory diagram showing an example of a specific configuration of the pixel unit 101. The pixel unit 101 has a plurality of pixel blocks 200. The plurality of pixel blocks 200 are arranged in the row and column directions in the pixel unit 101. Specifically, the plurality of pixel blocks 200 includes M×N (M and N are natural numbers) pixel blocks 200 arranged in the row and column directions in the pixel unit 101. Although the figure shows a case where M is equal to N, M and N may be different.

[0018] The pixel block 200 has a plurality of pixels 201. The plurality of pixels 201 are arranged in rows and columns in the pixel block 200. The pixel block 200 has m×n (m and n are natural numbers) pixels 201 arranged in the rows and columns. For example, the pixel block 200 has 16×16 pixels 201 arranged in the rows and columns. The number of pixels 201 corresponding to the pixel block 200 is not limited to this. Although the illustration shows a case where m is equal to n, m may be different from n.

[0019] The pixel block 200 has a plurality of pixels 201 connected to a common control line (for example, a transfer control line 311 and a discharge control line 312, which will be described later) in the row direction. For example, each pixel 201 in the pixel block 200 is connected to the common control line so that the pixels 201 are set to the same exposure time. Specifically, for example, every n pixels 201 arranged in the row direction are connected by the common control line.

[0020] On the other hand, between different pixel blocks 200, one pixel block 200 may be set to a different exposure time from the other pixel block 200. For example, when one pixel block 200 and the other pixel block 200 are arranged side by side in the row direction, the multiple pixels 201 included in one pixel block 200 and the multiple pixels 201 included in the other pixel block 200 are connected by different control lines. The multiple pixels 201 in the m-th row of one pixel block 200 are connected in common by a control line that is different from the common control line to which the multiple pixels 201 in the m-th row of the other pixel block 200 are connected. Furthermore, when one pixel block 200 and the other pixel block 200 are arranged side by side in the column direction, the multiple pixels 201 included in one pixel block 200 and the multiple pixels 201 included in the other pixel block 200 are connected by different control lines. The pixels 201 in the mth row of one pixel block 200 are commonly connected to a control line that is different from the common control line to which the pixels 201 in the mth row of the other pixel block 200 are connected.

[0021] Furthermore, for example, when one pixel block 200 and the other pixel block 200 are arranged side by side in the row direction, the multiple pixels 201 included in one pixel block 200 and the multiple pixels 201 included in the other pixel block 200 are connected by different signal lines 202. The multiple pixels 201 in the n-th column of one pixel block 200 are connected in common by a signal line 202 that is different from the common signal line 202 to which the multiple pixels 201 in the n-th column of the other pixel block 200 are connected. Furthermore, when one pixel block 200 and the other pixel block 200 are arranged side by side in the column direction, the multiple pixels 201 included in one pixel block 200 and the multiple pixels 201 included in the other pixel block 200 are connected in common by different signal lines 202. The multiple pixels 201 in the n-th column of one pixel block 200 are connected in common by a signal line 202 that is different from the common signal line 202 to which the multiple pixels 201 in the n-th column of the other pixel block 200 are connected.

[0022] The pixel blocks 200 are arranged corresponding to the control blocks 400A and 400B (see FIGS. 4 and 17) described later. That is, one pixel block 200 is arranged for one control block 400A and 400B.

[0023] Furthermore, multiple pixel blocks 200 may be arranged for one control block 400A, 400B. Even when multiple pixel blocks 200 are arranged for one control block 400A, 400B, different exposure times may be set for the respective pixel blocks 200. When two pixel blocks 200 arranged in the column direction are arranged for one control block, the control blocks 400A, 400B control 2m×n pixels 201. Specifically, for example, the control blocks 400A, 400B control 32×16 pixels 201. The number of pixels 201 corresponding to the control blocks 400A, 400B is not limited to this.

[0024] 3 is a circuit diagram showing an example of the circuit configuration of a pixel 201. The pixel 201 includes a photoelectric conversion unit 300 and a readout unit 310. The readout unit 310 has a transfer unit 301, a discharge unit 302, an FD (floating diffusion) 303, a reset unit 304, and a pixel output unit 305, and reads out a pixel signal based on the charge converted by the photoelectric conversion unit 300 to a signal line 202. The pixel output unit 305 has an amplifier unit 351 and a selection unit 352. The transfer unit 301, the discharge unit 302, the FD 303, the reset unit 304, the amplifier unit 351, and the selection unit 352 are collectively referred to as the readout unit 310. The readout unit 310 will be described as an N-channel FET, but the type of transistor is not limited to this.

[0025] The photoelectric conversion unit 300 has a photoelectric conversion function of converting light into electric charges. The photoelectric conversion unit 300 accumulates the electric charges generated by photoelectric conversion. The photoelectric conversion unit 300 is configured by, for example, a photodiode.

[0026] The transfer unit 301 transfers the charges in the photoelectric conversion unit 300 to the FD 303. The transfer unit 301 controls the electrical connection between the photoelectric conversion unit 300 and the FD 303. The transfer unit 301 is configured, for example, by a transistor. The transfer unit 301 may also be an element that has at least a gate terminal and configures part of a transistor with a part of the photoelectric conversion unit 300 as the source terminal and a part of the FD 303 as the drain terminal. The gate terminal of the transfer unit 301 is connected to a transfer control line 311 for inputting a transfer control signal φTX. The transfer control line 311 will be described later.

[0027] The discharge unit 302 discharges the charge accumulated in the photoelectric conversion unit 300 to a power supply wiring to which a power supply voltage VDD is supplied. The discharge unit 302 controls the connection between the photoelectric conversion unit 300 and the power supply wiring. The discharge unit 302 is configured, for example, by a transistor. The discharge unit 302 may also be an element that has at least a gate terminal and constitutes part of a transistor in which a part of the photoelectric conversion unit 300 serves as a source terminal and a part of a diffusion region connected to the power supply wiring serves as a drain terminal. The gate terminal of the discharge unit 302 is connected to a discharge control line 312 for inputting a discharge control signal φPDRST. Note that although the discharge unit 302 has been described as discharging the charge of the photoelectric conversion unit 300 to a power supply wiring to which a power supply voltage VDD is supplied, the discharge unit 302 may also be discharged to a power supply wiring to which a power supply voltage different from the power supply voltage VDD is supplied.

[0028] The FD 303 receives charges transferred from the photoelectric conversion unit 300 by the transfer unit 301. The FD 303 accumulates the charges transferred from the photoelectric conversion unit 300.

[0029] The reset unit 304 discharges the charge accumulated in the FD 303 to the power supply wiring to which the power supply voltage VDD is supplied. The reset unit 304 resets the potential of the FD 303 to the power supply voltage VDD, which is the reference potential. The reset unit 304 controls the electrical connection between the FD 303 and the power supply wiring. The reset unit 304 is configured, for example, by a transistor. The reset unit 304 may also be an element that has at least a gate terminal and configures part of a transistor with a part of the FD 303 as the source terminal and a part of a diffusion region connected to the power supply wiring as the drain terminal. The gate terminal of the reset unit 304 is connected to a reset control line 313 for inputting a reset control signal φRST. The reset control line 313 will be described later.

[0030] The pixel output unit 305 outputs a pixel signal based on the potential of the FD 303 to the signal line 202. The pixel output unit 305 has an amplifier unit 351 and a selection unit 352. The amplifier unit 351 is configured with a transistor. The amplifier unit 351 has a gate terminal connected to the FD 303, a drain terminal connected to a power supply line to which a power supply voltage VDD is supplied, and a source terminal connected to the drain terminal of the selection unit 352.

[0031] The selection unit 352 controls the electrical connection between the pixel 201 and the signal line 202. When the selection unit 352 electrically connects the pixel 201 and the signal line 202, a pixel signal is output from the pixel 201 to the signal line 202. The selection unit 352 is configured with a transistor. The selection unit 352 may also be an element that has at least a gate terminal and configures part of a transistor with a part of the amplifier unit 351 as a source terminal and a part of a diffusion region connected to the signal line 202 as a drain terminal. The gate terminal of the selection unit 352 is connected to a selection control line 314 that spans multiple pixel blocks 200 and is used to input a selection control signal φSEL. The source terminal of the selection unit 352 is connected to the load current source 306.

[0032] The load current source 306 is connected to the signal line 202 and supplies a current for reading out pixel signals from the pixels 201. This stabilizes the operation of the amplifier unit 351. The load current source 306 is also connected to the signal line 202. The load current source 306 may be provided on the first semiconductor substrate 110 or on the second semiconductor substrate 120.

[0033] Furthermore, the FD 303 and the pixel output unit 305 may be shared with other pixels 201. For example, the FD 303 and the pixel output unit 305 may be shared by a plurality of pixels 201 arranged side by side in the row or column direction. Furthermore, the pixel 201 may be configured with a plurality of photoelectric conversion units 300 and transfer units 301.

[0034] FIG. 4 is an explanatory diagram showing an example of a specific configuration of the control circuit unit 102. The control circuit unit 102 has multiple control blocks 400A. The multiple control blocks 400A are arranged in a row and column direction in the control circuit unit 102. Specifically, the control circuit unit 102 has M×N control blocks 400A. When one pixel block 200 is arranged for one control block 400A, the control circuit unit 102 has the control block 400A immediately below the pixel block 200. One pixel block 200 and one control block 400A have substantially the same shape and size. Furthermore, when multiple pixel blocks 200 arranged in a column direction are arranged for one control block 400A, the control circuit unit 102 has one control block 400A immediately below the multiple pixel blocks 200 arranged in a column direction.

[0035] The control block 400A is provided corresponding to the pixel block 200. As an example of the correspondence between the control block and the pixel block, for example, the control block 400A is located directly below the pixel block 200 in the direction in which the first semiconductor substrate 110 and the second semiconductor substrate 120 are stacked (stacking direction). The control block 400A is electrically connected to the pixel block 200 via a signal line 202, a transfer control line 311, and a discharge control line 312. Specifically, the control block 400A located directly below the pixel block 200 in the stacking direction is electrically connected to the pixel block 200 directly above it in the stacking direction (hereinafter referred to as the corresponding pixel block 200) via local control lines such as the transfer control line 311 and the discharge control line 312. The control block 400A receives pixel signals output from the pixels 201 of the corresponding pixel block 200 via the signal line 202.

[0036] The control block 400A controls the driving of the corresponding pixel block 200. For example, the control block 400A controls the exposure time of the pixels 201 included in the corresponding pixel block 200. The control block 400A also has a signal processing unit 402 that processes input signals, and processes pixel signals output from the pixels 201 included in the corresponding pixel block 200. For example, the control block 400A converts analog pixel signals output from the pixels 201 included in the corresponding pixel block 200 into digital signals.

[0037] The control block 400A has a pixel control unit 401 and a signal processing unit 402. The pixel control unit 401 has an autonomous exposure processing unit 411, an exposure control unit 412, and a pixel driving unit 413, and controls the pixels 201 of the pixel unit 101. The signal processing unit 402 has a signal input unit 421, a signal conversion unit 422, and a signal output unit 423, and converts analog pixel signals from the pixel unit 101 into digital signals and transfers them to the pixel control unit 401 and the data processing unit 103.

[0038] The autonomous exposure processor 411 is a circuit that calculates the exposure time of the pixels 201 included in the corresponding pixel block 200 based on the pixel signals converted into digital signals by the signal processor 402. Details of the autonomous exposure processor 411 will be described later.

[0039] The exposure control unit 412 is a circuit that controls the exposure of the pixels 201 included in the corresponding pixel block 200 based on the exposure time calculated by the autonomous exposure processing unit 411. Specifically, the exposure control unit 412 generates a control signal for controlling the exposure time (charge accumulation time of the photoelectric conversion unit 300) of the pixels 201 included in the corresponding pixel block 200. For example, the exposure control unit 412 adjusts the start timing or end timing of exposure of the pixels 201 included in the corresponding pixel block 200 to control the exposure time for each pixel block 200. The exposure control unit 412 is provided in the control block 400A, extending in the row direction.

[0040] The pixel driving unit 413 outputs the control signal generated by the exposure control unit 412 to the pixels 201 included in the corresponding pixel block 200. The pixel driving unit 413 is a driving circuit that drives the pixels 201 included in the corresponding pixel block 200. The pixel driving unit 413 drives the pixels 201 in a pixel row selected from the pixels 201 included in the corresponding pixel block 200. The pixel driving unit 413 is provided extending in the column direction. As a result, the pixel driving unit 413 is disposed at a position corresponding to the m pixels 201 arranged in the column direction. In the control block 400A, the autonomous exposure processing unit 411, exposure control unit 412, and pixel driving unit 413 are arranged in an L shape, with the pixel driving unit 413 extending in the column direction and the autonomous exposure processing unit 411 and exposure control unit 412 extending in the row direction.

[0041] The signal input unit 421 receives pixel signals output from pixels 201 included in the corresponding pixel block 200. The signal input unit 421 outputs the received pixel signals to the signal conversion unit 422. The signal input unit 421 may be provided for each n pixels 201 arranged in the row direction in the corresponding pixel block 200. The signal input unit 421 may include a processing circuit that performs signal processing such as noise reduction on the pixel signals output from the first semiconductor substrate 110. The signal input unit 421 may also include a voltage adjustment circuit that adjusts the voltage of the signal line 202 connected to the pixel 201 included in the corresponding pixel block 200 so that it does not fall below a predetermined value. When the load current source 306 is disposed on the second semiconductor substrate, it may be disposed in the signal input unit 421 included in the corresponding control block 400A.

[0042] The signal conversion unit 422 converts the pixel signals output from the signal input unit 421 into digital signals. The signal conversion unit 422 sequentially converts into digital signals the pixel signals output from m pixels 201 arranged in the column direction in the corresponding pixel block 200. The signal conversion unit 422 converts into parallel digital signals the pixel signals output from the pixels 201 arranged in n columns in the row direction in the corresponding pixel block 200.

[0043] The signal output unit 423 stores the pixel signals converted into digital signals by the signal conversion unit 422. The signal output unit 423 may have a latch circuit for storing the digital signals. The signal output unit 423 is arranged between the signal conversion unit 422 and the autonomous exposure processing unit 411 in the column direction. The signal output unit 423 outputs the pixel signals converted into digital signals to the outside of the control circuit unit 102. The signal output unit 423 is provided in the control block 400A and extends in the row direction. The signal output unit 423 is arranged between the signal conversion unit 422 and the autonomous exposure processing unit 411 in the column direction.

[0044] 5 is an explanatory diagram showing an example of the internal configuration of the control block 400A. The signal conversion unit 422 includes n comparators 501 and n storage units 502. The exposure control unit 412 includes a pixel block control unit 503 and a level shift unit 504. A combination of one comparator 501 and a storage unit 502 connected to that comparator 501 forms one ADC (Analog-to-Digital Converter) 500.

[0045] The comparators 501 are provided in the control block 400A, extending in the column direction. n comparators 501 are arranged side by side in the row direction. A comparator 501 is arranged for every m pixels 201 arranged in the column direction in the corresponding pixel block 200. The comparators 501 sequentially read out pixel signals from the m pixels 201 arranged in the column direction in the corresponding pixel block 200 and convert them into digital signals.

[0046] The storage unit 502 stores pixel signals converted into digital signals using the comparator 501. The storage unit 502 is provided on the negative side of the comparator 501 in the Y-axis direction in the signal conversion unit 422. For example, the storage unit 502 has a latch circuit. The storage unit 502 may have a memory configured with an SRAM or the like.

[0047] The pixel block control unit 503 controls the operation of the transfer unit 301 and discharge unit 302 of the pixels 201 included in the corresponding pixel block 200. Specifically, the pixel block control unit 503 outputs a transfer control signal φTX for controlling the transfer unit 301 of the pixels 201 included in the corresponding pixel block 200, and a discharge control signal φPDRST for controlling the discharge unit 302 of the pixels 201 included in the corresponding pixel block 200. The pixel block control unit 503 is provided extending in the row direction in the control block 400A. The pixel block control unit 503 is arranged between the level shift unit 504 and the autonomous exposure processing unit 411 in the column direction.

[0048] The level shift unit 504 adjusts the voltage level of the control signal output from the pixel block control unit 503. Specifically, the level shift unit 504 boosts the voltage level of the transfer control signal φTX output from the pixel block control unit 503. The level shift unit 504 also boosts the voltage level of the discharge control signal φPDRST output from the pixel block control unit 503.

[0049] The transfer unit 301 receives the transfer control signal φTX boosted by the pixel block control unit 503 via a transfer control line 311. The discharge unit 302 receives the discharge control signal φPDRST boosted by the pixel block control unit 503 via a discharge control line 312.

[0050] In this way, the pixel block control unit 503 boosts the transfer control signal φTX and the discharge control signal φPDRST to the voltage levels used in the transfer unit 301 and the discharge unit 302 of the readout unit 310 of the pixel 201. The level shift unit 504 is provided in the control block 400A, extending in the row direction.

[0051] The level shift unit 504 is provided closer to the outer periphery of the control block 400A than the pixel block control unit 503. The end of the level shift unit 504 on the positive side in the X-axis direction and the end on the negative side in the Y-axis direction are located at the outermost sides of the control block 400A. The end of the level shift unit 504 on the negative side in the X-axis direction is in contact with the pixel driving unit 413.

[0052] The level shift unit 504 and pixel drive unit 413 handle the level-shifted signal. On the other hand, the autonomous exposure processing unit 411, pixel block control unit 503, level shift unit 504, and pixel drive unit 413 handle the pixel signal output from the first semiconductor substrate 110.

[0053] Here, each component of the control block 400A is formed in a well region provided in the second semiconductor substrate 120. The well regions are provided separately according to the voltage level of the signals to be handled. The well regions are separated depending on whether the power supply used is a digital power supply or an analog power supply. Furthermore, even if the signal conversion unit 422 uses the same analog power supply, it may be separated from an area that uses another analog power supply from the standpoint of noise. Separating the well regions requires well isolation regions spaced apart according to the manufacturing process rules.

[0054] In the control block 400A, the well regions for forming the level shift unit 504 and the pixel driving unit 413 are separated from other well regions. For example, the level shift unit 504 and the pixel driving unit 413 can be provided in an L-shape, thereby sharing the well regions of the level shift unit 504 and the pixel driving unit 413. Sharing the well region makes it possible to omit a well isolation region, thereby improving layout efficiency.

[0055] The L-shaped pixel control unit 401 forms part of the outer periphery of the control block 400 A. This allows the well region to be shared with other control blocks 400 A adjacent in the row and column directions.

[0056] 6 is an explanatory diagram showing an example of signal transmission between the first semiconductor substrate 110 and the second semiconductor substrate 120 in the image sensor 100A. The global driving unit 600 is provided in the peripheral circuit unit 121 arranged on either side of the control circuit unit 102.

[0057] The transfer control line 311a and the discharge control line 312a are each connected to the pixels 201 included in the pixel block 200a. The transfer control line 311a is connected to the gate terminal of the transfer unit 301 of the pixel 201 included in the pixel block 200a, and the discharge control line 312a is connected to the gate terminal of the discharge unit 302 of the pixel 201 included in the pixel block 200a. The transfer control line 311a supplies the transfer control signal φTX output from the control block 400Aa to the transfer unit 301 of the pixel 201 included in the pixel block 200a. The discharge control line 312a supplies the discharge control signal φPDRST output from the control block 400Aa to the discharge unit 302 of the pixel 201 included in the pixel block 200a.

[0058] Similarly, the transfer control line 311b and the discharge control line 312b are each connected to the pixel 201 included in the pixel block 200b. The transfer control line 311b is connected to the gate terminal of the transfer unit 301 of the pixel 201 included in the pixel block 200b, and the discharge control line 312b is connected to the gate terminal of the discharge unit 302 of the pixel 201 included in the pixel block 200b. The transfer control line 311b supplies the transfer control signal φTX output from the control block 400Ab to the transfer unit 301 of the pixel 201 included in the pixel block 200b. The discharge control line 312b supplies the discharge control signal φPDRST output from the control block 400Ab to the discharge unit 302 of the pixel 201 included in the pixel block 200b.

[0059] When there is no need to distinguish between the transfer control lines 311a and 311b, they are referred to as transfer control lines 311. When there is no need to distinguish between the discharge control lines 312a and 312b, they are referred to as discharge control lines 312.

[0060] The transfer control line 311 and the discharge control line 312 are examples of local control lines connected to the first pixel of the pixel block 200. The transfer control line 311 and the discharge control line 312 are commonly connected to n pixels 201 arranged in the row direction in the pixel block 200.

[0061] The global driver 600 outputs a reset control signal φRST, a selection control signal φSEL, and a transfer selection control signal φTXSEL. The global driver 600 is connected to a reset control line 313, a selection control line 314, and a transfer selection control line 603 that output control signals to each pixel block 200.

[0062] The global driver 600 supplies a reset control signal φRST and a selection control signal φSEL to the plurality of pixel blocks 200 via a reset control line 313 and a selection control line 314. The global driver 600 supplies a transfer selection control signal φTXSEL to the plurality of control blocks 400A via a transfer selection control line 603.

[0063] The transfer selection control signal φTXSEL is supplied from the global driver 600 to the control block 400A to control the exposure time for each pixel block 200. The control block 400A, to which the transfer selection control signal φTXSEL is supplied, outputs the transfer selection control signal φTXSEL to the corresponding pixel block 200. The control block 400A determines whether to input the transfer selection control signal φTXSEL to the pixel 201 as the transfer control signal φTX or the discharge control signal φPDRST. As a result, input of the transfer control signal φTX or the discharge control signal φPDRST to the pixel 201 is skipped.

[0064] For example, when the transfer control signal φTX determines the end time of exposure, the control block 400A extends the exposure time by skipping the transfer control signal φTX. Also, when the transfer control signal φTX determines the start time of exposure, the control block 400A can shorten the exposure time by skipping the transfer control signal φTX. In this way, the exposure time of the pixel block 200 can be adjusted by the transfer selection control signal φTXSEL. The same applies when the discharge control signal φPDRST determines the start or end time of exposure.

[0065] The reset control line 313, the selection control line 314, and the transfer selection control line 603 are provided in common to multiple pixel blocks 200. The reset control line 313, the selection control line 314, and the transfer selection control line 603 are wired so as to cross the first semiconductor substrate 110 in the row direction. The reset control line 313, the selection control line 314, and the transfer selection control line 603 may also be wired so as to cross the first semiconductor substrate 110 in the column direction.

[0066] For example, the reset control line 313 is connected to the gate terminal of the reset unit 304 of the pixel 201 in the pixel block 200 and supplies the reset control signal φRST. The selection control line 314 is connected to the gate terminal of the selection unit 352 of the pixel 201 in the pixel block 200 and supplies the selection control signal φSEL. The transfer selection control line 603 is connected to each of the multiple control blocks 400A and supplies the transfer selection control signal φTXSEL to the pixel control unit 401.

[0067] Although the global driving unit 600 outputs the transfer selection control signal φTXSEL to the control block 400A from the second semiconductor substrate 120 via the first semiconductor substrate 110, the transfer selection control signal φTXSEL may be output to the control block 400A without passing through the first semiconductor substrate 110. In this case, the transfer selection control line 603 is provided on the second semiconductor substrate 120.

[0068] The bonding portion 610 is provided on the bonding surface where the first semiconductor substrate 110 and the second semiconductor substrate 120 are bonded to each other. The bonding portion 610 aligns the transfer control line 311, the discharge control line 312, and the transfer selection control line 603 between the first semiconductor substrate 110 and the second semiconductor substrate 120. Each of the bonding portions 610 is composed of a pair of conductive bonding pads, and is bonded and electrically connected by applying pressure to the first semiconductor substrate 110 and the second semiconductor substrate 120 or the like.

[0069] Image sensor 100A controls the exposure time for each pixel block 200 by changing the timing of at least one of transfer unit 301 and discharge unit 302 using local control lines such as transfer control line 311 and discharge control line 312. Image sensor 100A can control the exposure time with fewer control lines by combining local control lines such as transfer control line 311 and discharge control line 312 with global control lines such as reset control line 313, selection control line 314, and transfer selection control line 603.

[0070] FIG. 7 is an explanatory diagram showing an example of an XZ cross section of an image sensor 100A according to this embodiment. While FIG. 7 shows a back-illuminated image sensor 100A, the image sensor 100A is not limited to the back-illuminated type. The image sensor 100A includes a microlens layer 700, a color filter layer 702, a first semiconductor substrate 110, a second semiconductor substrate 120, and a third semiconductor substrate 130. As shown in the figure, light from a subject is incident in the direction indicated by the outline arrow (the negative Z-axis direction in the figure). The surface of the first semiconductor substrate 110 on which light is incident (the positive Z-axis side in the figure) may be referred to as the front surface, and the opposite surface (the negative Z-axis side in the figure) may be referred to as the back surface.

[0071] The microlens layer 700 has a plurality of microlenses 701. The plurality of microlenses 701 are stacked on the positive side of the Z axis relative to the color filter layer 702. Light is incident on the microlenses 701. The microlenses 701 focus the incident light onto the photoelectric conversion unit 300. A microlens 701 may be provided for each photoelectric conversion unit 300. The optical axis L of the microlens 701 is aligned with the stacking direction of the first semiconductor substrate 110, the second semiconductor substrate 120, and the third semiconductor substrate 130 (parallel to the Z axis).

[0072] The color filter layer 702 has a plurality of color filters 703 and a passivation film 704. The color filter layer 702 is stacked on the positive side of the Z axis from the first semiconductor layer 711. The color filter 703 is an optical filter that transmits light in a specific wavelength range. The color filter 703 is an optical filter that has specific spectral characteristics. The multiple color filters 703 have multiple optical filters with different spectral characteristics, and transmit light in different wavelength ranges. The multiple color filters 703 are arranged in a specific array (for example, a Bayer array).

[0073] An example of the first semiconductor substrate 110 is a back-illuminated CMOS image sensor. The first semiconductor substrate 110 has a first semiconductor layer 711 and a first wiring layer 712. The first semiconductor layer 711 is provided on the positive side of the Z axis relative to the first wiring layer 712. The first semiconductor layer 711 has a plurality of pixel blocks 200 arranged two-dimensionally in the row and column directions. The first semiconductor layer 711 has a plurality of pixels 201 arranged two-dimensionally in the row and column directions. Each of the plurality of pixels 201 has a plurality of photoelectric conversion units 300 that accumulate charge based on incident light, and a plurality of readout units 310.

[0074] The first wiring layer 712 is provided closer to the second semiconductor substrate 120 (toward the negative side of the Z axis in the drawing) than the first semiconductor layer 711. The first wiring layer 712 has a plurality of wires 713 made of a conductor film (metal film), a plurality of bonding pads 714, and an insulating film (insulating layer).

[0075] The first wiring layer 712 has a plurality of wirings 713 electrically connected to a power supply, a circuit, or the like. In the first semiconductor substrate 110, the wirings 713 are specifically, for example, a power supply wiring to which a predetermined power supply voltage is supplied, a signal line 202 that transmits pixel signals from the first semiconductor substrate 110 (pixels) to the second semiconductor substrate 120, a transfer control line 311 that transmits control signals from the second semiconductor substrate 120 to the first semiconductor substrate 110 (pixels), a discharge control line 312, a reset control line 313, a selection control line 314, and a transfer selection control line 603. The first wiring layer 712 may be multi-layered, and may include passive and active elements.

[0076] The bond pads 714 are provided on the surface (the surface on the negative side of the Z axis) of the first wiring layer 712 and are connected to the wiring 713. As will be described later, the bond pads 714 are also used to assist in connecting layers together. The bond pads 714 are formed of a conductive material such as copper. The bond pads 714 may also be formed of gold, silver, or aluminum. An insulating layer (insulating film) is formed between the multiple wirings 713 and between the multiple bond pads 714.

[0077] The second semiconductor substrate 120 has a second semiconductor layer 721, a second wiring layer 722, and a wiring layer 723. The second wiring layer 722 is provided closer to the first semiconductor substrate 110 than the second semiconductor layer 721 (on the positive side of the Z axis in the drawing). The wiring layer 723 is provided closer to the third semiconductor substrate 130 than the second semiconductor layer 721 (on the negative side of the Z axis in the drawing), and is provided between the second semiconductor layer 721 and the third semiconductor substrate 130. The second semiconductor layer 721 has a control circuit unit 102 and a peripheral circuit unit 121. The control circuit unit 102 has a plurality of control blocks 400A arranged two-dimensionally in the row and column directions.

[0078] Similar to the first semiconductor substrate 110, the second semiconductor substrate 120 has a plurality of wirings 713 provided on the second wiring layer 722, a plurality of bonding pads 714 provided on the second wiring layer 722 and the wiring layer 723, and an insulating film (insulating layer) provided on the second wiring layer 722 and the wiring layer 723.

[0079] The second wiring layer 722 has a plurality of wirings 713 and bonding pads 714 for electrically connecting to a power supply or circuitry, transmitting signals from the pixel unit 101 to the control circuit unit 102, and transmitting signals from the control circuit unit 102 to the pixel unit 101. In the second semiconductor substrate 120, the wirings 713 specifically include, for example, a power supply wiring for supplying a predetermined power supply voltage, a signal line 202 for transmitting pixel signals from the first semiconductor substrate 110 (pixels) to the second semiconductor substrate 120, and a transfer control line 311, a discharge control line 312, a reset control line 313, a selection control line 314, and a transfer selection control line 603 for transmitting control signals from the second semiconductor substrate 120 to the first semiconductor substrate 110 (pixels). The second wiring layer 722 may be multi-layered and may include passive and active elements. The wirings 713 and bonding pads 714 may also be provided in the wiring layer 723.

[0080] The second semiconductor substrate 120 further includes TSVs (through silicon vias) 724 that connect the circuits provided on the front and back surfaces to each other. The TSVs 724 are preferably provided in the peripheral region. The TSVs 724 transmit image data and the like generated by the data processing unit 103 to the first semiconductor substrate 110. The TSVs 724 may also be provided on the first semiconductor substrate 110 and the third semiconductor substrate 130.

[0081] The third semiconductor substrate 130 has a third semiconductor layer 731 in which the data processing unit 103 is provided, and a third wiring layer 732. The third wiring layer 732 is provided between the third semiconductor layer 731 and the second semiconductor substrate 120.

[0082] Similar to the first semiconductor substrate 110, the third semiconductor substrate 130 has wiring 713 and a plurality of bonding pads 714 provided on a third wiring layer 732. The third wiring layer 732 has the plurality of wirings 713 and bonding pads 714 for electrical connection to a power supply, a circuit, etc., for transmitting signals from the control circuit unit 102 to the data processing unit 103, and for transmitting signals from the data processing unit 103 to the control circuit unit 102 of the second semiconductor substrate 120.

[0083] The first semiconductor substrate 110, the second semiconductor substrate 120, and the third semiconductor substrate 130 are stacked by electrical connection between the bonding pads 714 provided on each layer and bonding between the wiring layers (insulating layers) of each layer.

[0084] When the first semiconductor substrate 110 and the second semiconductor substrate 120 are stacked, an interface 720 is formed between the negative surface of the first wiring layer 712 along the Z axis and the positive surface of the second wiring layer 722 along the Z axis. Similarly, when the second semiconductor substrate 120 and the third semiconductor substrate 130 are stacked, an interface 730 is formed between the negative surface of the wiring layer 723 along the Z axis and the positive surface of the third wiring layer 732 along the Z axis. A plurality of bonding pads 714 are arranged on the interface 720 and the interface 730. Specifically, corresponding bonding pads 714 are aligned, and the two layers are stacked, thereby electrically connecting the aligned bonding portions.

[0085] The first semiconductor substrate 110, the second semiconductor substrate 120, and the third semiconductor substrate 130 may be stacked in the form of a wafer before being made into chips, and then formed (singled) by dicing the stacked wafers, or may be formed by dicing each of the first semiconductor substrate 110, the second semiconductor substrate 120, and the third semiconductor substrate 130 wafers and then stacking them.

[0086] FIG. 8 is a timing chart showing an example 1 of imaging operation of the image sensor 100A. FIG. 8 shows an example of imaging operation in which the drive of the image sensor 100A is controlled by the transfer control signal φTX, the discharge control signal φPDRST, the reset control signal φRST, and the selection control signal φSEL. In FIG. 8, the discharge control signal φPDRST is locally controlled, and the transfer control signal φTX, the reset control signal φRST, and the selection control signal φSEL are globally controlled. Note that the suffixes at the end of each signal on the left side indicate <1> , <2> ,..., <m>indicates the row number of the pixel 201 within the pixel block.

[0087] The discharge control signal φPDRST controls the timing at which exposure starts. The exposure start timing corresponds to the falling edge of the discharge control signal φPDRST (for example, time T1). That is, before the exposure start time T1, the discharge control signal φPDRST turns on the discharge unit 302 to discharge the charge accumulated in the photoelectric conversion unit 300, and exposure starts at the falling edge of the discharge control signal φPDRST. Because the discharge control signal φPDRST is locally controlled, the exposure time can be adjusted for each pixel block 200.

[0088] The transfer control signal φTX controls the timing to end exposure. At time T3, the transfer control signal φTX turns on the transfer unit 301, thereby transferring the charge accumulated in the photoelectric conversion unit 300 to the FD 303. The timing to end exposure corresponds to the falling edge of the transfer control signal φTX (for example, time T4). Because the transfer control signal φTX is a globally controlled signal, the timing to end exposure is the same for each pixel block 200.

[0089] The reset control signal φRST controls the timing of discharging the charge accumulated in the FD 303. At time T2, the reset control signal φRST turns on the reset unit 304, thereby discharging the charge in the FD 303. By discharging the charge in the FD 303 before the end of exposure, the influence of the charge remaining in the FD 303 when the charge is transferred from the photoelectric conversion unit 300 can be suppressed.

[0090] The selection control signal φSEL is a signal for selecting an arbitrary pixel 201. The selection control signal φSEL controls the on / off of the selection unit 352. At time T2, the selection control signal φSEL is set to high. At time T3, the pixel 201 for which the selection control signal φSEL is set to high outputs a pixel signal to the signal line 202 in response to the transfer control signal φTX being turned on. On the other hand, the pixel 201 for which the selection control signal φSEL is not set to high does not output a pixel signal.

[0091] The image sensor 100A locally controls the discharge control signal φPDRST, thereby changing the exposure start timing for each pixel block 200 and controlling the exposure time for each pixel block 200. The image sensor 100A may also locally control the transfer control signal φTX to control the exposure end timing for each pixel block 200. The image sensor 100A may also locally control both the transfer control signal φTX and the discharge control signal φPDRST to control both the exposure start timing and end timing for each pixel block 200.

[0092] Fig. 9 is a timing chart showing a second imaging operation example of the image sensor 100A. Fig. 9 shows an imaging operation example in which the drive of the image sensor 100A is controlled by a transfer control signal φTX, a reset control signal φRST, and a selection control signal φSEL. The image sensor 100A differs from the case of Fig. 8 in that the timing of the start of exposure is controlled by a transfer control signal φTX. The differences from Fig. 8 will be particularly described.

[0093] The transfer control signal φTX controls the timing of the start and end of exposure. In frame (n), exposure starts at time T5 and ends at time T7.

[0094] At exposure start time T5, the transfer control signal φTX falls, thereby starting exposure. That is, before exposure start time T5, the transfer control signal φTX turns on the transfer unit 301 while the reset control signal φRST is on, thereby discharging the charge accumulated in the photoelectric conversion unit 300, and exposure starts at the falling edge of the transfer control signal φTX. Because the transfer control signal φTX is a locally controlled signal, the timing at which exposure starts in each pixel block 200 can be changed. However, the timing at which exposure starts in each pixel block 200 may also be synchronized.

[0095] Furthermore, at exposure end time T7, the transfer control signal φTX falls, thereby ending the exposure. That is, before exposure end time T7, the transfer control signal φTX turns on the transfer unit 301 while the reset control signal φRST is off, thereby transferring the charge accumulated in the photoelectric conversion unit 300 to the FD 303, and exposure ends at the falling edge of the transfer control signal φTX. Because the transfer control signal φTX is a locally controlled signal, the timing at which exposure ends can be changed for each pixel block 200. However, the timing at which exposure ends can also be synchronized for each pixel block 200.

[0096] The selection control signal φSEL is a signal for selecting an arbitrary pixel 201. At time T6, the pixel 201, for which the selection control signal φSEL is set high, outputs a pixel signal to the signal line 202.

[0097] The reset control signal φRST controls the timing of discharging the charge accumulated in the FD303. The reset control signal φRST may be a globally controlled signal. Since the reset control signal φRST is always on except at the timing of readout, no charge is accumulated in the FD303. On the other hand, by turning off the reset control signal φRST and turning on the transfer control signal φTX at the timing of readout, charge is transferred from the photoelectric conversion unit 300 to the FD303. The reset control signal φRST has the same switching timing as the readout, so it can be made common to the pulse of the selection control signal φSEL.

[0098] By locally controlling the transfer control signal φTX, the image sensor 100A can change the timing of the start or end of exposure for each pixel block 200, thereby controlling the exposure time for each pixel block 200. Furthermore, the image sensor 100A uses a common pulse for the reset control signal φRST and the selection control signal φSEL, which further simplifies the control circuit.

[0099] Fig. 10 is a timing chart showing an imaging operation of an image sensor according to a comparative example, in which the drive of the image sensor is controlled by the transfer control signal φTX, the reset control signal φRST, and the selection control signal φSEL, and the exposure time is not controlled for each pixel block 200.

[0100] In the comparative example, the start of exposure is controlled by the transfer control signal φTX and the reset control signal φRST. The exposure start timing is the timing (time t1) of the falling edges of the transfer control signal φTX and the reset control signal φRST. The exposure end timing is the timing (time t2) of the falling edge of the transfer control signal φTX. In the comparative example, the exposure start timing and end timing are controlled globally, and the exposure time is not controlled for each pixel block 200.

[0101] 11 is an explanatory diagram showing an example of a subject captured by the image sensor 100 A. In FIG. 11, the image sensor 100 A controls the exposure time for each pixel block 200 in a situation where the afternoon sun is shining outside a tunnel.

[0102] Areas 1 to 5 are five areas divided according to brightness. Areas 1 to 5 are numbered in order of brightness. Area 1 is the brightest area where the setting sun is directly visible. Area 2 is the area corresponding to the tunnel exit and is darker than Area 1. Area 3 is the area where the setting sun is reflected inside the tunnel and is darker than Area 2. Area 4 is the area inside the tunnel where the setting sun shines in from the exit and is darker than Area 3. Area 5 is the darkest area inside the tunnel where the setting sun does not shine in from the exit.

[0103] Image sensor 100A controls the exposure time for each pixel block 200 according to the brightness of each region. Image sensor 100A controls the exposure time so that the brighter the pixel block 200, the shorter the exposure time. The exposure time for region 1 is set to the shortest, and the exposure time for region 5 is set to the longest. For example, the exposure times for regions 1 to 5 are 1 / 19200 s, 1 / 1920 s, 1 / 960 s, 1 / 240 s, and 1 / 120 s.

[0104] Fig. 12 is a timing chart showing the exposure time for each of the regions 1 to 5 shown in Fig. 11. In Fig. 12, the image sensor 100A controls the exposure time for each of the pixel blocks 200 in the regions 1 to 5 shown in Fig. 11. The section from time T11 to time T19 corresponds to the video frame rate.

[0105] In region 1, the control block 400A controls driving so that the exposure time in the pixel block 200 is a predetermined exposure time ET1. The control block 400A controls the start of exposure with a discharge control signal φPDRST and the end of exposure with a transfer control signal φTX. In region 1, exposure ends at each of times T12 to T19.

[0106] In region 2, the control block 400A controls driving so that the exposure time in the pixel block 200 is exposure time ET2, which is longer than ET1. The control block 400A makes the exposure start time for region 2 earlier than region 1 and the exposure end time coincide with region 1. Therefore, in region 2, exposure ends at each of times T12 to T19. The exposure time ET2 for region 2 is shorter than the period of the sensor rate.

[0107] In region 3, the control block 400A controls driving so that the exposure time in the pixel block 200 is exposure time ET3, which is longer than ET2. The control block 400A makes the exposure start time for region 3 earlier than region 2 and the exposure end time coincide with region 2. Therefore, in region 3, exposure ends at each of times T12 to T19. The exposure time ET3 for region 3 is set to be the same as the period of the sensor rate.

[0108] In region 4, the control block 400A controls driving so that the exposure time in the pixel block 200 is an exposure time ET4 that is longer than ET3. The control block 400A sets the exposure start time for region 4 to the same time as region 3, but skips the end time of the exposure using the transfer selection control signal φTXSEL. The control block 400A skips three times using the transfer selection control signal φTXSEL, thereby achieving an exposure time four times longer than that of region 3. In region 4, the transfer selection control signal φTXSEL is supplied at each of times T12 to T14.

[0109] In region 5, the control block 400A controls driving so that the exposure time in the pixel block 200 is an exposure time ET5 that is longer than ET4. The control block 400A sets the same exposure start time for region 5 as for region 4, but increases the number of times to skip the end time of the exposure using the transfer selection control signal φTXSEL. The control block 400A skips seven times using the transfer selection control signal φTXSEL, thereby achieving an exposure time that is twice that of region 4. The exposure time ET5 for region 5 is set to be the same as the period of the video frame rate. In region 5, the transfer selection control signal φTXSEL is supplied at each of times T12 to T18.

[0110] The image sensor 100A achieves short-time exposure by shortening the interval between the transfer control signal φTX and the discharge control signal φPDRST. The image sensor 100 also achieves long-time exposure by skipping the control of the transfer control signal φTX using the transfer selection control signal φTXSEL. This allows for an expanded dynamic range.

[0111] 13 is a plan view showing an example layout of a plurality of control blocks 400A. The plurality of control blocks 400A are arranged in such a way that adjacent control blocks 400A are inverted. FIG. 13 illustrates 12 control blocks 400A out of the plurality of control blocks 400A provided in the control circuit section 102.

[0112] The inverted arrangement means that the areas in which the components of the control block 400A (for example, the exposure control unit 412, the pixel driving unit 413, the signal input unit 421, the signal conversion unit 422, and the signal output unit 423) are formed are arranged in a mirror-inverted arrangement (arranged in line symmetry) around the boundary between the control blocks 400A. The circuits of the components of the control block 400A do not have to be arranged in an inverted arrangement. Furthermore, the readout order of the pixels in the control block 400A is not limited to being inverted.

[0113] For example, when multiple control blocks 400A arranged adjacent to each other in the row direction are arranged in an inverted manner, the components of the control blocks 400A are arranged in an inverted manner in the row direction, so that the pixel driving units 413 of the control blocks 400A are arranged adjacent to each other at the boundary between the two control blocks 400A. This allows multiple pixel driving units 413 arranged adjacent to each other in the row direction to be laid out as a single pixel driving unit 413, thereby improving the layout efficiency of the control blocks 400A.

[0114] Similarly, when adjacent control blocks 400A in the column direction are arranged in an inverted manner, the components of the control blocks 400A are arranged in an inverted manner in the column direction, so that identical components are arranged adjacent to each other at the boundary between the two control blocks 400A. This allows the signal input units 421 adjacent to each other in the column direction to be laid out as a single signal input unit 421, improving the layout efficiency of the control blocks 400A.

[0115] The control blocks 400A are arranged in a mirrored arrangement relative to the adjacent control blocks 400A. All the control blocks 400A are arranged in a mirrored arrangement in the row and column directions, but they may be arranged in a mirrored arrangement in either the row or column directions. For example, the signal conversion unit 422 of a control block 400A is arranged in a mirrored arrangement relative to the signal conversion unit 422 of the control block 400A adjacent to it in the row direction. Furthermore, the signal conversion unit 422 of a control block 400A is also arranged in a mirrored arrangement relative to the signal conversion unit 422 of the control block 400A adjacent to it in the column direction.

[0116] The control block 400Aa and the control block 400Ab are arranged next to each other in the row direction. The control block 400Aa is arranged in an inverted manner relative to the control block 400Ab. The level shift unit 504 of the control block 400Aa is provided in the same well region as the level shift unit 504 of the control block 400Ab. Similarly, the pixel block control unit 503, the memory unit 502, and the signal output unit 423 are provided in the same well region in the control block 400Aa and the control block 400Ab.

[0117] The control block 400Ab and the control block 400Ac are arranged next to each other in the row direction. The control block 400Ab is arranged in an inverted manner relative to the control block 400Ac. The pixel driving unit 413 of the control block 400Ab is provided in the same well region as the pixel driving unit 413 of the control block 400Ac. The well region of the pixel driving unit 413 may also be shared with the well region of the level shift unit 504.

[0118] The control block 400Aa and the control block 400Ad are arranged next to each other in the column direction. The control block 400Aa is arranged in an inverted manner relative to the control block 400Ad. The pixel driving unit 413 of the control block 400Aa is provided in the same well region as the pixel driving unit 413 of the control block 400Ad. Furthermore, the signal conversion unit 422 of the control block 400Aa is provided in the same well region as the signal conversion unit 422 of the control block 400Ad.

[0119] The control block 400Ad and the control block 400Ae are arranged adjacent to each other in the column direction. The control block 400Ad is arranged in an inverted manner relative to the control block 400Ae. The pixel driving unit 413 and the level shifting unit 504 of the control block 400Ad are arranged in the same well region as the pixel driving unit 413 and the level shifting unit 504 of the control block 400Ae.

[0120] By arranging the control blocks 400A in an inverted manner, the image sensor 100 can improve the layout efficiency even when performing parallel signal processing for each control block 400A. By arranging the control blocks 400A in an inverted manner in the XY plane, the image sensor 100A can share well regions with adjacent control blocks 400A. This reduces the number of times well regions need to be switched, improving area efficiency.

[0121] 14 is a circuit diagram showing another example of the circuit configuration of pixel 201. In pixel 201, the same components as in FIG. 3 are assigned the same reference numerals, and descriptions thereof will be omitted. In pixel 201, the discharge unit 302 provided in pixel 201 is not provided. When discharging the charges accumulated in the photoelectric conversion unit 300 to the power supply wiring to which the power supply voltage VDD is supplied, a transfer control signal φTX is input to the gate terminal of the transfer unit 301, and a reset control signal φRST is input to the gate terminal of the reset unit 304.

[0122] Fig. 15 is a timing chart showing an imaging operation example 3 of the image sensor 100A. Fig. 15 shows an imaging operation example in which the pixel 201 shown in Fig. 14 is used to control the driving of the image sensor 100A by the transfer control signal φTX, the reset control signal φRST, and the selection control signal φSEL. The image sensor 100A differs from the case of Fig. 12 in that the timing of the start of exposure is controlled by the transfer control signal φTX. The differences from Fig. 12 will be particularly described.

[0123] The transfer control signal φTX controls the timing of the start and end of exposure. In frame (n), exposure starts at time T5 and ends at time T7.

[0124] At exposure start time T5, the transfer control signal φTX falls, thereby starting exposure. That is, before exposure start time T5, the transfer control signal φTX turns on the transfer unit 301 while the reset control signal φRST is on, thereby discharging the charge accumulated in the photoelectric conversion unit 300, and exposure starts at the falling edge of the transfer control signal φTX. Because the transfer control signal φTX is a locally controlled signal, the timing at which exposure starts in each pixel block 200 can also be changed.

[0125] Furthermore, at exposure end time T7, the transfer control signal φTX falls, thereby ending the exposure. That is, before exposure end time T7, the transfer control signal φTX turns on the transfer unit 301 while the reset control signal φRST is off, thereby transferring the charge accumulated in the photoelectric conversion unit 300 to the FD 303, and exposure ends at the falling edge of the transfer control signal φTX. Because the transfer control signal φTX is a locally controlled signal, the timing at which exposure ends can also be changed for each pixel block 200.

[0126] The selection control signal φSEL is a signal for selecting an arbitrary pixel 201. At time T6, the pixel 201, for which the selection control signal φSEL is set high, outputs a pixel signal to the signal line 202.

[0127] The reset control signal φRST controls the timing of discharging the charge accumulated in the FD303. The reset control signal φRST may be a globally controlled signal. Since the reset control signal φRST is always on except at the timing of readout, no charge is accumulated in the FD303. On the other hand, by turning off the reset control signal φRST and turning on the transfer control signal φTX at the timing of readout, charge is transferred from the photoelectric conversion unit 300 to the FD303. The reset control signal φRST has the same switching timing as the readout, so it can be made common to the pulse of the selection control signal φSEL.

[0128] 1 to 15, exposure is performed in units of pixel blocks 200 each consisting of a plurality of pixels 201, and pixel signals from the pixel blocks 200 are read out in units of control blocks 400A corresponding to the pixel blocks 200, converting analog signals into digital signals. Furthermore, the image sensor 100A reads out pixel signals in parallel for each pixel block 200 using the control blocks 400A provided for each pixel block 200. Therefore, the image sensor 100A can set the exposure time for each pixel block 200 according to the intensity of incident light, thereby expanding the dynamic range.

[0129] Next, the configuration of an image sensor 100B that performs exposure in units of pixel blocks 200, sequentially reads out pixel signals for each pixel row, and performs AD conversion for each pixel column will be described with reference to FIGS.

[0130] 16 is an exploded perspective view showing another example of an imaging element. The imaging element 100B includes a first semiconductor substrate 110, a second semiconductor substrate 120, and a third semiconductor substrate 130. As shown in FIG. 16, the first semiconductor substrate 110 is stacked on the second semiconductor substrate 120, and the second semiconductor substrate 120 is stacked on the third semiconductor substrate 130.

[0131] The first semiconductor substrate 110 has a pixel unit 101 and a connection region 1601. The pixel unit 101 outputs a pixel signal based on incident light. The connection region 1601 is arranged around the pixel unit 101. In the example of FIG. 16 , a pair of connection regions 1601 are arranged along two opposing sides of the first semiconductor substrate 110, in front of and behind the pixel unit 101.

[0132] The second semiconductor substrate 120 has a control circuit section 102 , a peripheral circuit section 121 and a signal processing section 1602 .

[0133] The control circuit section 102 outputs a control signal to the pixel section 101 to control the driving of the pixel section 101. The control circuit section 102 is disposed on the second semiconductor substrate 120 at a position facing the pixel section 101.

[0134] The peripheral circuit section 121 controls the driving of the control circuit section 102. The peripheral circuit section 121 is arranged around the control circuit section 102 on the second semiconductor substrate 120. The peripheral circuit section 121 may also be electrically connected to the first semiconductor substrate 110 and control the driving of the pixel section 101. The peripheral circuit section 121 is arranged along two opposing sides of the second semiconductor substrate 120, but the arrangement of the peripheral circuit section 121 is not limited to this example.

[0135] The signal processing unit 1602 receives analog pixel signals output from the first semiconductor substrate 110. The signal processing unit 1602 performs signal processing on the pixel signals. For example, the signal processing unit 1602 converts the analog pixel signals into digital signals. The signal processing unit 1602 may perform other signal processing. Examples of other signal processing include noise removal processing such as analog or digital CDS (Correlated Double Sampling). The signal processing unit 1602 is arranged on the periphery, i.e., outside, of the control circuit unit 102. In the example of FIG. 16 , a pair of signal processing units 1602 are arranged along two opposing sides of the second semiconductor substrate 120, in front and behind the control circuit unit 102. The signal processing units 1602 may be circuits included in the peripheral circuit unit 121.

[0136] The third semiconductor substrate 130 has a data processing unit 103. The data processing unit 103 uses the digital data output from the second semiconductor substrate 120 to perform addition processing, thinning processing, and other image processing.

[0137] Fig. 17 is an explanatory diagram showing another example of the specific configuration of the control circuit unit 102. In Fig. 17, the control block 400B has a pixel control unit 401 (autonomous exposure processing unit 411, exposure control unit 412, and pixel driving unit 413) but does not have a signal processing unit 402.

[0138] Instead of providing one control block 400B for one pixel block 200, one control block 400B may be provided for N pixel blocks 200 (N is a natural number greater than or equal to 2). The N pixel blocks 200 corresponding to one pixel block are sometimes referred to as a pixel block group. For example, two pixel blocks 200 arranged side by side in the column direction may be treated as one pixel block group, and one control block 400B may be provided for each pixel block group. In this case, the control block 400B may control the exposure time for each pixel block 200.

[0139] In other words, the control block 400B is electrically connected to at least one pixel block 200 and can be said to be the smallest unit of a circuit that controls exposure of the pixels 201 in the at least one pixel block 200.

[0140] 18 is an explanatory diagram showing the connection relationship between the first semiconductor substrate 110 and the second semiconductor substrate 120 in the image sensor 100B. The first semiconductor substrate 110 is provided around the pixel section 101 and includes connection regions 1801 and 1601 that are electrically connected to the pixel section 101. The second semiconductor substrate 120 is provided around the control circuit section 102 and includes connection regions 1802 and 1803 that are electrically connected to the control circuit section 102.

[0141] A pair of connection regions 1801 are connected to a pair of connection regions 1802 located opposite each other. The mutually connected connection regions 1801 and 1802 input control signals from the global driving unit 600 to the pixel unit 101 using global control lines.

[0142] The pair of connection regions 1601 are connected to a pair of connection regions 1803 located opposite each other. The mutually connected connection regions 1601 and 1803 input pixel signals from the pixel unit 101 to the corresponding ADC units 1820 and 1830 using a common signal line.

[0143] 19 is an explanatory diagram showing an example of signal transmission between the first semiconductor substrate 110 and the second semiconductor substrate 120 in the image sensor 100B. The global driver 600 outputs a reset control signal φRST, a selection control signal φSEL, and a transfer selection control signal φTXSEL. The global driver 600 is connected to a reset control line 1903 and a selection control line 1904 that output signals to each pixel block 200. The global driver 600 supplies the reset control signal φRST to the multiple pixel blocks 200 via the reset control line 1903 and the selection control signal φSEL via the selection control line 1904. The global driver 600 supplies the transfer selection control signal φTXSEL to the multiple control blocks 400B via a transfer selection control line 1905.

[0144] The transfer selection control signal φTXSEL is supplied from the global driver 600 to the control block 400B to control the exposure time for each pixel block 200. The control block 400B, to which the transfer selection control signal φTXSEL is supplied, outputs the transfer selection control signal φTXSEL to the corresponding pixel block 200. The pixel block 200 determines whether to input the transfer selection control signal φTXSEL to the pixel 201 as the transfer control signal φTX or the discharge control signal φPDRST. As a result, input of the transfer control signal φTX or the discharge control signal φPDRST to the pixel 201 is skipped.

[0145] For example, when the transfer control signal φTX determines the end time of exposure, the control block 400B extends the exposure time by skipping the transfer control signal φTX. Also, when the transfer control signal φTX determines the start time of exposure, the control block 400B can shorten the exposure time by skipping the transfer control signal φTX. In this way, the exposure time of the pixel block 200 can be adjusted by the transfer selection control signal φTXSEL. The same applies when the discharge control signal φPDRST determines the start or end time of exposure.

[0146] The reset control line 1903, the selection control line 1904, and the transfer selection control line 1905 are wired globally, i.e., are provided in common to a plurality of pixel blocks 200. The reset control line 1903, the selection control line 1904, and the transfer selection control line 1905 are wired in the row direction so as to cross the pixel unit 101. The reset control line 1903, the selection control line 1904, and the transfer selection control line 1905 may also be wired in the column direction so as to cross the pixel unit 101.

[0147] For example, the reset control line 1903 is connected to the gate terminal of the reset unit 304 of the pixel block 200 and supplies a reset control signal φRST. The selection control line 1904 is connected to the gate terminal of the selection unit 352 of the pixel block 200 and supplies a selection control signal φSEL. In addition, the transfer selection control line 1905 is connected to each of the multiple control blocks 400B and supplies a transfer selection control signal φTXSEL to the pixel control unit 401.

[0148] Although the global driving unit 600 outputs the transfer selection control signal φTXSEL from the second semiconductor substrate 120 to the first semiconductor substrate 110, the transfer selection control signal φTXSEL may be output to the control block 400B without being supplied to the first semiconductor substrate 110. In this case, the transfer selection control line 1905 is provided on the second semiconductor substrate 120.

[0149] On the other hand, the transfer control line 1901a and the discharge control line 1902a are connected to the pixel block 200a. The transfer control line 1901a is connected to the gate terminal of the transfer unit 301 provided in the pixel block 200a. The transfer control line 1901a supplies the transfer control signal φTX output from the control block 400Ba to the pixel block 200a. The discharge control line 1902a is connected to the gate terminal of the discharge unit 302 provided in the pixel block 200a. The discharge control line 1902a supplies the discharge control signal φPDRST output from the control block 400Ba to the pixel block 200a.

[0150] The transfer control line 1901b and the discharge control line 1902b are connected to the pixel block 200b. The transfer control line 1901b is connected to the gate terminal of the discharge transfer unit 301 provided in the pixel block 200b. The transfer control line 1901b supplies the transfer control signal φTX output from the control block 400Bb to the pixel block 200b. The discharge control line 1902b is connected to the gate terminal of the discharge unit 302 provided in the pixel block 200b. The discharge control line 1902b supplies the discharge control signal φPDRST output from the control block 400Bb to the pixel block 200b.

[0151] A plurality of junctions 610 are provided on the bonding surfaces where the first semiconductor substrate 110 and the second semiconductor substrate 120 are bonded to each other. The junctions 610 of the first semiconductor substrate 110 are aligned with the junctions 610 of the second semiconductor substrate 120. The opposing junctions 610 are bonded and electrically connected by, for example, applying pressure to the first semiconductor substrate 110 and the second semiconductor substrate 120. In this case, the junctions 610 of the global control lines may be located under the corresponding pixel block 200, or may be located in the connection region 1801 or the connection region 1802. On the other hand, the junctions 610 of the local control lines are provided under the corresponding pixel block 200 (and also on the control block 400B).

[0152] The image sensor 100B controls the exposure time for each pixel block 200 by changing the timing of at least one of the transfer unit 301 and the discharge unit 302 using local control lines. By combining local control lines and global control lines, the image sensor 100B can control the exposure time with fewer control lines.

[0153] 20 is an explanatory diagram showing the connection relationship between the ADC unit and pixel blocks. As shown in FIG. 20, a common signal line 202 extending in the column direction is arranged for each column within a pixel block 200c. Furthermore, this signal line 202 is also common to a plurality of pixel blocks 200c, 200d arranged in the column direction. Therefore, in this example, one signal line 202 is connected to m×M pixels 201 arranged in a single column, and pixel signals from these pixels 201 are output.

[0154] An ADC 2000 is connected to each of the signal lines 202 on the side of the second semiconductor substrate 120 via a joint 610. A plurality of ADCs 2000 corresponding to the plurality of signal lines 202 constitute an ADC unit 1820.

[0155] 20, the ADCs 2000 corresponding to the pixel blocks 200c and 200d in the odd-numbered columns are provided in the ADC unit 1820, and the ADCs 2000 corresponding to the pixel blocks 200e and 200f in the even-numbered columns are provided in the ADC unit 1830. However, the arrangement of the pixel blocks 200c, etc. and the corresponding ADC units 1820, etc. is not limited to this.

[0156] With the above configuration, each ADC 2000 converts pixel signals output sequentially from the m×M pixels 201 in one connected column into digital signals and outputs the converted signals. In this case, the ADC units 1820 and 1830 as a whole convert pixel signals from the pixels 201 arranged in n×N columns in the row direction into digital signals in parallel. From this perspective, this digital conversion can also be considered a type of so-called column ADC. Note that, although a single-slope ADC is an example of an ADC, other digital conversion methods may also be used. Furthermore, the connection positions of each pixel 201 and the signal line 202 are not limited to the form shown in FIG. 20 and may, for example, be within each pixel block 200c, etc.

[0157] 21 is a timing chart showing the imaging operation in the pixel block 200 of the image sensor 100B. Driving of the pixel block 200 is controlled by the transfer control signal φTX, the discharge control signal φPDRST, the reset control signal φRST, and the selection control signal φSEL.

[0158] The discharge control signal φPDRST controls the timing to start exposure. The exposure start timing corresponds to the falling edge of the discharge control signal φPDRST (for example, time T1). That is, before the exposure start time T1, the discharge control signal φPDRST turns on the discharge unit 302 to discharge the charge accumulated in the photoelectric conversion unit 300, and exposure starts at the falling edge of the discharge control signal φPDRST. Because the discharge control signal φPDRST is controlled locally, the exposure time can be adjusted for each pixel block 200.

[0159] The transfer control signal φTX controls the timing to end exposure. At time T3, the transfer control signal φTX turns on the transfer unit 301, thereby transferring the charges accumulated in the photoelectric conversion unit 300 to the FD 303. The timing to end exposure corresponds to the falling edge of the transfer control signal φTX (for example, time T4).

[0160] The reset control signal φRST controls the timing of discharging the charge accumulated in the FD 303. At time T2, the reset control signal φRST turns on the reset unit 304, thereby discharging the charge in the FD 303. By discharging the charge in the FD 303 before the end of exposure, the influence of the charge remaining in the FD 303 when the charge is transferred from the photoelectric conversion unit 300 can be suppressed.

[0161] The selection control signal φSEL is a signal for selecting an arbitrary pixel 201. The selection control signal φSEL controls the on / off of the selection unit 352. At time T2, the selection control signal φSEL is set to high. At time T3, the pixel 201 for which the selection control signal φSEL is set to high outputs a pixel signal to the signal line 202 in response to the transfer control signal φTX being turned on. On the other hand, the pixel 201 for which the selection control signal φSEL is not set to high does not output a pixel signal.

[0162] The image sensor 100B can locally control the discharge control signal φPDRST to change the exposure start timing for each pixel block 200 and control the exposure time for each pixel block 200. The image sensor 100B can also locally control the transfer control signal φTX to control the exposure end timing for each pixel block 200. The image sensor 100B can also locally control both the transfer control signal φTX and the discharge control signal φPDRST to control both the exposure start timing and end timing for each pixel block 200.

[0163] The pixel signal of each pixel 201 corresponds to the amount of charge accumulated in the photoelectric conversion unit 300. Therefore, controlling the timing of exposure of the pixel 201 can be said to be controlling the timing of charge accumulation in the photoelectric conversion unit 300. More specifically, controlling the timing of exposure of the pixel 201 can be said to be controlling the timing and length of the charge accumulation time from discharge to transfer of the charge.

[0164] 22 is an explanatory diagram showing an example of exposure timing for each pixel block 200. For three pixel blocks 200 arranged in a row, the exposure time is controlled for each pixel block 200. Here, the image sensor 100B changes the amount of exposure by shifting the pixel reset time for each pixel block 200.

[0165] Meanwhile, the timing of pixel signal readout is in order starting from the top pixel block 200. That is, pixel signals are read out from the pixels 201 in "pixel block 1," then from the pixels 201 in "pixel block 2," and then from the pixels 201 in "pixel block 3."

[0166] 21, pixel signals are read out sequentially from the pixels 201 in the upper rows within each pixel block 200. Therefore, when viewed from the entire pixel unit 101, pixel signals are read out sequentially from the upper row of the m×M pixels 201 in the same column that are connected to a common signal line 202. In other words, the global drive unit 600 sets the selection control signal φSEL to high for each row, from the first row to the m×Mth row, across the pixel blocks 200 arranged in a single column.

[0167] 20, for multiple pixel blocks 200 arranged in one row, a common selection control line 1904 is connected to the n×N pixels arranged in the same row. Therefore, pixel signals are read out in parallel from the n×N pixels 201 connected to the row for which the selection control signal φSEL is set high. This makes it possible to output pixel signals for one frame.

[0168] 20, these pixel signals are converted into digital form by the ADC units 1820 and 252. The digitally converted pixel signals are output to the subsequent image processing stage, where an image for one frame is formed.

[0169] As described above, from the viewpoint that pixel signals are read out sequentially from the top row of the same column among multiple pixel blocks 200, the readout method of this embodiment can also be said to be a so-called rolling shutter method for the entire pixel unit 101. However, it should be noted that even in this case, different exposure times can be set for each pixel block 200.

[0170] As described above, the image sensor 100B shown in FIGS. 16 to 22 performs exposure in units of pixel blocks 200, sequentially reading out pixel signals for each pixel row and performing AD conversion for each pixel column. Specifically, the image sensor 100B reads out pixel signals from the pixels 201 of the upper pixel block 200 among the pixel blocks 200 arranged in a row, and then reads out pixel signals from the pixels 201 of the pixel block 200 below it. This smooths out image distortion caused by the readout order when capturing an image of a moving subject, thereby reducing the sense of incongruity felt by the viewer. More specifically, when a moving subject is captured in parallel from the pixel blocks 200 arranged in a row, multiple sawtooth-like steps corresponding to the pixel blocks 200 appear in the vertical direction of the image (i.e., corresponding to the pixel column direction), causing the viewer to feel uncomfortable. In contrast, the image sensor 100B shown in FIGS. 16 to 22 does not display these steps in the image.

[0171] Furthermore, the image sensor 100B shown in FIGS. 16 to 22 does not include an ADC unit that converts analog signals to digital signals within the control block 400B, but instead has a signal processing unit 1602 located outside the control circuit unit 102. This allows the area of ​​the control block 400B to be reduced, thereby reducing the size of the pixel blocks 200 located at positions corresponding to the control block 400B. In other words, exposure control by the control block 400B can be performed in units of a small number of pixels. This allows for precise exposure time control within an image, making the boundaries of the pixel blocks 200 less noticeable on the image. Furthermore, since digital conversion is not performed directly below the pixels 201, the impact of noise on the pixels 201 due to heat generation can be suppressed.

[0172] The signal processing unit 1602 does not have to be provided in multiple separate regions, and may be provided in one region for the entire pixel portion 101.

[0173] As described above, from the viewpoint that pixel signals are ultimately read out sequentially from the top row of the same column among the multiple pixel blocks 200, just like in the image sensor 100A, the readout method of the image sensor 100B can also be said to be a so-called rolling shutter method for the entire pixel unit 101. However, even in this case, just like the image sensor 100A, it is possible to set different exposure times for each pixel block 200. As a result, just like the image sensor 100A, the image sensor 100B also smooths out image distortion caused by the readout order when capturing an image of a moving subject, thereby reducing the sense of incongruity felt by the viewer.

[0174] [Autonomous exposure processing unit 411] Next, we will explain the details of the autonomous exposure processing unit 411. In the following explanation, when there is no need to distinguish between the image sensors 100A and 100B, they will be referred to as image sensor 100, and when there is no need to distinguish between the control blocks 400A and 400B, they will be referred to as control block 400.

[0175] 4 and 17, the autonomous exposure processing unit 411 is implemented in the control block 400. The autonomous exposure processing unit 411 can also be implemented in the peripheral circuit unit 121 instead of in the control block 400, or it can be implemented in both the control block 400 and the peripheral circuit unit 121. These three patterns will be explained below with reference to FIGS. 23 to 25.

[0176] 23 is a block diagram showing an example configuration of autonomous exposure control system 1. Autonomous exposure control system 1 is an example configuration in which an autonomous exposure processing unit 411 is implemented within a control block 400. Adding the autonomous exposure processing unit 411 within the control block 400 increases the circuit size of the control block 400, but each pixel 201 in the pixel block 200 may become larger by that amount, making it possible to increase the light receiving area.

[0177] 23 will be described using the control block 400A as an example (the same applies to FIG. 25). The control block 400A has a signal conversion unit 422, a signal output unit 423, an autonomous exposure processing unit 411, an exposure control unit 412, and a pixel driving unit 413. For ease of explanation, the signal input unit 421 is omitted. In the case of the control block 400B, the signal input unit 421, the signal conversion unit 422, and the signal output unit 423 are not included in the control block 400B, but are arranged on the second semiconductor substrate 120 as a signal processing unit 1602 (the same applies to FIG. 25).

[0178] The signal conversion unit 422 has n ADCs 500. Each of the n ADCs 500 converts analog pixel signals from the m pixels 201 connected in the column direction into digital signals. The ADC 500 is configured with a comparator 501 and a storage unit 502.

[0179] The column selection circuit 2301 is included in the signal output unit 423. The column selection circuit 2301 sequentially selects columns of the pixel block 200 each time a readout column selection signal is input from an external device. Each time a horizontal transfer clock is input from an external device, the column selection circuit 2301 outputs digital pixel signals from m pixels 201 in the selected column to the peripheral circuit unit 121 via a horizontal transfer line 2300, and also outputs the signals to the autonomous exposure processing unit 411.

[0180] The autonomous exposure processor 411 calculates an exposure value that indicates the exposure time of the pixel block 200. Specifically, the autonomous exposure processor 411 has, for example, a preprocessing unit 2311, a controller 2312, and an exposure value calculation unit 2313.

[0181] The preprocessing unit 2311 acquires digital pixel signals for each pixel column of the pixel block 200 from the column selection circuit 2301. The preprocessing unit 2311 then calculates statistical values ​​(e.g., average, median, maximum, or minimum) of the acquired pixel signals. The preprocessing unit 2311 outputs the calculation results to the exposure value calculation unit 2313.

[0182] The controller 2312 inputs a reset signal to the pre-processing unit 2311, causing the pre-processing unit 2311 to reset the pre-processing. This causes the pre-processing unit 2311 to calculate statistical values ​​of pixel signals from the pixel block 200 each time it is reset, that is, for each frame.

[0183] The exposure value calculation unit 2313 determines the next exposure value based on the calculation result (statistical value of pixel signals) from the preprocessing unit 2311. Specifically, for example, the exposure value calculation unit determines the next exposure value based on the calculation result so as not to result in underexposure or overexposure. For example, the exposure value calculation unit 2313 holds a first threshold value and a second threshold value. The first threshold value is a threshold value for determining whether the calculation result will be underexposed. The second threshold value is a threshold value greater than the first threshold value and is a threshold value for determining whether the calculation result will be overexposed.

[0184] The exposure value calculation unit 2313 determines whether the calculation result is equal to or greater than the first threshold value and equal to or less than the second threshold value. If the calculation result is equal to or greater than the first threshold value and equal to or less than the second threshold value, the exposure value calculation unit outputs the calculation result as the exposure value to the latch circuit 2321 of the exposure control unit 412. If the calculation result is less than the first threshold value, the exposure value calculation unit 2313 outputs the first threshold value as the exposure value to the latch circuit 2321 of the exposure control unit 412. If the calculation result is greater than the second threshold value, the exposure value calculation unit outputs the second threshold value as the exposure value to the latch circuit 2321 of the exposure control unit 412.

[0185] The exposure value calculation unit 2313 may also hold multiple exposure value ranges. In this case, if the calculation result is equal to or greater than the first threshold value and equal to or less than the second threshold value, the exposure value calculation unit 2313 outputs the number of levels of the exposure value range that includes the calculation result as the exposure value to the latch circuit 2321 of the exposure control unit 412.

[0186] If the calculation result is less than the first threshold value, the exposure value calculation unit 2313 outputs a number that is one or more steps higher than the number of steps in the exposure value range that includes the calculation result as the exposure value to the latch circuit 2321 of the exposure control unit 412. If the calculation result exceeds the second threshold value, the exposure value calculation unit 2313 outputs a number that is one or more steps lower than the number of steps in the exposure value range that includes the calculation result as the exposure value to the latch circuit 2321 of the exposure control unit 412.

[0187] The exposure control unit 412 includes, for example, a latch circuit 2321, a shift register 2322, a pixel block control unit, and a level shift unit. The latch circuit 2321 holds the exposure value from the autonomous exposure processing unit. Each time a latch pulse is input from the outside, the latch circuit 2321 outputs the held exposure value to the pixel block control unit and the shift register 2322.

[0188] The shift register 2322 converts the exposure value from the latch circuit 2321 from parallel to serial and outputs the serial signal to the data processing unit.

[0189] If the exposure time is calculated by an external system outside the image sensor 100 and the calculation result is fed back to the image sensor 100, it takes time for the exposure time to be reflected in the image sensor 100, resulting in increased power consumption. In contrast, by providing an autonomous exposure processing unit 411 within the control block 400, it is possible to improve the speed at which the exposure time is reflected in the pixel block 200 and reduce power consumption.

[0190] 23 has described a case where one control block 400 controls the exposure of one pixel block 200, but when one control block 400 controls the exposure of multiple pixel blocks 200, the autonomous exposure processing unit 411 may calculate an exposure value by sequentially selecting one pixel block 200 from the multiple pixel blocks 200 in synchronization with a reset signal. A selector is provided on the output side of the exposure value calculation unit 2313, and the controller 2312 outputs a selection signal to the selector to select one pixel block 200 from the multiple pixel blocks 200.

[0191] Furthermore, in this case, the exposure control unit 412 has a latch circuit 2321 and a shift register 2322 for each pixel block 200. Each latch circuit 2321 is connected to a selector (not shown) in the autonomous exposure processing unit 411, and when an exposure value is input from the selector, the latch circuit 2321 outputs the held exposure value to the pixel block control unit 503 and the shift register 2322 each time a latch pulse is input. This makes it possible to achieve autonomous exposure even when one control block 400 controls the exposure of multiple pixel blocks 200.

[0192] 24 is a block diagram showing an example configuration of autonomous exposure control method 2. Autonomous exposure control method 2 is an example configuration in which an autonomous exposure processing unit 411 is implemented in the peripheral circuit unit 121. The autonomous exposure processing unit 411 is implemented in the peripheral circuit unit 121 rather than in the control block. This allows the circuit scale of the control block 400 to be smaller than in the case of FIG. 23.

[0193] The peripheral circuit unit 121 is connected to the pixel unit 101 via a horizontal transfer unit 2410. The horizontal transfer unit 2410 is connected to each pixel block 200 arranged in the row direction (hereinafter referred to as a pixel block row), and transfers pixel signals for each pixel block row to the peripheral circuit unit 121. Because the pixel unit 101 is a collection of pixel blocks 200 with M rows and N columns, the horizontal transfer unit 2410 transfers pixel signals to the peripheral circuit unit 121 for each M pixel block rows.

[0194] The peripheral circuit unit 121 has row-direction autonomous exposure processor groups 2400-1 to 2400-M (when not distinguishing between them, simply referred to as row-direction autonomous exposure processor groups 2400) for each pixel block row. The row-direction autonomous exposure processor group 2400 has a data sampling unit 2411 and autonomous exposure processors 411 (pre-processing units 2311, controllers 2312, and exposure value calculation units 2313) for the number N of columns of pixel blocks. In FIG. 24, since N=4, four sets of pre-processing units 2311, controllers 2312, and exposure value calculation units 2313 are implemented.

[0195] The data sampling unit 2411 divides the pixel signal sequence of the pixel block row from the horizontal transfer unit 2410 into N equal parts and samples them. The data sampling unit 2411 outputs each of the sampled pixel signal sequences to the corresponding pre-processing unit 2311.

[0196] As described above, the preprocessing unit 2311 calculates statistical values ​​of pixel signals from the corresponding pixel block 200. Furthermore, since the peripheral circuit unit 121 can have a larger circuit scale than the control block 400, the preprocessing unit 2311 can perform other processes in addition to calculating statistical values ​​of pixel signals.

[0197] For example, the preprocessing unit 2311 has a memory that stores the pixel numbers of defective pixels in the corresponding pixel block 200 that were defective during manufacturing, and when the data sampling unit 2411 samples a pixel signal of that pixel number, the preprocessing unit 2311 does not use the sampled pixel signal in calculating the statistical value of that pixel signal. This makes it possible to improve the accuracy of calculating the statistical value of the pixel signal.

[0198] Furthermore, the preprocessing unit 2311 may acquire calculation results from other preprocessing units 2311 that are responsible for pixel blocks 200 adjacent to the corresponding pixel block 200, and calculate statistical values ​​of pixel signals from the corresponding pixel block 200 based on the calculation results acquired from the other preprocessing units 2311. This makes it possible to smooth out exposure differences between adjacent pixel blocks 200.

[0199] Furthermore, the exposure value calculation unit 2313 is set with a first threshold value and a second threshold value, but at least one of the first threshold value and the second threshold value may be changeable according to the shooting mode of the imaging device in which the image sensor 100 is implemented, thereby enabling optimal exposure calculation according to the shooting mode.

[0200] The peripheral circuit unit 121 also has a latch circuit 2321 and a shift register 2322 for each exposure value calculation unit 2313. The shift register 2322 performs parallel-to-serial conversion on the exposure value from the latch circuit 2321, outputs the serial signal to the data processing unit 103, and also outputs the exposure value to the exposure control unit 412 in the control block 400 corresponding to the pixel block 200.

[0201] The configuration shown in FIG. 24 allows the circuit scale of the control block 400 to be smaller than that of FIG. 23, and the size of the corresponding pixel block 200 to be reduced. This increases the number of pixel blocks, enabling more precise autonomous exposure control. The exposure control unit 412 and pixel driving unit 413 may also be implemented in the peripheral circuit unit 121. This allows the circuit scale of the control block 400 to be further reduced, and the size of the corresponding pixel block 200 to be reduced.

[0202] 25 is a block diagram showing an example configuration of autonomous exposure control method 3. Autonomous exposure control method 3 is an example configuration in which autonomous exposure processing unit 411 is implemented both in control block 400A and in peripheral circuit unit 121. When performing automatic exposure control in control block 400A, data transmission such as sending pixel signals from control block 400A to peripheral circuit unit 121 and sending exposure values ​​from peripheral circuit unit 121 to pixel block 200 is not necessary. Therefore, feedback to the corresponding pixel block 200 is faster than when performing in peripheral circuit unit 121.

[0203] On the other hand, since the area of ​​the control block 400A is restricted by the area of ​​the corresponding pixel block 200, the circuit scale of the autonomous exposure processing unit 411 can be made larger by implementing it in the peripheral circuit unit 121 rather than implementing it within the control block 400A. For this reason, implementing it in the peripheral circuit unit 121 makes it possible to implement more advanced functions for autonomous exposure control (for example, removal of pixel signals from defective pixels, control of exposure gaps between adjacent pixel blocks 200, and calculation of optimal exposure according to the shooting mode, as explained in FIG. 24).

[0204] Therefore, in autonomous exposure control method 3, image sensor 100 performs autonomous exposure control depending on the situation, using peripheral circuitry 121 when performing high-performance calculations related to autonomous exposure control, or using control block 400A when performing high-speed feedback of exposure values. In Fig. 25, as an example, in autonomous exposure control method 3, autonomous exposure control is performed by row-direction autonomous exposure processing units 2400 in peripheral circuitry 121, but image sensor 100 performs autonomous exposure control for each control block 400A when a trigger is given to control circuitry 102.

[0205] For example, when a user selects high-performance calculations related to autonomous exposure control, the image sensor 100 executes autonomous exposure control in the peripheral circuit unit 121, and when a user selects high-speed execution of exposure value feedback, the image sensor 100 executes autonomous exposure control in the control block 400A. Furthermore, when the remaining battery charge falls below a predetermined level, the image sensor 100 may select and execute low-power consumption processing between high-performance calculations related to autonomous exposure control and high-speed execution of exposure value feedback.

[0206] The row-direction autonomous exposure processing unit group 2400 mounted in the peripheral circuit unit 121 has the same configuration as that shown in FIG. 24, and is therefore omitted in FIG.

[0207] The column selection circuit 2301 outputs an n-bit digital pixel signal to n OR circuits 2501. The autonomous exposure processing unit 2500 in the control block 400A has, in addition to the controller 2312, n OR circuits 2501, an output data latch circuit 2502, and an n-bit AND circuit 2503.

[0208] When the n-bit signal is output from the output data latch circuit 2502 , the controller 2312 inputs a reset signal to the output data latch circuit 2502 .

[0209] The OR circuit 2501 is a logic circuit with two inputs and one output. One input of the OR circuit 2501 is connected to the column selection circuit, and the other input is connected to the output of the n-bit AND circuit 2503.

[0210] The n OR circuits 2501 are connected to the input of an output data latch circuit 2502. The output data latch circuit 2502 holds the n-bit signal from the n OR circuits 2501. When a horizontal transfer clock is input, the output data latch circuit 2502 outputs an n-bit signal to an n-bit AND circuit 2503. When a reset signal is input from the controller 2312, the output data latch circuit 2502 resets the n-bit signal it is holding, and outputs an n-bit signal in which at least one bit of the n bits is 0 to the n-bit AND circuit 2503.

[0211] The n-bit AND circuit 2503 is an AND circuit with n inputs and 1 output, and the output of the output data latch circuit 2502 is connected to the input of the n-bit AND circuit 2503. The output of the n-bit AND circuit 2503 is connected to the selector 2512 of the exposure control unit 412 and the input of each OR circuit 2501. If the output from the n-bit AND circuit 2503 is "0", this indicates that the pixel row that output the n-bit digital pixel signal is not saturated. If the output from the n-bit AND circuit 2503 is "1", this indicates that the pixel row that output the n-bit digital pixel signal is saturated. Hereinafter, a 1-bit signal whose output is "1" from the n-bit AND circuit 2503 will be referred to as a saturation detection signal.

[0212] If the value of the digital pixel signal from a pixel 201 in a pixel column is "1," this indicates that the pixel 201 is saturated. If all values ​​of the n-bit signal from the column selection circuit 2301 are "1," this indicates that the entire pixel column is saturated. In this case, all "1"s are input to one input of each OR circuit 2501, and each OR circuit 2501 outputs a 1-bit signal with a value of "1" to the output data latch circuit 2502.

[0213] The output data latch circuit 2502 holds these n-bit signals, all of which have the value “1”, and outputs the held n-bit signal to an n-bit AND circuit 2503 when a horizontal transfer clock is input.

[0214] When an n-bit signal whose value is all "1" is input, the n-bit AND circuit 2503 outputs a saturation detection signal whose value is "1" to the selector 2512 and each OR circuit 2501. As a result, the output data latch circuit 2502 outputs an n-bit signal whose value is all "1" to the n-bit AND circuit 2503 until a reset signal is input. Therefore, the n-bit AND circuit 2503 outputs a saturation detection signal until a reset signal is input to the output data latch circuit 2502 from the controller 2312.

[0215] 24, the exposure control unit 412 has a shift register 2511 and a selector 2512. The shift register 2511 converts the exposure value from the peripheral circuit unit 121 from serial to parallel, and outputs the converted value to the level shift unit 504 and the selector 2512.

[0216] The selector 2512 receives the exposure value and the set exposure value from the shift register 2511. The selector 2512 selects either the exposure value from the shift register 2511 or the set exposure value based on the output signal from the n-bit AND circuit 2503, and outputs the selected exposure value to the latch circuit 2321. The set exposure value is an exposure value that corresponds to an exposure time that does not saturate the pixel 201, and is, for example, an exposure value that is set so as to minimize the exposure time.

[0217] The set exposure value is calculated and set, for example, by an external system outside the control block 400A. The set exposure value may be a fixed value or may be selected by the external system. The external system may be, for example, the peripheral circuit unit 121 in the image sensor 100, the data processing unit 103 on the third semiconductor substrate 130, or an image processing unit connected to the image sensor 100 in an imaging device having the image sensor 100.

[0218] Specifically, for example, when the output signal from the n-bit AND circuit 2503 is not a saturation detection signal, the selector 2512 selects the exposure value from the shift register 2511 and outputs it to the latch circuit 2321. On the other hand, when the output signal from the n-bit AND circuit 2503 is a saturation detection signal, the selector 2512 selects the set exposure value and outputs it to the latch circuit 2321.

[0219] In the control block 400A, the autonomous exposure processing unit 2500 and the exposure control unit 412 execute autonomous exposure control using the exposure value from the peripheral circuit unit 121 until saturation is detected in the control block 400A. When saturation is detected in the control block 400A, autonomous exposure control is executed using the set exposure value in the exposure control unit 412.

[0220] This makes it possible to select between a process in which a highly accurate exposure value is set for a non-saturated pixel column using the exposure value from the peripheral circuit unit 121, and a process that enables simple and high-speed feedback in which a set exposure value is changed to a non-saturated state for a saturated pixel column.

[0221] Furthermore, the autonomous exposure processing unit 2500 in the control block 400 may be the autonomous exposure processing unit 411 shown in Fig. 23. In this case, for example, it may be possible to make it possible to select between the autonomous exposure processing unit 411 in the peripheral circuit unit 121 and the autonomous exposure processing unit 411 in the control block 400 by user setting.

[0222] For example, an imaging device incorporating the image sensor 100 may be able to select between the autonomous exposure processing unit 411 in the peripheral circuit unit 121 and the autonomous exposure processing unit 411 in the control block 400 based on the remaining battery power. In this case, the imaging device may select autonomous exposure control by the autonomous exposure processing unit 411 in the peripheral circuit unit 121 if the remaining battery power is equal to or greater than a predetermined value, and may select autonomous exposure control by the autonomous exposure processing unit 411 in the control block 400 if the remaining battery power is less than the predetermined value. Furthermore, a user may select the autonomous exposure processing unit 411 in the peripheral circuit unit 121 if they want to capture high-quality images, or select the autonomous exposure processing unit 411 in the control block 400 if they want to reduce power consumption.

[0223] <Autonomous exposure control with additional memory 1> Next, autonomous exposure control 1 with additional memory in the above-described basic configuration will be described. Note that in the following description, when there is no need to distinguish between the image sensors 100A and 100B, they will be referred to as image sensor 100, and when there is no need to distinguish between the control blocks 400A and 400B, they will be referred to as control block 400. Autonomous exposure control 1 with additional memory is autonomous exposure control using pixel 201 with analog memory added to the above-described pixel 201, and will be described using Figures 26 to 45. Adding analog memory to pixel 201 suppresses image distortion due to rolling shutter operation as shown in Figures 8, 9, 15, and 21. Here, local control and global control in the above-described image sensor 100 will be described in detail.

[0224] 26 is an explanatory diagram showing local control and global control. Local control refers to the pixel control unit 401 of the control block 400 controlling the connected pixel blocks 200 so that the same pixel row in each of the multiple pixel blocks 200 located in the same pixel block row operates differently. Global control refers to the peripheral circuit unit 121 controlling the pixel blocks 200 so that the same pixel row in each of the multiple pixel blocks 200 located in the same pixel block row operates in the same way across the entire surface of the pixel unit 101. In global control, the same pixel row in different pixel block rows is controlled to operate in the same way.

[0225] In the pixel 201, a first transfer unit 2613 (hereinafter, the transfer unit 301 will be referred to as the second transfer unit 301, the transfer control signal φTX input to the gate terminal of the second transfer unit 301 will be referred to as the second transfer control signal φTX2, and the transfer control line 311 will be referred to as the second transfer control line 311) and a holding unit 2603 which is an analog memory are provided between the transfer unit 301 and the photoelectric conversion unit 300. The pixel 2601 on the left with a 6Tr (transistor) configuration is a pixel 201 in which the first transfer unit 2613 and the holding unit 2603 are added to the circuit configuration of the pixel 201 shown in FIG.

[0226] A gate terminal of the first transfer unit 2613 is connected to a first transfer control line 2610 for inputting a first transfer control signal φTX1. The first transfer control line 2610 is connected to a pixel control unit 401 of a control block 400 that controls a pixel block 200 including the pixel 201 in a locally controllable configuration, and is connected to a peripheral circuit unit 121 in a globally controllable configuration.

[0227] The pixel 2602 with a 5Tr configuration on the right side is the pixel 201 in which a first transfer unit 2613 and a holding unit 2603 are added to the circuit configuration of the pixel 201 shown in FIG.

[0228] The holding unit 2603 is composed of a capacitor, and the first transfer unit 2613 is composed of a transistor. The holding unit 2603 holds the charge of the photoelectric conversion unit 300. In the pixels 2601 and 2602, after the photoelectric conversion unit 300 is reset (PD reset) and before the second transfer unit 301 reads out the charge, the first transfer unit 2613 transfers the charge accumulated in the photoelectric conversion unit 300 to the holding unit 2603 when a first transfer control signal φTX1 is input to its gate terminal. The second transfer unit 301 then reads out the charge held in the holding unit 2603 and transfers it to the FD 303 serving as a storage unit. The pixel output unit 305 outputs a voltage signal based on the charge accumulated in the FD 303 to the signal line 202. When the pixels 2601 and 2602 are not to be distinguished, they are referred to as pixel 2600.

[0229] There are two types of autonomous exposure control for pixel blocks 200: an autonomous exposure control method by imager 100A in which imager 100A performs autonomous exposure control for each pixel block 200 and reads out and AD converts analog pixel signals for each pixel block 200, and an autonomous exposure control method by imager 100B in which imager 100B performs autonomous exposure control for each pixel block 200, but reads out analog pixel signals for each pixel row in sequence and AD converts the analog pixel signals for each pixel column spanning each pixel block 200 in the same pixel block column. In the autonomous exposure control method by imager 100B, analog pixel signals are read out at the same time for the same pixel column in different pixel block columns.

[0230] In addition, there are two ways to adjust the exposure time in the pixel block 200: "PD reset," which resets the photoelectric conversion unit 300, and "PD → FD transfer," which temporarily transfers and stores charge from the photoelectric conversion unit 300 to the storage unit 2603 (PD → memory transfer), and then transfers the charge stored in the storage unit 2603 to the FD 303 (FD readout).

[0231] In the case of PD reset, the exposure time can be adjusted by the start timing of exposure. In addition, in the case of PD reset, the drain unit 302 is the transistor required for local control in the pixel 2601, and the second transfer unit 301, reset unit 304, and first transfer unit 2613 are the transistors required for local control in the pixel 2602.

[0232] In the case of PD→FD transfer, the exposure time can be adjusted by timing at which the exposure ends. Also, in the case of PD→FD transfer, the first transfer unit 2613 is a transistor essential for local control.

[0233] Hereinafter, control will be described for each combination of the autonomous exposure control method (image sensor 100A or image sensor 100B), the circuit configuration of pixel 201 (pixel 2601 or pixel 2602), and the exposure time adjustment method (PD reset or PD → FD transfer). To simplify the explanation, a pixel block column consisting of six pixel blocks 200-1 to 200-6 will be described as an example.

[0234] [Autonomous exposure control system using image sensor 100A including pixel 2601 with a 6-transistor configuration] FIG. 27 is an explanatory diagram showing an example of a control method using an autonomous exposure control system by an image sensor 100A including pixels 2601 with a 6-transistor configuration. In FIG. 27, control method 1-1 is an example of control when the exposure time adjustment method is PD reset, and control method 1-2 is an example of control when the exposure time adjustment method is PD→FD transfer. Hereinafter, if the control method has a subnumber of "1," it indicates that the exposure time adjustment method is PD reset, and if it is "2," it indicates that the exposure time adjustment method is PD→FD transfer. Also, in FIG. 27, the vertical direction indicates the column direction of the pixel block 200, and the horizontal direction indicates the flow of time. This also applies to the explanatory diagrams showing the following control method examples.

[0235] Figure 28 is a pulse chart for control method 1-1, and Figure 29 is a pulse chart for control method 1-2. In Figures 28 and 29, the symbols (G) and (L) in parentheses at the end of the signal name indicate a global signal (G) under global control or a local signal (L) under local control. This also applies to the subsequent pulse charts.

[0236] 27 and 28, in control method 1-1, the discharge unit 302 is a transistor essential for local control. In each of pixel blocks 200-1 to 200-6, when a discharge control signal φPDRST is input to the gate terminal of the discharge unit 302 of pixel 2601 by local control, the photoelectric conversion unit 300 is reset, and exposure is started in the photoelectric conversion unit 300 (PD reset).

[0237] Next, PD→FD transfer is performed in the pixel blocks 200-1 to 200-6. Specifically, for example, when the first transfer control signal φTX1 is input to the gate terminal of the first transfer unit 2613 of the pixel 2601 under global control, the charge accumulated in the photoelectric conversion unit 300 is transferred to and held in the holding unit 2603 (PD→memory transfer). Because this is global control, different exposure times are set for the pixel blocks 200-1 to 200-6, which have different exposure start timings.

[0238] In pixel blocks 200-1 to 200-6, when a reset control signal φRST is input to the gate terminal of the reset unit 304 of pixel 2601 by global control, a second transfer control signal φTX2 is input to the gate terminal of the second transfer unit 301 by global control, and a selection signal SEL is input to the gate terminal of the selection unit 352 by global control, the charge accumulated in the holding unit 2603 is transferred to the FD 303 and output from the selection unit 352 as an analog pixel signal (FD readout).

[0239] In FIG. 27, in control method 1-1, PD reset and FD readout are performed in separate paths in pixel 2601, so that PD reset for frame 2 is possible before FD readout for frame 1 is completed.

[0240] 27 and 29, in control method 1-2, the first transfer unit 2613 is a transistor essential for local control. In the pixel blocks 200-1 to 200-6, when the discharge control signal φPDRST is input to the gate terminal of the discharge unit 302 of the pixel 2601 by global control, the photoelectric conversion unit 300 is reset, and exposure is started in the photoelectric conversion unit 300 (PD reset).

[0241] Next, PD→FD transfer is performed in each of the pixel blocks 200-1 to 200-6. Specifically, for example, when the first transfer control signal φTX1 is input to the gate terminal of the first transfer unit 2613 of the pixel 2601 under local control, the charge accumulated in the photoelectric conversion unit 300 is transferred to and held in the holding unit 2603 (PD→memory transfer). Because of local control, the exposure end timing differs for each of the pixel blocks 200-1 to 200-6. Therefore, a different exposure time is set for each of the pixel blocks 200-1 to 200-6.

[0242] In pixel blocks 200-1 to 200-6, when a reset control signal φRST is input to the gate terminal of the reset unit 304 of pixel 2601 by global control, a second transfer control signal φTX2 is input to the gate terminal of the second transfer unit 301 by global control, and a selection signal SEL is input to the gate terminal of the selection unit 352 by global control, the charge accumulated in the holding unit 2603 is transferred to the FD 303 and output from the selection unit 352 as an analog pixel signal (FD readout).

[0243] In Figure 27, in control method 1-2, as in control method 1-1, PD reset and FD readout are performed via separate routes in pixel 2601, but PD → memory transfer by the first transfer unit 2613 in frame 2 occurs after FD readout in frame 1 is completed.

[0244] [Autonomous exposure control system using image sensor 100A including pixel 2602 with a 5-transistor configuration] Fig. 30 is an explanatory diagram showing an example of a control method using an autonomous exposure control system by an image sensor 100A including 5Tr pixels 2602. In Fig. 30, control method 2-1 is a control example when the exposure time adjustment system is PD reset, and control method 2-2 is a control example when the exposure time adjustment system is PD → FD transfer.

[0245] Fig. 31 is a pulse chart for control method 2-1, and Fig. 32 is a pulse chart for control method 2-2. In Fig. 30 and Fig. 31, in control method 2-1, the second transfer unit 301, the reset unit 304, and the first transfer unit 2613 are transistors essential for local control. In each of the pixel blocks 200-1 to 200-6, when the first transfer control signal φTX1 is input to the gate terminal of the first transfer unit 2613 of the pixel 2602 by local control, the second transfer control signal φTX2 is input to the gate terminal of the second transfer unit 301 by local control, and the reset control signal φRST is input to the gate terminal of the reset unit 304 by local control, the photoelectric conversion unit 300 is reset, and exposure is started in the photoelectric conversion unit 300 (PD reset).

[0246] Next, in the pixel blocks 200-1 to 200-6, PD→FD transfer is performed. Specifically, for example, when a first transfer control signal φTX1 is input to the gate terminal of the first transfer unit 2613 of the pixel 2601 via a locally controllable first transfer control line 2610 (however, the transfer timing is a global operation over the entire surface of the pixel unit 101), the charge accumulated in the photoelectric conversion unit 300 is transferred to and held in the holding unit 2603 (PD→memory transfer). Because the PD reset was performed under local control, different exposure times are set for the pixel blocks 200-1 to 200-6, which have different exposure start timings.

[0247] In pixel blocks 200-1 to 200-6, a reset control signal φRST is input to the gate terminal of the reset unit 304 of pixel 2602 via a locally controllable reset control line 313 (however, the readout timing is a global operation with the same timing across the entire pixel unit 101 in the row direction), and a second transfer control signal φTX2 is input to the gate terminal of the second transfer unit 301 via a locally controllable second transfer control line 311 (however, the readout timing is a global operation with the same timing across the entire pixel unit 101 in the row direction), and when a selection signal SEL is input to the gate terminal of the selection unit 352 by global control, the charge accumulated in the holding unit 2603 is transferred to the FD303 and output from the selection unit 352 as an analog pixel signal (FD readout).

[0248] 30 and 32, in control method 2-2, the first transfer unit 2613 is a transistor essential for local control. In pixel blocks 200-1 to 200-6, a first transfer control signal φTX1 is input to the gate terminal of the first transfer unit 2613 of the pixel 2602 via a locally controllable first transfer control line 2610 (however, the reset timing is a global operation with the same timing across the entire pixel unit 101 in the row direction), a second transfer control signal φTX2 is input to the gate terminal of the second transfer unit 301 by global control, and a reset control signal φRST is input to the gate terminal of the reset unit 304 by global control, whereby the photoelectric conversion unit 300 is reset and exposure begins in the photoelectric conversion unit 300 (PD reset).

[0249] Next, PD→FD transfer is performed in each of the pixel blocks 200-1 to 200-6. Specifically, for example, when the first transfer control signal φTX1 is input to the gate terminal of the first transfer unit 2613 of the pixel 2601 under local control, the charge accumulated in the photoelectric conversion unit 300 is transferred to and held in the holding unit 2603 (PD→memory transfer). Because of local control, the exposure end timing differs for each of the pixel blocks 200-1 to 200-6. Therefore, a different exposure time is set for each of the pixel blocks 200-1 to 200-6.

[0250] In pixel blocks 200-1 to 200-6, when a reset control signal φRST is input to the gate terminal of the reset unit 304 of pixel 2601 by global control, a second transfer control signal φTX2 is input to the gate terminal of the second transfer unit 301 by global control, and a selection signal SEL is input to the gate terminal of the selection unit 352 by global control, the charge accumulated in the holding unit 2603 is transferred to the FD 303 and output from the selection unit 352 as an analog pixel signal (FD readout).

[0251] [Autonomous exposure control system using image sensor 100B including pixel 2601 with 6-transistor configuration] Fig. 33 is an explanatory diagram showing an example of a control method based on an autonomous exposure control system using an image sensor 100B including 6Tr pixels 2601. In Fig. 33, control method 3-1 is a control example when the exposure time adjustment method is PD reset, and control method 3-2 is a control example when the exposure time adjustment method is PD → FD transfer.

[0252] Fig. 34 is a pulse chart for control method 3-1, and Fig. 35 is a pulse chart for control method 3-2. In Fig. 33 and Fig. 34, in control method 3-1, the discharge unit 302 is a transistor essential for local control. In each of pixel blocks 200-1 to 200-6, when a discharge control signal φPDRST is input to the gate terminal of the discharge unit 302 of pixel 2601 by local control, the photoelectric conversion unit 300 is reset, and exposure is started in the photoelectric conversion unit 300 (PD reset).

[0253] Next, PD→FD transfer is performed in the pixel blocks 200-1 to 200-6. Specifically, for example, when the first transfer control signal φTX1 is input to the gate terminal of the first transfer unit 2613 of the pixel 2601 under global control, the charge accumulated in the photoelectric conversion unit 300 is transferred to and held in the holding unit 2603 (PD→memory transfer). Because this is global control, different exposure times are set for the pixel blocks 200-1 to 200-6, which have different exposure start timings.

[0254] In pixel blocks 200-1 to 200-6, when a reset control signal φRST is input to the gate terminal of the reset unit 304 of pixel 2601 by global control, a second transfer control signal φTX2 is input to the gate terminal of the second transfer unit 301 by global control, and a selection signal SEL is input to the gate terminal of the selection unit 352 by global control, the charge accumulated in the holding unit 2603 is transferred to the FD 303 and output from the selection unit 352 as an analog pixel signal (FD readout).

[0255] In FIG. 33, in control method 3-1, PD reset and FD readout are performed in separate paths in pixel 2601, so that PD reset for frame 2 is possible before FD readout for frame 1 is completed.

[0256] 33 and 35, in control method 3-2, the first transfer unit 2613 is a transistor essential for local control. In the pixel blocks 200-1 to 200-6, when the discharge control signal φPDRST is input to the gate terminal of the discharge unit 302 of the pixel 2601 by global control, the photoelectric conversion unit 300 is reset, and exposure is started in the photoelectric conversion unit 300 (PD reset).

[0257] Next, PD→FD transfer is performed in each of the pixel blocks 200-1 to 200-6. Specifically, for example, when the first transfer control signal φTX1 is input to the gate terminal of the first transfer unit 2613 of the pixel 2601 under local control, the charge accumulated in the photoelectric conversion unit 300 is transferred to and held in the holding unit 2603 (PD→memory transfer). Because of local control, the exposure end timing differs for each of the pixel blocks 200-1 to 200-6. Therefore, a different exposure time is set for each of the pixel blocks 200-1 to 200-6.

[0258] In pixel blocks 200-1 to 200-6, when a reset control signal φRST is input to the gate terminal of the reset unit 304 of pixel 2601 by global control, a second transfer control signal φTX2 is input to the gate terminal of the second transfer unit 301 by global control, and a selection signal SEL is input to the gate terminal of the selection unit 352 by global control, the charge accumulated in the holding unit 2603 is transferred to the FD 303 and output from the selection unit 352 as an analog pixel signal (FD readout).

[0259] In Figure 33, in control method 3-2, as in control method 3-1, PD reset and FD readout are performed via separate routes in pixel 2601, but PD → memory transfer by the first transfer unit 2613 in frame 2 occurs after FD readout in frame 1 is completed.

[0260] [Autonomous exposure control system using image sensor 100B including 5Tr pixel 2602] Fig. 36 is an explanatory diagram showing an example of a control method based on an autonomous exposure control system using an image sensor 100B including 5Tr pixels 2602. In Fig. 36, control method 4-1 is a control example when the exposure time adjustment method is PD reset, and control method 4-2 is a control example when the exposure time adjustment method is PD → FD transfer.

[0261] Fig. 37 is a pulse chart for control method 4-1, and Fig. 38 is a pulse chart for control method 4-2. In Fig. 36 and Fig. 37, in control method 4-1, the second transfer unit 301, the reset unit 304, and the first transfer unit 2613 are transistors essential for local control. In each of the pixel blocks 200-1 to 200-6, when the first transfer control signal φTX1 is input to the gate terminal of the first transfer unit 2613 of the pixel 2602 by local control, the second transfer control signal φTX2 is input to the gate terminal of the second transfer unit 301 by local control, and the reset control signal φRST is input to the gate terminal of the reset unit 304 by local control, the photoelectric conversion unit 300 is reset, and exposure is started in the photoelectric conversion unit 300 (PD reset).

[0262] Next, in the pixel blocks 200-1 to 200-6, PD→FD transfer is performed. Specifically, for example, when a first transfer control signal φTX1 is input to the gate terminal of the first transfer unit 2613 of the pixel 2601 via a locally controllable first transfer control line 2610 (however, the transfer timing is a global operation over the entire surface of the pixel unit 101), the charge accumulated in the photoelectric conversion unit 300 is transferred to and held in the holding unit 2603 (PD→memory transfer). Because the PD reset was performed under local control, different exposure times are set for the pixel blocks 200-1 to 200-6, which have different exposure start timings.

[0263] In pixel blocks 200-1 to 200-6, when a reset control signal φRST is input to the gate terminal of the reset unit 304 of pixel 2602 via a locally controllable reset control line 313, a second transfer control signal φTX2 is input to the gate terminal of the second transfer unit 301 via a locally controllable second transfer control line 311, and a selection signal SEL is input to the gate terminal of the selection unit 352 by global control, the charge accumulated in the holding unit 2603 is transferred to the FD 303 and output from the selection unit 352 as an analog pixel signal (FD readout).

[0264] 36 and 38, in control method 4-2, the first transfer unit 2613 is a transistor essential for local control. In the pixel blocks 200-1 to 200-6, a first transfer control signal φTX1 is input to the gate terminal of the first transfer unit 2613 of the pixel 2602 via a locally controllable first transfer control line 2610 (however, the reset timing is a global operation with the same timing across the entire pixel unit 101 in the row direction), a second transfer control signal φTX2 is input to the gate terminal of the second transfer unit 301 by global control, and a reset control signal φRST is input to the gate terminal of the reset unit 304 by global control, whereby the photoelectric conversion unit 300 is reset and exposure begins in the photoelectric conversion unit 300 (PD reset).

[0265] Next, PD→FD transfer is performed in each of the pixel blocks 200-1 to 200-6. Specifically, for example, when the first transfer control signal φTX1 is input to the gate terminal of the first transfer unit 2613 of the pixel 2601 under local control, the charge accumulated in the photoelectric conversion unit 300 is transferred to and held in the holding unit 2603 (PD→memory transfer). Because of local control, the exposure end timing differs for each of the pixel blocks 200-1 to 200-6. Therefore, a different exposure time is set for each of the pixel blocks 200-1 to 200-6.

[0266] In pixel blocks 200-1 to 200-6, when a reset control signal φRST is input to the gate terminal of the reset unit 304 of pixel 2601 by global control, a second transfer control signal φTX2 is input to the gate terminal of the second transfer unit 301 by global control, and a selection signal SEL is input to the gate terminal of the selection unit 352 by global control, the charge accumulated in the holding unit 2603 is transferred to the FD 303 and output from the selection unit 352 as an analog pixel signal (FD readout).

[0267] In this way, image distortion due to rolling shutter operation can be suppressed in each of eight combinations of the autonomous exposure control method (image sensor 100A or image sensor 100B), the circuit configuration of pixel 201 (pixel 2601 or pixel 2602), and the exposure time adjustment method (PD reset or PD → FD transfer).

[0268] [Frame spanning exposure] Next, we will explain frame-straddling exposure. Frame-straddling exposure is exposure for an exposure time longer than the exposure time of one frame, or exposure controlled to such an exposure time. By performing frame-straddling exposure in units of pixel blocks 200, long-time exposure longer than the exposure time of one frame is possible for each pixel block 200. Control methods that can perform frame-straddling exposure are control methods 1-1, 2-1, 3-1, and 4-1. In other words, these are control methods in which exposure time adjustment is performed by PD reset.

[0269] FIG. 39 is an explanatory diagram showing frame-straddle exposure. In FIG. 39, an example of frame-straddle exposure in the case of control method 1-1 is described, but the same applies to control methods 2-1, 3-1, and 4-1. In FIG. 39, the control block 400-3 that controls the pixel block 200-3 performs a PD reset and PD-to-memory transfer for frame 1, and then performs a specific FD readout or skips FD readout, while not performing a PD reset for frame 2. The specific FD readout is an operation that turns on the reset unit 304 and the selection unit 352 while keeping the second transfer unit 301 off.

[0270] If the exposure value of the frame immediately preceding frame 1 is less than a predetermined threshold, the control block 400-3 controls frame 1 so as not to perform frame-straddling exposure, i.e., not to perform PD reset for frame 2. This makes it possible to achieve frame-straddling exposure in units of pixel blocks 200.

[0271] [Flicker reduction control] Next, flicker reduction control will be described. For example, in an in-vehicle image sensor or a video camera, flicker occurs due to a mismatch between the shutter timing of the image sensor and the light emission timing of an LED (Light Emitting Diode). This flicker is called flicker. If flicker occurs in an imaging environment using the image sensor 100, different exposure times can be set for each pixel block 200, and therefore, some pixel blocks 200 may not be able to receive part or all of the subject light.

[0272] Fig. 40 is an explanatory diagram showing an example of flicker reduction control. Fig. 40 explains an example of flicker reduction control in the case of control method 3-1, but the same applies to control method 1-1. (A) shows basic operation without flicker reduction control applied, and (B) shows operation with flicker reduction control applied.

[0273] In (A), pixel blocks 200-2, 200-4, and 200-6 are unable to receive LED light. In contrast, in (B), the exposure time is set shorter than the flicker period. Therefore, the exposure time of each of pixel blocks 200-1 to 200-6 overlaps with the timing of receiving LED light. In (B), the exposure time of each of pixel blocks 200-1 to 200-6 is fragmented, but the total exposure time of each of pixel blocks 200-1 to 200-6 is the same as the exposure time in (A). In this way, flicker is reduced and the light-receiving efficiency of pixel block 200 is improved. Note that switching between operations (A) and (B) is performed by a user. Alternatively, the image sensor 100 may perform only the flicker reduction operation (B).

[0274] [Pixel group unit exposure control] Next, we will explain the pixel group unit exposure control in the above-mentioned control methods 1-1 to 4-2. When one pixel block 200 contains pixels 2600 of multiple colors, adjusting the exposure time of the pixel block 200 appropriately for one color may not be appropriate for the other colors. For example, if the pixel signal of a certain color becomes saturated, coloring that should not actually occur occurs in the pixels 2600 of that color.

[0275] For this reason, the control block 400 treats a group of pixels 2600 of the same color within the pixel block 200 as a pixel group, and makes it possible to set the exposure time in pixel group units.

[0276] Fig. 41 is an explanatory diagram showing pixel group unit exposure control example 1. Fig. 41 is a control example when the exposure time adjustment method is PD reset, but it is also applicable when the exposure time adjustment method is PD → FD transfer.

[0277] The pixel block 200 has a plurality of pixels 2600 arranged in a Bayer array. Here, as an example, the red pixels 2600 belong to pixel group A, the green pixels 2600 sandwiched between the red pixels 2600 in the row direction belong to pixel group B, the green pixels 2600 sandwiched between the red pixels 2600 in the column direction belong to pixel group C, and the blue pixels 2600 belong to pixel group D. Note that, because pixel groups B and C are both green pixels 2600, they may be combined into one pixel group.

[0278] The control block 400 executes PD reset 4100A for pixel group A, PD reset 4100B for pixel group B, PD reset 4100C for pixel group C, and PD reset 4100D for pixel group D at the timing when exposure of each of pixel groups A to D starts.

[0279] In addition, when the exposure time adjustment method is PD → FD transfer, the control block 400 performs PD → FD transfer for pixel group A, PD → FD transfer for pixel group B, PD → FD transfer for pixel group C, and PD → FD transfer for pixel group D at the timing when the exposure of each of pixel groups A to D ends.

[0280] Fig. 42 is an explanatory diagram showing an example of wiring in pixel group unit exposure control. Fig. 42 shows an example of wiring when the exposure time adjustment method is PD reset, but even if the exposure time adjustment method is PD → FD transfer, connections are made according to an appropriate connection relationship. In the pixels 2600, "R" is a red pixel 2600 belonging to pixel group A, "Ga" is a green pixel 2600 belonging to pixel group B, "Gb" is a green pixel 2600 belonging to pixel group C, and "B" is a blue pixel 2600 belonging to pixel group D.

[0281] 42, the symbols R, Ga, Gb, and B at the end of TX2 indicate the discharge control signal φPDRST input to the pixels 2600 of the colors R, Ga, Gb, and B. For example, TX2_Ga is the discharge control signal φPDRST input to the green pixel 2600 (Ga) belonging to pixel group B. The symbol i at the end of SEL, TX1, and RST indicates the row number of the pixel row to which the selection signal SEL, the second transfer control signal φTX2, and the reset control signal RST are input.

[0282] The control line 4201R is connected to the green pixels 2600(R) belonging to pixel group A and supplies a discharge control signal φPDRST_R to the red pixels 2600(R). The control line 4201Ga is connected to the green pixels 2600(Ga) belonging to pixel group B and supplies a discharge control signal φPDRST_Ga to the green pixels 2600(Ga). The control line 4201Gb is connected to the green pixels 2600(Gb) belonging to pixel group C and supplies a discharge control signal φPDRST_Gb to the green pixels 2600(Gb). The control line 4201B is connected to the blue pixels 2600(B) belonging to pixel group D and supplies a discharge control signal φPDRST_B to the blue pixels 2600(B).

[0283] The control line 4202 is connected to each pixel 2600 in the same pixel row, and supplies a first transfer control signal φTX1 to the gate terminal of the first transfer unit 2613 of the pixel 2600. The first transfer control signal φTX1 is a signal that is globally controlled simultaneously over the entire surface of the pixel unit 101.

[0284] The control line 4203 is connected to each pixel 2600 in the same pixel row, and supplies a selection signal SEL to the gate terminal of the selection unit 352 of the pixel 2600. The selection signal SEL is a signal that is globally controlled for each pixel row.

[0285] The control line 4204 is connected to each pixel 2600 in the same pixel row, and supplies the second transfer control signal φTX2 to the gate terminal of the second transfer unit 301 of the pixel 2600. The second transfer control signal φTX2 is a signal that is globally controlled for each pixel row.

[0286] The control line 4205 is connected to each pixel 2600 in the same pixel row, and supplies a reset control signal RST to the gate terminal of the reset unit 304 of the pixel 2600. The reset control signal RST is a signal that is globally controlled for each pixel row.

[0287] In this way, by executing pixel group unit exposure control, it is possible to set an appropriate exposure time for each color, and to suppress color shifts caused by inappropriate exposure times.

[0288] Fig. 43 is an explanatory diagram showing pixel group unit exposure control example 2. While pixel group unit exposure control example 1 in Fig. 41 takes an RGB color image sensor as an example, Fig. 43 shows an example of pixel group unit exposure control for image sensor 100 which is a monochrome image sensor with only white pixels. The white pixels are pixels 2600 which are provided with transparent filters instead of color filters 703.

[0289] In FIG. 43, among the pixels 2600 in a pixel block 200 containing only white pixels, pixel 2600 “A” belongs to pixel group A, pixel 2600 “B” belongs to pixel group B, pixel 2600 “C” belongs to pixel group C, and pixel 2600 “D” belongs to pixel group D.

[0290] At the start of exposure for each of pixel groups A to D, control block 400 executes PD reset 4100A for pixel group A, PD reset 4100B for pixel group B, PD reset 4100C for pixel group C, and PD reset 4100D for pixel group D. This allows control block 400 to set different exposure times for each of pixel groups A to D.

[0291] By applying pixel group unit exposure control to a monochrome image sensor as well, it is possible to suppress a lack of dynamic range when both a high-brightness subject and a low-brightness subject are captured within one pixel block 200.

[0292] Figures 44 and 45 are explanatory diagrams showing pixel group unit exposure control example 3. While pixel group unit exposure control example 1 in Figure 41 took an RGB color image sensor as an example, Figures 44 and 45 show an example in which the pixel block 200 is configured in a so-called quad Bayer array. In other words, Figures 44 and 45 show an example in which each pixel 2600 of a 2 x 2 pixel array of the same color belongs to a different pixel group.

[0293] 44 or 45, for example, the control block 400 can set shorter or longer exposure times for pixel groups A, B, C, and D in that order. Also, it is possible to set the exposure time for only a specific pixel group A to be shorter or longer than that of the other pixel groups B to D.

[0294] <Autonomous exposure control with additional memory 2> Next, autonomous exposure control 2 with the basic configuration described above will be explained using the addition of memory. Autonomous exposure control 2 with the addition of memory is an example in which a memory that holds a voltage corresponding to an electric charge is provided on the signal line 202 to realize a global shutter for each pixel block 200, thereby suppressing image distortion caused by reading out analog pixel signals, and will be explained using Figures 46 to 50.

[0295] 46 is a circuit diagram showing circuit configuration example 1 of autonomous exposure control 2 with additional memory. In FIG. 46, the pixel 201 has a circuit configuration in which the discharge portion 302 is not provided. The signal line 202 is wired from the first semiconductor substrate 110 to the second semiconductor substrate 120 via a bonding portion 610 at which a bonding pad 714a of the first semiconductor substrate 110 is bonded to a bonding pad 714b of the second semiconductor substrate 120. The signal line 202 branches into a first signal line 4621 and a second signal line 4622 on the second semiconductor substrate 120 and is connected to a readout circuit 4610.

[0296] Between the junction 610 and the readout circuit 4610, a first switch 4601 and a first memory 4611 are connected in series to a first signal line 4621. Similarly, between the junction 610 and the readout circuit 4610, a second switch 4602 and a second memory 4612 are connected in series to a second signal line 4622.

[0297] The first switch 4601 controls the output of a dark signal to a first memory 4611. The dark signal is a voltage signal related to the charge remaining in the FD 303 before FD readout. When a first switching control signal sw_d is input to the gate terminal of the first switch 4601, the first switch 4601 outputs the dark signal to the first memory 4611, and when the first switching control signal sw_d is not input to the gate terminal of the first switch 4601, the first switch 4601 does not output the dark signal to the first memory 4611. The first memory 4611 is connected to the readout circuit 4610 and is a memory that holds the dark signal.

[0298] The second switch 4602 controls the output of a voltage signal (hereinafter referred to as FD voltage signal) relating to the charge accumulated in the FD 303 after the dark signal is output to the second memory 4612. When the second switching control signal sw_s is input to the gate terminal of the second switch 4602, the second switch 4602 outputs the dark signal to the second memory 4612, and when the second switching control signal sw_s is not input to the gate terminal of the second switch 4602, the second switch 4602 does not output the FD voltage signal to the second memory 4612. The second memory 4612 is connected to the readout circuit 4610 and is a memory that holds the FD voltage signal.

[0299] The readout circuit 4610 is, for example, a CDS (Correlated Double Sampling) circuit, which reads out the difference between the FD voltage signal from the second memory 4612 and the dark signal from the first memory 4611, and outputs it to the signal conversion unit 422 as an analog pixel signal.

[0300] Fig. 47 is an explanatory diagram showing an example of the operation of autonomous exposure control in units of pixel blocks 200 in circuit configuration example 1 shown in Fig. 46, and Fig. 48 is a pulse chart showing an example of the operation of autonomous exposure control in units of pixel blocks 200 in circuit configuration example 1 shown in Fig. 46. In Fig. 47 and Fig. 48, it is assumed that in each of pixel blocks 200-1 to 200-4, PD reset is performed under local control using the second transfer control signal φTX2 and the reset control signal RST, and memory transfer of the dark signal and FD voltage signal is performed under global control using the second transfer control signal φTX2 and the reset control signal RST.

[0301] In this memory transfer, under collective control of the entire pixel unit 101, the first switch 4601 outputs a dark signal to the first memory 4611 in response to the input of the first switching control signal sw_d, and the second switch 4602 outputs an FD voltage signal to the second memory 4612 in response to the input of the second switching control signal sw_s. As a result, the dark signal is held in the first memory 4611, and the FD voltage signal is held in the second memory 4612.

[0302] During the memory readout period, signal readout is performed under global control in each of the pixel blocks 200-1 to 200-4. Specifically, for example, in each of the pixel blocks 200-1 to 200-4, dark signals are read out from the first memory 4611 in a rolling manner for each pixel row, and then FD voltage signals are read out from the second memory 4612 in a rolling manner.

[0303] In this way, by storing the dark signal in the first memory 4611 and the FD voltage signal in the second memory 4612, it becomes possible to perform PD reset at the same time by local control for all pixels 201 in the pixel block 200. Therefore, global transfer of the dark signal and FD voltage signal becomes possible, and distortion due to rolling readout for each pixel block 200 is eliminated.

[0304] 49 is a circuit diagram showing a circuit configuration example 2 of autonomous exposure control 2 with additional memory. In FIG. 49, a pixel 201 has a circuit configuration in which a discharge unit 302 is provided.

[0305] Fig. 50 is a pulse chart showing an example of the operation of autonomous exposure control in units of pixel blocks 200 in circuit configuration example 2 shown in Fig. 49. The example of the operation of autonomous exposure control in units of pixel blocks 200 in circuit configuration example 2 is the same as that in Fig. 47, so a description thereof will be omitted.

[0306] 47 and 50, it is assumed that in each of the pixel blocks 200-1 to 200-4, the PD reset is performed under local control using the discharge control signal φPDRST, and the memory transfer of the dark signal and the FD voltage signal is performed under global control using the second transfer control signal φTX2 and the reset control signal RST. In this memory transfer, under collective control of the entire pixel unit 101, the first switch 4601 outputs the dark signal to the first memory 4611 in response to the input of the first switching control signal sw_d, and the second switch 4602 outputs the FD voltage signal to the second memory 4612 in response to the input of the second switching control signal sw_s. As a result, the dark signal is held in the first memory 4611, and the FD voltage signal is held in the second memory 4612.

[0307] During the memory readout period, signal readout is performed under global control in each of the pixel blocks 200-1 to 200-4. Specifically, for example, in each of the pixel blocks 200-1 to 200-4, dark signals are read out from the first memory 4611 in a rolling manner for each pixel row, and then FD voltage signals are read out from the second memory 4612 in a rolling manner.

[0308] In this way, by storing the dark signal in the first memory 4611 and the FD voltage signal in the second memory 4612, it becomes possible to perform PD reset at the same timing by local control for all pixels 201 in the pixel block 200. This makes it possible to transfer the dark signal and FD voltage signal globally, eliminating distortion that accompanies rolling readout for each pixel block 200. Furthermore, in the case of circuit configuration example 2, local control is possible using only the discharge control signal φPDRST, which simplifies local control.

[0309] In the autonomous exposure control 2 with additional memory shown in FIGS. 46 to 50, the signal conversion unit 422 and the signal output unit 423 may be disposed on the third semiconductor substrate 130 instead of the second semiconductor substrate 120.

[0310] 51 is a block diagram showing an example of the configuration of an image capturing device 5100 according to an embodiment. The image capturing device 5100 includes an image sensor 100, a system control unit 5101, a drive unit 5102, a photometry unit 5103, a work memory 5104, a recording unit 5105, a display unit 5106, an operation unit 5108, a drive unit 5114, and a photographing lens 5120.

[0311] The photographing lens 5120 guides the subject light beam incident along the optical axis OA to the image sensor 100. The photographing lens 5120 is composed of a group of multiple optical lenses, and focuses the subject light beam from the scene near its focal plane. The photographing lens 5120 may be an interchangeable lens that can be attached to and detached from the image pickup device 5100. Note that in FIG. 51, the photographing lens 5120 is represented by a single virtual lens placed near the pupil.

[0312] The driver 5114 drives the photographing lens 5120. For example, the driver 5114 changes the focus position by moving the optical lens group of the photographing lens 5120. The driver 5114 may also drive an iris diaphragm in the photographing lens 5120 to control the amount of subject light entering the image sensor 100.

[0313] The drive unit 5102 has a control circuit that executes charge accumulation control such as timing control and area control of the image sensor 100 in accordance with instructions from the system control unit 5101. The operation unit 5108 also receives instructions from the photographer using a release button or the like.

[0314] The image sensor 100 passes pixel signals to an image processing unit 5111 of the system control unit 5101. The image processing unit 5111 generates image data by performing various image processes using a work memory 5104 as a workspace. For example, when generating image data in JPEG file format, a color video signal is generated from a signal obtained using the Bayer array, and then compression processing is performed. The generated image data is recorded in a recording unit 5105 and converted into a display signal, which is displayed on a display unit 5106 for a preset time.

[0315] The photometry unit 5103 detects the luminance distribution of a scene prior to a series of shooting sequences for generating image data. The photometry unit 5103 includes, for example, an AE sensor with approximately one million pixels. The calculation unit 5112 of the system control unit 5101 receives the output of the photometry unit 5103 and calculates the luminance of each region of the scene.

[0316] The calculation unit 5112 determines the shutter speed, aperture value, and ISO sensitivity in accordance with the calculated luminance distribution. The image sensor 100 may also serve as the photometry unit 5103. The calculation unit 5112 also executes various calculations for operating the image capture device 5100. Part or all of the drive unit 5102 may be mounted on the image sensor 100. Part of the system control unit 5101 may be mounted on the image sensor 100.

[0317] The present invention is not limited to the above-described contents, and may be implemented by any combination thereof. Furthermore, other embodiments conceivable within the scope of the technical concept of the present invention are also included in the scope of the present invention. [Explanation of symbols]

[0318] 100, 100A, 100B imaging element, 101 pixel unit, 102 control circuit unit, 103 data processing unit, 110 first semiconductor substrate, 120 second semiconductor substrate, 121 peripheral circuit unit, 130 third semiconductor substrate, 200 pixel block, 201 pixel, 202 signal line, 210 pixel group, 300 photoelectric conversion unit, 301 transfer unit, 302 discharge unit, 304 reset unit, 305 pixel output unit, 306 load current source, 310 readout unit, 351 amplifier unit, 352 selection unit, 400, 400A, 400B control block, 401 pixel control unit, 402 signal transfer unit, 411 autonomous exposure processing unit, 412 exposure control unit, 413 pixel drive unit, 421 signal input unit, 422 signal processing unit, 423 signal output unit< / m>

Claims

1. A first semiconductor substrate having a pixel section including: a first photoelectric conversion unit that converts light into electric charge; a second photoelectric conversion unit that converts light into electric charge and is arranged in the row direction alongside the first photoelectric conversion unit; a first transfer unit that transfers the charge converted by the first photoelectric conversion unit; a second transfer unit that transfers the charge converted by the second photoelectric conversion unit; a first holding unit that holds the charge transferred from the first photoelectric conversion unit by the first transfer unit; a second holding unit that holds the charge transferred from the second photoelectric conversion unit by the second transfer unit; a first storage unit to which the charge held in the first holding unit is transferred; a second storage unit to which the charge held in the second holding unit is transferred; a first reset unit that discharges the charge from the first storage unit; and a second reset unit that discharges the charge from the second storage unit. A semiconductor substrate laminated together with the first semiconductor substrate, comprising: a first circuit section including a first control block that outputs a first transfer control signal for controlling the first transfer section and a second control block that outputs a second transfer control signal for controlling the second transfer section; and a second circuit section disposed outside the first circuit section and outputting a reset control signal for controlling the first reset section and the second reset section, The first transfer unit is electrically connected to the first transfer control line from which the first transfer control signal is output. The second transfer unit is electrically connected to the second transfer control line from which the second transfer control signal is output. The first reset unit and the second reset unit are electrically connected to a reset control line on which the reset control signal is output. Image sensor.

2. In the image sensor according to Claim 1, The first circuit section is positioned opposite the pixel section in the stacking direction in which the first semiconductor substrate and the second semiconductor substrate are stacked. Image sensor.

3. In the image sensor according to Claim 2, The pixel unit includes a third transfer unit that transfers the charge held in the first holding unit to the first storage unit, and a fourth transfer unit that transfers the charge held in the second holding unit to the second storage unit. The first control block outputs a third transfer control signal for controlling the third transfer unit. The second control block outputs a fourth transfer control signal for controlling the fourth transfer unit. The third transfer unit is electrically connected to the third transfer control line on which the third transfer control signal is output. The fourth transfer unit is electrically connected to the fourth transfer control line to which the fourth transfer control signal is output. Image sensor.

4. In the image sensor according to claim 3, The pixel portion includes a first discharge portion for discharging the charge of the first photoelectric conversion portion and a second discharge portion for discharging the charge of the second photoelectric conversion portion. The first control block outputs a first discharge control signal for controlling the first discharge unit. The second control block outputs a second discharge control signal for controlling the second discharge unit. The first discharge unit is electrically connected to the first discharge control line from which the first discharge control signal is output. The second discharge unit is electrically connected to the second discharge control line from which the second discharge control signal is output. Image sensor.

5. In the image sensor according to claim 2, The pixel unit includes a third transfer unit that transfers the charge held in the first holding unit to the first storage unit, and a fourth transfer unit that transfers the charge held in the second holding unit to the second storage unit. The second circuit unit outputs a third transfer control signal for controlling the third transfer unit and the fourth transfer unit. The third transfer unit and the fourth transfer unit are electrically connected to the third transfer control line on which the third transfer control signal is output. Image sensor.

6. In the image sensor according to claim 5, The pixel portion includes a first discharge portion for discharging the charge of the first photoelectric conversion portion and a second discharge portion for discharging the charge of the second photoelectric conversion portion. The first control block outputs a first discharge control signal for controlling the first discharge unit. The second control block outputs a second discharge control signal for controlling the second discharge unit. The first discharge unit is electrically connected to the first discharge control line from which the first discharge control signal is output. The second discharge unit is electrically connected to the second discharge control line from which the second discharge control signal is output. Image sensor.

7. In the image sensor according to claim 1, The pixel unit includes a third transfer unit that transfers the charge held in the first holding unit to the first storage unit, and a fourth transfer unit that transfers the charge held in the second holding unit to the second storage unit. The first control block outputs a third transfer control signal for controlling the third transfer unit. The second control block outputs a fourth transfer control signal for controlling the fourth transfer unit. The third transfer unit is electrically connected to the third transfer control line on which the third transfer control signal is output. The fourth transfer unit is electrically connected to the fourth transfer control line to which the fourth transfer control signal is output. Image sensor.

8. In the image sensor according to claim 7, The pixel portion includes a first discharge portion for discharging the charge of the first photoelectric conversion portion and a second discharge portion for discharging the charge of the second photoelectric conversion portion. The first control block outputs a first discharge control signal for controlling the first discharge unit. The second control block outputs a second discharge control signal for controlling the second discharge unit. The first discharge unit is electrically connected to the first discharge control line from which the first discharge control signal is output. The second discharge unit is electrically connected to the second discharge control line from which the second discharge control signal is output. Image sensor.

9. In the image sensor according to claim 1, The pixel unit includes a third transfer unit that transfers the charge held in the first holding unit to the first storage unit, and a fourth transfer unit that transfers the charge held in the second holding unit to the second storage unit. The second circuit unit outputs a third transfer control signal for controlling the third transfer unit and the fourth transfer unit. The third transfer unit and the fourth transfer unit are electrically connected to the third transfer control line on which the third transfer control signal is output. Image sensor.

10. In the image sensor according to claim 9, The pixel portion includes a first discharge portion for discharging the charge of the first photoelectric conversion portion and a second discharge portion for discharging the charge of the second photoelectric conversion portion. The first control block outputs a first discharge control signal for controlling the first discharge unit. The second control block outputs a second discharge control signal for controlling the second discharge unit. The first discharge unit is electrically connected to the first discharge control line from which the first discharge control signal is output. The second discharge unit is electrically connected to the second discharge control line from which the second discharge control signal is output. Image sensor.

11. In the image sensor according to claim 1, The pixel portion includes a first discharge portion for discharging the charge of the first photoelectric conversion portion and a second discharge portion for discharging the charge of the second photoelectric conversion portion. The first control block outputs a first discharge control signal for controlling the first discharge unit. The second control block outputs a second discharge control signal for controlling the second discharge unit. The first discharge unit is electrically connected to the first discharge control line from which the first discharge control signal is output. The second discharge unit is electrically connected to the second discharge control line from which the second discharge control signal is output. Image sensor.

12. An imaging device comprising the image sensor according to any one of claims 1 to 11.

13. In the imaging device according to claim 12, An imaging device comprising an image processing unit that is electrically connected to the image sensor and generates image data.

14. In the imaging device according to claim 12, An imaging device comprising an optical system for emitting light to the aforementioned image sensor.

15. In the image sensor according to any one of claims 1 to 11, The first control block performs signal processing on the first signal based on the charge converted by the first photoelectric conversion unit. The second control block performs signal processing on the second signal based on the charge converted by the second photoelectric conversion unit. Image sensor.

16. An imaging device comprising the image sensor described in Claim 15.

17. In the image sensor according to claim 15, The first control block converts the first signal into a first digital signal, The second control block converts the second signal into a second digital signal. Image sensor.

18. In the image sensor according to claim 17, An image sensor comprising a third semiconductor substrate, which is laminated together with the first semiconductor substrate, and which has a data processing unit that performs data processing using at least one of the first digital signal and the second digital signal.

19. In the image sensor according to claim 18, The data processing unit performs an addition operation using at least one of the first digital signal and the second digital signal. Image sensor.

20. In the image sensor according to claim 18, The data processing unit performs image processing using at least one of the first digital signal and the second digital signal. Image sensor.

21. In the image sensor according to any one of claims 1 to 11, The second semiconductor substrate has a first signal processing unit that performs signal processing on a first signal based on the charge converted by the first photoelectric conversion unit, and a second signal processing unit that performs signal processing on a second signal based on the charge converted by the second photoelectric conversion unit. Image sensor.

22. An imaging device comprising the image sensor described in Claim 21.

23. In the imaging device according to claim 22, An imaging device comprising an image processing unit that is electrically connected to the image sensor and generates image data.

24. In the imaging device according to claim 22, An imaging device comprising an optical system for emitting light to the aforementioned image sensor.

25. In the image sensor according to claim 21, The first signal processing unit is located outside the first circuit section on the second semiconductor substrate. The second signal processing unit is located outside the first circuit section on the second semiconductor substrate. Image sensor.

26. In the image sensor according to claim 25, The first signal processing unit converts the first signal into a first digital signal, The second signal processing unit converts the second signal into a second digital signal. Image sensor.

27. ​​In the image sensor according to claim 26, An image sensor comprising a third semiconductor substrate, which is laminated together with the first semiconductor substrate, and which has a data processing unit that performs data processing using at least one of the first digital signal and the second digital signal.

28. In the image sensor according to claim 27, The data processing unit performs an addition operation using at least one of the first digital signal and the second digital signal. Image sensor.

29. In the image sensor according to claim 27, The data processing unit performs image processing using at least one of the first digital signal and the second digital signal. Image sensor.

Images