Semiconductor device

Abstract

To provide a semiconductor device capable of reducing defects in sinter bonding.SOLUTION: The semiconductor device A1 includes a support body 1 including a base material 10 having a first main surface 11 facing a thickness direction z, a semiconductor device 6, and a bonding material 5 bonding the support body 1 and the semiconductor device 6. The bonding material 5 includes a sintered metal portion 501 and a resin portion 502. The support 1 includes a metal layer 19 located on the first main surface 11 and having a stronger sintered bond with the sintered metal portion 501 than the base material 10. The bonding material 5 includes a first portion 51 in contact with the semiconductor element 6 and the metal layer 19, and a second portion 52 in contact with the semiconductor element 6 and the support 1.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] An example of a conventional semiconductor device is disclosed in Patent Document 1. The semiconductor device disclosed in this document includes leads and a semiconductor element. The semiconductor element is joined to the leads by sintering. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2024-027893

[0004] [overview] If cracks or the like occur in the sintered bonded portion, the semiconductor device may not function properly.

[0005] The present disclosure has been made in light of the above circumstances, and an object of the present disclosure is to provide a semiconductor device that can reduce defects in sinter bonding.

[0006] The semiconductor device provided by the present disclosure comprises a support including a base material having a first main surface facing in the thickness direction, a semiconductor element, and a bonding material that bonds the support and the semiconductor element, wherein the bonding material includes a sintered metal portion and a resin portion, the support includes a metal layer located on the first main surface and having a stronger sintered bond with the sintered metal portion than the base material, and the bonding material includes a first portion in contact with the semiconductor element and the metal layer and a second portion in contact with the semiconductor element and the base material.

[0007] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a perspective view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 3] FIG. 3 is a partial plan view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 4] FIG. 4 is a partial plan view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 5] FIG. 5 is a bottom view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a partial cross-sectional view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 9] FIG. 9 is a partially enlarged cross-sectional view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 10] FIG. 10 is a partial plan view showing a first modified example of the semiconductor device according to the first embodiment of the present disclosure. [Figure 11] FIG. 11 is a partial plan view showing a second modified example of the semiconductor device according to the first embodiment of the present disclosure. [Figure 12] FIG. 12 is a partial plan view showing a third modified example of the semiconductor device according to the first embodiment of the present disclosure. [Figure 13] FIG. 13 is a partial plan view showing a fourth modified example of the semiconductor device according to the first embodiment of the present disclosure. [Figure 14] FIG. 14 is a partial plan view showing a fifth modified example of the semiconductor device according to the first embodiment of the present disclosure. [Figure 15] FIG. 15 is a partial plan view showing a semiconductor device according to the second embodiment of the present disclosure. [Figure 16] FIG. 16 is a partial plan view showing a first modified example of the semiconductor device according to the second embodiment of the present disclosure. [Figure 17]FIG. 17 is a partial plan view showing a second modified example of the semiconductor device according to the second embodiment of the present disclosure. [Figure 18] FIG. 18 is a partial plan view showing a semiconductor device according to a third embodiment of the present disclosure. [Figure 19] FIG. 19 is a partial cross-sectional view showing a semiconductor device according to a fourth embodiment of the present disclosure.

[0009] [Detailed explanation] Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0010] The terms "first," "second," "third," etc. in this disclosure are used for identification purposes only and are not intended to impose any ranking on their objects.

[0011] In this disclosure, unless otherwise specified, the terms "a certain object A is formed on an object B" and "a certain object A is formed on an object B" include "a certain object A is formed directly on an object B" and "a certain object A is formed on an object B with another object interposed between the objects A and B." Similarly, the terms "a certain object A is disposed on an object B" and "a certain object A is disposed on an object B" include "a certain object A is disposed directly on an object B" and "a certain object A is disposed on an object B with another object interposed between the objects A and B," unless otherwise specified. Similarly, the term "a certain object A is located on an object B" includes "a certain object A is located on an object B in contact with the object B" and "a certain object A is located on an object B with another object interposed between the objects A and B," unless otherwise specified. Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, in this disclosure, "a surface A faces (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0012] [First embodiment] 1 to 9, a semiconductor device A1 according to a first embodiment of the present disclosure will be described. The semiconductor device A1 includes a support 1, a bonding material 5, and a semiconductor element 6. The semiconductor device A1 may include leads 2, 3, 4, wires 71 to 73, and a sealing resin 8.

[0013] FIG. 1 is a perspective view showing the semiconductor device A1. FIG. 2 is a perspective view showing the semiconductor device A1. FIG. 3 is a partial plan view showing the semiconductor device A1. FIG. 4 is a partial plan view showing the semiconductor device A1. FIG. 5 is a bottom view showing the semiconductor device A1. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 3. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 3. FIG. 8 is a partial cross-sectional view showing the semiconductor device A1. FIG. 9 is a partially enlarged cross-sectional view showing the semiconductor device A1. In FIGS. 2 and 3, the sealing resin 8 is indicated by an imaginary line (double-dashed line).

[0014] In these figures, the thickness direction of the present disclosure is defined as thickness direction z. A first side of thickness direction z is referred to as first side z1, and a second side opposite the first side of thickness direction z is referred to as second side z2. A direction perpendicular to thickness direction z is defined as first direction x. A first side of first direction x is referred to as first side x1, and a second side opposite the first side x1 is referred to as second side x2. A direction perpendicular to thickness direction z and first direction x is defined as second direction y. A first side of second direction y is referred to as first side y1, and a second side opposite the first side y1 is referred to as second side y2.

[0015] The semiconductor device A1 may be a device surface-mounted on a circuit board of various devices. The use and function of the semiconductor device A1 are not limited. The package format of the semiconductor device A1 may be DFN (Dual Flatpack No-leaded). The package format of the semiconductor device A1 is not limited to DFN. The shape of the semiconductor device A1 when viewed in the thickness direction is rectangular. For convenience of explanation, the thickness direction (direction when viewed from above) of the semiconductor device A1 is referred to as the thickness direction z, the direction along one side of the semiconductor device A1 perpendicular to the thickness direction z (the left-right direction in FIG. 3) is referred to as the first direction x, and the direction perpendicular to the thickness direction z and the first direction x (the up-down direction in FIG. 3) is referred to as the second direction y. Furthermore, one side of the thickness direction z (the lower side in FIGS. 6 and 7) is referred to as the first side z1, and the other side (the upper side in FIGS. 6 and 7) is referred to as the second side z2. One side in the first direction x (the left side in FIGS. 3 and 5) is referred to as the first side x1, and the other side (the right side in FIGS. 3 and 5) is referred to as the second side x2. One side in the second direction y (the lower side in FIG. 3) is referred to as the first side y1, and the other side (the upper side in FIG. 3) is referred to as the second side y2. The dimensions of the semiconductor device A1 are not particularly limited, and in this embodiment, the dimension in the first direction x may be approximately 8 mm, the dimension in the second direction y may be approximately 8 mm, and the dimension in the thickness direction z may be approximately 1 mm, for example.

[0016] The support 1 supports the semiconductor element 6. The support 1 may be electrically connected to the semiconductor element 6 or may not be electrically connected to the semiconductor element 6. The leads 2, 3, and 4 are electrically connected to the semiconductor element 6. The support 1, 2, 3, and 4 are formed, for example, by etching or punching a metal plate. The support 1, 2, 3, and 4 contain a metal, preferably Cu or Ni, or an alloy thereof or a 42 alloy. In this embodiment, the support 1, 2, 3, and 4 contain Cu. The thickness of the support 1, 2, 3, and 4 is not particularly limited and may be, for example, 0.08 mm or more and 0.3 mm or less, and in this embodiment, it may be approximately 0.2 mm.

[0017] As shown in FIG. 3, the support 1 is disposed at an end of the semiconductor device A1 on the second side y2 in the second direction y and extends over the entire first direction x. The leads 2, 3, and 4 are disposed at an end of the semiconductor device A1 on the first side y1 in the second direction y, each spaced apart from the support 1, and are arranged side by side in the first direction x and spaced apart from each other. The lead 2 is disposed at a corner of the semiconductor device A1 on the first side x1 in the first direction x and on the first side y1 in the second direction y (the lower left corner in FIG. 3). The lead 3 is disposed at a corner of the semiconductor device A1 on the second side x2 in the first direction x and on the first side y1 in the second direction y (the lower right corner in FIG. 3). The lead 4 is disposed between the leads 2 and 3.

[0018] The support 1 supports the semiconductor element 6 and has a first main surface 11, a first back surface 12, a back surface recess 13, a plurality of terminal back surfaces 18, a plurality of terminal end surfaces 14, and a plurality of connecting end surfaces 15.

[0019] The first main surface 11 and the first back surface 12 face opposite each other in the thickness direction z. The first main surface 11 faces a second side z2 in the thickness direction z. The first main surface 11 is a surface on which a semiconductor element 6 is mounted. In this embodiment, the shape of the first main surface 11 is a rectangle elongated in the first direction x, with portions protruding on both sides of the first direction x and on a second side y2 in the second direction y. There are four protruding portions on the second side y2 in the second direction y, which are arranged at equal intervals in the first direction x, and each of them reaches the edge of the second side y2 in the second direction y of the semiconductor device A1. There are two protruding portions on the first side x1 in the first direction x, which are arranged in the second direction y, and each of them reaches the edge of the first side x1 in the first direction x of the semiconductor device A1. There are two protruding portions on the second side x2 in the first direction x, which are arranged in the second direction y, and each of them reaches the edge of the second side x2 in the first direction x of the semiconductor device A1. The first back surface 12 faces a first side z1 in the thickness direction z. The first back surface 12 is exposed from the sealing resin 8. In this embodiment, the shape of the first back surface 12 is a rectangle that is long in the first direction x.

[0020] The back surface side recess 13 is a portion of the support 1 recessed from the first back surface 12 toward the first main surface 11, and is arranged to surround the first back surface 12. The thickness (dimension in the thickness direction z) of the portion of the support 1 where the back surface side recess 13 is located is approximately half the thickness of the portion where the first back surface 12 is located. The back surface side recess 13 is formed, for example, by half-etching. As shown in FIG. 5 , the back surface side recess 13 is not exposed from the sealing resin 8, but is covered by the sealing resin 8. This prevents the support 1 from peeling off from the sealing resin 8 toward the first side z1 in the thickness direction z.

[0021] The multiple terminal back surfaces 18 are arranged on the second side y2 of the first back surface 12 in the second direction y. The multiple terminal back surfaces 18 face the first side z1 in the thickness direction z and are exposed from the sealing resin 8. The multiple terminal back surfaces 18 are at the same position as the first back surface 12 in the thickness direction z and are separated from the first back surface 12 by the sealing resin 8. Like the first back surface 12, the multiple terminal back surfaces 18 are portions that remain unetched when the back surface recess 13 is formed by the half-etching process. In this embodiment, there are four terminal back surfaces 18, which are arranged at equal intervals in the first direction x and all reach the edge of the semiconductor device A1 on the second side y2 in the second direction y.

[0022] The multiple terminal end faces 14 are surfaces that are perpendicular to the first main surface 11 and the first back surface 12 and face the second side y2 in the second direction y. Each terminal end face 14 is connected to one of the protruding portions of the first main surface 11 on the second side y2 in the second direction y and to one of the terminal back surfaces 18, and is exposed from the sealing resin 8. The terminal end faces 14 are formed by dicing in a cutting process in the manufacturing process. In this embodiment, there are four terminal end faces 14, each separated by the sealing resin 8 and lined up at equal intervals in the first direction x. Each terminal end face 14 and the terminal back surface 18 connected thereto form a terminal exposed from the sealing resin 8 (see FIGS. 5 and 7).

[0023] The multiple connecting end faces 15 are surfaces that are perpendicular to the first main surface 11 and the first back surface 12 and face the first direction x. Each connecting end face 15 is connected to the first main surface 11 and the back surface recess 13 and is exposed from the sealing resin 8. The connecting end faces 15 are formed by dicing in a cutting step in the manufacturing process. In this embodiment, the multiple connecting end faces 15 include two connecting end faces 15 facing a first side x1 in the first direction x and two connecting end faces 15 facing a second side x2 in the first direction x. The two connecting end faces 15 facing the first side x1 in the first direction x are separated by the sealing resin 8 and lined up in the second direction y. The two connecting end faces 15 facing the second side x2 in the first direction x are separated by the sealing resin 8 and lined up in the second direction y.

[0024] The shape of the support 1 is not limited to the above. For example, the support 1 may not have the terminal end surface 14 and the terminal back surface 18, and the terminal back surface 18 may be connected to the first back surface 12. Furthermore, the support 1 may not have the back surface recess 13.

[0025] The support 1 has a base material 10 and a metal layer 19. The base material 10 can include metal, resin, etc. In this embodiment, the base material 10 includes a metal, preferably either Cu or Ni, or an alloy thereof or a 42 alloy. Such a support 1 is referred to as a lead, for example. The base material 10 forms a first main surface 11, a first back surface 12, a back surface recess 13, a terminal end surface 14, and a connecting end surface 15.

[0026] The metal layer 19 is located on the first main surface 11. The material of the metal layer 19 has a stronger sintered bond with the sintered metal portion 501 of the bonding material 5 described below than with the base material 10. The metal layer 19 may contain, for example, Ag, Au, Pd, etc. The metal layer 19 may be formed by, for example, a plating process.

[0027] The size and shape of the metal layer 19 are not limited in any way. At least a portion of the metal layer 19 overlaps with the semiconductor element 6 when viewed in the thickness direction z. In the example shown in FIG. 4, the entire metal layer 19 overlaps with the semiconductor element 6 when viewed in the thickness direction z. In the example shown, the center of the semiconductor element 6 overlaps with the metal layer 19. The four corners of the semiconductor element 6 do not need to overlap with the metal layer 19 when viewed in the thickness direction z. In the example shown, the metal layer 19 is rectangular when viewed in the thickness direction z. The area of ​​the metal layer 19 may be, for example, 70% to 80% of the area of ​​the semiconductor element 6.

[0028] The lead 2 has a second main surface 21 , a second back surface 22 , a back surface recess 23 , a plurality of terminal end surfaces 24 , and a connecting end surface 25 .

[0029] The second main surface 21 and the second back surface 22 face opposite each other in the thickness direction z. The second main surface 21 faces the second side z2 in the thickness direction z. The second main surface 21 is the surface to which the wire 71 is bonded. In this embodiment, the second main surface 21 has a shape of an elongated rectangle that is long in the first direction x and has a portion that protrudes toward the first side y1 in the second direction y. There are two protruding portions, which are aligned in the first direction x and both reach the edge of the semiconductor device A1 on the first side y1 in the second direction y. The second back surface 22 faces the first side z1 in the thickness direction z. The second back surface 22 is exposed from the sealing resin 8 and serves as a back surface terminal. In this embodiment, the second back surface 22 has a U-shape that is open on the first side y1 in the second direction y. Both ends of the U-shape reach the edge of the semiconductor device A1 on the first side y1 in the second direction y.

[0030] The rear surface-side recess 23 is a portion of the lead 2 recessed from the second rear surface 22 toward the second main surface 21, and is disposed around the second rear surface 22. The thickness (dimension in the thickness direction z) of the portion of the lead 2 where the rear surface-side recess 23 is located is approximately half the thickness of the portion where the second rear surface 22 is located. The rear surface-side recess 23 is formed, for example, by half-etching. As shown in FIG. 5 , the rear surface-side recess 23 is not exposed from the sealing resin 8, but is covered by the sealing resin 8. This prevents the lead 2 from peeling off from the sealing resin 8 toward the first side z1 in the thickness direction z.

[0031] The multiple terminal end faces 24 are surfaces that are perpendicular to the second main surface 21 and the second back surface 22 and face the first side y1 in the second direction y. Each terminal end face 24 is connected to one of the protruding portions of the second main surface 21 and one of the two ends of the U-shape of the second back surface 22, and is exposed from the sealing resin 8. The terminal end faces 24 are formed by dicing in the cutting step of the manufacturing process. In this embodiment, there are two terminal end faces 24, which are spaced apart by the sealing resin 8 and lined up in the first direction x. Each terminal end face 24 and the second back surface 22 connected thereto form a terminal exposed from the sealing resin 8 (see FIGS. 2, 5, and 7).

[0032] The connecting end surface 25 is a surface that is perpendicular to the second main surface 21 and the second back surface 22 and faces the first side x1 in the first direction x. The connecting end surface 25 is connected to the second main surface 21 and the back surface-side recess 23, and is exposed from the sealing resin 8. The connecting end surface 25 is formed by dicing in a cutting step in the manufacturing process.

[0033] The shape of the lead 2 is not limited to the above. For example, the lead 2 does not need to have the rear surface recess 23.

[0034] The lead 3 has a third main surface 31 , a third back surface 32 , a back surface recess 33 , a terminal end surface 34 , and a connecting end surface 35 .

[0035] The third main surface 31 and the third back surface 32 face opposite each other in the thickness direction z. The third main surface 31 faces the second side z2 in the thickness direction z. The third main surface 31 is a surface to which the wire 73 is bonded. In this embodiment, the third main surface 31 has a shape of an elongated rectangle that is long in the first direction x and has a portion that protrudes toward the first side y1 in the second direction y. The protruding portion reaches the edge of the semiconductor device A1 on the first side y1 in the second direction y. The third back surface 32 faces the first side z1 in the thickness direction z. The third back surface 32 is exposed from the sealing resin 8 and serves as a back surface terminal. In this embodiment, the third back surface 32 has a rectangular shape. The third back surface 32 reaches the edge of the semiconductor device A1 on the first side y1 in the second direction y.

[0036] The rear surface-side recess 33 is a portion of the lead 3 recessed from the third rear surface 32 toward the third main surface 31, and is disposed around the third rear surface 32. The thickness (dimension in the thickness direction z) of the portion of the lead 3 where the rear surface-side recess 33 is located is approximately half the thickness of the portion where the third rear surface 32 is located. The rear surface-side recess 33 is formed, for example, by half-etching. As shown in FIG. 5 , the rear surface-side recess 33 is not exposed from the sealing resin 8, but is covered by the sealing resin 8. This prevents the lead 3 from peeling off from the sealing resin 8 toward the first side z1 in the thickness direction z.

[0037] The terminal end surface 34 is a surface that is perpendicular to the third main surface 31 and the third back surface 32 and faces the first side y1 in the second direction y. The terminal end surface 34 is connected to the protruding portion of the third main surface 31 and the second back surface 22, and is exposed from the sealing resin 8. The terminal end surface 34 is formed by dicing in a cutting step in the manufacturing process. The terminal end surface 34 and the third back surface 32 become terminals exposed from the sealing resin 8 (see FIGS. 2 and 5).

[0038] The connecting end surface 35 is a surface that is perpendicular to the third main surface 31 and the third back surface 32 and faces the second side x2 in the first direction x. The connecting end surface 35 connects the third main surface 31 and the back surface-side recess 33, and is exposed from the sealing resin 8. The connecting end surface 35 is formed by dicing in a cutting step in the manufacturing process.

[0039] The shape of the lead 3 is not limited to the above. For example, the lead 3 does not need to have the recess 33 on the rear surface side.

[0040] The lead 4 has a fourth main surface 41, a fourth back surface 42, a back surface recess 43, and a terminal end surface 44.

[0041] The fourth main surface 41 and the fourth back surface 42 face opposite each other in the thickness direction z. The fourth main surface 41 faces the second side z2 in the thickness direction z. The fourth main surface 41 is a surface to which the wire 72 is bonded. In this embodiment, the fourth main surface 41 has a rectangular shape with a portion protruding toward the first side y1 in the second direction y. The protruding portion reaches the edge of the semiconductor device A1 on the first side y1 in the second direction y. The fourth back surface 42 faces the first side z1 in the thickness direction z. The fourth back surface 42 is exposed from the sealing resin 8 and serves as a back surface terminal. In this embodiment, the fourth back surface 42 has a rectangular shape. The fourth back surface 42 reaches the edge of the semiconductor device A1 on the first side y1 in the second direction y.

[0042] The rear surface-side recess 43 is a portion of the lead 4 recessed from the fourth rear surface 42 toward the fourth main surface 41, and is disposed around the fourth rear surface 42. The thickness (dimension in the thickness direction z) of the portion of the lead 4 where the rear surface-side recess 43 is located is approximately half the thickness of the portion where the fourth rear surface 42 is located. The rear surface-side recess 43 is formed, for example, by half-etching. As shown in FIG. 5 , the rear surface-side recess 43 is not exposed from the sealing resin 8, but is covered by the sealing resin 8. This prevents the lead 4 from peeling off from the sealing resin 8 toward the first side z1 in the thickness direction z.

[0043] The terminal end surface 44 is a surface that is perpendicular to the fourth main surface 41 and the fourth back surface 42 and faces the first side y1 in the second direction y. The terminal end surface 44 is connected to the protruding portion of the fourth main surface 41 and the fourth back surface 42, and is exposed from the sealing resin 8. The terminal end surface 44 is formed by dicing in a cutting step in the manufacturing process. The terminal end surface 44 and the fourth back surface 42 become terminals exposed from the sealing resin 8 (see FIGS. 2 and 5).

[0044] The shape of the lead 4 is not limited to the above. For example, the lead 4 does not need to have the rear surface recess 43.

[0045] The semiconductor element 6 is an element that performs the electrical functions of the semiconductor device A1. The type of the semiconductor element 6 is not particularly limited. In this embodiment, the semiconductor element 6 may be a MOSFET (metal-oxide-semiconductor field-effect transistor). The semiconductor element 6 may be another switching element such as an IGBT (insulated gate bipolar transistor) or a HEMT (high electron mobility transistor). The semiconductor element 6 may have an element body 60, a first electrode 61, a second electrode 62, and a third electrode 63.

[0046] The element body 60 has a rectangular plate shape when viewed in the thickness direction z. The element body 60 includes a semiconductor material, and in this embodiment, includes Si (silicon). The element body 60 may include other semiconductor materials, such as SiC (silicon carbide) or GaN (gallium nitride). The element body 60 has a primary surface 6a and a back surface 6b. The primary surface 6a and the back surface 6b face opposite each other in the thickness direction z. The primary surface 6a faces a second side z2 in the thickness direction z. The back surface 6b faces a first side z1 in the thickness direction z. A first electrode 61 and a second electrode 62 are disposed on the primary surface 6a. A third electrode 63 is disposed on the back surface 6b. In this embodiment, the first electrode 61 is a source electrode, the second electrode 62 is a gate electrode, and the third electrode 63 is a drain electrode. The material of the bonding material 5 of the third electrode 63, which will be described later, is preferably a material suitable for sintering and bonding with the sintered metal portion 501, and may include, for example, Ag, Au, Pd, or the like.

[0047] 6 and 7, the semiconductor element 6 is mounted approximately at the center of the first main surface 11 of the support body 1 via a bonding material 5. The semiconductor element 6 has a back surface 6b bonded to the first main surface 11 of the support body 1 via the bonding material 5. In this embodiment, the third electrode 63 of the semiconductor element 6 is electrically connected to the support body 1 via the bonding material 5. As a result, the support body 1 is electrically connected to the third electrode 63 (drain electrode) of the semiconductor element 6 and functions as a drain terminal.

[0048] As shown in FIG. 9 , the bonding material 5 includes a sintered metal portion 501 and a resin portion 502. The sintered metal portion 501 may include a metal such as Ag or Cu. The sintered metal portions 501 are sintered and bonded to each other by a sintering process, which may create minute gaps. The resin portion 502 may fill the minute gaps created by the sintered metal portion 501. The resin portion 502 may include, for example, an epoxy resin, an acrylic resin, or the like, and may have heat shrinkability.

[0049] The bonding material 5 includes a first portion 51 and a second portion 52. The first portion 51 contacts the semiconductor element 6 and the metal layer 19. In the illustrated example, the first portion 51 contacts the third electrode 63. The second portion 52 contacts the semiconductor element 6 and the base material 10. In the illustrated example, the second portion 52 contacts the third electrode 63. In FIG. 4, for ease of understanding, the metal layer 19 is indicated by a shaded line (dotted line), the first portion 51 is hatched with a plurality of discrete dots, and the second portion 52 is hatched with a plurality of oblique lines.

[0050] In the first portion 51, the sintered metal portion 501 is joined to the third electrode 63 by sintering. The sintered metal portion 501 is joined to the metal layer 19 by sintering. As a result, the third electrode 63 and the metal layer 19 are joined via the sintered metal portion 501 of the joining material 5, and in the example shown, they are electrically joined. In the first portion 51, the bonding force of the sintered metal portion 501 between the third electrode 63 and the metal layer 19 is stronger and may be dominant than the bonding force between the resin portion 502 and the third electrode 63. If the semiconductor element 6 has a metal layer (not shown) that does not perform an electrical function, different from the third electrode 63, the semiconductor element 6 may be configured not to be electrically connected to the support 1.

[0051] In the second portion 52, the strength of the sintered bond between the sintered metal portion 501 and the base material 10 is weaker than the strength of the sintered bond between the sintered metal portion 501 and the metal layer 19. Therefore, the bonding strength between the resin portion 502 and the base material 10 is stronger than the bonding strength between the sintered metal portion 501 and the base material 10, and may be dominant.

[0052] The bonding material 5 may protrude from the semiconductor element 6 when viewed in the thickness direction z, or may entirely overlap the semiconductor element 6 .

[0053] As shown in FIG. 3, the second electrode 62 of the semiconductor element 6 is conductively connected to the lead 3 via a wire 73. As a result, the lead 3 is conductively connected to the second electrode 62 (gate electrode) of the semiconductor element 6 and functions as a gate terminal. Furthermore, as shown in FIG. 3, the first electrode 61 of the semiconductor element 6 is conductively connected to the lead 2 via a wire 71. As a result, the lead 2 is conductively connected to the first electrode 61 (source electrode) of the semiconductor element 6 and functions as a source terminal. Furthermore, as shown in FIG. 3, the first electrode 61 of the semiconductor element 6 is also conductively connected to the lead 4 via a wire 72. As a result, the lead 4 is conductively connected to the first electrode 61 (source electrode) of the semiconductor element 6 and functions as a sense source terminal. The sense source terminal is a terminal for detecting the potential of the first electrode 61 (source electrode).

[0054] The wires 71 to 73 connect the semiconductor element 6 to the lead 2, the lead 3, and the lead 4, and provide electrical continuity therebetween. The wires 71 to 73 include metals such as Cu, Au, Ag, and Al. The material of the wires 71 to 73 is not limited. As shown in FIG. 3 , each of the multiple wires 71 is bonded to the first electrode 61 of the semiconductor element 6 and the second main surface 21 of the lead 2. In this embodiment, the first electrode 61 is connected to the support 1 by six wires 71. The number of wires 71 is not limited. The wire 72 is bonded to the first electrode 61 of the semiconductor element 6 and the fourth main surface 41 of the lead 4. In this embodiment, the first electrode 61 is connected to the lead 4 by one wire 72. The number of wires 72 is not limited. The wire 73 is bonded to the second electrode 62 of the semiconductor element 6 and the third main surface 31 of the lead 3. In this embodiment, the second electrode 62 is connected to the lead 3 by one wire 73. There is no limitation on the number of wires 73. In addition, instead of the wires 71 to 74, other conductive members such as conductive members made of a metal plate material may be used.

[0055] The sealing resin 8 covers the support 1, parts of the leads 2, 3, and 4, the semiconductor element 6, the bonding material 5, and the wires 71 to 73. The sealing resin 8 is made of, for example, a black epoxy resin. The material of the sealing resin 8 is not limited.

[0056] The sealing resin 8 has a resin main surface 81, a resin back surface 82, and four resin side surfaces 83. The resin main surface 81 and the resin back surface 82 face opposite each other in the thickness direction z. The resin main surface 81 faces a second side z2 in the thickness direction z, and the resin back surface 82 faces a first side z1 in the thickness direction z.

[0057] The four resin side surfaces 83 are each perpendicular to the resin main surface 81 and the resin back surface 82, connect the resin main surface 81 and the resin back surface 82, and face outward in the first direction x or the second direction y. Each resin side surface 83 is formed by dicing in a cutting step in the manufacturing process. The four resin side surfaces 83 include a resin side surface 831, a resin side surface 832, a resin side surface 833, and a resin side surface 834. The resin side surface 831 and the resin side surface 832 face opposite each other in the first direction x. The resin side surface 831 is a surface disposed on a first side x1 in the first direction x and faces the first side x1 in the first direction x, and the resin side surface 832 is a surface disposed on a second side x2 in the first direction x and faces the second side x2 in the first direction x. The resin side surface 833 and the resin side surface 834 face opposite each other in the second direction y. The resin side surface 833 is a surface that is positioned on a first side y1 in the second direction y and faces the first side y1 in the second direction y, and the resin side surface 834 is a surface that is positioned on a second side y2 in the second direction y and faces the second side y2 in the second direction y.

[0058] As shown in Figures 2 and 5, the first back surface 12 and multiple terminal back surfaces 18 of the support body 1, the second back surface 22 of the lead 2, the third back surface 32 of the lead 3, and the fourth back surface 42 of the lead 4 are exposed from the resin back surface 82 of the sealing resin 8 and are flush with each other.

[0059] Two connecting end faces 15 of support 1 facing a first side x1 in the first direction x and connecting end face 25 of lead 2 are exposed from a resin side surface 831 and are flush with each other. Two connecting end faces 15 of support 1 facing a second side x2 in the first direction x and connecting end face 35 of lead 3 are exposed from a resin side surface 832 and are flush with each other. Multiple terminal end faces 24 of lead 2, terminal end face 34 of lead 3, and terminal end face 44 of lead 4 are exposed from a resin side surface 833 and are flush with each other. Multiple terminal end faces 14 of support 1 are exposed from a resin side surface 834 and are flush with each other.

[0060] Next, the operation of the semiconductor device A1 will be described.

[0061] As shown in FIGS. 4 and 6 to 9 , the bonding material 5 includes a first portion 51 and a second portion 52. The first portion 51 has a relatively strong sintered bond due to the sintered metal portion 501. On the other hand, the second portion 52 has a relatively strong bond due to the resin portion 502. This allows for a stronger bond due to the first portion 51 while providing flexibility due to the bond due to the second portion 52. Unlike this embodiment, if the entire bonding material 5 corresponds to the first portion 51, strong sintering bonding is achieved across the entire bonding material 5, which may result in excessive stress, such as thermal stress. Such stress may cause defects, such as cracking and peeling, in the bonding material 5. However, according to this embodiment, the flexibility of the second portion 52 makes it possible to suppress excessive stress. Therefore, defects in the bonding material 5 can be reduced.

[0062] The semiconductor element 6 has a rectangular shape when viewed in the thickness direction z, and the four corners of the semiconductor element 6 do not overlap the metal layer 19 when viewed in the thickness direction z. The four corners of the semiconductor element 6 are joined to the base material 10 by the second portions 52. When the semiconductor element 6 repeatedly generates heat during use of the semiconductor device A1, excessive stress is likely to be generated in the portions of the bonding material 5 that bond the four corners of the semiconductor element 6. In this embodiment, the second portions 52 can deform more flexibly at the four corners of the semiconductor element 6, which makes it possible to prevent excessive stress from being generated in the bonding material 5. This is therefore preferable for reducing defects in the bonding material 5.

[0063] The metal layer 19 has a rectangular shape when viewed in the thickness direction z. When a semiconductor element 6 of the illustrated size is mounted on the support 1, the metal layer 19 is smaller than the semiconductor element 6. This causes the four corners of the semiconductor element 6 to protrude from the metal layer 19. On the other hand, when a semiconductor element 6 of a size equal to or smaller than the metal layer 19 is mounted on the support 1, the semiconductor element 6 can be bonded to the metal layer 19 only by the first portion 51. When the semiconductor element 6 is small, stress generated at the four corners of the semiconductor element 6 can be significantly reduced. Therefore, even when the semiconductor element 6 is bonded to the metal layer 19 only by the first portion 51, defects such as cracks and peeling are unlikely to occur, and the entire surface of the third electrode 63 can be conductively bonded to the metal layer 19 by sintering. This is advantageous for reducing resistance and promoting heat transfer between the semiconductor element 6 and the support 1.

[0064] The semiconductor element 6 of this embodiment is a switching element including a MOSFET. Switching elements are required to switch large currents, and heat generation due to current flow is often significant. This embodiment has the advantage of being suitable for the passage of large currents due to its low resistance, and of facilitating heat dissipation from the semiconductor element 6.

[0065] Since the first rear surface 12 of the support body 1 is exposed from the sealing resin 8, heat dissipation from the semiconductor element 6 can be further promoted.

[0066] 10 to 19 show other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are given the same reference numerals. Furthermore, the configurations of the various parts in each of the modified examples and each of the embodiments can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0067] 10 shows a first modified example of the semiconductor device A11. In the semiconductor device A11 of this modification, the configurations of the metal layer 19, the first portion 51, and the second portion 52 are different from those in the above-described example.

[0068] In this modification, the metal layer 19 has a cross shape when viewed in the thickness direction z. The metal layer 19 includes a portion extending in the first direction x and a portion extending in the second direction y. When viewed in the thickness direction z, the metal layer 19 can overlap the center of the semiconductor element 6. When viewed in the thickness direction z, the four corners of the semiconductor element 6 do not overlap with the metal layer 19. When viewed in the thickness direction z, the metal layer 19 protrudes from the semiconductor element 6 in the first direction x and the second direction y.

[0069] Corresponding to the shape of the metal layer 19, the first portion 51 has a cross shape when viewed in the thickness direction z. The first portion 51 includes a portion extending along the first direction x and a portion extending along the second direction y. The bonding material 5 of this modified example includes a plurality of second portions 52. Specifically, the bonding material 5 includes four second portions 52 separated from each other by the first portions 51. Each of the four second portions 52 overlaps one of the four corners of the semiconductor element 6.

[0070] This modification can reduce defects in the bonding material 5. As can be seen from this modification, the shape and size of the metal layer 19 are not limited in any way. By making the metal layer 19 cross-shaped, it is possible to enlarge the size of the first portion 51 while ensuring that the four corners of the semiconductor element 6 do not overlap with the metal layer 19. This is preferable for improving the bonding strength between the semiconductor element 6 and the support 1.

[0071] Since the metal layer 19 is configured to protrude from the semiconductor element 6, when a semiconductor element 6 larger than the illustrated semiconductor element 6 is mounted, the bonding material 5 can be configured to include the illustrated first portion 51 and four second portions 52. Therefore, it is possible to accommodate semiconductor elements 6 of a wider variety of sizes.

[0072] 11 shows a second modified example of the semiconductor device A1. In the semiconductor device A12 of this modified example, the metal layer 19 is strip-shaped and extends in the first direction x. The metal layer 19 does not extend beyond the semiconductor element 6 in the second direction y. The metal layer 19 does not overlap the four corners of the semiconductor element 6, but may overlap the center of the semiconductor element 6.

[0073] This modification can reduce defects in the bonding material 5. This modification also has the effect of preventing the four corners of the semiconductor element 6 from overlapping with the metal layer 19.

[0074] 12 shows a third modified example of the semiconductor device A1. In the semiconductor device A13 of this modified example, the metal layer 19 is strip-shaped and extends in the first direction x. The metal layer 19 overlaps with two of the four corners of the semiconductor element 6 that are located on the first side y1 in the second direction y, but does not overlap with two that are located on the second side y2. The metal layer 19 may or may not overlap with the center of the semiconductor element 6.

[0075] This modification can reduce defects in the bonding material 5. For example, thermal deformation of the semiconductor element 6 can become asymmetric when viewed in the thickness direction z depending on the shape, internal structure, heat generation mode, or configuration of the conductive member including the wire 71 of the semiconductor element 6. In such a case, defects in the bonding material 5 can be reduced by using a configuration in which two of the four corners of the semiconductor element 6 that are subject to relatively little thermal deformation are bonded by the first portion 51 and the other two are bonded by the second portion 52.

[0076] FIG. 13 shows a fourth modified example of the semiconductor device A1. In a semiconductor device A14 of this modified example, the metal layer 19 is strip-shaped extending in the second direction y and does not overlap with the four corners of the semiconductor element 6. FIG. 14 shows a fifth modified example of the semiconductor device A1. In a semiconductor device A15 of this modified example, the metal layer 19 overlaps with two of the four corners of the semiconductor element 6 located on the first side x1 in the first direction x and does not overlap with two located on the second side x2. This configuration can be expected to produce the same effects as the semiconductor devices A12 and A13. Furthermore, when the metal layer 19 is strip-shaped, the direction in which the metal layer 19 extends is not limited in any way and may be the first direction x, the second direction y, or a direction inclined relative to both the first direction x and the second direction y.

[0077] 15 shows a semiconductor device according to a second embodiment of the present disclosure. In the semiconductor device A2 of this embodiment, the metal layer 19 includes a plurality of individual regions 191.

[0078] The multiple individual regions 191 are spaced apart from one another when viewed in the thickness direction z. The number, shape, size, and relative positional relationship of the multiple individual regions 191 are not limited in any way. In the illustrated example, each of the multiple individual regions 191 is strip-shaped and extends along the first direction x. The multiple individual regions 191 are aligned in the second direction y. The multiple individual regions 191 do not have to overlap with the four corners of the semiconductor element 6. Any of the multiple individual regions 191 may overlap with the center of the semiconductor element 6.

[0079] Corresponding to the configuration of the metal layer 19, the bonding material 5 includes a plurality of first portions 51 and a plurality of second portions 52. The plurality of first portions 51 and the plurality of second portions 52 each have a strip shape extending in the first direction x.

[0080] This embodiment can reduce defects in the bonding material 5. Since the metal layer 19 includes a plurality of individual regions 191, stress that may occur in the first portion 51 can be reduced.

[0081] 16 shows a first modified example of the semiconductor device A2. In the semiconductor device A21 of this modified example, the multiple individual regions 191 each extend in the second direction y. This modified example can achieve the same effect as the semiconductor device A2. As can be seen from this modified example, when each of the multiple individual regions 191 is strip-shaped, the direction in which each of the multiple individual regions 191 extends is not limited in any way and may be the first direction x, the second direction y, or a direction inclined relative to both the first direction x and the second direction y.

[0082] 17 shows a second modified example of the semiconductor device A2. In the semiconductor device A22 of this modified example, a plurality of individual regions 191 are arranged in a matrix.

[0083] The individual regions 191 are spaced apart from one another in the first direction x and the second direction y. In the illustrated example, the individual regions 191 are arranged in a matrix along the first direction x and the second direction y.

[0084] This modification can reduce defects in the bonding material 5. The arrangement of the multiple individual regions 191 spaced apart from one another in a two-dimensional manner can reduce stress that may occur in the first part 51. Examples of the arrangement of the multiple individual regions 191 spaced apart from one another in a two-dimensional manner are not limited to the example shown in the drawings, and may be, for example, a staggered arrangement or an irregular arrangement.

[0085] 18 shows a semiconductor device according to a third embodiment of the present disclosure. In the semiconductor device A3 of this embodiment, the metal layer 19 includes a plurality of individual regions 191. In the example shown, the metal layer 19 includes four individual regions 191. Each of the four individual regions 191 overlaps one of the four corners of the semiconductor element 6.

[0086] In the present embodiment, the bonding material 5 includes a plurality of first portions 51 and one second portion 52 corresponding to the configuration of the metal layer 19. The second portion 52 has a cross shape when viewed in the thickness direction z, and separates the plurality of first portions 51. Each of the plurality of first portions 51 bonds one of the four corners of the semiconductor element 6 to the metal layer 19.

[0087] This embodiment can reduce defects in the bonding material 5. Each of the multiple individual regions 191 overlaps one of the four corners of the semiconductor element 6, so that the four corners of the semiconductor element 6 can be relatively firmly bonded to the metal layer 19 (support 1). On the other hand, since the multiple individual regions 191 are spaced apart from one another, the multiple first portions 51 can move independently. This makes it possible to bond the four corners of the semiconductor element 6 more firmly while reducing stress that may occur in the bonding material 5 (first portions 51).

[0088] 19 shows a semiconductor device according to a fourth embodiment of the present disclosure. In the semiconductor device A4 of this embodiment, the base material 10 contains resin. An example of such a support 1 is a printed wiring board. The base material 10 may contain, for example, glass epoxy resin.

[0089] This embodiment can reduce defects in the bonding material 5. As can be seen from this embodiment, the base material 10 can be made of various materials such as metal and resin, as appropriate.

[0090] The semiconductor device according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the semiconductor device according to the present disclosure can be freely modified in various ways.

[0091] [Appendix 1] A support (1) including a base material (10) having a first main surface (11) facing in a thickness direction (z); A semiconductor element (6), a bonding material (5) that bonds the support (1) and the semiconductor element (6), The joining material (5) includes a sintered metal part (501) and a resin part (502), the support (1) includes a metal layer (19) located on the first main surface (11) and having a stronger sintered bond with the sintered metal portion (501) than with the base material (10), The semiconductor device (A1) includes a first portion (51) in contact with the semiconductor element (6) and the metal layer (19), and a second portion (52) in contact with the semiconductor element (6) and the base material (10). [Appendix 2] The semiconductor device (A1) according to Appendix 1, wherein the semiconductor element (6) is electrically connected to the support (1). [Appendix 2-1] The semiconductor device (A1) according to Appendix 2, wherein the semiconductor element (6) has a third electrode (63) electrically connected to the support (1) by the bonding material (5). [Appendix 3] 3. The semiconductor device (A1) according to claim 1 or 2, wherein the metal layer (19) overlaps only a portion of the semiconductor element (6) when viewed in the thickness direction (z). [Appendix 4] The semiconductor element (6) has a rectangular shape when viewed in the thickness direction (z), 4. The semiconductor device (A1) according to claim 3, wherein four corners of the semiconductor element (6) do not overlap with the metal layer (19) when viewed in the thickness direction (z). [Appendix 4-1] 5. The semiconductor device (A1) according to claim 4, wherein the metal layer (19) overlaps the center of the semiconductor element (6) when viewed in the thickness direction (z). [Appendix 5] 5. The semiconductor device (A1) according to claim 4, wherein the metal layer (19) is cross-shaped when viewed in the thickness direction (z). [Appendix 6] The semiconductor device (A12, A14) according to appendix 3 or 4, wherein the metal layer (19) has a strip shape extending in a direction intersecting the thickness direction (z) when viewed in the thickness direction (z). [Appendix 7] A semiconductor device (A13, A15) according to Appendix 6, wherein the metal layer (19) overlaps two of the four corners of the semiconductor element (6) when viewed in the thickness direction (z), but does not overlap the other two. [Appendix 8] 8. The semiconductor device (A2) according to any one of appendices 1 to 7, wherein the metal layer (19) includes a plurality of individual regions (191) that are separated from each other when viewed in the thickness direction (z). [Appendix 9] The semiconductor device (A2, A21) according to appendix 8, wherein each of the plurality of individual regions (191) is in the shape of a strip extending in a direction intersecting the thickness direction (z). [Appendix 10] The semiconductor device (A2, A22) according to appendix 8, wherein the plurality of individual regions (191) are arranged in a matrix when viewed in the thickness direction (z). [Appendix 11] The semiconductor device (A3) according to appendix 8, wherein the plurality of individual regions (191) include those that overlap four corners of the semiconductor element (6) when viewed in the thickness direction (z). [Appendix 12] 12. The semiconductor device (A3) according to claim 11, wherein the plurality of individual regions (191) do not overlap with the center of the semiconductor element (6) when viewed in the thickness direction (z). [Appendix 13] 13. The semiconductor device (A1) according to any one of appendices 1 to 12, wherein the metal layer (19) protrudes from the semiconductor element (6) when viewed in the thickness direction (z). [Appendix 14] 14. The semiconductor device (A1) according to any one of appendices 1 to 13, wherein the base material (10) includes a metal. [Appendix 14-1] 15. The semiconductor device (A1) according to claim 14, wherein the base material (10) contains Cu. [Appendix 15] 14. The semiconductor device (A1) according to any one of appendices 1 to 13, wherein the base material (10) contains a resin. [Appendix 16] 16. The semiconductor device (A1) according to any one of appendices 1 to 15, wherein the sintered metal portion (501) contains Ag or Cu. [Appendix 17] 17. The semiconductor device (A1) according to any one of appendixes 1 to 16, wherein the resin portion (502) contains an epoxy resin or an acrylic resin. [Appendix 18] 18. The semiconductor device (A1) according to any one of appendices 1 to 17, comprising a sealing resin (8) that covers the semiconductor element (6). [Appendix 19] The support (1) has a first back surface (12) facing the opposite side to the first main surface (11), 19. The semiconductor device (A1) according to claim 18, wherein the first back surface (12) is exposed from the sealing resin (8). [Appendix 20] 20. The semiconductor device (A1) according to any one of appendices 1 to 19, wherein the semiconductor element (6) is a switching element. [Explanation of symbols]

[0092] A1, A11, A12, A13, A14, A15, A2, A21, A22, A3, A4: semiconductor device 1:Support 2,3,4: Lead 5: Bonding material 6: Semiconductor elements 6a: Element main surface 6b: Back side of element 8: Sealing resin 10: Base material 11: First main surface 12: First back side 13: Recessed portion on the back side 14:Terminal end face 15: Connection end face 18: Back side of terminal 19: Metal layer 21: Second main surface 22: Second back side 23: Recessed portion on the back side 24:Terminal end face 25: Connection end face 31: Third main surface 32: Third reverse side 33: Recessed portion on the back side 34:Terminal end face 35: Connection end face 41: Fourth main surface 42: 4th back side 43: Recessed portion on the back side 44:Terminal end face 51: Part 1 52: Part 2 60: Element body 61: 1st electrode 62: 2nd electrode 63:Third electrode 71, 72, 73, 74: Wire 81: Resin main surface 82: Resin back 83: Resin side 191 :Individual area 501: Sintered metal section 502: Resin part 831, 832, 833, 834: Resin side x :1st direction y: second direction z: thickness direction

Claims

1. a support including a base material having a first main surface facing in a thickness direction; A semiconductor element; a bonding material that bonds the support body and the semiconductor element, the bonding material includes a sintered metal portion and a resin portion, the support body includes a metal layer located on the first main surface and having a stronger sintered bond with the sintered metal portion than the base material, The bonding material includes a first portion in contact with the semiconductor element and the metal layer, and a second portion in contact with the semiconductor element and the base material.

2. The semiconductor device according to claim 1 , wherein the semiconductor element is electrically connected to the support.

3. The semiconductor device according to claim 1 , wherein the metal layer overlaps only a portion of the semiconductor element when viewed in the thickness direction.

4. the semiconductor element has a rectangular shape when viewed in the thickness direction, The semiconductor device according to claim 3 , wherein four corners of the semiconductor element do not overlap with the metal layer when viewed in the thickness direction.

5. The semiconductor device according to claim 4 , wherein the metal layer has a cross shape when viewed in the thickness direction.

6. The semiconductor device according to claim 3 , wherein the metal layer has a strip shape extending in a direction intersecting the thickness direction when viewed in the thickness direction.

7. The semiconductor device according to claim 6 , wherein the metal layer overlaps two of the four corners of the semiconductor element and does not overlap the other two corners when viewed in the thickness direction.

8. The semiconductor device according to claim 1 , wherein said metal layer includes a plurality of individual regions spaced apart from one another when viewed in the thickness direction.

9. 9. The semiconductor device according to claim 8, wherein each of said plurality of individual regions is in the shape of a strip extending in a direction intersecting said thickness direction.

10. The semiconductor device according to claim 8 , wherein the plurality of individual regions are arranged in a matrix when viewed in the thickness direction.

11. The semiconductor device according to claim 8 , wherein the plurality of individual regions include regions that overlap four corners of the semiconductor element when viewed in the thickness direction.

12. The semiconductor device according to claim 11 , wherein the plurality of individual regions do not overlap with a center of the semiconductor element when viewed in the thickness direction.

13. The semiconductor device according to claim 1 , wherein the metal layer protrudes from the semiconductor element when viewed in the thickness direction.

14. The semiconductor device according to claim 1 , wherein the base material includes a metal.

15. The semiconductor device according to claim 1 , wherein the base material includes a resin.

Images