Semiconductor module and semiconductor device

Abstract

To provide a semiconductor module capable of reducing parasitic inductance without increasing power loss accompanying the operation of each circuit.SOLUTION: The semiconductor module B10 includes a semiconductor device A10 and a base material 40. The semiconductor device A10 includes a first terminal 21, a second terminal 22, a third terminal 23, a semiconductor device 10, and a sealing resin 30. A first circuit and a second circuit are formed in the semiconductor element 10. The first circuit is electrically connected to the first terminal 21 and the third terminal 23. The second circuit is electrically connected to a second terminal 22 and a third terminal 23. The base material 40 includes a first conductive layer 41, a second conductive layer 42, a third conductive layer 43, and an insulating layer 45. The mounting surface 451 of the insulating layer 45 includes a first region 451A and a second region 451B. As viewed in the first direction z, the size D2 in the second direction x of the portion of the third conductive layer 43 overlapping the second region 451B is larger than the minimum size D1 of the first region 451A in the first direction z.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor circuit and a semiconductor device including the semiconductor circuit. [Background technology]

[0002] Patent Document 1 discloses an example of a power supply circuit for a step-down DC-DC converter. The power supply circuit includes two transistors. In the power supply circuit, the two transistors form a half-bridge circuit. The power supply voltage input to the power supply circuit is stepped down to a predetermined voltage by an inductor and an output capacitor driven by each of the two transistors and connected to the output side of the half-bridge circuit.

[0003] In the power supply circuit disclosed in Patent Document 1, the conductive path connected to the input side of the half-bridge circuit has parasitic inductance. Therefore, when the power supply voltage input to the half-bridge circuit increases, a surge voltage occurs in the conductive path. If the surge voltage becomes excessive, the two transistors that make up the half-bridge circuit may be destroyed. It is possible to reduce the surge voltage by lengthening the on / off transition time of each of the two transistors. However, this solution raises concerns about increased power loss due to the operation of the two transistors. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-132514

[0005] [overview] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor module and a semiconductor device that are capable of reducing parasitic inductance without increasing power loss associated with the operation of each circuit.

[0006] A semiconductor module provided by a first aspect of the present disclosure includes a substrate and a semiconductor device located on one side of the substrate in a first direction and conductively bonded to the substrate. The semiconductor device includes a first terminal, a second terminal, and a third terminal, a semiconductor element located on one side of the first terminal, the second terminal, and the third terminal in the first direction, and a sealing resin covering the semiconductor element. The semiconductor element includes a first circuit and a second circuit connected in series to each other. The first circuit is electrically connected to the first terminal and the third terminal. The second circuit is electrically connected to the second terminal and the third terminal. The sealing resin has a bottom surface facing the substrate. The first terminal, the second terminal, and the third terminal each have a first mounting surface, a second mounting surface, and a third mounting surface exposed from the bottom surface. In a second direction perpendicular to the first direction, the second mounting surface is spaced apart from the first mounting surface. The first mounting surface includes a first edge extending in a third direction perpendicular to the first and second directions. The second mounting surface includes a second edge extending in the third direction and located adjacent to the first edge in the second direction. The third mounting surface is located between the first edge and its extension and the second edge and its extension. The bottom surface includes a third edge extending in the second direction and spaced apart from the third mounting surface. The base material includes an insulating layer having a mounting surface facing the bottom surface, and a first conductive layer, a second conductive layer, and a third conductive layer, each mounted on the mounting surface. The first mounting surface, the second mounting surface, and the third mounting surface are individually conductively bonded to the first conductive layer, the second conductive layer, and the third conductive layer, respectively. The mounting surface includes a first region and a second region, each entirely overlapping the bottom surface when viewed in the first direction. When viewed in the first direction, the first region is sandwiched between the first conductive layer and the second conductive layer. When viewed in the first direction, the second region is located on the opposite side of the first region from the third edge, and when viewed in the first direction, a dimension in the second direction of a portion of the third conductive layer that overlaps the second region is greater than a minimum dimension in the second direction of the first region.

[0007] A second aspect of the present disclosure provides a semiconductor device comprising: a first terminal, a second terminal, and a third terminal; a semiconductor element located on one side of the first terminal, the second terminal, and the third terminal in a first direction; and a sealing resin covering the semiconductor element. The semiconductor element includes a first circuit and a second circuit connected in series to each other. The first circuit is electrically connected to the first terminal and the third terminal. The second circuit is electrically connected to the second terminal and the third terminal. The sealing resin has a bottom surface facing the other side of the first direction. The first terminal, the second terminal, and the third terminal each have a first mounting surface, a second mounting surface, and a third mounting surface exposed from the bottom surface. The third mounting surface is located on the opposite side of the first mounting surface relative to the second mounting surface in a second direction perpendicular to the first direction. In a third direction perpendicular to both the first direction and the second direction, each of the dimensions of the first mounting surface and the second mounting surface is 40% or more of the dimension of the sealing resin.

[0008] A third aspect of the present disclosure provides a semiconductor device comprising: a first terminal, a second terminal, and a third terminal; a semiconductor element located on one side of the first terminal, the second terminal, and the third terminal in a first direction; and a sealing resin covering the semiconductor element. The semiconductor element includes a first circuit and a second circuit connected in series to each other. The first circuit is electrically connected to the first terminal and the third terminal. The second circuit is electrically connected to the second terminal and the third terminal. The sealing resin has a bottom surface facing the other side of the first direction. The first terminal, the second terminal, and the third terminal each have a first mounting surface, a second mounting surface, and a third mounting surface exposed from the bottom surface. The third mounting surface is located on the opposite side of the first mounting surface with respect to the second mounting surface in a second direction perpendicular to the first direction. When viewed in the first direction, the first mounting surface and the third mounting surface overlap the first circuit and the second circuit, respectively. When viewed in the first direction, the second mounting surface overlaps at least one of the first circuit and the second circuit.

[0009] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view of a semiconductor module according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view corresponding to FIG. 1, seen through the sealing resin. [Figure 3] FIG. 3 is a plan view corresponding to FIG. 2, further showing the semiconductor element. [Figure 4] FIG. 4 is a bottom view of the semiconductor device included in the semiconductor module shown in FIG. [Figure 5] FIG. 5 is a front view of a semiconductor device included in the semiconductor module shown in FIG. [Figure 6] 6 is a rear view of the semiconductor device included in the semiconductor module shown in FIG. [Figure 7] 7 is a right side view of the semiconductor device included in the semiconductor module shown in FIG. [Figure 8] 8 is a left side view of the semiconductor device included in the semiconductor module shown in FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. [Figure 10] FIG. 10 is a cross-sectional view taken along line XX in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. [Figure 12] FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. [Figure 13] FIG. 13 is a circuit diagram of a step-down DC-DC converter including the semiconductor module shown in FIG. 1 as a component. [Figure 14] FIG. 14 is a plan view of the semiconductor module according to the second embodiment of the present disclosure, seen through the sealing resin. [Figure 15] FIG. 15 is a plan view corresponding to FIG. 14, further showing the semiconductor element. [Figure 16] 16 is a bottom view of the semiconductor device included in the semiconductor module shown in FIG. [Figure 17] FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. [Figure 18] FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. [Figure 19] FIG. 19 is a plan view of the semiconductor module according to the third embodiment of the present disclosure, seen through the sealing resin. [Figure 20] FIG. 20 is a plan view corresponding to FIG. 19, further showing the semiconductor element. [Figure 21] 21 is a bottom view of the semiconductor device included in the semiconductor module shown in FIG. [Figure 22] FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. [Figure 23] FIG. 23 is a plan view of the semiconductor module according to the fourth embodiment of the present disclosure, seen through the sealing resin. [Figure 24] FIG. 24 is a plan view corresponding to FIG. 23, further showing the semiconductor element. [Figure 25] 25 is a bottom view of the semiconductor device included in the semiconductor module shown in FIG. [Figure 26] FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. [Figure 27] FIG. 27 is a cross-sectional view taken along line XXVII-XXVII in FIG. [Figure 28] FIG. 28 is a plan view of the semiconductor device according to the fifth embodiment of the present disclosure, seen through the sealing resin. [Figure 29] FIG. 29 is a bottom view of the semiconductor device shown in FIG. [Figure 30] 30 is a bottom view of a semiconductor element included in the semiconductor device shown in FIG. [Figure 31] FIG. 31 is a partially enlarged cross-sectional view of the semiconductor device shown in FIG. 28, showing a plurality of second electrodes of the semiconductor element and their vicinity. [Figure 32] FIG. 32 is a partially enlarged cross-sectional view of the semiconductor device shown in FIG. 28, showing a plurality of third electrodes of the semiconductor element and their vicinity.

[0011] [Detailed explanation] The details of the present disclosure will be described with reference to the accompanying drawings.

[0012] [First embodiment] A semiconductor module B10 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 12. The semiconductor module B10 constitutes, for example, part of a circuit of a DC-DC converter. The semiconductor module B10 includes a semiconductor device A10, a substrate 40, and an input capacitor 50. The semiconductor device A10 is surface-mounted on the substrate 40. For ease of understanding, FIG. 2 shows a perspective view of the sealing resin 30. In FIG. 2, the penetrated sealing resin 30 is shown by an imaginary line (two-dot chain line). For ease of understanding, FIG. 3 shows a perspective view of the semiconductor element 10, which is further penetrated than FIG. 2. In FIG. 3, the penetrated sealing resin 30 and the semiconductor element 10 are each shown by an imaginary line.

[0013] In describing the semiconductor module B10, for convenience, the normal direction to the bottom surface 32 (details of which will be described later) of the sealing resin 30 will be referred to as the "first direction z." The direction perpendicular to the first direction z will be referred to as the "second direction x." The direction perpendicular to both the first direction z and the second direction x will be referred to as the "third direction y."

[0014] First, the semiconductor device A10 included in the semiconductor module B10 will be described. The semiconductor device A10 has a rectangular shape when viewed in the first direction z. The semiconductor device A10 includes a semiconductor element 10, a first terminal 21, a second terminal 22, a third terminal 23, multiple fourth terminals 24, and a sealing resin 30.

[0015] 9 to 12, the sealing resin 30 covers the semiconductor element 10. The sealing resin 30 also covers a portion of each of the first terminal 21, the second terminal 22, and the third terminal 23, and a portion of each of the plurality of fourth terminals 24. The sealing resin 30 has electrical insulation properties. The sealing resin 30 is made of a material containing, for example, black epoxy resin.

[0016] As shown in FIG. 1 and FIGS. 4 to 8 , the sealing resin 30 has a top surface 31, a bottom surface 32, a first side surface 33, a second side surface 34, a third side surface 35, and a fourth side surface 36. The top surface 31 faces one side in a first direction z. The bottom surface 32 faces the opposite side from the top surface 31 in the first direction z. In the semiconductor module B10, the bottom surface 32 faces the base material 40. The first side surface 33 faces one side in a second direction x. The second side surface 34 faces the opposite side from the first side surface 33 in the second direction x. The third side surface 35 faces one side in a third direction y. The fourth side surface 36 faces the opposite side from the third side surface 35 in the third direction y. The first side surface 33, the second side surface 34, the third side surface 35, and the fourth side surface 36 are connected to the top surface 31 and the bottom surface 32, respectively.

[0017] 4, the bottom surface 32 includes a third edge 32A and a fourth edge 32B. The third edge 32A and the fourth edge 32B each extend in the second direction x. The third edge 32A and the fourth edge 32B are spaced apart from each other in the third direction y.

[0018] As shown in FIGS. 9 to 12, the first terminal 21, the second terminal 22, the third terminal 23, and the plurality of fourth terminals 24 carry the semiconductor element 10. Each of the first terminal 21, the second terminal 22, the third terminal 23, and the plurality of fourth terminals 24 forms a conductive path between the substrate 40 and the semiconductor element 10. The first terminal 21, the second terminal 22, the third terminal 23, and the plurality of fourth terminals 24 all contain copper (Cu). The first terminal 21, the second terminal 22, the third terminal 23, and the plurality of fourth terminals 24 are obtained from the same lead frame.

[0019] 3 and 4, the first terminal 21 is located on the opposite side of the third terminal 23 from the second terminal 22 in the second direction x. The first terminal 21 extends in the third direction y. The first terminal 21 has a first connecting surface 211, a first mounting surface 212, and two first end surfaces 213.

[0020] As shown in FIGS. 9 to 11, the first connection surface 211 faces the same side as the top surface 31 of the sealing resin 30 in the first direction z. The first connection surface 211 faces the semiconductor element 10. The first connection surface 211 is covered with the sealing resin 30. The first mounting surface 212 faces the opposite side from the first connection surface 211 in the first direction z. As shown in FIG. 4, the first mounting surface 212 is exposed from the bottom surface 32 of the sealing resin 30. The first mounting surface 212 reaches the third edge 32A of the bottom surface 32 and is spaced apart from the fourth edge 32B of the bottom surface 32. The dimension L1 of the first mounting surface 212 in the third direction y is 40% or more of the dimension L0 of the sealing resin 30 in the third direction y. As shown in FIGS. 2 and 11, the two first end surfaces 213 face opposite each other in the third direction y. One of the two first end faces 213 is exposed from a third side face 35 of the sealing resin 30. The other of the two first end faces 213 is exposed from a fourth side face 36 of the sealing resin 30.

[0021] 3 and 4, the second terminal 22 is located on the opposite side of the third terminal 23 from the first terminal 21 in the second direction x. The second terminal 22 extends in the third direction y. The second terminal 22 has a second connecting surface 221, a second mounting surface 222, and a plurality of second end surfaces 223.

[0022] 9 and 10 , the second connection surface 221 faces the same side as the top surface 31 of the sealing resin 30 in the first direction z. The second connection surface 221 faces the semiconductor element 10. The second connection surface 221 is covered by the sealing resin 30. The second mounting surface 222 faces the opposite side from the second mounting surface 222 in the first direction z. As shown in FIG. 4 , the second mounting surface 222 is exposed from the bottom surface 32 of the sealing resin 30. The second mounting surface 222 is spaced apart from the first mounting surface 212 of the first terminal 21 in the second direction x. The second mounting surface 222 reaches the third edge 32A of the bottom surface 32 and is spaced apart from the fourth edge 32B of the bottom surface 32. A dimension L2 of the second mounting surface 222 in the third direction y is 40% or more of a dimension L0 of the sealing resin 30 in the third direction y. 2 and 9, each of the second end faces 223 faces either the second direction x or the third direction y. Each of the second end faces 223 is exposed from one of the second side face 34, the third side face 35, and the fourth side face 36 of the sealing resin 30.

[0023] 3 and 4, the third terminal 23 is located between the first terminal 21 and the second terminal 22 in the second direction x. The third terminal 23 extends in the third direction y. The third terminal 23 has a third connection surface 231, a third mounting surface 232, and two third end surfaces 233.

[0024] 9, 10, and 12, the third connection surface 231 and the first connection surface 211 face the same side as the top surface 31 of the sealing resin 30 in the first direction z. The third connection surface 231 faces the semiconductor element 10. The third connection surface 231 is covered with the sealing resin 30. The third mounting surface 232 faces the opposite side to the third connection surface 231 in the first direction z.

[0025] As shown in FIG. 4, the third mounting surface 232 is exposed from the bottom surface 32 of the sealing resin 30. The first mounting surface 212 of the first terminal 21 includes a first edge 212A extending in the third direction y. The second mounting surface 222 of the second terminal 22 includes a second edge 222A extending in the third direction y. The second edge 222A is located adjacent to the first edge 212A in the second direction x. As shown in FIG. 3, the third mounting surface 232 is located between the first edge 212A and its extension and the second edge 222A and its extension. The third mounting surface 232 is located on the opposite side of the bottom surface 32 from the side where the third edge 32A of the bottom surface 32 is located, with respect to the first mounting surface 212 and the second mounting surface 222 in the third direction y. A predetermined distance is provided between the third mounting surface 232 and each of the first mounting surface 212 and the second mounting surface 222 in the third direction y. The third mounting surface 232 reaches the fourth edge 32B of the bottom surface 32.

[0026] 2 and 12 , the two third end faces 233 face opposite each other in the third direction y. One of the two third end faces 233 is exposed from a third side surface 35 of the sealing resin 30. The other of the two third end faces 233 is exposed from a fourth side surface 36 of the sealing resin 30.

[0027] 12, the third terminal 23 includes a first portion 23A and a second portion 23B. The first portion 23A includes a third mounting surface 232 and one of two third end faces 233. The second portion 23B is connected to the first portion 23A and includes the other of the two third end faces 233. The second portion 23B is covered with sealing resin 30. The third connection surface 231 is included in each of the first portion 23A and the second portion 23B. The dimension of the second portion 23B in the first direction z is smaller than the dimension of the first portion 23A in the first direction z.

[0028] 3 and 4, the multiple fourth terminals 24 are located on the opposite side of the first terminal 21 from the third terminal 23 in the second direction x. Each of the multiple fourth terminals 24 has a fourth connection surface 241, a fourth mounting surface 242, and a fourth end surface 243.

[0029] As shown in FIGS. 9 and 10 , the fourth connection surface 241 faces the same side as the top surface 31 of the sealing resin 30 in the first direction z. The fourth connection surface 241 faces the semiconductor element 10. The fourth connection surface 241 is covered by the sealing resin 30. The fourth mounting surface 242 faces the opposite side from the fourth connection surface 241 in the first direction z. As shown in FIG. 4 , the fourth mounting surface 242 is exposed from the bottom surface 32 of the sealing resin 30. The dimension L1 in the third direction y of the first mounting surface 212 of the first terminal 21 and the dimension L2 in the third direction y of the second mounting surface 222 of the second terminal 22 are larger than the dimensions of the fourth mounting surface 242 in the second direction x and the third direction y, respectively. As shown in FIGS. 2 , 9 , and 10 , the fourth end surface 243 faces either the second direction x or the third direction y. The fourth end face 243 is exposed from any one of the first side face 33 , the third side face 35 , and the fourth side face 36 of the sealing resin 30 .

[0030] 9 to 11, the semiconductor element 10 is located on one side in the first direction z of the first terminal 21, the second terminal 22, the third terminal 23, and the plurality of fourth terminals 24. The semiconductor element 10 has a body 11, a plurality of first electrodes 121, a plurality of second electrodes 122, a plurality of third electrodes 123, and a plurality of fourth electrodes 124.

[0031] The main body 11 includes a semiconductor substrate and a semiconductor layer stacked on the semiconductor substrate. A first circuit C1, a second circuit C2, and a third circuit C3 are configured in the semiconductor layer. The first circuit C1 and the second circuit C2 are connected in series to each other. Each of the first circuit C1 and the second circuit C2 includes a switching element. The switching element is, for example, an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET). This disclosure focuses on a case where each of the first circuit C1 and the second circuit C2 includes an n-channel MOSFET. A half-bridge circuit is configured in the main body 11 by the first circuit C1 and the second circuit C2. The third circuit C3 is electrically connected to each of the first circuit C1 and the second circuit C2. The third circuit C3 controls each of the first circuit C1 and the second circuit C2.

[0032] 2, when viewed in the first direction z, the first mounting surface 212 of the first terminal 21 and the second mounting surface 222 of the second terminal 22 overlap the first circuit C1 and the second circuit C2, respectively. When viewed in the first direction z, the third mounting surface 232 of the third terminal 23 overlaps at least one of the first circuit C1 and the second circuit C2.

[0033] Each of the plurality of first electrodes 121 is electrically connected to the first circuit C1. As shown in Fig. 2, when viewed in the first direction z, each of the plurality of first electrodes 121 overlaps the first circuit C1. As shown in Figs. 9 to 11, each of the plurality of first electrodes 121 is conductively joined to the first connection surface 211 of the first terminal 21 via solder or the like.

[0034] Each of the second electrodes 122 is electrically connected to the second circuit C2. As shown in Fig. 2, when viewed in the first direction z, each of the second electrodes 122 overlaps the second circuit C2. As shown in Fig. 9 and Fig. 10, each of the second electrodes 122 is electrically conductively joined to the second connection surface 221 of the second terminal 22 via solder or the like.

[0035] Each of the multiple third electrodes 123 is electrically connected to the first circuit C1 and the second circuit C2. As shown in Fig. 2, when viewed in the first direction z, each of the multiple third electrodes 123 overlaps either the first circuit C1 or the second circuit C2. As shown in Figs. 9, 10, and 11, each of the multiple third electrodes 123 is conductively joined to the third connection surface 231 of the third terminal 23 via solder or the like. Furthermore, each of the multiple third electrodes 123 is conductively joined to either the first portion 23A of the third terminal 23 or the second portion 23B of the third terminal 23.

[0036] Each of the multiple fourth electrodes 124 is electrically connected to the third circuit C3. As shown in Fig. 2, each of the multiple fourth electrodes 124 overlaps the third circuit C3 when viewed in the first direction z. As shown in Fig. 9 and Fig. 10, each of the multiple fourth electrodes 124 is electrically conductively joined to one of the fourth connection surfaces 241 of the multiple fourth terminals 24 via solder or the like.

[0037] Next, the substrate 40 and the input capacitor 50 included in the semiconductor module B10 will be described.

[0038] The substrate 40 is, for example, a PWB (Printed Wiring Board). The substrate 40 includes a first conductive layer 41, a second conductive layer 42, a third conductive layer 43, a plurality of fourth conductive layers 44, and an insulating layer 45. Each of the first conductive layer 41, the second conductive layer 42, the third conductive layer 43, and the plurality of fourth conductive layers 44 contains copper. The insulating layer 45 is made of a material containing, for example, epoxy resin.

[0039] 9 to 12, the insulating layer 45 faces the semiconductor device A10. The insulating layer 45 has a mounting surface 451 facing the bottom surface 32 of the sealing resin 30.

[0040] As shown in FIG. 3 and FIGS. 9 to 12, the first conductive layer 41, the second conductive layer 42, the third conductive layer 43, and the plurality of fourth conductive layers 44 are mounted on a mounting surface 451 of the insulating layer 45. The first mounting surface 212 of the first terminal 21 is conductively bonded to the first conductive layer 41 via a bonding layer 60. The bonding layer 60 is, for example, solder. The second conductive layer 42 is located adjacent to the first conductive layer 41 in the second direction x. The second mounting surface 222 of the second terminal 22 is conductively bonded to the second conductive layer 42 via the bonding layer 60. The third conductive layer 43 is located on one side of the first conductive layer 41 and the second conductive layer 42 in the third direction y. The third mounting surface 232 of the third terminal 23 is conductively bonded to the third conductive layer 43 via the bonding layer 60. The plurality of fourth conductive layers 44 are located on one side of the first conductive layer 41 and the third conductive layer 43 in the second direction x. The fourth mounting surfaces 242 of the plurality of fourth terminals 24 are individually conductively bonded to the plurality of fourth conductive layers 44 via bonding layers 60 .

[0041] 3, 9, and 10, the mounting surface 451 of the insulating layer 45 includes a first region 451A and a second region 451B. As viewed in the first direction z, the entire first region 451A and the entire second region 451B overlap the bottom surface 32 of the sealing resin 30. As viewed in the first direction z, the first region 451A is sandwiched between the first conductive layer 41 and the second conductive layer 42. As viewed in the first direction z, the second region 451B is located on the opposite side of the third edge 32A of the bottom surface 32 with respect to the first region 451A in the third direction y. As viewed in the first direction z, a dimension D2 in the second direction x of a portion of the third conductive layer 43 overlapping the second region 451B is greater than a minimum dimension D1 in the second direction x of the first region 451A.

[0042] 1 to 3, the input capacitor 50 is located on the opposite side of the first mounting surface 212 of the first terminal 21 and the second mounting surface 222 of the second terminal 22 in the third direction y, with the third edge 32A of the bottom surface 32 of the sealing resin 30 as the reference. The input capacitor 50 has two electrodes 51. As shown in FIG. 11, one of the two electrodes 51 is conductively bonded to the first conductive layer 41 via a bonding layer 60. As shown in FIG. 12, the other of the two electrodes 51 is conductively bonded to the second conductive layer 42 via the bonding layer 60.

[0043] Next, a step-down DC-DC converter circuit including a semiconductor module B10 as a component will be described with reference to Fig. 13. The circuit includes a semiconductor module B10, an inductor L, and an output capacitor C.

[0044] The inductor L is electrically connected to the third conductive layer 43. Therefore, the inductor L is electrically connected to the source of the first circuit C1 and the drain of the second circuit C2 via the third conductive layer 43 and the third terminal 23.

[0045] The output capacitor C is electrically connected to the inductor L. More specifically, the positive electrode of the output capacitor C is electrically connected to the inductor L. The negative electrode of the output capacitor C is externally grounded. In this circuit, the inductor L and the output capacitor C form a low-pass filter.

[0046] Next, the operation of the circuit will be described. in When the input voltage V is applied, the third circuit C3 drives the first circuit C1. in As a result, the third conductive layer 43 is grounded corresponding to the pulsed input voltage V in At this time, a gate voltage based on PWM (Pulse Width Modulation) control by the third circuit C3 is applied to the first circuit C1. In this case, the input capacitor 50 contributes to stabilizing the waveform of the pulsed input voltage Vin. Next, the second circuit C2 is driven by the third circuit C3. As a result, the pulsed input voltage V in is smoothed by the inductor L and the output capacitor C, resulting in the stepped-down output voltage V out The output voltage V out is output to the outside. Therefore, the circuit employs a synchronous rectification method.

[0047] Next, the effects of the semiconductor module B10 will be described.

[0048] The semiconductor module B10 includes a semiconductor device A10 and a substrate 40. The semiconductor device A10 includes a first terminal 21, a second terminal 22, a third terminal 23, a semiconductor element 10, and a sealing resin 30. A first circuit C1 and a second circuit C2 are configured in the semiconductor element 10. The substrate 40 includes a first conductive layer 41, a second conductive layer 42, a third conductive layer 43, and an insulating layer 45. A mounting surface 451 of the insulating layer 45 includes a first region 451A and a second region 451B. As viewed in the first direction z, the first region 451A is sandwiched between the first conductive layer 41 and the second conductive layer 42. As viewed in the first direction z, the second region 451B is located on the opposite side of the first region 451A from the third edge 32A of the bottom surface 32 of the sealing resin 30. As viewed in the first direction z, the dimension D2 in the second direction x of the portion of the third conductive layer 43 overlapping the second region 451B is greater than the minimum dimension D1 in the first direction z of the first region 451A. This configuration further shortens the conductive path from the first conductive layer 41 to the second conductive layer 42 via the first terminal 21, the first circuit C1, the second circuit C2, and the second terminal 22. Furthermore, the distance between the current flowing through the conductive path in the first conductive layer 41 and the current flowing through the conductive path in the second conductive layer 42 is further reduced. This further reduces parasitic inductance due to this conductive path in the semiconductor module B10. Therefore, this configuration enables the semiconductor module B10 to reduce parasitic inductance without increasing power loss associated with the operation of the first circuit C1 and the second circuit C2.

[0049] The semiconductor element 10 has a first electrode 121, a second electrode 122, and a third electrode 123. The first electrode 121, the second electrode 122, and the third electrode 123 are individually conductively bonded to the first terminal 21, the second terminal 22, and the third terminal 23, respectively. With this configuration, the semiconductor device A10 is flip-chip connected to the first terminal 21, the second terminal 22, and the third terminal 23. This makes it possible to reduce parasitic inductance in the semiconductor device A10.

[0050] The dimensions L1, L2 in the third direction y of each of the first mounting surface 212 of the first terminal 21 and the second mounting surface 222 of the second terminal 22 are 40% or more of the dimension L0 in the third direction y of the sealing resin 30. This configuration allows a larger current to flow from each of the first conductive layer 41 and the second conductive layer 42 to the semiconductor device A10.

[0051] The semiconductor module B10 further includes an input capacitor 50 conductively bonded to the first conductive layer 41 and the second conductive layer 42. The input capacitor 50 is located on the opposite side of the first mounting surface 212 of the first terminal 21 and the second mounting surface 222 of the second terminal 22 with respect to the third edge 32A of the bottom surface 32 of the sealing resin 30 in the third direction y. This configuration makes it easier to optimize the conductive paths of the first conductive layer 41 and the second conductive layer 42 between the input voltage side and the semiconductor device A10 in the circuit configuration of the DC-DC converter shown in FIG.

[0052] Second Embodiment A semiconductor module B20 according to a second embodiment of the present disclosure will be described with reference to FIGS. 14 to 18. In these figures, elements that are the same as or similar to those in the semiconductor module B10 and semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. Here, for ease of understanding, FIG. 14 shows the sealing resin 30 in a see-through view. In FIG. 14, the see-through sealing resin 30 is shown by imaginary lines. For ease of understanding, FIG. 15 shows the semiconductor element 10 in a see-through view compared to FIG. 14. In FIG. 15, the see-through sealing resin 30 and semiconductor element 10 are each shown by imaginary lines.

[0053] The semiconductor module B20 includes the semiconductor device A20, a substrate 40, and an input capacitor 50. The semiconductor device A20 includes a semiconductor element 10, a first terminal 21, a second terminal 22, a third terminal 23, a plurality of fourth terminals 24, and a sealing resin 30. In the semiconductor module B20, the configurations of the semiconductor element 10, the first terminal 21, the second terminal 22, and the third terminal 23 differ from those of the semiconductor module B10.

[0054] As shown in FIG. 14, the area occupied by each of the first circuit C1 and the second circuit C2 in the main body 11 of the semiconductor element 10 as viewed in the first direction z is set to be smaller than that of the semiconductor module B10.

[0055] 15, when viewed in the first direction z, the third mounting surface 232 of the third terminal 23 is spaced apart from the first circuit C1 and the second circuit C2 of the semiconductor element 10. As shown in FIG. 18, each of the multiple third electrodes 123 of the semiconductor element 10 is conductively joined to the third connecting surface 231 of the second portion 23B of the third terminal 23.

[0056] As shown in Figures 15 and 16, the dimension L1 in the third direction y of the first mounting surface 212 of the first terminal 21 and the dimension L2 in the third direction y of the second mounting surface 222 of the second terminal 22 are each set to be larger than the configuration of the semiconductor module B10.

[0057] Next, the effects of the semiconductor module B20 will be described.

[0058] The semiconductor module B20 includes a semiconductor device A20 and a substrate 40. The semiconductor device A20 includes a first terminal 21, a second terminal 22, a third terminal 23, a semiconductor element 10, and a sealing resin 30. A first circuit C1 and a second circuit C2 are configured in the semiconductor element 10. The substrate 40 includes a first conductive layer 41, a second conductive layer 42, a third conductive layer 43, and an insulating layer 45. A mounting surface 451 of the insulating layer 45 includes a first region 451A and a second region 451B. As viewed in the first direction z, the first region 451A is sandwiched between the first conductive layer 41 and the second conductive layer 42. As viewed in the first direction z, the second region 451B is located on the opposite side of the first region 451A from the third edge 32A of the bottom surface 32 of the sealing resin 30. As viewed in the first direction z, the dimension D2 in the second direction x of the portion of the third conductive layer 43 that overlaps the second region 451B is greater than the minimum dimension D1 in the first direction z of the first region 451A. Therefore, with this configuration, the semiconductor module B20 can also reduce parasitic inductance without increasing power loss associated with the operation of each of the first circuit C1 and the second circuit C2. Furthermore, by having a configuration in common with the semiconductor module B10, the semiconductor module B20 achieves the same effects as the semiconductor module B10.

[0059] In the semiconductor module B20, the third mounting surface 232 of the third terminal 23 is spaced apart from the first circuit C1 and the second circuit C2 of the semiconductor element 10 when viewed in the first direction z. This configuration further shortens the conductive path from the first conductive layer 41 to the second conductive layer 42, passing through the first terminal 21, the first circuit C1, the second circuit C2, and the second terminal 22 in this order. This makes it possible to more effectively reduce the parasitic inductance caused by this conductive path in the semiconductor module B20.

[0060] Third Embodiment A semiconductor module B30 according to a third embodiment of the present disclosure will be described with reference to FIGS. 19 to 22. In these figures, elements that are the same as or similar to those in the semiconductor module B10 and semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. For ease of understanding, FIG. 19 shows the sealing resin 30 in a see-through view. In FIG. 19, the see-through sealing resin 30 is shown by imaginary lines. For ease of understanding, FIG. 20 shows the semiconductor element 10 in a see-through view compared to FIG. 19. In FIG. 20, the see-through sealing resin 30 and semiconductor element 10 are each shown by imaginary lines.

[0061] The semiconductor module B30 includes the semiconductor device A30, a substrate 40, and an input capacitor 50. The semiconductor device A30 includes a semiconductor element 10, a first terminal 21, a second terminal 22, a third terminal 23, a plurality of fourth terminals 24, and a sealing resin 30. In the semiconductor module B30, the configurations of the first terminal 21 and the second terminal 22 differ from those of the semiconductor module B20 described above.

[0062] 20 to 22, the first mounting surface 212 of the first terminal 21 includes a first surface 212B and a second surface 212C that are spaced apart from each other in the third direction y. The first surface 212B and the second surface 212C are each spaced apart from the third edge 32A of the bottom surface 32 of the sealing resin 30. In the semiconductor module B30, the dimension L1 of the first mounting surface 212 in the third direction y corresponds to the distance in the third direction y from the end of the first surface 212B that is closest to the fourth edge 32B of the bottom surface 32 to the end of the second surface 212C that is closest to the third edge 32A of the bottom surface 32.

[0063] 20 and 21 , the second mounting surface 222 of the second terminal 22 includes a third surface 222B and a fourth surface 222C that are spaced apart from each other in the third direction y. Each of the third surface 222B and the fourth surface 222C is spaced apart from the third edge 32A of the bottom surface 32 of the sealing resin 30. In the semiconductor module B30, the dimension L2 of the second mounting surface 222 in the third direction y corresponds to the distance in the third direction y from the end of the third surface 222B that is closest to the fourth edge 32B of the bottom surface 32 to the end of the fourth surface 222C that is closest to the third edge 32A of the bottom surface 32.

[0064] Next, the effects of the semiconductor module B30 will be described.

[0065] The semiconductor module B30 includes a semiconductor device A30 and a substrate 40. The semiconductor device A30 includes a first terminal 21, a second terminal 22, a third terminal 23, a semiconductor element 10, and a sealing resin 30. A first circuit C1 and a second circuit C2 are configured in the semiconductor element 10. The substrate 40 includes a first conductive layer 41, a second conductive layer 42, a third conductive layer 43, and an insulating layer 45. A mounting surface 451 of the insulating layer 45 includes a first region 451A and a second region 451B. As viewed in the first direction z, the first region 451A is sandwiched between the first conductive layer 41 and the second conductive layer 42. As viewed in the first direction z, the second region 451B is located on the opposite side of the first region 451A from the third edge 32A of the bottom surface 32 of the sealing resin 30. As viewed in the first direction z, the dimension D2 in the second direction x of the portion of the third conductive layer 43 that overlaps the second region 451B is greater than the minimum dimension D1 in the first direction z of the first region 451A. Therefore, with this configuration, even in the semiconductor module B30, it is possible to reduce parasitic inductance without increasing power loss associated with the operation of each of the first circuit C1 and the second circuit C2. Furthermore, by having a configuration in common with the semiconductor module B10, the semiconductor module B30 achieves the same effects as the semiconductor module B10.

[0066] In the semiconductor module B30, the first mounting surface 212 of the first terminal 21 includes a first surface 212B and a second surface 212C that are spaced apart from each other in the third direction y. With this configuration, the portion of the first terminal 21 located between the first surface 212B and the second surface 212C in the third direction y is sandwiched between the sealing resin 30 on both sides in the first direction z. This more effectively prevents the first terminal 21 from falling off the bottom surface 32 of the sealing resin 30.

[0067] [Fourth embodiment] A semiconductor module B40 according to a fourth embodiment of the present disclosure will be described with reference to FIGS. 23 to 27. In these figures, elements that are the same as or similar to those in the semiconductor module B10 and semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. For ease of understanding, FIG. 23 shows the sealing resin 30 in a see-through view. In FIG. 23, the see-through sealing resin 30 is shown by imaginary lines. For ease of understanding, FIG. 24 shows the semiconductor element 10 in a see-through view compared to FIG. 23. In FIG. 24, the see-through sealing resin 30 and semiconductor element 10 are each shown by imaginary lines.

[0068] The semiconductor module B40 includes the semiconductor device A40, a substrate 40, and an input capacitor 50. The semiconductor device A40 includes a semiconductor element 10, a first terminal 21, a second terminal 22, a third terminal 23, a plurality of fourth terminals 24, and a sealing resin 30. In the semiconductor module B40, the configurations of the first terminal 21 and the second terminal 22 differ from those of the semiconductor module B10.

[0069] 24 and 25, the first mounting surface 212 of the first terminal 21 extends from the third edge 32A to the fourth edge 32B of the bottom surface 32 of the sealing resin 30. As a result, the dimension L1 of the first mounting surface 212 in the third direction y is equal to the dimension L0 of the sealing resin 30 in the third direction y.

[0070] 24 and 25, the second mounting surface 222 of the second terminal 22 extends from the third edge 32A to the fourth edge 32B of the bottom surface 32 of the sealing resin 30. As a result, the dimension L2 of the second mounting surface 222 in the third direction y is equal to the dimension L0 of the sealing resin 30 in the third direction y.

[0071] 23 to 27, when viewed in the first direction z, the area of ​​the portion of the first conductive layer 41 that overlaps the sealing resin 30 is larger than that of the configuration of semiconductor module B10. As shown in FIGS. 23 to 26, when viewed in the first direction z, the area of ​​the portion of the second conductive layer 42 that overlaps the sealing resin 30 is larger than that of the configuration of semiconductor module B10. As shown in FIG. 24, the second region 451B of the mounting surface 451 of the insulating layer 45 is located between the first conductive layer 41 and the second conductive layer 42 in the second direction x.

[0072] Next, the effects of the semiconductor module B40 will be described.

[0073] The semiconductor module B40 includes a semiconductor device A40 and a substrate 40. The semiconductor device A40 includes a first terminal 21, a second terminal 22, a third terminal 23, a semiconductor element 10, and a sealing resin 30. A first circuit C1 and a second circuit C2 are configured in the semiconductor element 10. The substrate 40 includes a first conductive layer 41, a second conductive layer 42, a third conductive layer 43, and an insulating layer 45. A mounting surface 451 of the insulating layer 45 includes a first region 451A and a second region 451B. As viewed in the first direction z, the first region 451A is sandwiched between the first conductive layer 41 and the second conductive layer 42. As viewed in the first direction z, the second region 451B is located on the opposite side of the first region 451A from the third edge 32A of the bottom surface 32 of the sealing resin 30. As viewed in the first direction z, the dimension D2 in the second direction x of the portion of the third conductive layer 43 that overlaps the second region 451B is greater than the minimum dimension D1 in the first direction z of the first region 451A. Therefore, with this configuration, even in the semiconductor module B40, it is possible to reduce parasitic inductance without increasing power loss associated with the operation of each of the first circuit C1 and the second circuit C2. Furthermore, by having a configuration in common with the semiconductor module B10, the semiconductor module B40 achieves the same effects as the semiconductor module B10.

[0074] Fifth Embodiment A semiconductor device A50 according to a fifth embodiment of the present disclosure will be described with reference to Figures 28 to 32. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, Figure 28 shows the sealing resin 30 in a perspective view. In Figure 28, the transparent sealing resin 30 is shown by imaginary lines.

[0075] The semiconductor device A50 includes a semiconductor element 10, a first terminal 21, a second terminal 22, a third terminal 23, a plurality of fourth terminals 24, and a sealing resin 30. In the semiconductor device A50, the configurations of the semiconductor element 10, the first terminal 21, the second terminal 22, and the third terminal 23 differ from those of the semiconductor device A10.

[0076] As shown in Figures 28 and 29, the third mounting surface 232 of the third terminal 23 is located on the opposite side of the first mounting surface 212 of the first terminal 21 in the second direction x, with the second mounting surface 222 of the second terminal 22 as the reference.

[0077] 29, the first mounting surface 212 of the first terminal 21 extends from the third edge 32A to the fourth edge 32B of the bottom surface 32 of the sealing resin 30. As a result, the dimension L1 of the first mounting surface 212 in the third direction y is equal to the dimension L0 of the sealing resin 30 in the third direction y. Therefore, the dimension L1 is 40% or more of the dimension L0. As shown in FIG. 28, the first mounting surface 212 overlaps the first circuit C1 of the semiconductor element 10 when viewed in the first direction z.

[0078] 29, the second mounting surface 222 of the second terminal 22 extends from the third edge 32A to the fourth edge 32B of the bottom surface 32 of the sealing resin 30. As a result, the dimension L2 of the second mounting surface 222 in the third direction y is equal to the dimension L0 of the sealing resin 30 in the third direction y. Therefore, the dimension L2 is 40% or more of the dimension L0. As shown in FIG. 28, when viewed in the first direction z, the second mounting surface 222 overlaps at least one of the first circuit C1 and the second circuit C2 of the semiconductor element 10.

[0079] 29, the third mounting surface 232 of the third terminal 23 extends from the third edge 32A to the fourth edge 32B of the bottom surface 32 of the sealing resin 30. As a result, the dimension L3 of the third mounting surface 232 in the third direction y is equal to the dimension L0 of the sealing resin 30 in the third direction y. As shown in FIG. 28, the third mounting surface 232 overlaps the second circuit C2 of the semiconductor element 10 when viewed in the first direction z.

[0080] 28, in the semiconductor element 10, each of the second electrodes 122 overlaps either the first circuit C1 or the second circuit C2. In the semiconductor element 10, each of the third electrodes 123 overlaps the second circuit C2.

[0081] As shown in FIGS. 30 to 32, the semiconductor element 10 has a plurality of first pads 131, a plurality of second pads 132, a plurality of third pads 133, a plurality of first rewirings 14, a plurality of second rewirings 15, and a protective film 16.

[0082] As shown in FIG. 30 , when viewed in the first direction z, each of the multiple first pads 131 overlaps the second circuit C2. Each of the multiple first pads 131 is electrically connected to the second circuit C2. When viewed in the first direction z, each of the multiple second pads 132 overlaps the second circuit C2. Each of the multiple second pads 132 is electrically connected to the second circuit C2. When viewed in the first direction z, each of the multiple third pads 133 overlaps the first circuit C1. Each of the multiple third pads 133 is electrically connected to the first circuit C1.

[0083] 30 and 31 , each of the multiple first rewirings 14 electrically connects two of the multiple first pads 131 to two of the multiple second electrodes 122. Each of the multiple first rewirings 14 extends in the second direction x. When viewed in the first direction z, each of the multiple first rewirings 14 overlaps with each of the first circuits C1 and the second circuits C2.

[0084] 30 and 32, each of the multiple second rewirings 15 electrically connects one of the multiple second pads 132, one of the multiple third pads 133, and two of the multiple third electrodes 123. Each of the multiple second rewirings 15 extends in the second direction x. When viewed in the first direction z, each of the multiple second rewirings 15 overlaps one of the first circuits C1 and the second circuits C2.

[0085] As shown in FIGS. 30 to 32, the protective film 16 covers one side of the main body 11 in the first direction z, the plurality of first rewirings 14, and the plurality of second rewirings 15. The protective film 16 is an insulator. The protective film 16 is made of a material containing, for example, polyimide. Each of the plurality of first electrodes 121, the plurality of second electrodes 122, the plurality of third electrodes 123, and the plurality of fourth electrodes 124 protrudes from the protective film 16 in the first direction z.

[0086] Next, the effects of the semiconductor device A50 will be described.

[0087] The semiconductor device A50 includes a first terminal 21, a second terminal 22, a third terminal 23, a semiconductor element 10, and a sealing resin 30. A first circuit C1 and a second circuit C2 are configured on the semiconductor element 10. The third mounting surface 232 of the third terminal 23 is located on the opposite side of the first mounting surface 212 of the first terminal 21 in the second direction x, relative to the second mounting surface 222 of the second terminal 22. The dimensions L1 and L2 of the first mounting surface 212 and the second mounting surface 222 in the third direction y are 40% or more of the dimension L0 of the sealing resin 30 in the third direction y. This configuration further shortens the conductive path from the first terminal 21 through the first circuit C1 and the second circuit C2 to the second terminal 22. This further reduces parasitic inductance due to this conductive path in the semiconductor device A50. Therefore, with this configuration, in the semiconductor device A50, it is possible to reduce the parasitic inductance without increasing the power loss that accompanies the operations of the first circuit C1 and the second circuit C2.

[0088] The semiconductor device A50 includes a first terminal 21, a second terminal 22, a third terminal 23, a semiconductor element 10, and a sealing resin 30. A first circuit C1 and a second circuit C2 are configured on the semiconductor element 10. A third mounting surface 232 of the third terminal 23 is located on the opposite side of the first mounting surface 212 of the first terminal 21 in the second direction x, with the second mounting surface 222 of the second terminal 22 as the reference. As viewed in the first direction z, the first mounting surface 212 and the third mounting surface 232 overlap the first circuit C1 and the second circuit C2, respectively. As viewed in the first direction z, the second mounting surface 222 overlaps at least one of the first circuit C1 and the second circuit C2. This configuration further shortens the conductive path from the first terminal 21 to the second terminal 22 via the first circuit C1 and the second circuit C2. This further reduces the parasitic inductance caused by the conductive path in the semiconductor device A50. Therefore, with this configuration, the semiconductor device A50 can reduce the parasitic inductance without increasing the power loss associated with the operation of each of the first circuit C1 and the second circuit C2.

[0089] In the semiconductor device A50, even if the positions of the first terminal 21 and the second terminal 22 are interchanged, the above-described operational effects can be achieved.

[0090] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0091] The semiconductor modules B10 to B40 and the semiconductor device A50 in this disclosure are intended for application to step-down DC-DC converters. In addition, the semiconductor modules B10 to B40 and the semiconductor device A50 in this disclosure can be applied to step-up or inverting converters, and other switching applications other than converters.

[0092] The present disclosure includes the embodiments described in the appendix below. [Appendix 1] A substrate (40) and a semiconductor device (A10) located on one side of the base in the first direction (z) and conductively bonded to the base, The semiconductor device includes: a first terminal (21), a second terminal (22) and a third terminal (23); a semiconductor element (10) located on one side of the first terminal, the second terminal, and the third terminal in the first direction; and a sealing resin (30) that covers the semiconductor element. The semiconductor element includes a first circuit (C1) and a second circuit (C2) connected in series with each other, the first circuit is electrically connected to the first terminal and the third terminal; the second circuit is electrically connected to the second terminal and the third terminal; The sealing resin has a bottom surface (32) facing the base material, the first terminal, the second terminal, and the third terminal each have a first mounting surface (212), a second mounting surface (222), and a third mounting surface (232) exposed from the bottom surface, the second mounting surface is spaced apart from the first mounting surface in a second direction (x) perpendicular to the first direction; the first mounting surface includes a first edge (212A) extending in a third direction (y) perpendicular to the first direction and the second direction; the second mounting surface extends in the third direction and includes a second edge (222A) located adjacent to the first edge in the second direction; the third mounting surface is located between the first edge and its extension line and the second edge and its extension line, the bottom surface includes a third edge (32A) extending in the second direction and spaced apart from the third mounting surface; The substrate is an insulating layer (45) having a mounting surface (451) facing the bottom surface; a first conductive layer (41), a second conductive layer (42), and a third conductive layer (43), each mounted on the mounting surface; the first mounting surface, the second mounting surface, and the third mounting surface are conductively bonded to the first conductive layer, the second conductive layer, and the third conductive layer, respectively; the mounting surface includes a first region (451A) and a second region (451B), each of which entirely overlaps the bottom surface when viewed in the first direction; When viewed in the first direction, the first region is sandwiched between the first conductive layer and the second conductive layer, When viewed in the first direction, the second region is located on the opposite side of the first region from the third edge, A semiconductor module (B10) in which, when viewed in the first direction, the dimension (D2) in the second direction of the portion of the third conductive layer that overlaps the second region is greater than the minimum dimension (D1) in the second direction of the first region. [Appendix 2] The semiconductor element (10) has a first electrode (121) electrically connected to the first circuit (C1), a second electrode (122) electrically connected to the second circuit (C2), and a third electrode (123) electrically connected to the first circuit and the second circuit, A semiconductor module (B10) described in Appendix 1, wherein the first electrode, the second electrode, and the third electrode are individually conductively connected to the first terminal, the second terminal, and the third terminal, respectively. [Appendix 3] A semiconductor module (B10) described in Appendix 2, wherein the third mounting surface (232) is located on the opposite side of the third edge (32A) from the side on which the first mounting surface (212) and the second mounting surface (222) are located in the third direction (y). [Appendix 4] A semiconductor module (B10) described in Appendix 3, wherein a predetermined distance is provided between the third mounting surface (232) and each of the first mounting surface (212) and the second mounting surface (222) in the third direction. [Appendix 5] A semiconductor module (B10) described in Appendix 4, wherein the dimensions (L1, L2) of each of the first mounting surface (212) and the second mounting surface (222) in the third direction (y) are 40% or more of the dimension (L0) of the sealing resin (30) in the third direction. [Appendix 6] A semiconductor module (B10) described in Appendix 3, wherein, when viewed in the first direction (z), the first mounting surface (212) and the second mounting surface (222) individually overlap the first circuit (C1) and the second circuit (C2), respectively. [Appendix 7] the third terminal (23) has a first portion (23A) including the third mounting surface (232) and a second portion (23B) connected to the first portion and covered with the sealing resin (30), The dimension of the second portion in the first direction (z) is smaller than the dimension of the first portion in the first direction, The semiconductor module (B10) according to appendix 6, wherein the third electrode (123) is conductively joined to the second portion. [Appendix 8] the bottom surface (32) extends in the second direction (x) and includes a fourth edge (32B) located on the opposite side to the third edge (32A) with respect to the first mounting surface (212) and the second mounting surface (222), The semiconductor module (B10) according to appendix 7, wherein the third mounting surface (232) reaches the fourth edge. [Appendix 9] The semiconductor module (B10) according to Appendix 8, wherein each of the first mounting surface (212) and the second mounting surface (222) reaches the third edge (32A). [Appendix 10] A semiconductor module (B20) according to Appendix 9, wherein, when viewed in the first direction (z), the third mounting surface (232) is spaced apart from each of the first circuit (C1) and the second circuit (C2). [Appendix 11] A semiconductor module (B10) described in Appendix 9, wherein, when viewed in the first direction (z), the third mounting surface (232) overlaps at least one of the first circuit (C1) and the second circuit (C2). [Appendix 12] The semiconductor module (B30) according to appendix 8, wherein the first mounting surface (212) includes a first surface (212B) and a second surface (212C) spaced apart from each other in the third direction (y). [Appendix 13] Further provided with a fourth terminal (24), The semiconductor element (10) includes a third circuit (C3) that is electrically connected to each of the first circuit (C1) and the second circuit (C2), the fourth terminal is electrically connected to the third circuit; the fourth terminal has a fourth mounting surface (242) exposed from the bottom surface (32), A semiconductor module (B10) described in any one of Appendices 6 to 12, wherein the dimensions of each of the first mounting surface (212) and the second mounting surface (222) in the third direction (y) are greater than the dimensions of each of the fourth mounting surface in the second direction (x) and the third direction. [Appendix 14] A semiconductor module (B10) according to Appendix 13, wherein the fourth terminal (24) is located on the opposite side of the third terminal (23) relative to the first terminal (21) in the second direction (x). [Appendix 15] further comprising an input capacitor (50) conductively coupled to the first conductive layer (41) and the second conductive layer (42); A semiconductor module (B10) described in Appendix 14, wherein the input capacitor is located on the opposite side of the first mounting surface (212) and the second mounting surface (222) relative to the third edge (32A) in the third direction (y). [Appendix 16] a first terminal (21), a second terminal (22) and a third terminal (23); a semiconductor element (10) located on one side of the first terminal, the second terminal, and the third terminal in the first direction (z); and a sealing resin (30) that covers the semiconductor element. The semiconductor element includes a first circuit (C1) and a second circuit (C2) connected in series with each other, the first circuit is electrically connected to the first terminal and the third terminal; the second circuit is electrically connected to the second terminal and the third terminal; the sealing resin has a bottom surface (32) facing the other side in the first direction, the first terminal, the second terminal, and the third terminal each have a first mounting surface (212), a second mounting surface (222), and a third mounting surface (232) exposed from the bottom surface, the third mounting surface is located on the opposite side of the first mounting surface with respect to the second mounting surface in a second direction (x) perpendicular to the first direction, A semiconductor device (A50) in which, in a third direction (y) perpendicular to each of the first direction and the second direction, the dimensions of each of the first mounting surface and the second mounting surface are 40% or more of the dimensions of the sealing resin. [Appendix 17] a first terminal (21), a second terminal (22) and a third terminal (23); a semiconductor element (10) located on one side of the first terminal, the second terminal, and the third terminal in the first direction (z); and a sealing resin (30) that covers the semiconductor element. The semiconductor element includes a first circuit (C1) and a second circuit (C2) connected in series with each other, the first circuit is electrically connected to the first terminal and the third terminal; the second circuit is electrically connected to the second terminal and the third terminal; the sealing resin has a bottom surface (32) facing the other side in the first direction, the first terminal, the second terminal, and the third terminal each have a first mounting surface (212), a second mounting surface (222), and a third mounting surface (232) exposed from the bottom surface, the third mounting surface is located on the opposite side of the first mounting surface with respect to the second mounting surface in a second direction (x) perpendicular to the first direction, When viewed in the first direction, the first mounting surface and the third mounting surface overlap the first circuit and the second circuit, respectively; The semiconductor device (A50) has the second mounting surface overlapping at least one of the first circuit and the second circuit when viewed in the first direction. [Appendix 18] The semiconductor element (10) has a first electrode (121) electrically connected to the first circuit (C1), a second electrode (122) electrically connected to the second circuit (C2), and a third electrode (123) electrically connected to the first circuit and the second circuit, A semiconductor device (A50) described in Appendix 16 or 17, wherein the first electrode, the second electrode, and the third electrode are individually conductively connected to the first terminal (21), the second terminal (22), and the third terminal (23), respectively. [Appendix 19] The semiconductor element (10) has a first pad (131) that is electrically connected to the second circuit (C2) and a first rewiring (14) that electrically connects the first pad and the second electrode (122), The semiconductor device (A50) according to Appendix 18, wherein the first rewiring overlaps each of the first circuit (C1) and the second circuit when viewed in the first direction (z). [Appendix 20] the semiconductor element (10) has a second pad (132) that is electrically connected to the first circuit (C1) and a second rewiring (15) that electrically connects the second pad and the third electrode (123); The semiconductor device (A50) according to Appendix 19, wherein the second rewiring (15) overlaps each of the first circuit and the second circuit (C2) when viewed in the first direction (z). [Appendix 21] A semiconductor module (B10) described in Appendix 9, wherein, in the third direction (y), the entire first mounting surface (212) and the entire second mounting surface (222) are located between the third edge (32A) and the second region (451B). [Appendix 22] The semiconductor module (B40) according to Appendix 11, wherein each of the first mounting surface (212) and the second mounting surface (222) reaches the fourth edge (32B). [Appendix 23] The semiconductor module (B30) according to appendix 12, wherein the second mounting surface (222) includes a third surface (222B) and a fourth surface (222C) spaced apart from each other in the third direction (y). [Appendix 24] Further provided with a fourth terminal (24), The semiconductor element (10) includes a third circuit (C3) that is electrically connected to each of the first circuit (C1) and the second circuit (C2), the fourth terminal is electrically connected to the third circuit; the fourth terminal has a fourth mounting surface (242) exposed from the bottom surface (32), A semiconductor device (A50) described in Appendix 20, wherein the dimensions of each of the first mounting surface (212) and the second mounting surface (222) in the third direction (y) are greater than the dimensions of each of the fourth mounting surface in the second direction (x) and the third direction. [Explanation of symbols]

[0093] B10 to B40: Semiconductor modules A10 to A50: Semiconductor device 10: Semiconductor element 11: Main body C1, C2, C3: 1st circuit, 2nd circuit, 3rd circuit 121~124: 1st electrode ~ 4th electrode 131, 132, 133: 1st pad, 2nd pad, 3rd pad 14,15: 1st rewiring, 2nd rewiring 16:Protective film 21: 1st terminal 211: First connection surface 212: First mounting surface 212A: First Edge 212B, 212C: 1st side, 2nd side 213: First end surface 22: 2nd terminal 221: Second connection surface 222: Second mounting surface 222A: Second Edge 222B, 222C: 3rd side, 4th side 223: Second end surface 23: 3rd terminal 23A, 23B: Part 1, Part 2 231: Third connection surface 232: Third mounting surface 233: Third end surface 24: 4th terminal 241: 4th connection surface 242: 4th mounting surface 243: 4th end face 30: Sealing resin 31:Top surface 32: Bottom 32A, 32B: 3rd edge, 4th edge 33~36: 1st side ~ 4th side 40: Base material 41 to 44: First conductive layer to fourth conductive layer 45: Insulating layer 451: Mounting surface 451A.451B: 1st area, 2nd area 50: Input capacitor 51: Electrode 60: Bonding layer L: inductor C: Output capacitor z,x,y: 1st direction, 2nd direction, 3rd direction

Claims

1. Substrate and a semiconductor device located on one side of the base material in a first direction and conductively connected to the base material, The semiconductor device includes: a first terminal, a second terminal, and a third terminal; a semiconductor element located on one side of the first terminal, the second terminal, and the third terminal in the first direction; a sealing resin that covers the semiconductor element, The semiconductor element includes a first circuit and a second circuit connected in series with each other, the first circuit is electrically connected to the first terminal and the third terminal; the second circuit is electrically connected to the second terminal and the third terminal; the sealing resin has a bottom surface facing the base material, the first terminal, the second terminal, and the third terminal each have a first mounting surface, a second mounting surface, and a third mounting surface exposed from the bottom surface, the second mounting surface is spaced apart from the first mounting surface in a second direction perpendicular to the first direction; the first mounting surface includes a first edge extending in a third direction perpendicular to the first direction and the second direction; the second mounting surface extends in the third direction and includes a second edge located adjacent to the first edge in the second direction; the third mounting surface is located between the first edge and its extension line and the second edge and its extension line, the bottom surface extends in the second direction and includes a third edge spaced from the third mounting surface; The substrate is an insulating layer having a mounting surface facing the bottom surface; a first conductive layer, a second conductive layer, and a third conductive layer, each mounted on the mounting surface; the first mounting surface, the second mounting surface, and the third mounting surface are conductively bonded to the first conductive layer, the second conductive layer, and the third conductive layer, respectively; the mounting surface includes a first region and a second region, each of which entirely overlaps the bottom surface when viewed in the first direction; When viewed in the first direction, the first region is sandwiched between the first conductive layer and the second conductive layer, When viewed in the first direction, the second region is located on the opposite side of the first region from the third edge, A semiconductor module, wherein, when viewed in the first direction, a dimension in the second direction of a portion of the third conductive layer that overlaps the second region is greater than a minimum dimension in the second direction of the first region.

2. the semiconductor element has a first electrode electrically connected to the first circuit, a second electrode electrically connected to the second circuit, and a third electrode electrically connected to the first circuit and the second circuit; 2. The semiconductor module according to claim 1, wherein the first electrode, the second electrode, and the third electrode are conductively connected to the first terminal, the second terminal, and the third terminal, respectively.

3. The semiconductor module according to claim 2 , wherein the third mounting surface is located on an opposite side to a side on which the third edge is located, with the first mounting surface and the second mounting surface as references in the third direction.

4. The semiconductor module according to claim 3 , wherein a predetermined distance is provided between the third mounting surface and each of the first mounting surface and the second mounting surface in the third direction.

5. 5. The semiconductor module according to claim 4, wherein the dimension in the third direction of each of the first mounting surface and the second mounting surface is 40% or more of the dimension in the third direction of the sealing resin.

6. The semiconductor module according to claim 3 , wherein the first mounting surface and the second mounting surface overlap the first circuit and the second circuit, respectively, when viewed in the first direction.

7. the third terminal has a first portion including the third mounting surface and a second portion connected to the first portion and covered with the sealing resin, a dimension of the second portion in the first direction is smaller than a dimension of the first portion in the first direction; The semiconductor module according to claim 6 , wherein the third electrode is conductively joined to the second portion.

8. the bottom surface extends in the second direction and includes a fourth edge located on the opposite side of the third edge with respect to the first mounting surface and the second mounting surface; The semiconductor module according to claim 7 , wherein the third mounting surface reaches the fourth edge.

9. The semiconductor module according to claim 8 , wherein each of the first mounting surface and the second mounting surface reaches the third edge.

10. The semiconductor module according to claim 9 , wherein the third mounting surface is spaced apart from each of the first circuit and the second circuit when viewed in the first direction.

11. The semiconductor module according to claim 9 , wherein the third mounting surface overlaps at least one of the first circuit and the second circuit when viewed in the first direction.

12. The semiconductor module according to claim 8 , wherein the first mounting surface includes a first surface and a second surface spaced apart from each other in the third direction.

13. Further comprising a fourth terminal; a third circuit is configured in the semiconductor element and is electrically connected to each of the first circuit and the second circuit; the fourth terminal is electrically connected to the third circuit; the fourth terminal has a fourth mounting surface exposed from the bottom surface, 13. The semiconductor module according to claim 6, wherein the dimensions of each of the first mounting surface and the second mounting surface in the third direction are larger than the dimensions of each of the fourth mounting surface in the second direction and the third direction.

14. The semiconductor module according to claim 13 , wherein the fourth terminal is located on an opposite side to the third terminal with respect to the first terminal in the second direction.

15. an input capacitor conductively coupled to the first conductive layer and the second conductive layer; 15 . The semiconductor module according to claim 14 , wherein the input capacitor is located on an opposite side to the first mounting surface and the second mounting surface with respect to the third edge in the third direction.

16. a first terminal, a second terminal, and a third terminal; a semiconductor element located on one side of the first terminal, the second terminal, and the third terminal in a first direction; a sealing resin that covers the semiconductor element, The semiconductor element includes a first circuit and a second circuit connected in series with each other, the first circuit is electrically connected to the first terminal and the third terminal; the second circuit is electrically connected to the second terminal and the third terminal; the sealing resin has a bottom surface facing the other side in the first direction, the first terminal, the second terminal, and the third terminal each have a first mounting surface, a second mounting surface, and a third mounting surface exposed from the bottom surface, the third mounting surface is located on the opposite side of the first mounting surface with respect to the second mounting surface in a second direction perpendicular to the first direction, In a third direction perpendicular to each of the first direction and the second direction, the dimensions of each of the first mounting surface and the second mounting surface are 40% or more of the dimensions of the sealing resin.

17. a first terminal, a second terminal, and a third terminal; a semiconductor element located on one side of the first terminal, the second terminal, and the third terminal in a first direction; a sealing resin that covers the semiconductor element, The semiconductor element includes a first circuit and a second circuit connected in series with each other, the first circuit is electrically connected to the first terminal and the third terminal; the second circuit is electrically connected to the second terminal and the third terminal; the sealing resin has a bottom surface facing the other side in the first direction, the first terminal, the second terminal, and the third terminal each have a first mounting surface, a second mounting surface, and a third mounting surface exposed from the bottom surface, the third mounting surface is located on the opposite side of the first mounting surface with respect to the second mounting surface in a second direction perpendicular to the first direction, When viewed in the first direction, the first mounting surface and the third mounting surface overlap the first circuit and the second circuit, respectively; When viewed in the first direction, the second mounting surface overlaps at least one of the first circuit and the second circuit.

18. the semiconductor element has a first electrode electrically connected to the first circuit, a second electrode electrically connected to the second circuit, and a third electrode electrically connected to the first circuit and the second circuit; 18. The semiconductor device according to claim 16, wherein the first electrode, the second electrode, and the third electrode are conductively connected to the first terminal, the second terminal, and the third terminal, respectively.

19. the semiconductor element has a first pad electrically connected to the second circuit and a first rewiring electrically connecting the first pad and the second electrode; 19. The semiconductor device according to claim 18, wherein the first rewiring overlaps each of the first circuit and the second circuit when viewed in the first direction.

20. the semiconductor element has a second pad electrically connected to the first circuit and a second rewiring electrically connecting the second pad and the third electrode; 20. The semiconductor device according to claim 19, wherein the second rewiring overlaps each of the first circuit and the second circuit when viewed in the first direction.

Images