Semiconductor device and method of manufacturing the same

Abstract

To provide a miniaturized semiconductor device and a manufacturing method of the semiconductor device.SOLUTION: The semiconductor device 10 includes a first substrate 110, a first wiring member 210 through which a current flows, a first semiconductor element 310 through which the current flows in a thickness direction, a third wiring member 230 through which the current flows, a second semiconductor element 320 through which the current flows in the thickness direction, a second wiring member 220 through which the current flows, and a second substrate 120 that are stacked in this order. The second semiconductor element controls a current flowing between the second wiring member and the third wiring member.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] There is a demand for miniaturization of semiconductor devices.

[0003] Patent Document 1 describes a semiconductor device that is miniaturized by stacking a semiconductor element 106 with a second adhesive layer on a semiconductor element 16 with a first adhesive layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-129897 Summary of the Invention [Problem to be solved by the invention]

[0005] One example of an object of the present invention is to miniaturize semiconductor devices. [Means for solving the problem]

[0006] According to the present invention, the following semiconductor device and method for manufacturing the semiconductor device are provided. [1] a first substrate; a first wiring member through which a current flows; a first semiconductor element through which a current flows in a thickness direction; a third wiring member through which a current flows; a second semiconductor element through which a current flows in the thickness direction; a second wiring member through which a current flows; a second substrate; are layered in this order, the first semiconductor element controls a current flowing between the first wiring member and the third wiring member; The second semiconductor element controls the current flowing between the second wiring member and the third wiring member. [2] At least one of a surface of the first substrate opposite to the first wiring member and a surface of the second substrate opposite to the second wiring member has a heat dissipation member. The semiconductor device according to [1]. [3] a sealing layer that seals the first substrate, the first wiring member, the first semiconductor element, the third wiring member, the second semiconductor element, the second wiring member, and the second substrate; the first substrate has at least a part of a surface opposite to the first wiring member exposed from the sealing layer; The semiconductor device according to [1], wherein at least a portion of the surface of the second substrate opposite to the second wiring member is exposed from the sealing layer. [4] At least one of the first substrate and the second substrate has at least one of a recess and a protrusion in a portion exposed from the sealing member. The semiconductor device according to [3]. [5] a conductive bonding layer is provided at least one between the first wiring member and the first semiconductor element, between the first semiconductor element and the third wiring member, between the second wiring member and the second semiconductor element, or between the second semiconductor element and the third wiring member; The semiconductor device according to any one of [1] to [4]. [6] a portion of the third wiring member located between the first semiconductor element and the second semiconductor element is thicker than other portions of the third wiring member; The semiconductor device according to any one of [1] to [5]. [7] In a plan view, the terminal portion of the first wiring member, the terminal portion of the second wiring member, and the terminal portion of the third wiring member overlap each other. The semiconductor device according to any one of [1] to [6]. [8] In a plan view, the terminal portion of the first wiring member and the terminal portion of the third wiring member, and the terminal portion of the second wiring member and the terminal portion of the third wiring member are spaced apart from each other by 5 mm or more. The semiconductor device according to any one of [1] to [7]. [9] a fixing step of fixing a first substrate, a first wiring member, a first semiconductor element, a third wiring member, a second semiconductor element, a second wiring member, and a second substrate in a stacked state in this order; A method for manufacturing a semiconductor device.

[10] a sealing step of sealing the first substrate, the first wiring member, the first semiconductor element, the third wiring member, the second semiconductor element, the second wiring member, and the second substrate with a sealing layer; [9] A method for manufacturing a semiconductor device according to [9].

[11] a first lamination step of laminating and fixing a first substrate, a first wiring member, and a first semiconductor element in this order; a first sealing step of sealing the first substrate, the first wiring member, and the first semiconductor element with a sealing material; a second lamination step of laminating and fixing a second substrate, a second wiring member, and a second semiconductor element in this order; a second sealing step of sealing the second substrate, the second wiring member, and the second semiconductor element with a sealing layer; a fixing step of fixing the first semiconductor element and the second semiconductor element to opposite surfaces of a third wiring member; A method for manufacturing a semiconductor device, comprising: [Effects of the Invention]

[0007] According to the present invention, the semiconductor device can be miniaturized. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a diagram showing an example of a cross section of a semiconductor device according to an embodiment of the present invention; [Figure 2]1 is a first example of a plan view of a semiconductor device viewed from the second substrate side. [Figure 3] 10 is a second example of a plan view of the semiconductor device as viewed from the second substrate side. [Figure 4] FIG. 1 is a first diagram showing a first manufacturing method of a semiconductor device according to the present embodiment. [Figure 5] FIG. 2 is a second diagram showing the first manufacturing method of the semiconductor device according to the present embodiment. [Figure 6] FIG. 3 is a third diagram showing the first manufacturing method of the semiconductor device according to the present embodiment. [Figure 7] FIG. 4 is a fourth diagram showing the first manufacturing method of the semiconductor device according to the present embodiment. [Figure 8] FIG. 1 is a first diagram showing a second manufacturing method of a semiconductor device according to this embodiment. [Figure 9] FIG. 2 is a second diagram showing the second manufacturing method of the semiconductor device according to the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all drawings, like components are designated by like reference numerals, and explanations thereof will be omitted where appropriate. Note that the drawings are for illustrative purposes only. The shapes and dimensional ratios of the components in the drawings do not necessarily correspond to the actual products.

[0010] In this specification, unless otherwise specified, the expression "a to b" in the description of a range of numerical values ​​means not less than a but not more than b. For example, "1% by mass to 5% by mass" means "not less than 1% by mass and not more than 5% by mass."

[0011] 1 is a diagram showing an example of a cross section of a semiconductor device 10 according to this embodiment. The semiconductor device 10 includes a first substrate 110 and a second substrate 120, a wiring member 200 including a first wiring member 210, a second wiring member 220, and a third wiring member 230, and a semiconductor element 300 including a first semiconductor element 310 and a second semiconductor element 320. As shown in FIG. 1, the semiconductor device 10 includes a first substrate 110, a first wiring member 210, a first semiconductor element 310, a third wiring member 230, a second semiconductor element 320, a second wiring member 220, and a second substrate 120 stacked in this order. The total thickness T0 of the semiconductor device 10 is not particularly limited, but is preferably, for example, 3 mm or more and 50 mm or less, and more preferably 3 mm or more and 30 mm or less.

[0012] The semiconductor device 10 of this embodiment has a configuration in which semiconductor elements are stacked in the thickness direction, which allows the semiconductor elements to be mounted at a high density relative to the area of ​​the first substrate 110 and the second substrate 120, making it possible to reduce the size.

[0013] 1, a heat dissipation layer 400 (described later) may be formed between the first substrate 110 and the second substrate 120 and each wiring member 200. A conductive layer 500 (described later) may be formed between each semiconductor element 300 and each wiring member 200. Of the above configurations, a sealing layer 600 that seals at least the semiconductor element 300 may be formed.

[0014] Moreover, the wiring member 200 includes wiring portions 201 (wiring portion 211 of the first wiring member 210, wiring portion 221 of the second wiring member 220, and wiring portion 231 of the third wiring member 230) and terminal portions 202 (wiring portion 212 of the first wiring member 210, wiring portion 222 of the second wiring member 220, and wiring portion 232 of the third wiring member 230). At least a portion of the wiring portion 201 is stacked with the semiconductor element 300 and is electrically and physically connected to it. Moreover, the terminal portion 202 is a portion of the wiring member 200 that is connected to external wiring, or an end of a drawn-out wiring that is connected to the wiring member 200.

[0015] Each component will be described in detail below.

[0016] [Semiconductor element 300] The semiconductor element 300 controls the flow of current in the thickness direction of the semiconductor device 10. In other words, it controls the current between the wiring members 200.

[0017] The semiconductor element 300 is, for example, a power semiconductor. The semiconductor element 300 controls, for example, a current of 1 A or more. This current may be 10 A or more, or even 100 A or more.

[0018] The first semiconductor element 310 and the second semiconductor element 320 may be the same element or different elements. The dimensions of the first semiconductor element 310 and the second semiconductor element 320 are preferably the same, but may be different.

[0019] [First Substrate 110 and Second Substrate 120] In the following description, the first substrate 110 will be described as a representative of the first substrate 110 and the second substrate 120. However, the second substrate 120 also has the same configuration as the first substrate 110.

[0020] The first substrate 110 supports the above-mentioned components and also dissipates heat generated by the semiconductor element 300 via the wiring member 200 .

[0021] From the viewpoint of more efficiently dissipating the heat generated by the semiconductor element 300, the first substrate 110 preferably includes a heat dissipation member 111 as shown in FIG. 1 . Furthermore, it is more preferable that the second substrate 120 further includes a heat dissipation member 121. Heat dissipation fins or radiators can be used as the heat dissipation members 111 and 121. The heat dissipation members 111 and 121 may be integrated with the first substrate 110 and the second substrate 120, respectively, or may be attached to the first substrate 110 and the second substrate 120, respectively.

[0022] From the viewpoints of thermal conductivity and mechanical strength, the material constituting the first substrate 110 can be one or a combination of two or more selected from metals such as copper, copper alloys, aluminum, and aluminum alloys. Among these, from the viewpoint of strength, the material constituting the first substrate 110 preferably contains at least one of copper and aluminum.

[0023] Although there are no particular limitations on the thickness T1 of the first substrate 110, the upper limit of the thickness T1 of the first substrate 110 is, for example, 5 mm or less, preferably 3 mm or less, and more preferably 1 mm or less. If the thickness T1 of the first substrate 110 is set to this numerical value or less, the entire semiconductor device 100 can be made thinner. The lower limit of the thickness T1 of the first substrate 110 is, for example, 0.1 mm or more, preferably 0.3 mm or more, and more preferably 0.5 mm or more. If the thickness T1 of the first substrate 110 is set to this value or more, the heat dissipation properties of the first substrate 110 can be improved.

[0024] Furthermore, the size (W01 and W02) of the first substrate 110 in a plan view is not particularly limited, but the upper limit of W01 and W02 is, for example, 200 mm or less, preferably 100 mm or less, and more preferably 50 mm or less. The lower limit values ​​of W01 and W02 are, for example, 10 mm or more, preferably 20 mm or more, and more preferably 50 mm or more.

[0025] As described above, the semiconductor device 10 according to this embodiment includes the encapsulating layer 600, which encapsulates the first substrate 110, the first wiring member 210, the first semiconductor element 310, the second wiring member 220, the second semiconductor element 320, the third wiring member 230, and the second substrate 120. However, in this case, it is preferable that at least a portion of the surface of the first substrate 110 opposite the first wiring member 210 is exposed from the encapsulating layer 600, and that at least a portion of the surface of the second substrate 120 opposite the second wiring member 220 is exposed from the encapsulating layer 600. Furthermore, it is preferable that the first substrate 110 and the second substrate 120 have at least one of a recessed portion and a protruding portion in the portion exposed from the encapsulating layer 600, which function as the heat dissipation members 111, 121.

[0026] [Wiring member 200] The wiring member 200 is a wiring for supplying current to the semiconductor element 300 and discharging the current that has flowed through the semiconductor element 300 to the outside. As described above, the wiring member 200 includes a wiring portion 201 connected to the semiconductor element 300 and a terminal portion 202 connected to an external terminal of the semiconductor device 10. As an example, the first wiring member 210 and the second wiring member 220 are connected to the same electrical component, for example, a power source such as a battery, and the third wiring member 230 is connected to the UVW terminals of a motor. However, the first wiring member 210 and the second wiring member 220 may be connected to the UVW terminals of a motor, and the third wiring member 230 may be connected to a power source such as a battery.

[0027] An example of the wiring member 200 is a lead frame. From the viewpoints of electrical conductivity and mechanical strength, the material constituting the wiring member 200 can be one or a combination of two or more selected from metals such as copper, copper alloys, aluminum, and aluminum alloys. Among these, from the viewpoints of heat resistance and cost, it is preferable that the material constituting the substrate 100 contains copper.

[0028] Note that the wiring member 200 may be manufactured by attaching a member including the terminal portion 202 to the wiring portion 201. Therefore, as shown in Fig. 1, the wiring portion 201 and the terminal portion 202 may have different heights in a cross-sectional view.

[0029] Furthermore, thickness T2 of wiring portion 211 of first wiring member 210 and wiring portion 221 of second wiring member 220 is not particularly limited, but the upper limit of thickness T2 is, for example, 5 mm or less, preferably 3 mm or less, and more preferably 2 mm or less. By setting thickness T2 at this value or less, the entire semiconductor device 10 can be made thinner. The lower limit of the thickness T2 is, for example, 0.1 mm or more, preferably 0.2 mm or more, and more preferably 0.3 mm or more. When the thickness T2 is set to this value or more, the conductivity of the first wiring member 210 and the second wiring member 220 can be improved.

[0030] Furthermore, the thickness T3 of the wiring portion 231 of the third wiring member 230 is not particularly limited, but the upper limit of the thickness T3 is, for example, 5 mm or less, preferably 3 mm or less, and more preferably 2 mm or less. If the thickness T3 is set to this numerical value or less, the entire semiconductor device 10 can be made thinner. The lower limit of the thickness T3 is, for example, 0.1 mm or more, preferably 0.3 mm or more, and more preferably 0.5 mm or more. When the thickness T3 is set to this value or more, the conductivity of the third wiring member 230 can be improved.

[0031] 1, thickness T3 of wiring portion 231 of third wiring member 230 may be greater than thickness of terminal portion 232 of third wiring member 230. In this case, distance T4 in the thickness direction between terminal portion 232 of third wiring member 230 and terminal portion 212 of first wiring member 210 and terminal portion 222 of second wiring member 220 is increased, thereby improving insulation between terminal portion 232 and terminal portion 212 and terminal portion 222.

[0032] [Heat dissipation layer 400] The heat dissipation layer 400 functions as an insulating layer for maintaining insulation between the substrate 100 and the wiring member 200, and also functions as a bonding layer for bonding the substrate 100 and the wiring member 200. In addition, the heat dissipation layer 400 preferably has thermal conductivity.

[0033] The thickness of the heat dissipation layer 400 is appropriately set depending on the purpose. From the viewpoint of more effectively transferring heat from the semiconductor elements to the substrate 100 while improving mechanical strength and heat resistance, the thickness of the heat dissipation layer 400 is preferably 30 μm or more and 300 μm or less. From the viewpoint of even better balance between heat dissipation and insulation properties throughout the substrate 100, the thickness is more preferably set to 50 μm or more and 200 μm or less. By setting the thickness of the heat dissipation layer 400 to the above upper limit value or less, heat from the semiconductor elements can be easily transferred to the substrate 100. Furthermore, by setting the thickness of the heat dissipation layer 400 to the above lower limit value or more, the heat dissipation layer 400 can sufficiently mitigate thermal stress caused by the difference in thermal expansion coefficients between the substrate 100 and the heat dissipation layer 400. Furthermore, the insulation properties of the substrate 100 are improved.

[0034] Furthermore, the heat dissipation layer 400 according to this embodiment preferably has a thermal conductivity of 3 W / (m·K) or more, more preferably 7 W / (m·K) or more, and even more preferably 12 W / (m·K) or more.

[0035] The heat dissipation layer 400 is formed, for example, by attaching a resin sheet containing a thermosetting resin as a binder resin and an insulating, thermally conductive filler to the first substrate 110 and the second substrate 120 and then thermally curing the resin sheet. Alternatively, the heat dissipation layer 400 is formed by applying a resin paste containing the above materials and then thermally curing the resin paste.

[0036] <Thermosetting resin> The thermosetting resin in the resin paste may be one or a combination of two or more selected from, for example, epoxy resin, phenol resin, urea resin, melamine resin, polyester (unsaturated polyester) resin, polyimide resin, silicone resin, and polyurethane resin.

[0037] The upper limit of the amount of thermosetting resin contained in 100 parts by mass of resin paste is preferably 80 parts by mass or less, more preferably 70 parts by mass or less, and even more preferably 60 parts by mass or less. The lower limit of the amount of thermosetting resin contained in 100 parts by mass of resin paste is preferably 10 parts by mass or more, more preferably 15 parts by mass or more, and even more preferably 20 parts by mass or more.

[0038] <Thermal conductive filler> The thermally conductive filler in the resin paste may be made of, for example, at least one of a metal oxide such as alumina and a nitride such as boron nitride.

[0039] The upper limit of the amount of the thermally conductive filler per 100 parts by mass of the thermosetting resin is preferably 400 parts by mass or less, more preferably 350 parts by mass or less, and even more preferably 320 parts by mass or less. The lower limit of the amount of the thermally conductive filler per 100 parts by mass of the thermosetting resin is preferably 150 parts by mass or more, more preferably 200 parts by mass or more, and even more preferably 250 parts by mass or more.

[0040] [Conductive layer 500] The conductive layer 500 electrically connects the semiconductor element 300 and the wiring member 200 and also functions as a bonding layer that bonds the semiconductor element 300 and the wiring member 200 together.

[0041] The thickness of the conductive layer 500 is set appropriately depending on the purpose, but is preferably, for example, 30 μm or more and 300 μm or less, and more preferably 30 μm or more and 300 μm or less.

[0042] The conductive layer 500 is formed from a metal particle-containing paste that includes metal particles that are sintered by heat treatment to form a particle interconnection structure and a dispersion medium for dispersing the metal particles. The conductive layer 500 is formed, for example, by applying the metal particle-containing paste and then performing a heat treatment. In addition to silver particles, we anticipate the use of copper particles, so we would appreciate it if you could add them.

[0043] <Metal particles> Metal particles include both particles that are entirely made of metal and particles whose surfaces are coated with a metal. Particles whose surfaces are coated with a metal are, for example, metal-coated resin particles in which the surfaces of resin particles such as silicone resin particles are coated with a metal. The metal constituting the metal particles includes, for example, at least one of silver and copper.

[0044] The shape of the metal particles is not particularly limited, but may be, for example, spherical, dendritic, string-like, flake-like, aggregated, polyhedral, etc. From the viewpoint of improving the sinterability of the metal particles and improving the uniformity of sintering, it is preferable to include spherical metal particles. Furthermore, from the viewpoint of reducing costs, it is preferable to include flake-like metal particles.

[0045] The metal particles preferably have a particle diameter D50 of 0.1 μm or more, more preferably 1.0 μm or more, and even more preferably 2.0 μm or more, at which the cumulative frequency is 50% in a volume-based cumulative frequency distribution curve measured using a laser diffraction particle size analyzer. The metal particles preferably have a particle diameter D50 of 10 μm or less, more preferably 8.0 μm or less, even more preferably 5.0 μm or less, and even more preferably 3.0 μm or less.

[0046] The upper limit of the metal particle content in 100 parts by mass of the metal particle-containing paste is preferably 95% by mass or less, and more preferably 93% by mass or less, and the lower limit of the metal particle content in 100 parts by mass of the metal particle-containing paste is preferably 70% by mass or more, and more preferably 80% by mass or more.

[0047] <Dispersion medium> Examples of the dispersion medium contained in the metal particle-containing paste include alcohols such as methanol, ethanol, 1-propanol, 2-propanol, 1-butanol, 2-butanol, ethylene glycol monomethyl ether, ethylene glycol monoethyl ether, ethylene glycol monopropyl ether, ethylene glycol monobutyl ether, propylene glycol monomethyl ether, propylene glycol monoethyl ether, propylene glycol monopropyl ether, propylene glycol monobutyl ether, methyl methoxybutanol, α-terpineol, β-terpineol, hexylene glycol, benzyl alcohol, 2-phenylethyl alcohol, isopalmityl alcohol, isostearyl alcohol, lauryl alcohol, ethylene glycol, propylene glycol, butylpropylene triglyceride, and glycerin; Ketones such as acetone, methyl ethyl ketone, methyl isobutyl ketone, cyclohexanone, diacetone alcohol (4-hydroxy-4-methyl-2-pentanone), 2-octanone, isophorone (3,5,5-trimethyl-2-cyclohexen-1-one), and diisobutyl ketone (2,6-dimethyl-4-heptanone); Esters such as ethyl acetate, butyl acetate, diethyl phthalate, dibutyl phthalate, acetoxyethane, methyl butyrate, methyl hexanoate, methyl octanoate, methyl decanoate, methyl cellosolve acetate, ethylene glycol monobutyl ether acetate, propylene glycol monomethyl ether acetate, 1,2-diacetoxyethane, tributyl phosphate, tricresyl phosphate, and tripentyl phosphate; ethers such as tetrahydrofuran, dipropyl ether, ethylene glycol dimethyl ether, ethylene glycol diethyl ether, ethylene glycol dibutyl ether, propylene glycol dimethyl ether, ethoxyethyl ether, 1,2-bis(2-diethoxy)ethane, 1,2-bis(2-methoxyethoxy)ethane, tripropylene glycol mono-n-butyl ether, and ethylene glycol mono-2-ethylhexyl ether; Ester ethers such as 2-(2-butoxyethoxy)ethane acetic acid; Ether alcohols such as 2-(2-methoxyethoxy)ethanol; Hydrocarbons such as toluene, xylene, n-paraffin, isoparaffin, dodecylbenzene, turpentine, kerosene, and diesel; nitriles such as acetonitrile or propionitrile; Amides such as acetamide and N,N-dimethylformamide; One or a combination of two or more selected from the group consisting of silicone oils such as low molecular weight volatile silicone oils and volatile organic modified silicone oils can be used.

[0048] The upper limit of the content of the dispersion medium in 100 parts by mass of the metal particle-containing paste is preferably 20% by mass or less, more preferably 10% by mass or less, and the lower limit of the content of the dispersion medium in 100 parts by mass of the metal particle-containing paste is preferably 1% by mass or more, more preferably 3% by mass or more.

[0049] [Sealing layer 600] The sealing layer 600 is formed, for example, from a cured thermosetting resin. The thermosetting resin may be one or a combination of two or more selected from the group consisting of epoxy resin, phenolic resin, polyimide resin, bismaleimide resin, urea resin, melamine resin, polyurethane resin, cyanate ester resin, silicone resin, oxetane resin (oxetane compound), (meth)acrylate resin, unsaturated polyester resin, diallyl phthalate resin, and benzoxazine resin. In particular, when the material constituting the heat dissipation layer 400 includes an epoxy resin, it is preferable that the thermosetting resin includes an epoxy resin. When both the heat dissipation layer 400 and the sealing layer 600 include an epoxy resin, the adhesion between the heat dissipation layer 400 and the sealing resin layer 40 is improved.

[0050] More specific examples of the thermosetting resin include novolac-type phenolic resins such as phenol novolac resin, cresol novolac resin, bisphenol A-type novolac resin, and triazine skeleton-containing phenol novolac resin; phenolic resins such as unmodified resol phenolic resins, resol-type phenolic resins such as oil-modified resol phenolic resins modified with tung oil, linseed oil, walnut oil, etc., phenol aralkyl resins, aralkyl-type phenolic resins such as biphenyl aralkyl-type phenolic resins, and triphenylmethane-type phenolic resins; Bisphenol-type epoxy resins such as bisphenol A-type epoxy resin, bisphenol F-type epoxy resin, tetramethylbisphenol F-type epoxy resin, bisphenol S-type epoxy resin, bisphenol E-type epoxy resin, bisphenol M-type epoxy resin, bisphenol P-type epoxy resin, and bisphenol Z-type epoxy resin; novolac-type epoxy resins such as phenol novolac-type epoxy resin and cresol novolac-type epoxy resin; Epoxy resins such as biphenyl-type epoxy resins, biphenylaralkyl-type epoxy resins, arylalkylene-type epoxy resins, naphthalene-type epoxy resins, anthracene-type epoxy resins, phenoxy-type epoxy resins, dicyclopentadiene-type epoxy resins, norbornene-type epoxy resins, adamantane-type epoxy resins, fluorene-type epoxy resins, and trisphenylmethane-type epoxy resins; One or a combination of two or more selected from the following can be used: resins having a triazine ring, such as urea resins and melamine resins; unsaturated polyester resins; maleimide resins, such as bismaleimide compounds; polyurethane resins; diallyl phthalate resins; silicone-based resins; benzoxazine resins; polyimide resins; polyamide-imide resins; and cyanate ester resins, such as benzocyclobutene resins, novolac cyanate resins, bisphenol A cyanate resins, bisphenol E cyanate resins, and tetramethylbisphenol F cyanate resins.

[0051] The sealing layer 600 may also contain a filler. Examples of materials that can be used for the filler include silica, alumina, kaolin, talc, clay, mica, rock wool, wollastonite, glass powder, glass flakes, glass beads, glass fiber, silicon carbide, silicon nitride, aluminum nitride, carbon black, graphite, titanium dioxide, calcium carbonate, calcium sulfate, barium carbonate, magnesium carbonate, magnesium sulfate, barium sulfate, cellulose, aramid, and wood, and the like can be used alone or in combination.

[0052] Next, each diagram in Figure 2 is a first example of a plan view of the semiconductor device 10 shown in Figure 1 as seen from the second substrate 120 side. Note that Figure 2(A) omits the illustration of the second substrate 120, the second wiring member 220, and the second semiconductor element 320. Figure 2(B) omits the illustration of the second substrate 120 and the second wiring member 220. Figure 2(C) illustrates the illustration of each component without omitting any details.

[0053] 2, two first semiconductor elements 310 and two second semiconductor elements 320 are provided. The first semiconductor elements 310a and 310b are mounted on the wiring portion 211 of the first wiring member 210. The wiring portion 231 of the third wiring member 230 is positioned so as to partially overlap the first semiconductor elements 310a and 310b. The second semiconductor elements 320a and 320b are positioned so as to partially overlap the wiring portion 231 of the third wiring member 230.

[0054] 2, the first semiconductor elements 310a and 310b are connected in parallel to the first wiring member 210 and the third wiring member 230. The second semiconductor elements 320a and 320b are connected in parallel to the second wiring member 220 and the third wiring member 230. In the structure shown in FIG. 2, the first semiconductor elements 310a and 310b are preferably the same semiconductor element, and the second semiconductor elements 320a and 320b are preferably the same semiconductor element.

[0055] 2, when viewed from a direction perpendicular to the substrate 110, at least a portion of the terminal portion 212 of the first wiring member 210, at least a portion of the terminal portion 222 of the second wiring member 220, and at least a portion of the terminal portion 232 of the third wiring member 230 overlap one another. For example, the width W2 of the terminal portion 212 and the terminal portion 222 is larger than the width W1 of the terminal portion 232, and the entire terminal portion 232 overlaps the terminal portion 212 and the terminal portion 222 in the width direction. According to the above configuration, the parasitic inductance caused by the wiring member 200 of the semiconductor device 10 can be reduced.

[0056] It is also preferable that the first substrate 110 and the second substrate 120 have the same dimensions in a plan view and overlap entirely, but the first substrate 110 and the second substrate 120 may only partially overlap in a plan view.

[0057] In addition, in the example shown in FIG. 2, the terminal portion 212 of the first wiring member 210, the terminal portion 222 of the second wiring member 220, and the terminal portion 232 of the third wiring member 230 overlap, but the terminal portions 202 do not have to overlap.

[0058] 3 is a second example of a plan view of the semiconductor device 10 as viewed from the second substrate 120 side. In the example shown in FIG. 3, the terminal portions 202 do not overlap, the terminal portions 212 and 232 are separated in the width direction by a width W3, and the terminal portions 222 and 232 are separated in the width direction by a width W4. In this case, the insulation between the terminal portion 232 and the terminal portions 212 and 222 can be improved. The widths W3 and W4 are, for example, 5 mm or more.

[0059] 2, there are two each of the first semiconductor elements 310 and the second semiconductor elements 320, but there may be one each of the first semiconductor elements 310 and the second semiconductor elements 320, or three or more each of them. Furthermore, it is preferable that the number of first semiconductor elements 310 and the number of second semiconductor elements 320 are the same, but they may be different.

[0060] [Method of Manufacturing the Semiconductor Device 10] Next, a method for manufacturing the semiconductor device 10 according to this embodiment will be described. Figures 4 to 7 are cross-sectional views showing the steps of manufacturing the semiconductor device 10 according to this embodiment.

[0061] First, as shown in FIG. 4, a first substrate 110 and a second substrate 120 are prepared. Next, a first wiring member 210 is fixed to the first substrate 110, and a second wiring member 220 is fixed to the second substrate 120 (step S10). For example, the above-described resin sheet is disposed on the first substrate 110 and the second substrate 120, or the above-described resin paste is applied thereto, and the first wiring member 210 and the second wiring member 220 are disposed in the area where the resin sheet is disposed or the resin paste is applied, respectively, and a heat treatment is performed to harden the thermosetting resin contained in the resin sheet or the resin paste. At this time, a heat dissipation layer 400 is formed between the first substrate 110 and the first wiring member 210, and between the second substrate 120 and the second wiring member 220.

[0062] 5, a first semiconductor element 310 is fixed to the surface of the first wiring member 210 opposite the first substrate 110, and a second semiconductor element 320 is fixed to the surface of the second wiring member 220 opposite the second substrate 120 (step S20). For example, the metal particle-containing paste described above is applied to the surface of the first wiring member 210 opposite the first substrate 110, and the first semiconductor element 310 is placed in the area where the metal particle-containing paste is applied and heat-treated, thereby fixing the first semiconductor element 310. Similarly, a metal particle-containing paste is applied to the surface of the second wiring member 210 opposite the second substrate 120, and the second semiconductor element 320 is placed in the area where the metal particle-containing paste is applied and heat-treated, thereby fixing the second semiconductor element 320.

[0063] 6, the surface of the first semiconductor element 310 opposite to the first wiring member 210 is fixed to the first surface of the third wiring member 230, and the surface of the second semiconductor element 320 opposite to the second wiring member 220 is fixed to the second surface (the surface opposite to the first surface) of the third wiring member 230 (step S30). For example, the metal particle-containing paste described above is applied to the first and second surfaces of the wiring portion 231 of the third wiring member 230. Then, the surface of the first semiconductor element 310 opposite to the first wiring member 210 is placed on the first surface of the wiring portion 231, and the surface of the second semiconductor element 320 opposite to the second wiring member 220 is placed on the second surface of the wiring portion 231. The metal particle-containing paste is then heat-treated to fix the surface of the first semiconductor element 310 opposite the first wiring member 210 and the surface of the second semiconductor element 320 opposite the second wiring member 220 to the third wiring member 230.

[0064] 7, the region including the first semiconductor element 310 and the second semiconductor element 320 is sealed with a sealing layer 600 (step S40). For example, the above-described laminated structure is placed in a mold, and the above-described thermosetting resin is poured into the mold and thermally cured to form the sealing layer 600. The shape of the mold is not particularly limited, but it is preferable that the mold has a shape that does not form the sealing layer 600 on the surface of the first substrate 110 and the second substrate 120 opposite to each wiring member 200. By not forming the sealing layer 600 on the surface of the first substrate 110 and the second substrate 120 opposite to each wiring member 200, the heat dissipation properties of the first substrate 110 and the second substrate 120 can be improved.

[0065] Next, a description will be given of a modified method of manufacturing the semiconductor device 10. Figures 8 and 9 are cross-sectional views showing steps in a modified method of manufacturing the semiconductor device 10.

[0066] 8, after step S20, a region of the stack of the first substrate 110, the first wiring member 210, and the first semiconductor element 310 that includes the first semiconductor element 310 is sealed with a sealing layer 600, and similarly, a region of the stack of the second substrate 120, the second wiring member 220, and the second semiconductor element 320 that includes the second semiconductor element 320 is sealed with the sealing layer 600 (step S30). Specifically, the stack of the first substrate 110, the first wiring member 210, and the first semiconductor element 310 and the stack of the second substrate 120, the second wiring member 220, and the second semiconductor element 320 are each placed in a mold, and the above-mentioned thermosetting resin is poured into the mold and thermally cured to form the sealing layer 600. However, the sealing layer 600 is not formed on at least a part of the surface of the first semiconductor element 310 and the second semiconductor element 320 opposite to the wiring member 200 .

[0067] 9, the surface of the first semiconductor element 310 opposite the first wiring member 210 and the surface of the second semiconductor element 320 opposite the second wiring member 220 are fixed to the third wiring member 230 (step S40). Specifically, the metal particle-containing paste described above is applied to both surfaces of the wiring portion 231 of the third wiring member 230, the surface of the first semiconductor element 310 opposite the first wiring member 210 is placed on one surface of the wiring portion 231, and the surface of the second semiconductor element 320 opposite the second wiring member 220 is placed on the other surface of the wiring portion 231, and heat treatment is performed. In this way, the semiconductor device 10 according to this embodiment can be manufactured even in this modified example.

[0068] In this way, the semiconductor device 10 according to this embodiment can be made smaller than conventional semiconductor devices.

[0069] Although the embodiments of the present invention have been described above with reference to the drawings, these are merely examples of the present invention, and various other configurations can also be adopted. [Explanation of symbols]

[0070] 10 Semiconductor devices 110 first substrate 120 Second substrate 200 Wiring materials 210 First wiring member 220 Second wiring member 230 Third wiring member 300 Semiconductor elements 310 First semiconductor element 320 Second semiconductor element 400 Heat dissipation layer 500 conductive layer 600 sealing layer

Claims

1. a first substrate; a first wiring member through which a current flows; a first semiconductor element through which a current flows in a thickness direction; a third wiring member through which a current flows; a second semiconductor element through which a current flows in the thickness direction; a second wiring member through which a current flows; a second substrate; are layered in this order, the first semiconductor element controls a current flowing between the first wiring member and the third wiring member; The second semiconductor element controls a current flowing between the second wiring member and the third wiring member.

2. At least one of a surface of the first substrate opposite to the first wiring member and a surface of the second substrate opposite to the second wiring member has a heat dissipation member. The semiconductor device according to claim 1 .

3. a sealing layer that seals the first substrate, the first wiring member, the first semiconductor element, the third wiring member, the second semiconductor element, the second wiring member, and the second substrate; the first substrate has at least a part of a surface opposite to the first wiring member exposed from the sealing layer; The semiconductor device according to claim 1 , wherein at least a part of the surface of said second substrate opposite to said second wiring member is exposed from said sealing layer.

4. At least one of the first substrate and the second substrate has at least one of a recess and a protrusion in a portion exposed from the sealing member. The semiconductor device according to claim 3 .

5. a conductive bonding layer is provided at least one between the first wiring member and the first semiconductor element, between the first semiconductor element and the third wiring member, between the second wiring member and the second semiconductor element, or between the second semiconductor element and the third wiring member; 3. The semiconductor device according to claim 1.

6. a portion of the third wiring member located between the first semiconductor element and the second semiconductor element is thicker than other portions of the third wiring member; 3. The semiconductor device according to claim 1.

7. In a plan view, the terminal portion of the first wiring member, the terminal portion of the second wiring member, and the terminal portion of the third wiring member overlap each other.

3. The semiconductor device according to claim 1.

8. In a plan view, the terminal portion of the first wiring member and the terminal portion of the third wiring member, and the terminal portion of the second wiring member and the terminal portion of the third wiring member are spaced apart from each other by 5 mm or more.

3. The semiconductor device according to claim 1.

9. a fixing step of fixing a first substrate, a first wiring member, a first semiconductor element, a third wiring member, a second semiconductor element, a second wiring member, and a second substrate in a stacked state in this order; A method for manufacturing a semiconductor device.

10. a sealing step of sealing the first substrate, the first wiring member, the first semiconductor element, the third wiring member, the second semiconductor element, the second wiring member, and the second substrate with a sealing layer; The method for manufacturing a semiconductor device according to claim 9 .

11. a first lamination step of laminating and fixing a first substrate, a first wiring member, and a first semiconductor element in this order; a first sealing step of sealing the first substrate, the first wiring member, and the first semiconductor element with a sealing material; a second lamination step of laminating and fixing a second substrate, a second wiring member, and a second semiconductor element in this order; a second sealing step of sealing the second substrate, the second wiring member, and the second semiconductor element with a sealing layer; a fixing step of fixing the first semiconductor element and the second semiconductor element to opposite surfaces of a third wiring member; A method for manufacturing a semiconductor device, comprising:

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