Front-end integrated circuit incorporating different silicon-on-insulator technologies

Abstract

To provide a silicon-on-insulator (SOI)-based front-end integrated circuit providing a fully integrated front-end integrated circuit (FEIC) including a switch, a low noise amplifier (LNA) and a power amplifier (PA), and to provide a method of manufacturing the same.SOLUTION: In the FEIC100a, the PA110 is incorporated into the thick-film region 108a of the IC to be a partially-depleted silicon-on-insulator PA (PDSOIPA), and the switch device 130 and the LNA120 are incorporated into the thin-film region 108b of the IC to be a fully-depleted silicon-on-insulator (FDSOI) switch and LNA. The resulting fully integrated FEIC includes a PSDSOIPA with an FDSOI switch and LNA. Passive components can be incorporated in thick-film regions, thin-film regions, or both.SELECTED DRAWING: FIG. 1A

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application is a division of "Different Silicon-on-Insulator Techniques," filed on November 12, 2020. U.S. Provisional Application No. 63 / 112,951 entitled "Front-End Integrated Circuit Incorporating Technology" No. 60 / 699,992, filed on Dec. 1, 2003, which is expressly incorporated herein by reference in its entirety.

[0002] The present disclosure generally relates to front-end integrated circuits for radio frequency applications. do. [Background technology]

[0003] The front-end module (FEM) is a component in the radio front-end circuit of a wireless device. It is a built-in module that integrates various functional components used in the The module supports broadband cellular network technologies (e.g., 3G, 4G, 5G, Long-Term Evolution (LTE), wireless network technologies (e.g., Wi-Fi), short-range Wireless technologies (e.g., Bluetooth®), and Global Positioning Systems (GPOSS) Processes radio frequency (RF) signals compatible with various wireless protocols, such as PS technology The front-end module typically converts the radio frequency signal into Circuitry between the antenna and the digital baseband system sufficient to transmit and receive The FEM includes an electrical component that processes the modulated signal received by the antenna. Required to provide a signal suitable for input to a baseband analog-to-digital converter (ADC) All filters, low noise amplifiers (LNA) and down-conversion mixers are The FEM may also include a transmitter power supply that processes the signal for transmission via the antenna. It may contain power amplifiers (PA) and other circuits. The FEM is a surface mount technology (SMT) module. The FEM may be a PA block, LN A block, input / output matching, MIPI standard digital control block, filter, duplexer , multiplexers, antenna switches, band selection switches, etc. An integrated circuit (FEIC) is a single semiconductor die that contains the functionality of the FEM. Summary of the Invention

[0004] According to a number of implementations, the present disclosure provides a semiconductor device comprising a substrate, an insulator layer on top of the substrate, and and a semiconductor layer on top of the insulator, The body layer forms a thin film region and a thick film region, and the thin film region is formed by one or more fully depleted silicon oxide layers. a fiber-defect-insulator (FDSOI) low noise amplifier (LNA) device and one or more FDSs The thick film region includes one or more partially depleted silicon-on-insulator (OI) switch devices. Includes a power amplifier (PA) device.

[0005] In some embodiments, the insulator layer is at least 100 nm thick. In some embodiments, the semiconductor layer in the thin film region is at least 5 nm thick. and a thickness of 50 nm or less. In some further embodiments, the thick film The semiconductor layer in the region is at least about 50 nm thick and no thicker than 180 nm. It is thickness.

[0006] In some embodiments, the insulator layer is a buried oxide layer. In some embodiments, the semiconductor layer in the thin film region may comprise one or more FDSOI LNA devices. In some embodiments, the front-end integrated circuit is Additionally, it may include one or more passive devices integrated into the thin film region of the semiconductor layer. In an embodiment, the front-end integrated circuit is further integrated into the thick film region of the semiconductor layer. It includes one or more passive devices.

[0007] In some embodiments, the thin film region of the semiconductor layer is formed using localized thinning. In some embodiments, the thick region of the semiconductor layer is grown using selective epitaxial growth. It is formed using

[0008] According to a number of implementations, the present disclosure relates to a method for manufacturing a front-end integrated circuit. The method includes forming an insulator layer on top of the substrate. The method also includes forming a semiconductor layer on top of the modulator layer. Incorporating a flat-type silicon-on-insulator (FDSOI) low-noise amplifier (LNA) device The method also includes incorporating an FDSOI switch device in the semiconductor layer. The method also includes increasing the thickness of a portion of the semiconductor layer to form a thickened region of the semiconductor layer. The method also includes: The device is located in the thin film region of the semiconductor layer and is a partially depleted silicon-on-insulator (P DSOI (Discrete on Insulator) power amplifier (PA) devices are located in the thick-film region. This also includes incorporating the device into a thick region of the semiconductor layer.

[0009] In some embodiments, the insulator layer is at least about 100 nm thick. In some embodiments, the thin film region of the semiconductor layer is at least about 5 nm thick. and is about 50 nm or less in thickness. The thick region of the layer is at least about 50 nm thick and no more than 180 nm thick. do.

[0010] In some embodiments, the thin film region of the semiconductor layer is a gate electrode for the FDSOI LNA device. In some embodiments, the method further comprises: In some embodiments, the method also includes incorporating a semiconductor device into the thin film region of the semiconductor layer. It also includes incorporating one or more passive devices in the thickened region of the semiconductor layer. In one embodiment, increasing the thickness may be achieved by using selective epitaxial growth. Includes:

[0011] According to a number of implementations, the present disclosure relates to a method for manufacturing a front-end integrated circuit. The method includes forming an insulator layer on top of the substrate. The method also includes forming a semiconductor layer on top of the modulator layer. Incorporating a planar silicon-on-insulator (PDSOI) power amplifier (PA) device The method also includes thinning a thickness of a portion of the semiconductor layer to form a thin film region of the semiconductor layer. The method also includes reducing the thickness of a fully depleted silicon-on-insulator (FDS) This also includes incorporating a low noise amplifier (LNA) device into the thin film region of the semiconductor layer. The method also includes providing a PDSOIPA device in a thick film region of a semiconductor layer and providing a FDSOIL As the NA device and the FDSOI switch device are in the thin film region of the semiconductor layer, It also includes incorporating FDSOI switch devices in thin film regions of the semiconductor layer.

[0012] In some embodiments, the insulator layer is at least about 100 nm thick. In some embodiments, the thin film region of the semiconductor layer is at least about 5 nm thick. and is about 50 nm or less in thickness. The thick region of the layer is at least about 50 nm thick and no more than 180 nm thick. do.

[0013] In some embodiments, the thin film region of the semiconductor layer is a gate electrode for the FDSOI LNA device. In some embodiments, the method further comprises: In some embodiments, the method also includes incorporating a semiconductor device into the thin film region of the semiconductor layer. It also includes incorporating one or more passive devices in the thickened region of the semiconductor layer. In an embodiment, reducing the thickness comprises using local thinning.

[0014] According to a number of implementations, the present disclosure relates to a method for manufacturing a front-end integrated circuit. The method includes forming an insulator layer on top of the substrate. The method also includes forming a semiconductor layer having a first thickness on top of the modulator layer. Increasing the thickness of a portion of the semiconductor layer causes the remaining portion of the semiconductor layer to have a first thickness. The method also includes forming a thick region of the semiconductor layer so that the portion becomes a thin region. The method also includes incorporating voltage analog circuits in the thick film region. This also includes incorporating analog circuits.

[0015] In some embodiments, the insulator layer is at least about 100 nm thick. In some embodiments, the thin film region of the semiconductor layer is at least about 5 nm thick. and is about 50 nm or less in thickness. The thick region of the layer is at least about 50 nm thick and no more than 180 nm thick. do.

[0016] In some embodiments, the high voltage analog circuitry includes a low dropout regulator. In some embodiments, the high voltage analog circuitry includes a high voltage power amplifier. In some embodiments, the method further includes incorporating digital circuitry in the thin film region. nothing.

[0017] According to a number of implementations, the present disclosure relates to a method for manufacturing a front-end integrated circuit. The method includes forming an insulator layer on top of the substrate. The method also includes forming a semiconductor layer having a first thickness on top of the modulator layer. Reducing the thickness of a portion of the semiconductor layer leaves the remainder of the semiconductor layer having a first thickness. forming a thin film region of the semiconductor layer such that the portion becomes a thick film region. The method also includes incorporating a radio frequency (RF) device in the thick film region. This also includes incorporating analog or digital circuits into the device.

[0018] In some embodiments, the insulator layer is at least about 100 nm thick. In some embodiments, the thin film region of the semiconductor layer is at least about 5 nm thick. and is about 50 nm or less in thickness. The thick region of the layer is at least about 50 nm thick and no more than 180 nm thick. do.

[0019] In some embodiments, the RF device in the thick film region is a power amplifier (PA). In some further embodiments, the PA device comprises a partially depleted silicon dioxide (CVD) semiconductor device. Includes silicon-on-insulator (PDSOI) PA devices.

[0020] In some embodiments, the digital circuitry includes logic gates.

[0021] For purposes of summarizing this disclosure, certain aspects, advantages, and novel features have been described herein. Not all such advantages may be achieved in accordance with any particular embodiment. It should be understood that the disclosed embodiments do not constitute a substitute for the teachings herein. One advantage taught herein is achieved without necessarily achieving other advantages that may be shown or implied. Or, it may be implemented in a manner that achieves or optimizes a set of advantages. [Brief explanation of the drawings]

[0022] [Figure 1A] A fully integrated front-end integrated circuit (FEIC) fabricated using silicon-on-insulator (SOI) processing technology is shown. [Figure 1B] Another fully integrated FEIC fabricated using SOI processing technology is shown. [Figure 2A] 1 shows an exemplary FEIC at different stages in the manufacturing process. [Figure 2B] 1 shows an exemplary FEIC at different stages in the manufacturing process. [Figure 2C]1 shows an exemplary FEIC at different stages in the manufacturing process. [Figure 2D] 1 shows an exemplary FEIC at different stages in the manufacturing process. [Figure 3A] 2A-2D illustrate a variation of the FEIC integration process described in connection with FIGS. [Figure 3B] 2A-2D illustrate a variation of the FEIC integration process described in connection with FIGS. [Figure 3C] 2A-2D illustrate a variation of the FEIC integration process described in connection with FIGS. [Figure 3D] 2A-2D illustrate a variation of the FEIC integration process described in connection with FIGS. [Figure 4A] 10A-10C illustrate other exemplary FEICs at different stages in the manufacturing process. [Figure 4B] 10A-10C illustrate other exemplary FEICs at different stages in the manufacturing process. [Figure 4C] 10A-10C illustrate other exemplary FEICs at different stages in the manufacturing process. [Figure 4D] 10A-10C illustrate other exemplary FEICs at different stages in the manufacturing process. [Figure 5A] 4A-4D illustrate a variation of the FEIC integration process described in connection with FIGS. [Figure 5B] 4A-4D illustrate a variation of the FEIC integration process described in connection with FIGS. [Figure 5C] 4A-4D illustrate a variation of the FEIC integration process described in connection with FIGS. [Figure 5D] 4A-4D illustrate a variation of the FEIC integration process described in connection with FIGS. [Figure 6A] A method for incorporating an integrated FEIC with a partially depleted silicon-on-insulator (PDSOI) power amplifier (PA) device, a fully depleted silicon-on-insulator (FDSOI) low noise amplifier (LNA) device, and an FDSOI switch device is presented. [Figure 6B]A method for incorporating an integrated FEIC with a partially depleted silicon-on-insulator (PDSOI) power amplifier (PA) device, a fully depleted silicon-on-insulator (FDSOI) low noise amplifier (LNA) device, and an FDSOI switch device is presented. [Figure 7A] Additional methods for incorporating an integrated FEIC with PDSOIPA, FDSOILNA, and FDSOI switch devices are presented. [Figure 7B] Additional methods for incorporating an integrated FEIC with PDSOIPA, FDSOILNA, and FDSOI switch devices are presented. DETAILED DESCRIPTION OF THE INVENTION

[0023] The headings provided herein, if any, are for convenience only and do not necessarily reflect the nature of the invention claimed. It does not affect the scope or meaning of the subject matter. overview

[0024] Semiconductor Front-End Integrated Circuit (FEIC) is a Front-End Module (FEM) The ever-increasing demand for higher performance, smaller size, and lower cost It is desirable to develop the technology base of FEIC to satisfy the following requirements. Analog circuits are typical The analog circuitry used in the FEIC is a low noise amplifier ( LNA), switches, power amplifiers (PA), passive devices, analog circuits (e.g., level shifters, summing devices, current mirrors, etc.), digital circuits (e.g. logic gates), regulators This includes elements such as regulators (e.g., low dropout regulators), and charge pumps. A fully integrated radio frequency (RF) FEIC, as the term is used herein, is a The elements for both transmission and reception are integrated into a single die. These elements include the PA, LNA, and and switches, along with appropriate passive devices, analog and digital circuits, regulators, etc. It may include.

[0025] A promising route to creating fully integrated RFFEICs is silicon-on-insulator (S-on-insulator). SOI is a process technology that integrates silicon semiconductor devices into a layer of silicon on insulator (SOI) technology. - Insulator - Manufactured on a silicon substrate, reducing the parasitic capacitance within the device The performance is improved by reducing the SOI process technology. For example, LNA performance with high bandwidth, low noise figure (NF), high linearity, power efficiency, small size SOI allows for small package footprint, low insertion loss, etc. The wells of the conductors should extend deep into the substrate and stop at the insulator layer above the substrate layer. The bulk transistor or device may differ from the bulk process technology, including The source and drain are incorporated into the silicon substrate and dopants adjust their conductive properties. As device size decreases (e.g., As bulk transistors become increasingly complex, for example, at about 28 nm and below, SOI technology is being used. It would be advantageous to use these to construct transistors.

[0026] The SOI structure is made up of an insulating layer (e.g., a buried oxide or BOX The silicon layer comprises a silicon film (e.g., crystalline silicon) separated from a bulk substrate by a thin layer of silicon dioxide. The BOX layer reduces the drain-body capacitance, at least in part due to Improved isolation, reduced short channel effects, reduced leakage current, improved switching speed, etc. In SOI wafers, the insulator is usually thermal silicon oxide ( The substrate is a silicon wafer. Depending on the type of application, The thickness of the silicon film is variable (e.g., from less than about 50 nm to tens of micrometers) Similarly, the thickness of the BOX can be adjusted depending on the application (e.g., from tens of nanometers to several micrometers). The SOI fabrication technology is isolation by implanted oxygen (SIMOX) ), Bond-Etch-Back SOI (BESOI), Epitaxial Layer Transfer (ELTRAN (registered trademark), NANOCLEAVE (registered trademark), SMARTCUT (registered trademark), etc. Includes:

[0027] SOI technology can be implemented using complementary metal oxide semiconductor (CMOS) SOICMOS is a semiconductor that uses a metal oxide semiconductor layer on a thin layer of semiconductor (e.g., silicon or germanium). This involves building a semiconductor field effect transistor (MOSFET). A thin layer of semiconductor The device is separated from the substrate by an insulator layer (e.g., buried oxide) and The insulator layers of the SOI device electrically insulate the semiconductor substrate and each other. The thickness may be any thickness between about 5 nm and about 400 nm, and the thickness of the semiconductor film may be between about 5 nm and about It may have any thickness up to 24 nm.

[0028] MOSFETs on SOI wafers contain a channel depletion layer between the source and drain. SOI devices are classified into two types depending on the degree of channel depletion compared to the thickness of the silicon film. They can be divided into two types: partially depleted SOI (PDSOI) devices and fully depleted There are two types of devices: PDSOI devices, which are thin films of silicon, and FDSOI devices. The device includes a device where the gate depletion layer width is greater than the maximum gate depletion layer width, and such a device includes a floating body. FDSOI devices exhibit the effect of the gate dielectric constant (D) of the silicon film, which is the gate dielectric constant of the silicon film. This includes devices that are thin enough to be depleted before

[0029] FDSOI devices consist of an insulator (buried oxide) placed on top of a substrate. The ultrathin silicon film contains an ultrathin layer of silicon dioxide (or BOX) to form the transistor channel. FDSOI devices typically use undoped or lightly doped channels. The thin silicon layer is typically about 5 nm to about 50 nm thick, or about 1 / 4 of the gate length. 4 is typical. In addition, the insulating BOX layer may be thick (e.g., about 100 nm to about 40 0 nm), or may be ultra-thin (for example, about 5 nm to about 50 nm). In this case, the silicon layer underneath the gate insulator is completely depleted of mobile charge carriers. Such devices are "fully depleted" because they are thin enough to allow the depletion region The buried oxide region is responsible for the switching of the FDSOI device from the off state to the on state. Reaching things.

[0030] In FDSOI devices, the semiconductor film is made extremely thin so that the depletion region covers the entire film. In FDSOI devices, the gate oxide (GOX) supports depletion charges that Since the inversion charge is less than that of the gate drive, the switching speed is faster. The depletion charge limitation by the BOX causes the suppression of the depletion capacitance, which in turn suppresses the subthreshold This results in a substantial reduction in the swing under This allows operation at low power levels, resulting in low power operation.

[0031] PDSOI devices have a thicker silicon layer on top of the BOX layer than FDSOI devices. The top silicon layer is typically about 50 nm to about 180 nm thick. The underlying silicon is partially depleted of mobile charge carriers, so the resulting device The BOX layer is typically about 100 nm to about 400 nm thick. .

[0032] CMOS technology is the most promising technology for fully integrated FEICs due to its high integration capability and low cost. Typically, it is one of the most difficult devices to build using CMOS technology. The device is a high-power PA device, which has traditionally been used for high-power applications at low frequencies. For the purpose of LDMOS and EDMOS PAs are typically based on bulk or It is easier to build using thick SOI technology. However, the size of the device Smaller sizes (say, less than about 28 nm) present difficulties. For example, silicon films are very thin, ,Fabrication typically requires etching through the BOX layer on the wafer. As a result, the resulting PA is a thick film or bulk device rather than an FDSOI device. Existing CMOS technologies are bulk CMOS, thick SOICMO, All of them, whether S or thin-film SOICMOS, use LDMO switches and LNAs. Inconveniences in integrating with the SPA or the high cost of integrating these elements It is beneficial.

[0033] Therefore, to address these and other issues, described herein is a method for SOI-based technology platform provides a fully integrated FEIC including a switch, LNA, and PA. The PA is embedded in the thick film area of ​​the integrated circuit to form a PDS0IPA. The switches and LNAs are integrated in the thin film area of ​​the integrated circuit and are called FDSOI switches and LNAs. The resulting fully integrated FEIC consists of a PDSO with an FDSOI switch and an LNA. Passive components may be assembled in thick film regions, thin film regions, or both. In some implementations, the FEIC may incorporate one or more electrodes in the thick film region. In some implementations, the FEIC includes a power amplifier and RF circuitry in the membrane region. The thick film region contains high voltage analog circuitry, and the thin film region contains low power analog circuitry. In the example, the FEIC has an RF device mounted in the thick film area and an RF device mounted in the thin film area. and analog and / or digital circuits.

[0034] Attempts to build a fully integrated FEIC have focused on using bulk technology to integrate each device (PA, LN) A, switch) or build each device using PDSOI technology. Attempts have also been made to develop bulk LDMOS with FDSOI and switches. The attempt also included constructing the PA (e.g., by removing the BOX layer). ,PDSOILDMOSPA with LDMOSLNA in the thick film area, and the switch in the local thin film area. This included building into membrane regions.

[0035] In contrast to these attempts, what is disclosed here is the FDSO in addition to the PDS0IPA. It is a fully integrated FEIC that also includes an I-switch and an LNA. In contrast to the above attempts, there is no BOX layer removal. Instead, switches and The LNA is integrated in the thin film region and the PA is integrated in the thick film region. and constructing the switch and LNA (e.g., by selective epitaxial growth). or SEG) to build up the thick film area and This can also be achieved by incorporating PA into the thick film. and constructing PAs in thick regions and using local thinning to create thin regions. This can also be achieved by forming a thin film region on the substrate and constructing a switch and an LNA in the thin film region. This also involves preparing the BOX layer and the thin film layer, and Increasing the thickness of the part to result in a thick film region and then and switch devices in the thin film region, and PDS0IPA devices in the thick film region. This can also be achieved by constructing the BOX layer and the thick film layer. and reducing the thickness of a portion of the thick film region to provide a thin film region; Then, the PDSOIPA device was constructed in the thick film region, and the FDSOILNA device and This can also be achieved by building the switching device in a thin film region.

[0036] That is, the disclosed FEIC is a fully integrated CMOS IC with improved performance and low cost. MOS front-end integrated circuits. Some of the resulting structures of the FEICs disclosed Embodiments include a thin film region comprising one or more FDSOI switches and one or more FDSOI nanowires. and a thick film region with one or more PDS0IPAs (LDMOSPAs or EDMOSPAs). In the disclosed FEIC, the passive components include a thick film (with PA) Incorporating into the thin film region (with the switch and LNA) or both In some embodiments, the disclosed FEIC includes a high voltage power amplifier and and / or thick film regions forming high voltage analog circuitry which may include low dropout regulators In some embodiments, the disclosed FEIC includes one or more devices. The thin film region contains low voltage analog circuitry and / or Includes digital circuitry.

[0037] Advantageously, the disclosed FEIC reduces parasitics to the PA compared to bulk implementation. This results in high active device performance and other ultimate performance advantages for the FEIC. Another advantage of the disclosed FEIC is that it allows for the construction of devices (e.g., PAs) in thick film regions. There is no need to remove a portion of the buried oxide layer. The integrated circuit in the thin film region is a predetermined implementation of the integrated circuit with the FDSOIPA or PA in the thin film region. The silicon film or layer may be thicker than the conventional silicon film or layer. As a result, the thicker film area may have a robust active area. There is high performance of the device and high performance of the passive device. The overall performance of

[0038] Front-end integrated circuit structure

[0039] FIG. 1A shows a fully fabricated silicon-on-insulator (SOI) processing technology. An integrated front-end integrated circuit (FEIC) 100a is shown. 102 (e.g., a handle wafer) and an insulator layer 104 (e.g., a buried Inlaid oxide (BOX) and active device layer or silicide layer on top of insulator layer 104. and a silicon layer 106 (e.g., a silicon film such as crystalline silicon). In this embodiment, the BOX layer 104 may have a thickness of about 100 nm to about 400 nm. The silicon layer 106 forms thick regions 108a and thin regions 108b. In this case, the thick film region 108a may have a thickness of about 50 nm to about 180 nm. In this embodiment, the thin film region 108b may have a thickness of about 5 nm to about 50 nm. In certain implementations, thick region 108a is at least about twice as thick as thin region 108b. and is at least about 2.5 times thicker and / or not more than about 20 times thicker; or At least about 5 times thicker and / or no more than about 15 times thicker.

[0040] A partially depleted SOI (PDSOI) power amplifier (PA) device 110 is formed on the thick film region 10 8a. Fully depleted SOI (FDSOI) low noise amplifier (LNA) device 1 The PDS 20 and FDSOI switch device 130 are formed in the thin film region 108b. The OIPA device 110, the FDSOI device 120, and the FDSOI switch device Each of the devices 130 may include an n-MOSFET and / or a p-MOSFET.

[0041] The PDSOIPA device 110 comprises a gate conductor 112 (e.g., polysilicon) and a gate One or more MOSFETs with gate structures that are insulated by a gate insulator 119 (e.g., oxide). The PDSOIPA device 110 includes a source diffusion 114 and a In certain implementations, the source diffusion 114 and / or the drain diffusion 116 may be The rain diffusion 116 penetrates deep into the silicon layer 106 and reaches the insulator layer 104. In some embodiments, the drain diffusion 116 may reach or nearly reach the PD The SOIPA device 110 is a laterally diffused MOSFET (LDMOS) or extended drain M It can be configured to be an OSFET (EDMOS) or a PDSIOIPA device. 110 is a gate insulator 11 between a source diffusion 114 and a drain diffusion 116. The channels 118 are configured to achieve target performance characteristics. The channel 118 can be looped when the PDS0IPA device 110 is in the ON state. At some point, the depletion layer has a thickness such that it partially covers the space below the gate insulator 119. Therefore, the PDS0IPA device 110 can be configured as follows. It is partially depleted due at least in part to its incorporation into 8a.

[0042] The FDSOI LNA device 120 also includes a gate conductor 122 and a gate insulator 129. Under the gate, source diffusion 124, drain diffusion 126 and gate insulator 129 The PDS OIPA device is similar to the PDS OIPA device 110 in that it includes a layer of channel 128. In the OILNA device 120, the channel 128 is The thickness is set so that the depletion layer covers the space under the gate insulator 129 when the gate insulator 129 is in the on state. Thus, the FDSOILNA device 120 can be configured to have a thin film It is fully depleted due at least in part to being incorporated into region 108b. In some embodiments, the channel 128 is undoped or lightly doped.

[0043] The FDSOI switch device 130 also includes a gate conductor 132 and a gate insulator 139. The gate, source diffusion 134, drain diffusion 136, and gate insulator 139 are It is similar to the FDSOLNA device 120 in that it includes an underlying channel 138. The gate insulator 138 is electrically connected to the gate insulator 136 when the FDSOI switch device 130 is in the on state. The thickness of the depletion layer can be configured to cover the space below 139. Thus, the FDSOI switch device 130 is preferably incorporated into the thin film region 108b. In some embodiments, the channel 1 38 is undoped or lightly doped.

[0044] The FEIC 100a includes a substrate 102, an insulator layer 104 on top of the substrate, and and a semiconductor layer 106 on top of the insulator layer 104. The semiconductor layer 106 is a thin film region. The thin film region 108b is formed by one or more FDSOI The thick film region includes an LNA device 120 and one or more FDSOI switch devices 130. Region 108a includes one or more PDS0IPA devices 110. That is, semiconductor layer 106 is higher in the LNA device 120 and the switch device 1 than in the PA device 110. At 30 it is thinner.

[0045] FIG. 1B shows another fully integrated FEIC 100b fabricated using SOI processing technology. The FEIC 100b includes a substrate 102 and an insulator layer 104 on top of the substrate. FEIC 100a and FEIC 100b in that they include a semiconductor layer 106 on top of an insulator layer 104. The semiconductor layer 106 includes a thin film region 108b and a thick film region 108a. The thick film region 108a includes various thick film devices 140. In some embodiments, The thick film device 140 is used in analog circuits (e.g., high voltage PA, LDO, high voltage breakdown, ES protection, charge pump, high power switch, power control unit, etc.) Area 108b includes various thin film devices 150. In some embodiments, the thin film devices The device 150 may include analog circuits (e.g., low-power analog circuits, level shifters, summing devices, etc.). , current mirrors, etc.) and / or digital circuits (e.g., logic gates). The semiconductor layer 106 is also thicker in the thin film device 15 than in the thick film device 140 region. In some embodiments, the thick film region of the FEIC 100b is Area 108a is used for high voltage analog circuitry. Region 108b may be used for RF circuitry. In certain embodiments, the FEIC The thick film region 108a of 100b is used for RF circuitry (e.g., PA), and the thin film region 10 8b is analog circuitry (e.g., low-power analog circuitry) and / or digital circuitry (e.g., logic gate).

[0046] 2A, 2B, 2C, and 2D show an example of a semiconductor device at different stages in the manufacturing process. The FEIC 200 includes a substrate 102 and an interface circuit on the substrate 102. The FEIC 100a and 100b are similar to the FEICs 100a and 100b in that they include a substrate 10 and a silicide layer 104. 2 may be a silicon support wafer or handle wafer. The insulator layer 104 is It may be a buried oxide such as silicon dioxide. The insulator layer 104 may have a thickness of about 100 nm to about 400 nm.

[0047] In FIG. 2A, the FEIC 200 includes an active layer or silicon layer 20 of substantially uniform thickness. 6. The silicon layer 206 may be a silicon film. The thickness of the silicon layer 206 is FD For example, the thickness of the silicon layer 206 may be about 5 nm. FDSOI devices may be ∼50 nm thick or may be embedded in silicon layer 206 It may be about 1 / 4 of the gate length.

[0048] In FIG. 2B, the FEIC 200 includes an FDSOI LNA device 220 and an FDSOI LNA device 230. The FDSOI device 220 includes a gate insulator 22. 9, a gate structure with a gate conductor 222 on top of the source diffusion 224, and a drain diffusion 226. 1A in that it includes a portion 226 and a channel 228. Similarly, the FDSOI switch device 230 has a gate conductor on top of a gate insulator 239. A gate structure with a body 232, a source diffusion 234, a drain diffusion 236, and a channel 1A in that it includes a gate electrode 238. Although several FDSOILNA devices 220 are shown, multiple FDSOILNA devices It should be understood that the A device may be incorporated into the silicon layer 206. Although one FDSOI switch device 230 is shown, multiple FDSOI switches may be used. It should also be understood that the switch device may be integrated into the silicon layer 206.

[0049] In FIG. 2C, the FEIC 200 increases the thickness of the silicon film 206 in the target area. The build-up portion 207 may be formed by any suitable process. The silicon film 206 can be built up using a process. An example of a process that uses selective epitaxial growth (SEG) is FDSOI device 206. You can play it.

[0050] The build-up portion 207 provides a region larger than the thin film region 208b of the silicon layer 206. A thick region 208a of the silicon layer 206 having a thickness is obtained. The thickness of a may be suitable for the construction of a PDSOI device. For example, the thickness of thick film region 208a may be The thickness of the silicon layer 206 in this build-up may be about 50 nm to about 180 nm. The top portion 207 is shown as a shaded area on top of the silicon layer 206, but is not part of the silicon film. The resulting increase in thickness of 206 does not necessarily result in an additional layer on top of silicon layer 206. It should be understood that the additional thickness of the build-up portion 207 is not limited to: This represents an increase in the thickness of the silicon layer 206 itself.

[0051] In FIG. 2D, the FEIC 200 is embedded in a thick region 208a of the silicon layer 206. The PDS0IPA device 210 includes a gate insulator. A gate structure comprising a gate conductor 212 on an insulating layer 219, a source diffusion 214, and a drain 1A in that it includes an in-diffusion 216 and a well 218. The PDSOIPA device 210 is similar to an LDMOSPA device or an EDMO Although a singular PDS0IPA device 210 is shown, It is understood that multiple PDS0IPA devices may be incorporated into silicon layer 206 without the need for a single PDS0IPA device. The FEIC 200 has either a thick film region 208a or a thin film region 208b. may both include passive devices.

[0052] For example, a suitable method for fabricating the FEIC 200 is to deposit an insulating film on top of the substrate 102. The method includes forming a semiconductor insulator layer 104 on top of the insulator layer 104. The method includes forming a semiconductor layer 206. The method includes forming a FDSOI LNA device in the semiconductor layer 206. The method includes constructing a FDSOI switch device 220 in the semiconductor layer 206. 30. The thickness of a portion of the semiconductor layer 206 is increased to form the semiconductor layer 206. The method includes forming a thick film region 208b of the FDSOI LNA device 220 and and FDSOI switch device 230 resides in thin film region 208b of semiconductor layer 206, The PDS0IPA device 210 is located in the thick region 208a of the semiconductor layer 206. In addition, the PDSOIPA device 210 is incorporated into the thick region 208a of the semiconductor layer 206. Includes:

[0053] 3A, 3B, 3C, and 3D are the same as those in the FEIC described in relation to FIGS. 2A to 2D. 200. In this variation, the FEIC 200 is As shown in Figure 3A, we start with a thin silicon layer 206. In Figure 3B, the FEIC The build-up region 207 is formed before forming devices in the thin film region 208b. The build-up portion 207 can be formed by depositing a silicon film using any suitable process, such as SEG. The build-up portion 207 allows the silicon layer 206 to be built up. The thick region 208a of the silicon layer 206 has a thickness greater than that of the thin region 208b. The thickness of the resulting thick film region 208a is, for example, about 50 nm to about 180 nm. This build-up portion 207 may be suitable for constructing an OI device. The resulting increase in thickness of silicon film 206 is shown as the shaded area on top of layer 206. It should be understood that this does not necessarily result in an additional layer on top of silicon layer 206. Rather, the additional thickness of the build-up portion 207 is less than the thickness of the silicon layer 206 itself. Once the thick region 208a is formed, the devices 210, 22 2B and 2D, thick film region 208a and thin film region 208b. 4, and drain diffusions 216, 226, 236 are connected to channels 218, 228, 238. FIG. 3D shows that in some embodiments, these can be formed. After the gate insulators 219, 229, 239 are formed on the corresponding source and drain diffusions. Above these corresponding gate insulators, a gate conductor can be formed between the gate insulator and the gate electrode. In certain implementations, the gate insulator 219 is formed. The mask used to build the gate insulators 229, 239 is the same as the mask used for the gate insulators 229, 239. Similarly, the mask used to form the gate conductor 212 may be shared. The mask may be the same as that used for the bodies 222, 232.

[0054] 4A, 4B, 4C, and 4D show other examples of the semiconductor device at different stages in the manufacturing process. An exemplary FEIC 300 is shown. The FEIC 300 includes a substrate 102 and a The FEIC 100a is similar to the FEIC 100a in that it includes an insulator layer 104. The substrate 102 is The insulator layer 104 may be a silicon support wafer or handle wafer. It may be a buried oxide such as silicon. The data layer 104 may have a thickness of about 100 nm to about 400 nm.

[0055] In FIG. 4A, the FEIC 300 includes an active layer or silicon layer 30 of substantially uniform thickness. 6. The silicon layer 306 may be a silicon film. The thickness of the silicon layer 306 is PD For example, the thickness of silicon layer 306 may be about 50 nm. The thickness may be about 100 nm to about 180 nm.

[0056] In FIG. 4B, the FEIC 300 includes a PDS0IPA embedded in a silicon layer 306. The PDS0IPA device 310 includes a gate insulator 319 on top of which is a gate insulating layer 319. a gate structure with a gate conductor 312, a source diffusion 314, and a drain diffusion 316; 1A in that it includes a well 318. The SOIPA device 310 may be an LDMOSPA device or an EDMOSPA device. Although a single PDS OIPA device 310 is shown, multiple PDS OIPA devices may be used. It should be understood that the OIPA device may be integrated into the silicon layer 306 .

[0057] In FIG. 4C, the FEIC 300 reduces the thickness of the silicon layer 306 in the target area. The silicon layer 306 includes an area 307 that represents a portion of the silicon layer 306 that has been removed to reduce the thickness. The moiety 307 can be removed from the silicon film 306 using any suitable process. An example of a process for removing a portion of a silicon film is local thinning. 3. Using selective thinning, remove the portion of silicon layer 306 that does not contain any PDSOI devices. can be removed.

[0058] The removed portion 307 provides a thickness greater than that of the thin film region 308b of the silicon layer 306. The resulting thick region 308a of the silicon layer 306 is the thickness of the resulting thin region 308b. This may be suitable for the construction of FDSOI devices. The silicon layer 306 may have a thickness of about 5 nm to about 50 nm, and is incorporated into the thin film region 308b. The gate length may be approximately 1 / 4 of the gate length of the FDSOI device to be used.

[0059] In FIG. 4B, the FEIC 300 includes an FDSOI LNA device 320 and an FDSOI LNA device 320. The FDSOI device 320 includes a gate insulator 32. 9, a gate structure with a gate conductor 322 on top of the source diffusion 324, and a drain diffusion 326. 1A in that it includes a portion 326 and a channel 328. Similarly, the FDSOI switch device 330 has a gate conductor on top of a gate insulator 339. A gate structure with a body 332, a source diffusion 334, a drain diffusion 336, and a channel 1A in that it includes a gate electrode 338. Although several FDSOILNA devices 320 are shown, multiple FDSOILNA devices It should be understood that the A device may be incorporated into the silicon layer 306. Although one FDSOI switch device 330 is shown, multiple FDSOI switches may be used. It should also be understood that the FET device may be integrated into the silicon layer 306. 300 includes passive devices in either or both of the thick film region 308a and the thin film region 308b. It may include.

[0060] For example, a suitable method for fabricating the FEIC 300 is to deposit an insulating film on top of the substrate 102. The method includes forming a semiconductor insulator layer 104 on top of the insulator layer 104. forming a semiconductor layer 306. The method also includes forming a PDS0IPA device on the semiconductor layer 306. The method also includes reducing the thickness of a portion of the semiconductor layer 306. forming a thin film region 308b of the semiconductor layer 306. The method also includes: The method also includes constructing a FDSOI LNA device 320 in the thin film region 308b of the sixth embodiment. Also, an FDSOI switch device 330 is constructed in the thin film region 308b of the semiconductor layer 306. The PDSOIPA device 310 is located in the thick region 308a of the semiconductor layer 306. The FDSOI NAND device 320 and the FDSOI switch device 330 are semiconductors. It is present in thin film region 308 b of layer 306 .

[0061] 5A, 5B, 5C, and 5D are the same as those in the FEIC described in relation to FIGS. 4A to 4D. 300. In this variation, the FEIC 300 is As shown in Figure 5A, we start with a thin silicon layer 306. In Figure 5B, the FEIC 300 is removed to reduce the thickness of the silicon layer 306 in the target area. The silicon layer 306 includes a region 307 that represents a portion of the silicon layer 306. The removed region 307 is a thinned region, such as a localized thinning. Any suitable process can be used to remove the silicon film 306. The removed portion 307 has a thickness greater than that of the thin film region 308b of the silicon layer 306. A thick region 308a of the silicon layer 306 is obtained. The resulting thin region 308b has a thickness of This may be suitable for the construction of FDSOI devices. For example, it may be about 5 nm to about 50 nm. or about 1 / 4 of the gate length of the FDSOI device incorporated in thin film region 308b. Once thin film region 308b is formed, devices 310, 320, 330 may , thick film region 308a and thin film region 308b, as described herein with reference to FIGS. 4B and 4D. 5C shows the source diffusions 314, 324, 334 and the drain diffusions 308b. In-diffusions 316, 326, 336 are formed along with channels 318, 328, 338. FIG. 5D shows that in some embodiments, after these are formed, the gate Insulators 319, 329, 339 are formed between corresponding source and drain diffusions. Above these corresponding gate insulators, gate conductors 312, 32 2, 332 are formed. In certain implementations, the gate insulator 319 is formed using The mask used may be the same as the mask used for the gate insulators 329, 339. Similarly, the mask used to form gate conductor 312 also forms gate conductors 322, 3 May be used in conjunction with the mask used for 32.

[0062] Front-end integrated circuit manufacturing

[0063] FIG. 6A shows a partially depleted silicon-on-insulator (PDSOI) power amplifier (PA). Device, Fully Depleted Silicon-on-Insulator (FDSOI) Low Noise Amplifier (LNA) ) device, and an integrated front-end integrated circuit ( 2A-2D show a method 600 for constructing a FEIC. 1 shows an example of a FEIC manufactured in response to the

[0064] In block 605, a substrate having a buried oxide (BOX) layer and a thin silicon layer is The substrate with the BOX layer and thin film silicon is prepared, e.g., silicon-on-insulator. The SOI wafer may be prepared in block 6. Rather than requiring the fabrication of an SOI wafer, step 05 It may be done in separate processes, such as receiving or giving. The structure has also been refined to allow active devices to be built in the thin silicon layer. 2A includes any steps performed to produce the An example of FEIC is shown below.

[0065] The substrate may be a handle wafer. The BOX layer may be a silicon dioxide (SiO2) layer. It may be any suitable insulator. The thin silicon layer is made of crystalline silicon. The thickness of the BOX layer may be about 5 nm to about 40 nm. The thickness may be any thickness up to about 100 nm, and may be at least about 100 nm and / or up to about 200 nm. This is in comparison to thin or ultra-thin BOX layers, which are typically about 5 nm to about 50 nm. The thickness of the thin silicon layer is about 5 nm to about 5 0 nm, or about 1 / 2 of the gate length of the active device incorporated in the thin silicon layer. / 4. Separation by implanted oxygen (SIMOX), bond and etch back SOI (B ESOI), Epitaxial Layer Transfer (ELTRAN®), NANOCLEAV Using any suitable process, including E®, SMARTCUT®, etc. SOI wafers can be prepared by the following steps.

[0066] At block 610, one or more FDSOI LNA devices and one or more FDSOI Switching devices are integrated into the thin silicon layer. These active devices are The channel between the source and drain diffusions may be constructed without doping, and The thickness of the thin silicon may be such that the active device is in the on state. At some point, the channel may be fully depleted. An example of FEIC is shown below.

[0067] In block 615, the thickness of the thin silicon region is increased to remove any FDSOI This results in thick regions that do not contain any active devices. The area of ​​thin silicon that has not undergone processing may be referred to as the thin region of the silicon layer. The thin film region of the FDSOI layer may include one or more FDSOI nanodevices and one or more FDSOI switch devices. The thickness of the resulting thick film region may be about 50 nm to about 180 nm. C shows an example of the FEIC in block 615.

[0068] To increase the thickness of the silicon layer, an epitaxial deposition process or epitaxy is performed. These processes can be used to form silicon films (e.g., crystalline silicon) or substrates. It can be used to grow a layer of silicon (eg, crystalline silicon) on the plate. Selective epitaxial growth (SEG) is the process of growing silicon on exposed silicon areas of a silicon film. This is an example process that can be used to extend the area where silicon growth is not desired. The area is masked with a dielectric film, typically silicon dioxide or silicon nitride. Epitaxial growth is the condensation of liquid or gaseous precursors to form a film on a substrate. The gas precursors may be deposited, for example, by chemical vapor deposition and / or laser ablation. You can get this.

[0069] At block 620, one or more PDS0IPA devices are incorporated into the thick film region. One or more PDS0IPA devices may be LDMOS and / or EDMOS PA devices. The thickness of the thick silicon is determined so that the channel is partially 2D shows an example of the FEIC in block 620. Optionally, in block 625, thin film regions, thick film regions, or both thin film regions and thick film regions are selected. A passive device may be constructed for this purpose.

[0070] The method 600 offers several advantages. For example, the associated parasitics are significantly less than those achieved using bulk technology. Compared to the implementation example, the LDMOSPA and EDMOSPA devices on SOI have fewer This improves the performance of the active devices. A thicker BOX layer (rather than an ultra-thin layer) may be used to achieve desired performance characteristics. This results in robust active device performance, high power capability, and improved passive device performance. As another example, the resulting FEIC may be used to fabricate FDSOI active devices (e.g., switch devices). Both PDSOI active devices (e.g., PA devices) and PDSOI active devices (e.g., LNA devices) It has advantages.

[0071] FIG. 6B shows the PDS0IPA device, the FDSOINA device, and the FDSOI switch. 3A-3D show a method 650 for constructing an integrated FEIC with a switch device. 6 illustrates an example of a FEIC manufactured in accordance with the steps of method 650. Note that Method 650 is substantially similar to method 600 described with reference to FIG. 6A. 00. The difference between method 600 and method 650 is the order of the steps of the method. The method 650 prepares a substrate prior to building a device. In particular, the method 650 includes: The sequence of constructing a device in the thin film region and increasing the thickness of a portion of the thin film region. The order is reversed to result in a thick film region. Therefore, the description of method 650 is the same as the description of method 600. For clarity, the details of the method 650 are simplified.

[0072] In block 655, a substrate is prepared with a BOX layer and a thin silicon layer, e.g., For example, the FEIC may be in the form of an SOI wafer. FIG. 3A shows an example of the FEIC in block 655. represent.

[0073] At block 660, the thickness of the thin silicon region is increased to result in a thick silicon region. Therefore, the area of ​​thin silicon that has not been subjected to the process of thickening the silicon film layer This may be referred to as the thin film region of the silicon layer. The thickness of the resulting thick film region is about 50 nm to about 1 3B shows an example of the FEIC in block 660.

[0074] At block 665, one or more FDSOI devices and one or more FDSOI Switch devices are integrated into the thin film region of the silicon layer. These active devices: A channel between the source and drain diffusions may be constructed without doping. The thickness of the thin silicon may be such that the active device is turned on. In block 670, the channel may be fully depleted when the , one or more PDS0IPA devices are incorporated into the thick film region. The devices may be LDMOS and / or EDMOS PA devices. The thickness should be such that the channel is partially depleted when the active device is in the on state. Optionally, in block 675, the thin film regions, the thick film regions, or the thin film regions and the thick film regions are Both may incorporate passive devices.

[0075] 3C and 3D show an example of the FEIC in blocks 665 and 670. Blocks 665 and 670 are used to fabricate the thick film after the device is built into the thin film region. Although shown to be embedded in a region, other implementations of method 650 may be implemented (e.g., 3C) after partially incorporating the device into the thin and thick film regions (e.g. This involves completing the device in both areas (e.g., as shown in Figure 3D). It should be understood that in some implementations, devices may be A shared mask may be used to complete this. This also allows the device to be divided into thin and thick regions. In some cases, a shared mask may be used after partial incorporation into the domain. It is also possible to apply the method 600 to be completed in a separate step.

[0076] FIG. 7A shows the PDS0IPA device, the FDSOINA device, and the FDSOI switch. 4A-4D show a method 700 for constructing an integrated FEIC with a switch device. 5 illustrates an example of a FEIC manufactured in accordance with the steps of method 500.

[0077] In block 505, a substrate having a buried oxide (BOX) layer and a thick silicon layer is The substrate with the BOX layer and thick silicon is prepared, e.g., silicon-on-insulator. The SOI wafer may be prepared in block 5. Rather than requiring the fabrication of an SOI wafer, step 05 It may be done in separate processes, such as receiving or giving. We also engineered the structure to allow for building active devices in thick silicon layers. 4A includes any steps performed to produce the This shows an example of a FEIC.

[0078] The substrate may be a handle wafer. The BOX layer may be a silicon dioxide (SiO2) layer. It may be any suitable insulator. The thin silicon layer is made of crystalline silicon. The thickness of the BOX layer may be about 5 nm to about 40 nm. The thickness may be any thickness up to about 100 nm, and may be at least about 100 nm and / or up to about 200 nm. This is in comparison to thin or ultra-thin BOX layers, which are typically about 5 nm to about 50 nm. The thickness of the thick silicon layer is about 50 nm to about 100 nm. 180nm is acceptable. Separation by implanted oxygen (SIMOX), bond and etch back SO I (BESOI), Epitaxial Layer Transfer (ELTRAN®), NANOCL Any suitable process, including EAVE®, SMARTCUT®, etc. can be used to prepare SOI wafers.

[0079] At block 510, one or more PDS0IPA devices are incorporated into the thick silicon layer. One or more PDS0IPA devices may be LDMOS and / or EDMOS PA devices. The thickness of the thick silicon may be determined by the channel thickness when the active device is in the on-state. 4B shows an example of the FEIC in block 510. Shows.

[0080] At block 515, the thickness of the thin silicon region is reduced to remove any PDSOI. This results in a thin film region that does not contain any active devices. The areas of thick silicon that have not undergone processing may be referred to as thick regions of the silicon layer. The thick film region contains one or more PDS0IPA devices. The resulting thin film region has a thickness of about Active devices typically incorporated into the thin film region may be 5 nm to about 50 nm thick. 4C shows an example of the FEIC in block 515. Shows.

[0081] Thinning the thick silicon layer may include any suitable process for localized thinning. For example, thinning can be achieved by mechanical grinding, chemical mechanical planarization, wet etching, atmospheric downstream etching, etc. These may include room plasma dry chemical etching (ADPDCE), etc.

[0082] At block 510, one or more FDSOI LNA devices and one or more FDSOI Switching devices are incorporated into the thin film region. These active devices are connected to their source diffusion The channel between the doped portion and the drain diffusion may be constructed without doping, or the channel may be formed by doping the doped portion. The thickness of the thin film region is determined by the thickness of the active device when it is in the on state. 4D shows the FEIC in block 520. Optionally, in block 525, thin film regions, thick film regions, or thin film regions and Both thick film regions may incorporate passive devices.

[0083] The method 500 offers several advantages. For example, the associated parasitics are significantly less than those achieved using bulk technology. Compared to the implementation example, the LDMOSPA and EDMOSPA devices on SOI have fewer This improves the performance of the active devices. A thicker BOX layer (rather than an ultra-thin layer) may be used to achieve desired performance characteristics. This results in robust active device performance, high power capability, and improved passive device performance. As another example, the resulting FEIC may be used to fabricate FDSOI active devices (e.g., switch devices). Both PDSOI active devices (e.g., PA devices) and PDSOI active devices (e.g., LNA devices) Additionally, method 500 may be less expensive than method 400. Thinning is typically Generally, it is a cheaper process than epitaxial growth or deposition.

[0084] FIG. 7B shows the PDS0IPA device, the FDSOINA device, and the FDSOI switch. 5A-5D show a method 750 for constructing an integrated FEIC with a switch device. 7 shows an example of a FEIC manufactured in accordance with the steps of method 750. Note that Method 750 is substantially similar to method 700 described with reference to FIG. 7A. 00. The difference between method 700 and method 750 is the order of the steps of the method. The method 750 prepares a substrate prior to building a device. In particular, the method 750 includes: The sequence of building a device in a thick film region and then reducing the thickness of a portion of the thick film region. The order is reversed to result in a thin film region. Therefore, the description of method 750 is equivalent to the description of method 700. For clarity, the details of method 750 are simplified.

[0085] In block 755, a substrate is prepared with a BOX layer and a thick silicon layer, e.g., For example, the FEIC may be in the form of an SOI wafer. FIG. 5A shows an example of the FEIC in block 755. show.

[0086] At block 760, the thickness of the thick silicon region is reduced to result in a thin silicon region. Therefore, the area of ​​thick silicon that has not been subjected to the process of thinning the silicon film layer This can be referred to as the thick film region of the silicon layer. The thickness of the resulting thin film region is about 5 nm to about 50 nm. nm. FIG. 5B shows an example of the FEIC in block 760.

[0087] At block 765, one or more PDS0IPA devices are incorporated into the thick film region. One or more PDS0IPA devices may be LDMOS and / or EDMOS PA devices. The thickness of the thick silicon is determined so that the channel is partially At block 770, one or more FDSOILNA devices may be and one or more FDSOI switch devices are embedded in the thin film region of the silicon layer. These active devices may be constructed without doping the channel between the source diffusion and the drain diffusion, or may be lightly doped. The thickness of the thin film silicon may be such that the channel is fully depleted when the active device is in the on state. Optionally, in block 775, passive devices may be incorporated in either the thin film region, the thick film region, or both the thin film region and the thick film region.

[0088] Figures 5C and 5D illustrate examples of FEICs in blocks 765 and 770. Although blocks 765 and 770 show that the device is incorporated into the thick film region after being incorporated into the thin film region, other implementations of method 750 may include (as shown in, for example, Figure 5C) partially incorporating the device into both the thin film region and the thick film region and then (as shown in, for example, Figure 5D) completing the device in both regions. It should be understood that in some implementations, a shared mask may be used to complete the device as described herein. This can also be applied to method 600, which may be completed in a separate step where in some examples a shared mask may be used after the device is partially incorporated into the thin film region and the thick film region.

[0089] In addition, it should be understood that FEIC 100b shown in Figure 1B can be prepared using methods 600, 650, 700, 750. Modified examples of methods 600, 650, 700, 750 would involve replacing the steps of preparing a specific PDSOIPA device, FDSOILNA device, and / or FDSOI switch with other circuits described in relation to Figure 1B.

[0090] Additional Embodiments and Terminology

[0091] This disclosure describes various features, only one of which may be advantageously described herein. It is understood that the various features described herein may be It may be combined, modified or omitted as would be apparent to one skilled in the art. Other combinations and subcombinations will be apparent to those skilled in the art. It is intended to form part of this disclosure. Various methods are described herein in relation to the phases. It will be understood that in many cases Certain steps and / or phases may be combined together, resulting in a flow chart. The multiple steps and / or phases shown in the chart may be replaced with a single step and / or phase. Certain steps and / or phases may also be performed as separate steps and / or phases. In some examples, the steps and and / or the order of the phases may be rearranged, and certain steps and / or phases may be omitted entirely. Also, the methods described herein may be omitted in addition to those shown and described herein. It is understood to be open-ended, so that other steps and / or phases may also be performed. It should be.

[0092] Unless the context clearly requires otherwise, throughout the specification and claims In this regard, the words "including," "comprises," and the like are used in an inclusive sense as opposed to an exclusive or exhaustive sense. In general, the term "including but not limited to" should be interpreted as meaning "including but not limited to" The term "coupled" as used herein means that two or more elements are directly connected or joined together through one or more interconnections. It is noted that the present application may be either connected via an inter-connection element. When used herein, the terms "herein," "above," "below," and words of similar import shall mean the Reference is made to the application as a whole and not to any particular portion of this application. Where permitted, terms in the above detailed description using singular or plural number refer to the respective "Or" and "if" refer to a list of two or more items. The term "or" means any of the items in a list, Covers all of the items in the list, and any combination of the items in the list. The word "exemplary" is used herein solely to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is intended to be illustrative and not restrictive. The examples should not necessarily be construed as preferred or advantageous.

[0093] The present disclosure is not intended to be limited to the implementation examples shown herein. Various modifications to the implementation may be readily apparent to those skilled in the art and may be incorporated into the methods defined herein. The general principles may be applied to other implementations without departing from the spirit or scope of the disclosure. The teachings of the present invention provided herein may be applied to other methods and systems, and may be incorporated into the methods described above. The present invention is not limited to the methods and systems described above. Further embodiments may be provided. Thus, the novel methods and systems described herein The system may be embodied in various other forms. Various omissions, substitutions and changes in aspects may be made without departing from the spirit of the present disclosure. The accompanying claims and their equivalents are intended to cover any form or It is intended to cover modifications.

Claims

1. 1. A front-end integrated circuit comprising: A substrate; an insulator layer on top of the substrate; a semiconductor layer on top of the insulator layer; Including, the semiconductor layer forms a thin film region and a thick film region; The thin film region may comprise one or more fully depleted silicon-on-insulator (FDSOI) low noise a low noise amplifier (LNA) device and one or more FDSOI switch devices; The thickened region may include one or more partially depleted silicon-on-insulator (PDSOI) power boosters. A front-end integrated circuit including a power amplifier (PA) device.

2. 10. The front-end integration of claim 1, wherein the insulator layer is at least 100 nm thick. circuit.

3. The semiconductor layer in the thin film region is at least 5 nm thick and not more than 50 nm thick.

2. The front-end integrated circuit of claim 1, wherein:

4. The semiconductor layer in the thick film region is at least about 50 nm thick and 4. The front-end integrated circuit of claim 3, wherein the front-end integrated circuit is no more than 1 m thick.

5. 2. The front-end integrated circuit of claim 1, wherein the insulator layer is a buried oxide layer.

6. The semiconductor layer in the thin film region may form a gate for the one or more FDSOILNA devices.

2. The front-end integrated circuit of claim 1, wherein the length is one-quarter of the length of the front-end integrated circuit.

7. 10. The method of claim 9, further comprising: 1 front-end integrated circuit.

8. 10. The method of claim 9, further comprising: 1 front-end integrated circuit.

9. The front of claim 1 , wherein the thin film region of the semiconductor layer is formed using local thinning. End integrated circuit.

10. 10. The method of claim 9, wherein the thick region of the semiconductor layer is formed using selective epitaxial growth. 1 front-end integrated circuit.

11. 1. A method for manufacturing a front-end integrated circuit, comprising: forming an insulator layer on top of the substrate; forming a semiconductor layer on top of the insulator layer; Fully depleted silicon-on-insulator (FDSOI) low noise amplifier (LNA) device into the semiconductor layer; Incorporating a FDSOI switch device into said semiconductor layer; increasing the thickness of a portion of the semiconductor layer to form a thickened region of the semiconductor layer; 、 FDSOI NA devices and FDSOI switch devices are formed in the thin film region of the semiconductor layer. Partially depleted silicon-on-insulator (PDSOI) power amplifiers (PA ) placing the PDS-IOPA device in the semiconductor layer so that the device is in the thick film region; Incorporating into said thick film region; A method comprising:

12. The method of claim 11 , wherein the insulator layer is at least about 100 nm thick.

13. The thin film region of the semiconductor layer is at least about 5 nm thick and not more than about 50 nm thick. The method of claim 11 .

14. The thick region of the semiconductor layer is at least about 50 nm thick and not more than 180 nm thick.

14. The method of claim 13, wherein:

15. The thin film region of the semiconductor layer is 1 / 4 of the gate length of the FDSOILNA device. The method of claim 11 .

16. further comprising incorporating one or more passive devices into the thin film region of the semiconductor layer. Item 12. The method of item 11.

17. further comprising incorporating one or more passive devices into the thick film region of the semiconductor layer. Item 12. The method of item 11.

18. 10. The method of claim 1, wherein the step of increasing the thickness comprises using selective epitaxial growth. Method 1.

19. 1. A method for manufacturing a front-end integrated circuit, comprising: forming an insulator layer on top of the substrate; forming a semiconductor layer on top of the insulator layer; Partially depleted silicon-on-insulator (PDSOI) power amplifier (PA) devices Incorporating the semiconductor layer; reducing a thickness of a portion of the semiconductor layer to form a thinned region of the semiconductor layer; 、 Fully depleted silicon-on-insulator (FDSOI) low noise amplifier (LNA) device into the thin film region of the semiconductor layer; The PDSOIPA device is present in the thick film region of the semiconductor layer, and the FDSOI An LNA device and an FDSOI switch device reside in the thin film region of the semiconductor layer. Incorporating the FDSOI switch device into the thin film region of the semiconductor layer so as to Toto A method comprising:

20. 20. The method of claim 19, wherein the insulator layer is at least about 100 nm thick.

21. The thin film region of the semiconductor layer is at least about 5 nm thick and not more than about 50 nm thick.

20. The method of claim 19.

22. The thick region of the semiconductor layer is at least about 50 nm thick and not more than 180 nm thick.

22. The method of claim 21, wherein:

23. The thin film region of the semiconductor layer is 1 / 4 of the gate length of the FDSOILNA device.

20. The method of claim 19.

24. further comprising incorporating one or more passive devices into the thin film region of the semiconductor layer. Item 19. The method of item 19.

25. further comprising incorporating one or more passive devices into the thick film region of the semiconductor layer. Item 19. The method of item 19.

26. 20. The method of claim 19, wherein reducing the thickness comprises using localized thinning.

27. 1. A method for manufacturing a front-end integrated circuit, comprising: forming an insulator layer on top of the substrate; forming a semiconductor layer of a first thickness on top of the insulator layer; The thickness of a portion of the semiconductor layer is reduced to form the semiconductor layer having the first thickness. forming a thick region of the semiconductor layer such that other portions of the semiconductor layer are thin region; Incorporating high voltage analog circuitry into said thick film region; Incorporating low voltage analog circuitry into the thin film region; A method comprising:

28. 28. The method of claim 27, wherein the insulator layer is at least about 100 nm thick.

29. The thin film region of the semiconductor layer is at least about 5 nm thick and not more than about 50 nm thick.

28. The method of claim 27.

30. The thick region of the semiconductor layer is at least about 50 nm thick and not more than 180 nm thick.

30. The method of claim 29, wherein:

31. 28. The method of claim 27, wherein the high voltage analog circuitry includes a low dropout regulator.

32. 28. The method of claim 27, wherein the high voltage analog circuitry comprises a high voltage power amplifier.

33. 28. The method of claim 27, further comprising incorporating digital circuitry into the thin film region.

34. 1. A method for manufacturing a front-end integrated circuit, comprising: forming an insulator layer on top of the substrate; forming a semiconductor layer of a first thickness on top of the insulator layer; The thickness of a portion of the semiconductor layer is reduced to form the semiconductor layer having the first thickness. forming a thin film region of the semiconductor layer such that other portions of the semiconductor layer are thick film regions; incorporating a radio frequency (RF) device into said thick film region; Incorporating analog or digital circuitry into said thin film region; A method comprising:

35. 35. The method of claim 34, wherein the insulator layer is at least about 100 nm thick.

36. The thin film region of the semiconductor layer is at least about 5 nm thick and not more than about 50 nm thick. The method of claim 34.

37. The thick region of the semiconductor layer is at least about 50 nm thick and not more than 180 nm thick.

35. The method of claim 34, wherein:

38. 4. The RF device in the thick film region includes a power amplifier (PA) device. Method 4.

39. The PA device is a partially depleted silicon-on-insulator (PDSOI) PA device.

39. The method of claim 38, comprising:

40. 35. The method of claim 34, wherein the digital circuitry comprises logic gates.

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