Semiconductor device

Abstract

To provide a semiconductor device capable of achieving both high insulation and miniaturization of the device.SOLUTION: The semiconductor device 1 includes a semiconductor device 2 having a main surface 2A and a back surface 2B facing opposite sides in a plate thickness direction X, an insulating heat dissipation substrate 3 bonded to the back surface 2B side, and a sealing insulating layer 4 provided on the main surface 2A side. The insulating heat dissipation substrate 3 includes an electrically insulating ceramic substrate 31 and a conductive layer 32 bonded to one side of the ceramic substrate 31, and the semiconductor device 2 includes a main surface-side electrode layer 21 on a main surface 2A and a back surface-side electrode layer 22 on a back surface 2B. The backside electrode layer 22 is thermally and electrically directly joined to the conductive layer 32, and an element embedding layer 5 for insulating and protecting the semiconductor element 2 is arranged between the insulating heat dissipation substrate 3 and the sealing insulating layer 4 in the plate surface direction Y.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Patent document 1 discloses a semiconductor device including a semiconductor substrate having a first main surface and a second main surface, a semiconductor chip arranged on the first main surface, a sealing insulating layer that seals the semiconductor chip on the first main surface so as to expose the second main surface of the semiconductor substrate, and an external terminal formed by penetrating the sealing insulating layer so as to be exposed from the sealing main surface of the sealing insulating layer facing the first main surface of the semiconductor substrate.

[0003] In order to improve heat dissipation, this semiconductor device has a sealing insulating layer disposed only on the first main surface side of a semiconductor substrate made of Si or the like, and heat generated in the semiconductor chip can be dissipated to the outside from the exposed second main surface and the side surfaces of the substrate. Specifically, a wiring layer made of a copper plating layer or the like is formed on the first main surface via a main surface insulating layer made of an inorganic insulating material such as SiN or SiO2, and the second main surface of the semiconductor chip is bonded onto the wiring layer via a conductive bonding material such as solder.

[0004] In the semiconductor device of Patent Document 1, a semiconductor chip is embedded in a sealing insulating layer on a first main surface of a semiconductor substrate. In this case, columnar electrode layers connecting each electrode layer to an external terminal are formed in advance by electrolytic copper plating using a resist mask or the like, and a sealing insulating layer made of an organic insulating material or an inorganic insulating material is formed to cover the entire electrode layers, and then the sealing insulating layer is partially removed to the position where the columnar electrode layers are exposed. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2022-179747 Summary of the Invention [Problem to be solved by the invention]

[0006] In the semiconductor device of Patent Document 1, a conductive bonding material made of a low-melting-point metal such as solder or a sintered metal paste such as sintered silver is used to bond the semiconductor substrate and semiconductor chip. While these conductive bonding materials have the effect of alleviating distortion and stress caused by differences in the thermal expansion coefficients of the components that make up the device, there is a risk of cracks occurring in the solder itself when exposed to high temperatures in later processes, for example. Alternatively, when highly elastic sintered silver is used, there is a concern that cracks may occur in other components or short circuits may occur due to ion migration.

[0007] Therefore, in the post-bonding process, film formation processes at high temperatures or under high vacuum conditions cannot be used, and the insulating materials are limited, so the insulating layer tends to become thick in order to ensure the desired insulation properties, which places a limit on how miniaturized the device can be.

[0008] The present invention has been made in view of the above problems, and aims to provide a semiconductor device that can achieve both high insulation properties and miniaturization of the device. [Means for solving the problem]

[0009] One aspect of the present invention is A semiconductor device (1) having a main surface (2A) and a back surface (2B) facing opposite to each other in a plate thickness direction (X), the semiconductor element (2) having an element formation region on the main surface side, an insulating heat dissipation substrate (3) bonded to the back surface side, and a sealing insulating layer (4) provided on the main surface side, The insulating heat dissipation substrate includes an electrically insulating ceramic substrate (31) and a conductive layer (32) bonded to one side of the ceramic substrate in the plate thickness direction, the semiconductor element has a main surface-side electrode layer (21) on the main surface and a back surface-side electrode layer (22) on the back surface, and the back surface-side electrode layer is directly bonded to the conductive layer and thermally and electrically connected thereto; In the semiconductor device, an element embedding layer (5) for insulating and protecting the semiconductor element is disposed between the insulating heat dissipation substrate and the sealing insulating layer in the thickness direction. [Effects of the Invention]

[0010] In the semiconductor device having the above configuration, the backside electrode layer of the semiconductor element and the conductive layer of the insulating heat dissipation substrate are directly bonded, eliminating the need for conductive bonding materials such as solder or metal paste. Since no conductive bonding material is interposed between the bonding surfaces, the semiconductor device has excellent thermal and electrical bonding properties. Furthermore, since the insulating material and film-forming conditions used in the post-bonding process are not limited, for example, a high-temperature or high-vacuum film-forming process can be used to form a dense inorganic film with excellent insulation resistance. Therefore, while maintaining the desired insulation properties, the thickness of the element-embedding layer and the distance between the electrodes or wiring of the semiconductor element can be reduced, thereby achieving a compact and highly reliable semiconductor device.

[0011] As described above, according to the above aspect, it is possible to provide a semiconductor device that can achieve both high insulation and miniaturization of the device. In addition, the symbols in parentheses described in the claims and the means for solving the problems indicate the correspondence with the specific means described in the embodiments described below, and do not limit the technical scope of the present invention. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a schematic cross-sectional view showing a configuration of a main part of a semiconductor device according to a first embodiment. [Figure 2] 1 is a schematic cross-sectional view showing the overall configuration of a semiconductor device according to a first embodiment. [Figure 3] 2A and 2B are a plan view, a cross-sectional view taken along line AA, and a plan view of the back surface side showing an example of the configuration of a semiconductor element according to the first embodiment. [Figure 4] 4 is a graph showing the relationship between the thickness of the semiconductor element and the stress (equivalent strain) during bonding in the first embodiment. [Figure 5] 3A to 3C are process diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] 3A to 3C are process diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] 3A to 3C are process diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] 3 is a schematic perspective view of an insulating heat dissipation substrate showing an example of a slit pattern formed in an element-side conductive layer of the semiconductor device according to the first embodiment. FIG. [Figure 9] 1 is a schematic perspective view showing an example of the configuration of an insulating heat dissipation substrate used when manufacturing a semiconductor device according to the first embodiment. [Figure 10] 10A to 10C are process diagrams illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 11] FIG. 10 is a schematic cross-sectional view showing the configuration of a main part of a semiconductor device according to a third embodiment. [Figure 12] FIG. 10 is a plan view showing an example of the configuration of a semiconductor element according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] (Embodiment 1) An embodiment of a semiconductor device will be described with reference to the drawings. As shown in Fig. 1, a semiconductor device 1 of this embodiment constitutes a power converter or the like as a power semiconductor element used in, for example, a power module. Such a semiconductor device 1 is prone to heat generation due to the flow of a large current, and therefore is provided so as to be cooled, for example, by being placed on a cooler 100 provided next to the power module, as shown in Fig. 2. The main components thereof will be outlined below.

[0014] 1, the semiconductor device 1 includes a semiconductor element 2, an insulating heat dissipation substrate 3, and a sealing insulating layer 4. The semiconductor element 2 has a pair of surfaces 2A and 2B facing opposite each other in the plate thickness direction X, and has an element formation region on one of the surfaces, the main surface 2A (here, the top surface shown in FIG. 1). The other surface, the back surface 2B (here, the bottom surface shown in FIG. 1), is bonded to the insulating heat dissipation substrate 3. The sealing insulating layer 4 is provided on the main surface 2A side of the semiconductor element 2.

[0015] The plate thickness direction X is the thickness direction of the semiconductor element 2 and the insulating heat dissipation substrate 3, and corresponds to the up-and-down direction in Fig. 1. The direction along the plate surfaces of the semiconductor element 2 and the insulating heat dissipation substrate 3, which is perpendicular to the plate thickness direction X, will hereinafter be referred to as the plate surface direction Y.

[0016] The insulating heat dissipation substrate 3 has an electrically insulating ceramic substrate 31 and a conductive layer 32 bonded to one side of the ceramic substrate 31 in the plate thickness direction X. The insulating heat dissipation substrate 3 may also have a conductive layer 33 bonded to the other side of the ceramic substrate 31 in the plate thickness direction X. Hereinafter, a configuration in which the conductive layers 32, 33 are bonded to both sides of the ceramic substrate 31 will be described. That is, the conductive layer 32 is bonded and fixed to one surface (here, the upper surface shown in FIG. 1) of the ceramic substrate 31 adjacent to the semiconductor element 2, and the conductive layer 33 is bonded and fixed to the other surface (here, the lower surface shown in FIG. 1).

[0017] The semiconductor element 2 has a main surface-side electrode layer 21 on its main surface 2A, and a back surface-side electrode layer 22 on its back surface 2B, which is opposite the main surface 2A in the plate thickness direction X. The back surface-side electrode layer 22 is directly bonded to one of the conductive layers 32, 33 of the insulating heat dissipation substrate 3, and is thermally and electrically connected to it. Hereinafter, the one side bonded to the semiconductor element 2 will be referred to as the element-side conductive layer 32 as appropriate. Furthermore, the other side positioned on the opposite side of the ceramic substrate 31 from the semiconductor element 2 will be referred to as the heat dissipation-side conductive layer 33 as appropriate.

[0018] The backside electrode layer 22 of the semiconductor element 2 and the element-side conductive layer 32 of the insulating heat dissipation substrate 3 are directly bonded by, for example, diffusion bonding. Diffusion bonding is a method of forming a bond by holding metals together under heat and pressure, thereby diffusing atoms at the bonding interface. This not only achieves a bonding strength equivalent to the metal bulk strength at the bonded portion, but also high thermal conductivity, resulting in excellent heat dissipation to the insulating heat dissipation substrate 3.

[0019] Preferably, the backside electrode layer 22 of the semiconductor element 2 and the element-side conductive layer 32 of the insulating heat dissipation substrate 3 are made of the same metal, but they may be made of different metals. Temperature and pressure conditions below the melting point can be appropriately selected so that pressure bonding by interdiffusion through the interface is possible. Furthermore, to improve bonding, it is desirable to perform pretreatment such as planarization of the bonding surfaces of the backside electrode layer 22 and the element-side conductive layer 32.

[0020] In the plate thickness direction X, an element embedding layer 5 is provided between the sealing insulating layer 4 and the insulating heat dissipation substrate 3. The element embedding layer 5 is a layer that covers the surface of the semiconductor element 2 with an insulating material and is provided inside the insulating material to insulate and protect the semiconductor element 2. The insulating material is not particularly limited, but can be appropriately selected so as to have excellent insulation resistance and to obtain desired characteristics depending on the application, wiring structure, etc. of the semiconductor device 1. Similarly, the sealing insulating layer 4 can be made of the same or a different material as the element embedding layer 5.

[0021] Specifically, the sealing insulating layer 4 and the element embedding layer 5 are preferably made of an organic insulating material or an inorganic insulating material having a dielectric strength of 3 MV / cm or more. Examples of such organic insulating materials include polyimide and polybenzoxazole. Examples of inorganic insulating materials include SiO2, SiN, SiCN, and SiON. Of course, materials other than these that have the desired high insulating properties may also be used.

[0022] Preferably, at least a portion of the element embedding layer 5 formed on the side of the outer side surface 23 and the side of the main surface 2A of the semiconductor element 2 is made of an inorganic insulating material. More preferably, the entire element embedding layer 5 located on the side of the outer side surface 23 of the semiconductor element 2 in the plate surface direction Y can be made of an inorganic insulating material. Since inorganic insulating materials have better insulation resistance than organic insulating materials, by using an inorganic insulating material for at least a portion covering the surface of the semiconductor element 2, it is possible to efficiently achieve desired insulating characteristics.

[0023] In this case, the inorganic insulating material constituting the element burying layer 5 preferably has a dielectric strength of 10 MV / cm or more. The inorganic insulating materials of oxides or nitrides of Si described above all have a dielectric strength of 10 MV / cm or more and can be suitably used as the element burying layer 5.

[0024] Such a configuration is possible because the back-side electrode layer 22 of the semiconductor element 2 and the element-side conductive layer 32 of the insulating heat dissipation substrate 3 are directly bonded to each other. That is, a high-temperature process, which will be described later, can be used to form the element embedding layer 5, and the element embedding layer 5 having excellent insulation resistance can be easily formed. Therefore, the insulation provided by the element embedding layer 5 and the sealing insulating layer 4 can be improved, and the reliability of the semiconductor device 1 can be improved while suppressing an increase in size.

[0025] Note that, for example, a voltage of 1000 V or more is applied between the wirings or between the wirings and elements of the semiconductor device 1, and a voltage of 3000 V or more may be applied momentarily. For example, if the spacing between wirings is to be 10 μm or less in order to achieve miniaturization and high integration of the semiconductor device 1, a breakdown voltage of 3 MV / cm or more is required. Furthermore, to further improve the breakdown voltage margin or the performance of the semiconductor device 1, it is desirable for the semiconductor device 1 to have a breakdown voltage of more than 3 MV / cm.

[0026] Next, the configuration of each part of the semiconductor device 1 will be specifically described. 2, the entire semiconductor device 1 is placed on a cooling surface 101 of a cooler 100. Specifically, the cooler 100 is configured as a known heat sink, and heat dissipation fins 102 are provided on the side opposite to the surface that serves as the cooling surface 101 (here, the upper surface shown in FIG. 2) in the plate thickness direction X.

[0027] In the semiconductor device 1, the heat-dissipation-side conductive layer 33 of the insulating heat-dissipation substrate 3 is bonded to the cooling surface 101 via a bonding material layer 103. The bonding material layer 103 may be, for example, a heat-dissipating gel or solder, and thermally bonds the heat-dissipation-side conductive layer 33, which serves as the heat-dissipation surface of the semiconductor device 1, to the cooling surface 101. The heat-dissipating fins 102 of the cooler 100 are provided so as to be able to exchange heat with a cooling fluid flowing through the cooling mechanism of the power module, for example.

[0028] This allows for more effective heat dissipation from the insulating heat dissipation substrate 3, which is directly bonded to the semiconductor element 2, which is the heat-generating part. Here, the size of the cooling surface 101 of the cooler 100 is set to be equal to the size of the heat-dissipation-side conductive layer 33 of the insulating heat dissipation substrate 3, but the size of the cooling surface 101 may be made larger, and the heat dissipation path will expand outward, which will tend to improve heat dissipation.

[0029] The outer shape of the insulating heat dissipation substrate 3 is larger than the outer shape of the semiconductor element 2, and an element embedding layer 5 is disposed on the side of the semiconductor element 2 in the plate surface direction Y so as to surround the entire outer surface portion 23 of the semiconductor element 2. The outer size of the insulating heat dissipation substrate 3 is set so that it can support the entire semiconductor element 2 and so that the element embedding layer 5 on the side thereof has a thickness sufficient to maintain insulation.

[0030] In this embodiment, the insulating heat dissipation substrate 3 is configured as a three-layer laminate in which conductive layers, an element-side conductive layer 32 and a heat-dissipation-side conductive layer 33, are bonded to both sides of an electrically insulating ceramic substrate 31. The ceramic substrate 31 is made of insulating ceramics with good electrical insulation, such as AlO2, SiN, or AlN, and the element-side conductive layer 32 and the heat-dissipation-side conductive layer 33 are made of metal plates with good electrical and thermal conductivity, such as Cu or Al.

[0031] In the insulating heat dissipation substrate 3, the ceramic substrate 31 is formed in the shape of a rectangular plate having a thickness sufficient to ensure sufficient electrical insulation, and a heat dissipation-side conductive layer 33 is formed on the entire surface thereof. The surface of the heat dissipation-side conductive layer 33 opposite the ceramic substrate 31 becomes the outermost surface on the back side of the semiconductor device 1, and is in close contact with the cooling surface 101 of the cooler 100 via a bonding material layer 103, functioning as a heat dissipation surface that dissipates heat from the semiconductor device 1.

[0032] The outer shape of the element-side conductive layer 32 is larger than the outer shape of the back-side electrode layer 22 of the semiconductor element 2 and smaller than the outer shape of the ceramic substrate 31. Specifically, the element-side conductive layer 32 is formed to a size that can support the entire back-side electrode layer 22 and protrudes laterally beyond the outer shape of the back-side electrode layer 22 to enable electrode extraction to the main surface 2A. The element-side conductive layer 32 and the heat-dissipation-side conductive layer 33 are both formed to a predetermined thickness that is sufficiently thinner than the ceramic substrate 31, and are arranged on both sides of the ceramic substrate 31 to suppress increases in warpage and the like during heating. Note that if the amount of warpage can be controlled by the thickness of the element-side conductive layer 32, the heat-dissipation-side conductive layer 33 may be omitted.

[0033] Furthermore, the element-side conductive layer 32 is not a single plate of uniform thickness overall, but is formed in a plate shape partially having slits 321. The intervals and widths of the slits 321 are not particularly limited, and for example, a plurality of parallel slits 321 are formed in the region in contact with the semiconductor element 2 and open toward the back-side electrode layer 22. This makes it possible to relieve stress caused by differences in the thermal expansion coefficients of the respective members during bonding with the semiconductor element 2 and in subsequent processes.

[0034] The semiconductor element 2 generally has a semiconductor layer formed on a semiconductor substrate, the surface of which is used as an element formation region. The semiconductor element 2 is, for example, a transistor such as a MOSFET (i.e., a metal oxide semiconductor field effect transistor), and in the element formation region, a large number of cells having a known transistor structure are formed and connected to a main surface side electrode layer 21 and a back surface side electrode layer 22.

[0035] 3, a gate electrode 21G and a source electrode 21S are formed as a main-surface-side electrode layer 21 in a predetermined region on the main surface 2A of the semiconductor element 2, and a drain electrode 22D is formed as a back-surface-side electrode layer 22 over the entire back surface 2B of the semiconductor element 2. For the semiconductor substrate, a semiconductor such as Si, SiC, GaN, or Ga2O3 can be used.

[0036] In Figure 2, the gate electrode 21G and source electrode 21S as the main surface side electrode layer 21 are drawn out from the side of the sealing insulating layer 4 via rewiring layers 24G, 24S and drawing portions 25G, 25S, which are wiring layers 24 provided inside the sealing insulating layer 4 covering the semiconductor element 2.

[0037] Furthermore, the drain electrode 22D serving as the back-side electrode layer 22 is directly bonded to the element-side conductive layer 32, and is connected to a conductor portion disposed in an opening 6 penetrating the element embedding layer 5 covering the surface of the element-side conductive layer 32 on the side of the semiconductor element 2. This conductor portion is further connected to a rewiring layer 24D, which is the wiring layer 24 provided inside the sealing insulating layer 4, and is drawn out from the side of the sealing insulating layer 4 via a drawing portion 25D.

[0038] Metallic materials with good electrical conductivity, such as Cu and Al, are used for the wiring layer 24 and the lead-out portion 25. The semiconductor element 2 is not limited to a MOSFET, but may be a transistor such as an IGBT (i.e., an insulated gate bipolar transistor) or other elements.

[0039] In this case, it is desirable that the semiconductor element 2 be a thin element to improve embedding by the element embedding layer 5. Preferably, the thickness of the semiconductor element 2 is, for example, about 100 μm or less. This makes it easier to select a highly insulating inorganic material, and enables the insulating film that becomes the element embedding layer 5 to be formed by a high-temperature process, thereby improving insulation. Furthermore, in a configuration in which the back-side electrode layer 22 is directly bonded to the element-side conductive layer 32 of the insulating heat dissipation substrate 3, it becomes possible to alleviate stress caused by differences in the linear expansion coefficients of the respective members.

[0040] In this embodiment, the element embedding layer 5 is configured as a laminated film of a first embedding layer 51 and a second embedding layer 52. The first embedding layer 51 is arranged so as to embed the element-side conductive layer 32 of the insulating heat dissipation substrate 3 to which the semiconductor element 2 is bonded, and is a layer including a portion formed on the outer side surface portion 23 side and the main surface 2A side of the semiconductor element 2 described above. The second embedding layer 52 is arranged above the first embedding layer 51. The second embedding layer 52 is formed integrally with the first embedding layer 51 so as to embed the entire semiconductor element 2 including the main surface-side electrode layer 21 and the back surface-side electrode layer 22.

[0041] The element burying layer 5 can be formed by sequentially depositing the first burying layer 51 and the second burying layer 52 as layers made of the same or different inorganic insulating materials. Preferably, they are made of the same inorganic insulating material. This improves the insulation resistance near the semiconductor element 2 and enhances reliability in semiconductor devices 1 that are becoming increasingly smaller and more highly integrated.

[0042] The encapsulating insulating layer 4 is further deposited on top of the element burying layer 5. If the element burying layer 5 ensures insulation resistance in the vicinity of the semiconductor element 2, the encapsulating insulating layer 4 does not necessarily need to have the same high dielectric strength as the element burying layer 5, and a material satisfying the required characteristics can be appropriately selected from organic or inorganic insulating materials. Such a combination of the encapsulating insulating layer 4 and the element burying layer 5 widens the options for insulating materials and deposition methods, making it possible to efficiently achieve desired insulation characteristics.

[0043] FIG. 4 shows the relationship between the thickness (unit: μm) of the semiconductor element 2 formed on the SiC substrate and the stress (equivalent strain; unit: %) applied to the semiconductor element 2 when forming the element embedding layer 5. SiO2 is used for the insulating film that becomes the element embedding layer 5. The simulation results shown in FIG. 4 show that the thinner the thickness of the semiconductor element 2, the lower the stress, reaching a minimum at around 100 μm. On the other hand, when the thickness of the semiconductor element 2 becomes even thinner and falls below 50 μm, the stress tends to increase again. Therefore, it is preferable to select the thickness of the semiconductor element 2 appropriately from the range of 50 μm to 100 μm.

[0044] 5 to 7, a method for manufacturing the semiconductor device 1 having the configuration shown in Fig. 1 will be specifically described. In steps (1) to (4) of Fig. 5, an insulating heat dissipation substrate 3 is used, in which an element-side conductive layer 32 and a heat-dissipation-side conductive layer 33 made of, for example, a Cu plate are bonded to both sides of a ceramic substrate 31, and a first buried layer 51 of the buried layer 5 is formed on the element-side conductive layer 32. Fig. 8 shows an example of a slit pattern of the element-side conductive layer 32, and Fig. 9 shows an example in which the insulating heat dissipation substrate 3 is used as a support substrate 30 when manufacturing multiple semiconductor devices 1.

[0045] 5(1), a Cu plate 320 that will become the element-side conductive layer 32 on the insulating heat dissipation substrate 3 is first plated with Cu. The element-side conductive layer 32, including the Cu plating layer 300, is then formed to a desired thickness. Then, in step (2), slits 321 are formed in the element-side conductive layer 32 to form a predetermined pattern. Then, in step (3), an inorganic insulating film 50 that will become the first buried layer 51 is formed so as to embed the element-side conductive layer 32. The first buried layer 51 can be formed by depositing, for example, an SiO2 film that is the inorganic insulating film 50 using a vapor deposition method such as CVD (Chemical Vapor Deposition).

[0046] Although the film formation conditions by the CVD method are not necessarily limited, the film density and strength of the obtained film tend to increase with increasing film formation temperature, and the insulating properties tend to improve. Therefore, it is preferable to introduce the source gas at a high temperature of 400°C or higher and in a high vacuum atmosphere, which makes it possible to obtain a dense film having a dielectric strength of, for example, 10 MV / cm or higher.

[0047] The insulating film that becomes the first burying layer 51 is not limited to the inorganic insulating film 50. An organic insulating film made of an organic insulating material such as polyimide can also be formed by spin coating. The film formation conditions by spin coating are not necessarily limited, but the resulting film tends to have increased film density and strength as the film formation temperature increases, improving its insulating properties. Therefore, it is preferable to use a high temperature of 300°C or higher and a low-oxygen atmosphere, which makes it possible to obtain a dense film with a dielectric strength of, for example, 3 MV / cm or higher.

[0048] Next, in step (4), a cutting or grinding process is performed to expose and flatten the element-side conductive layer 32, which will be the bonding surface. Specifically, a portion of the surface side of the formed inorganic insulating film 50 is removed by a process such as CMP (Chemical Mechanical Polishing) to expose the flat surface of the element-side conductive layer 32. At this time, the process may be performed so that the surface of the first buried layer 51 and the exposed surface of the element-side conductive layer 32 are flush with each other, or so that the exposed surface of the element-side conductive layer 32 protrudes slightly.

[0049] 6(5) to (7), the semiconductor element 2 is mounted and embedded in the element-embedding layer 5. First, in step (5) of FIG. 6(5), the semiconductor element 2 is placed on the insulating heat dissipation substrate 3, and the back-side electrode layer 22 of the semiconductor element 2 and the element-side conductive layer 32 of the insulating heat dissipation substrate 3 are integrated by metal-to-metal diffusion bonding. Specifically, the surfaces of the back-side electrode layer 22 and the element-side conductive layer 32, which will be the bonding surfaces, are each subjected to a hydrophilic treatment, and then the two can be pressure-bonded at a temperature of, for example, room temperature to 300°C.

[0050] At this time, the back-side electrode layer 22 is brought into alignment with the element-side conductive layer 32 having slits 321 of a predetermined pattern, for example, as shown in FIG. 8( a), and then the entire semiconductor element 2 is gradually bonded. During this process, voids (air bubbles) that occur within the bonding surface can be gradually pushed toward the slits 321 during bonding. As a result, the generation of voids within the bonding surface can be suppressed, and the expansion and explosion of gas within the voids (air bubbles) can be suppressed even during subsequent manufacturing processes and at high temperatures during operation, thereby improving the quality of the bonded portion and the reliability of the device.

[0051] The shape and arrangement of the slits 321 in the element-side conductive layer 32 of the insulating heat dissipation substrate 3 are arbitrary. As shown in FIG. 8( a), multiple parallel slits 321 extending in the plate surface direction Y may be used. Alternatively, as shown in FIG. 8( b), multiple orthogonal cross-shaped slits 321 may be used. Alternatively, as shown in FIG. 8( c), the slits 321 may be formed in the shape of a rectangular frame surrounding the outermost periphery of the element-side conductive layer 32. Alternatively, as shown in FIG. 8( d), the slits 321 may be formed inside the outermost periphery of the element-side conductive layer 32. The number of slits 321 is not necessarily limited; it is preferable that the element-side conductive layer 32 is roughly evenly divided by one or more slits 321. The slits 321 may not penetrate between opposing sides of the element-side conductive layer 32, but may be shaped so that the divided element-side conductive layers 32 are thermally or electrically connected to each other.

[0052] 6(6), an inorganic insulating film 50 that becomes the second buried layer 52 is formed so as to embed the semiconductor element 2. The second buried layer 52 can be formed by the same CVD method as the first buried layer 51. This allows the inorganic insulating film 50, for example, an SiO2 film, to be formed as a dense film with desired insulation resistance, covering the exposed surfaces of the first buried layer 51 and the element-side conductive layer 32, and the surface of the semiconductor element 2.

[0053] 6(7), the main surface side electrode layer 21 of the semiconductor element 2 is exposed and a cutting or grinding process is performed for planarization. This process can be performed in the same manner as the process of FIG. 5(4), and a portion of the deposited inorganic insulating film 50 is removed by a process such as CMP so as to expose the main surface side electrode layer 21. Furthermore, a portion of the deposited inorganic insulating film 50 is removed by dry etching or the like above the element-side conductive layer 32 located on the side of the semiconductor element 2, to form an opening 6 for electrode extraction that penetrates the inorganic insulating film 50. For example, SF6 gas or the like can be used for dry etching.

[0054] In this manner, the element burying layer 5 consisting of the first and second burying layers 51 and 52 can be formed.

[0055] Thereafter, in steps (8) to (10) of Fig. 7, rewiring for connecting the electrodes is performed. First, in step (8) of Fig. 7, a seed layer 20 is formed on the entire surfaces of the semiconductor element 2 and the element embedding layer 5. The seed layer 20 is formed prior to plating for rewiring, and may have a two-layer structure such as Ti / Cu, which is commonly used in Cu electroplating. The thickness of the Ti / Cu layers that form the seed layer 20 is preferably in the range of 100 nm to 300 nm.

[0056] Next, in step (9), photoresist patterning is performed using the seed layer 20 formed on the entire surface, and then Cu electroplating is performed to form redistribution layers 24G and 24S in predetermined positions corresponding to the gate electrode 21G and source electrode 21S. 24D is also formed. Then, a redistribution layer 24D corresponding to the drain electrode 22D is formed. Then, the photoresist and seed layer 20 are removed.

[0057] Furthermore, in step (10), a sealing and insulating layer 4 is formed to provide insulation between the formed rewiring layers 24G, 24S, and 24D. Specifically, an insulating film that becomes the sealing and insulating layer 4 is formed to cover the entire surface on which the rewiring layers 24G, 24S, and 24D are formed, and then the rewiring layers 24G, 24S, and 24D are exposed. The sealing and insulating layer 4 is, for example, an organic insulating film such as polyimide. In this case, openings 6 can be formed in the polyimide, which is a photosensitive insulating film, by an exposure process.

[0058] The sealing insulating layer 4 may be made of an inorganic insulating film such as SiO2, and in that case, the portions to be connected to the external electrodes can be opened using dry etching or the like to form the openings 6.

[0059] 2, the process of depositing multiple insulating films and forming openings 6 is repeated to form rewiring layers 24G, 24S, and 24D in openings 6, and also to form lead portions 25G, 25S, and 25D. In this case, lead portions 25G and 25S can be formed on the surface of different insulating films, while lead portions 25G and 25D can be formed on the surface of the same insulating film and led out in different directions. This facilitates connection to external electrodes, and the entire device can be made compact because wire bonding or the like is not used.

[0060] As described above, according to this embodiment, the element embedding layer 5 using the inorganic insulating film 50 can ensure the desired insulating properties, so that the thickness of the element embedding layer 5 and the distance between the electrodes or wirings of the semiconductor element 2 can be reduced, thereby realizing a small and highly reliable semiconductor device 1.

[0061] 9, such an insulating heat dissipation substrate 3 can be configured as a support substrate 30 including a plurality of element-side conductive layers 32 for mounting a plurality of semiconductor elements 2. In this case, the support substrate 30 includes a plurality of pairs (for example, six pairs in the configuration shown in FIG. 9) of insulating heat dissipation substrates 3, each of which has an element-side conductive layer 32 and a heat-dissipation-side conductive layer 33 configured as shown in FIG. 5 arranged on both sides of a ceramic substrate 31. By subjecting the support substrate 30 including these plurality of insulating heat dissipation substrates 3 to the processes shown in FIGS. 5 to 7, a semiconductor element 2 can be mounted on each pair of element-side conductive layers 32.

[0062] Thereafter, semiconductor elements 2 are mounted corresponding to each pair, and the insulating heat dissipation substrate 3 that has been rewired is cut into individual chips in a dicing process to form the semiconductor device 1. In this way, a plurality of semiconductor devices 1 can be simultaneously produced using the insulating heat dissipation substrate 3 as the support substrate 30, which enables cost reduction by streamlining the manufacturing process.

[0063] (Embodiment 2) A second embodiment of the semiconductor device 1 will be described with reference to Figure 10. The basic configuration of the semiconductor device 1 of this embodiment is the same as that of the first embodiment, except for the configuration of the element burying layer 5. Steps (1) and (2) in Figure 10 correspond to steps (6) and (7) in Figure 6, and the other steps can be performed in the same way as in the first embodiment. The following description will focus on the differences. Note that, among the symbols used in the second and subsequent embodiments, the same symbols as those used in the previous embodiments represent the same components, etc. as those in the previous embodiments, unless otherwise specified.

[0064] 10(2), in the semiconductor device 1 of this embodiment, the element burying layer 5 also has a first burying layer 51 formed so as to cover the element-side conductive layer 32 of the insulating heat dissipation substrate 3, and a second burying layer 52 above it. The configuration and formation method of the first burying layer 51 are the same as those of the first embodiment, but the configuration and formation method of the second burying layer 52 are different.

[0065] In this embodiment, the second buried layer 52 is formed only on the outer side surface 23 side and part of the main surface 2A side of the semiconductor element 2. In this case, the second buried layer 52 does not need to be formed to cover the surface of the first buried layer 51. A third buried layer 53 is separately formed on the surface of the first buried layer 51.

[0066] For the second burying layer 52, a vapor phase growth method such as CVD can be used as in the first embodiment, or alternatively, a spin-on-glass (SOG) method can be used. This method involves forming the inorganic insulating film 50 by spin coating and then hardening it by heat treatment, and since it is not necessary to bury the entire semiconductor element 2, it is possible to shorten the time required for the film formation process. In addition, it is generally desirable for the heat treatment temperature to be 400°C or higher, and by performing heat treatment at a high temperature, it is possible to form a dense film similar to that in the first embodiment.

[0067] 10(1), in this case, first, a SiO2 film or the like is formed by spin coating so as to cover the main surface 2A side and outer side surface portion 23 of the semiconductor element 2 and the surface of the first buried layer 51, and then heat treatment is performed to form the inorganic insulating film 50. Thereafter, as in the first embodiment, the main surface-side electrode layer 21 is exposed and a planarization process is performed. At this time, in the plate surface direction Y, the inorganic insulating film 50 above the element-side conductive layer 32 is removed, leaving a portion covering the outer side surface portion 23, to expose the surface of the element-side conductive layer 32.

[0068] Thereafter, on the outer periphery of the semiconductor element 2, a third buried layer 53 is formed integrally with the first buried layer 51 and the second buried layer 52 on the surface of the element-side conductive layer 32 excluding the portion that will become the opening 6 and on the surface of the first buried layer 51. This third buried layer 53 does not need to be formed of an inorganic insulating film, but may be an organic insulating film. In the latter case, for example, it can be formed simultaneously when the upper sealing insulating layer 4 is formed.

[0069] As described above, according to the configuration of this embodiment, the element embedding layer 5 can be formed by a simpler process. That is, by forming an inorganic insulating film that covers only the main surface 2A and the surface of the outer side surface portion 23 of the semiconductor element 2, the thickness of the formed film can be reduced, and the semiconductor element 2 can be embedded with sufficient dielectric strength. Therefore, a small-sized and highly reliable semiconductor device 1 can be realized.

[0070] (Embodiment 3) 11 and 12, a third embodiment of the semiconductor device 1 will be described. The semiconductor device 1 of this embodiment has the same basic configuration as the first embodiment, and has the same element-burying layer 5 as the second embodiment, but differs in the configuration of the back-side electrode layer 22 of the semiconductor element 2 bonded to the insulating heat dissipation substrate 3. The following description will focus on the differences.

[0071] 11, in the semiconductor device 1 of this embodiment, the configuration of the element-side conductive layer 32 of the insulating heat dissipation substrate 3 is the same as in the first embodiment, and is formed in a plate shape having a plurality of slits 321. In this embodiment, as shown in Fig. 12, similar slits 221 are also formed in the back-side electrode layer 22 of the semiconductor element 2 that is joined to the element-side conductive layer 32.

[0072] The slits 221 in the back-side electrode layer 22 are, for example, multiple parallel slits extending in the plate surface direction Y and opening toward the element-side conductive layer 32, and can be formed at the same positions as the slits 321 in the element-side conductive layer 32. In this case, the back-side electrode layer 22 and the element-side conductive layer 32 can be bonded in the same manner. This configuration also enhances the effect of mitigating distortion and stress caused by the difference in linear expansion coefficients. That is, since the slits 221, 321 are formed on both sides that serve as bonding surfaces, distortion and stress can be easily absorbed when the temperature rises during post-processing or operation.

[0073] The slits 221 in the back-side electrode layer 22 do not need to be formed in the same shape and at the same position as the slits 321 in the element-side conductive layer 32, but it is preferable that they at least partially overlap with each other. This prevents a decrease in the bonding area between the back-side electrode layer 22 and the element-side conductive layer 32, and further enhances the effect of alleviating distortion and stress while maintaining bonding.

[0074] In this way, also in the configuration of this embodiment, it is possible to realize a semiconductor device 1 that is small in size and has excellent reliability.

[0075] Although the element-burying layer 5 of this embodiment has been exemplified as having the first to third burying layers 51 to 53, as in the second embodiment, the present invention is not limited thereto and can also be applied to a configuration having the element-burying layer 5 of the first embodiment. Furthermore, the shape and arrangement of the slits 321, 221 formed in the element-side conductive layer 32 of the insulating heat dissipation substrate 3 or the back-side electrode layer 22 of the semiconductor element 2 can be changed as appropriate. In such cases, the changed configuration can also be applied to the configurations of the other embodiments.

[0076] In the above embodiments, the insulating heat dissipation substrate 3 has been shown as an example of a configuration in which conductive layers 32, 33 are bonded to both sides of the ceramic substrate 31. However, it is sufficient that the insulating heat dissipation substrate 3 has at least the element-side conductive layer 32 arranged on the element side, and the heat dissipation-side conductive layer 33 may not be included. Also, while the insulating heat dissipation substrate 3 and semiconductor element 2 of the semiconductor device 1 are shown as square, the outer shapes of the device and the substrate may be any shape. Furthermore, the arrangement and shapes of the gate electrode 21G, source electrode 21S, and drain electrode 22D formed on the semiconductor element 2 are not particularly limited and may be changed as appropriate.

[0077] Furthermore, in the above embodiment, an example of single-sided cooling has been described in which the insulating heat dissipation substrate 3 on the back surface 2B of the semiconductor element 2 is placed on the cooler 100 to serve as the heat dissipation surface, but the invention can also be applied to a double-sided cooling structure in which heat can be dissipated from the main surface 2A of the semiconductor element 2. Also, an example has been shown in which the semiconductor device 1 is applied as a power element to a power module that constitutes a power conversion device, but the invention can be used for any application other than this.

[0078] The present invention is not limited to the above-described embodiments, and can be applied to various embodiments within the scope of the present invention. [Explanation of symbols]

[0079] 1. Semiconductor device 2. Semiconductor elements 2A main surface 2B back side 21 Principal surface electrode layer 22 Back side electrode layer 3. Insulating heat dissipation substrate 32 Element side conductive layer (conductive layer) 4. Sealing insulation layer 5. Embedded element layer

Claims

1. A semiconductor device (1) having a main surface (2A) and a back surface (2B) facing opposite sides in a plate thickness direction (X), the semiconductor element (2) having an element formation region on the main surface side, an insulating heat dissipation substrate (3) bonded to the back surface side, and a sealing insulating layer (4) provided on the main surface side, The insulating heat dissipation substrate has an electrically insulating ceramic substrate (31) and a conductive layer (32) bonded to one side of the ceramic substrate in the plate thickness direction, the semiconductor element has a main surface-side electrode layer (21) on the main surface and a back surface-side electrode layer (22) on the back surface, and the back surface-side electrode layer is directly bonded to the conductive layer and thermally and electrically connected thereto; The semiconductor device has an element embedding layer (5) disposed between the insulating heat dissipation substrate and the sealing insulating layer in the thickness direction of the plate for insulating and protecting the semiconductor element.

2. 2. The semiconductor device according to claim 1, wherein said sealing insulating layer and said element burying layer are made of an organic insulating material or an inorganic insulating material having a dielectric strength of 3 MV / cm or more.

3. 2. The semiconductor device according to claim 1, wherein at least a portion of said element embedding layer formed on the outer side surface portion (23) side of said semiconductor element and on said main surface side is made of an inorganic insulating material.

4. 4. The semiconductor device according to claim 3, wherein the inorganic insulating material has a dielectric strength of 10 MV / cm or more.

5. 5. The semiconductor device according to claim 4, wherein the semiconductor element has a thickness of 100 [mu]m or less.

6. 2. The semiconductor device according to claim 1, wherein the insulating heat dissipation substrate has a plurality of slits (321) in the conductive layer directly joined to the back surface electrode layer, the slits extending in a plate surface direction (Y) and opening toward the back surface electrode layer.

7. 7. The semiconductor device according to claim 6, wherein said back surface side electrode layer has a plurality of slits (221) extending in a plate surface direction (Y) and opening toward said conductive layer.

8. 2. The semiconductor device according to claim 1, wherein the main surface side electrode layer and the back surface side electrode layer are connected to a wiring layer (24) for external extraction that is arranged in an opening (6) provided in the sealing insulating layer.

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