Semiconductor equipment and devices

Abstract

This suppresses deterioration in image quality due to fluctuations in the potential of the voltage supply line. [Solution] A structure having a pixel array having a plurality of pixels arranged across a plurality of rows and a plurality of columns, a circuit section that scans the plurality of pixels or processes signals output from the plurality of pixels, and a voltage generation circuit that generates a first voltage, and a wiring section provided outside the structure, wherein the first voltage is supplied from the voltage generation circuit to the circuit section via the wiring section.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices and apparatus. [Background technology]

[0002] Semiconductor devices having functional elements provided in a semiconductor element layer are known. As an example of such a semiconductor device, an imaging device having a driver unit that selects a pixel row from which a signal is to be read and a power supply unit that supplies a voltage to the driver unit is disclosed in Patent Document 1. A voltage is supplied to the driver unit via wiring from a power supply unit provided inside the imaging device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2022-23639 Summary of the Invention [Problem to be solved by the invention]

[0004] Potential fluctuations may occur in the wiring path that supplies voltage from the voltage generating circuit to the functional element, which may result in a decrease in the operational accuracy of the functional element. [Means for solving the problem]

[0005] One aspect of the present disclosure is a semiconductor device comprising: a structure having a pixel array having a plurality of pixels arranged across a plurality of rows and a plurality of columns; a circuit unit that scans the plurality of pixels or processes signals output from the plurality of pixels; and a voltage generation circuit that generates a first voltage; and a wiring unit provided outside the structure, wherein the first voltage is supplied from the voltage generation circuit to the circuit unit via the wiring unit. [Effects of the Invention]

[0006] According to at least one embodiment of the present disclosure, it is possible to provide a technique for reducing potential fluctuations in a wiring path that supplies a voltage from a voltage generating circuit to a functional element. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic diagram of an imaging device according to a first embodiment. [Figure 2] 1 is a schematic diagram of an imaging device according to a first embodiment. [Figure 3] 1 is a schematic diagram of an imaging device according to a first embodiment. [Figure 4] 1 is a schematic diagram of an imaging device according to a first embodiment. [Figure 5] 1 is a schematic diagram of an imaging device according to a first embodiment. [Figure 6] 1 is a schematic diagram of an imaging device according to a first embodiment. [Figure 7] 10 is a comparative example of an imaging device for explaining the effect of the first embodiment. [Figure 8] 10 is a comparative example of an imaging device for explaining the effect of the first embodiment. [Figure 9] 1 is a schematic diagram of an imaging device according to a first embodiment. [Figure 10] 1 is a schematic diagram of an imaging device according to a first embodiment. [Figure 11] FIG. 10 is a schematic diagram of an imaging device according to a second embodiment. [Figure 12] 10 is a comparative example of an imaging device for explaining the effect of the second embodiment. [Figure 13] 10 is a comparative example of an imaging device for explaining the effect of the second embodiment. [Figure 14] 10 is a comparative example of an imaging device for explaining the effect of the second embodiment. [Figure 15] FIG. 10 is a schematic diagram of an imaging device according to a third embodiment. [Figure 16] FIG. 10 is a schematic diagram of an imaging device according to a fourth embodiment. [Figure 17] FIG. 10 is a schematic diagram of an imaging device according to a fourth embodiment. [Figure 18]FIG. 10 is a schematic diagram of a device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following description and drawings, common reference numerals are used to designate components common to multiple drawings. Therefore, common components will be described with mutual reference to multiple drawings, and descriptions of components with common reference numerals will be omitted as appropriate.

[0009] In the following embodiments, a solid-state imaging device will be mainly described as an example of a semiconductor device. However, the embodiments are not limited to solid-state imaging devices and can be applied to other examples of semiconductor devices. For example, a distance measuring device (a device for measuring distance using focus detection or TOF (Time Of Flight)) or a photometric device (a device for measuring the amount of incident light) can be used.

[0010] Furthermore, the metal members such as wiring and pads described in this specification may be composed of a single metal element or a mixture (alloy). For example, wiring described as copper wiring may be composed of copper alone, or may be composed mainly of copper and further contain other components.

[0011] Furthermore, for example, the pads connected to external terminals may be made of aluminum alone, or may contain aluminum as the main component and other components as well. The copper wiring and aluminum pads shown here are merely examples, and various metals can be used instead.

[0012] Furthermore, the wiring and pad portions shown here are an example of metal members used in semiconductor devices, and the present invention can also be applied to other metal members.

[0013] In the following embodiments, the connection between elements of a circuit may be described. In this case, even if another element is interposed between the elements of interest, the elements of interest are treated as being connected to each other unless otherwise specified. For example, assume that element A is connected to one node of a capacitive element C having multiple nodes, and element B is connected to the other node. Even in such a case, element A and element B are treated as being connected to each other unless otherwise specified.

[0014] (First embodiment) 1 to 6 are schematic diagrams of a solid-state imaging device according to Embodiment 1. A solid-state imaging device 1000 of this embodiment is a laminated body in which a pixel substrate 110 and a circuit substrate 150 are bonded together.

[0015] 1 is a schematic diagram of a pixel substrate 110 constituting a solid-state imaging device, viewed from the top of the imaging device (in the direction normal to the light-receiving surface of the solid-state imaging device). The pixel substrate 110 is provided with a pixel array 100 in which a plurality of pixels 10 are arranged across a plurality of rows and a plurality of columns. In addition, a plurality of pad sections 16 are arranged in a peripheral region 15.

[0016] The plurality of pad sections 16 conduct electricity between the solid-state imaging device and a signal processing device or the like disposed outside the solid-state imaging device. The plurality of pad sections 16 include a pad section that outputs a signal from the solid-state imaging device to the outside and a pad section that inputs a power supply voltage or the like to the solid-state imaging device.

[0017] 2 is a schematic diagram of the circuit board 150 when viewed from the top of the solid-state imaging device (in the direction normal to the light-receiving surface of the imaging device). The circuit board 150 is provided with a row selection circuit 180 and a row selection circuit 200. The row selection circuit 180 and the row selection circuit 200 supply row selection signals to each row of the pixel array 100 via junctions that electrically connect the pixel substrate 110 and the circuit board 150. The pixels 10 included in the pixel row to which the row selection signal is input output signals having signal levels corresponding to the amount of incident light to signal lines 30, which will be described later.

[0018] The circuit board 150 is also provided with ADCs (AD converters) 220 and 222 that process signals from the respective pixels 10. The circuit board 150 is also provided with logic circuits 230 and 232 that process signals from the ADCs 220 and 222.

[0019] Furthermore, the circuit board 150 is provided with an IF circuit 240 and an IF circuit 242 that output signals from the logic circuit 230 and the logic circuit 232 to the outside. The circuit board 150 is also provided with a voltage generating circuit 500. Furthermore, a wiring section 510, a capacitive element 520, and a capacitive element 521 are provided outside the circuit board 150.

[0020] 3 is a cross-sectional view taken along the line XX′ in FIG. 3. FIG. 3 shows a state in which the pixel substrate 110 and the circuit substrate 150 are bonded at the bonding surface 3. A trench that becomes the pad portion 16 is formed at the end of the semiconductor element layer 11. The trench is formed in the depth direction from the light incident surface of the semiconductor element layer 11, and is formed to a depth that reaches the wiring pattern of the wiring layer 342 of the circuit substrate 150.

[0021] In the pad portion 16, a wiring layer 342 formed on the circuit board 150 is electrically connected to the outside of the imaging element by a bonding wire 5. For example, a material containing gold as a main component is preferably used as the material for the bonding wire.

[0022] The wiring structure 12 of the pixel substrate 110 and the wiring structure 34 of the circuit substrate 150 are located between the semiconductor element layer 11 of the pixel substrate 110 and the semiconductor element layer 23 of the circuit substrate 150. In FIG. 3 , the wiring structure 12 has three wiring layers, 121, 122, and 123, and the wiring structure 34 has three wiring layers, 341, 342, and 343.

[0023] The wiring structure 12 has three wiring layers: wiring layers 121, 122, and 123. The wiring layers 121, 122, and 123 may be, for example, Cu wiring layers. In Fig. 3, the wiring layer 123 forms the metal portion 21 of the metal junction 20. The metal junction 20 is embedded in a recess formed in an interlayer insulating film and has a damascene structure.

[0024] The wiring structure 34 has three wiring layers: wiring layers 341, 342, and 343. The wiring layers 341, 342, and 343 can be Cu wiring layers. In FIG. 3, the wiring layer 343 forms the metal portion 22 of the metal junction 20. The metal portion 22 is embedded in a recess formed in the interlayer insulating film and has a damascene structure.

[0025] An interlayer insulating film having a recess in which metal portion 21 is buried, an interlayer insulating film having a recess in which metal portion 22 is buried, and metal portions 21 and 22 are bonded (contacted) to each other. Metal portion 21 and metal portion 22 are bonded to each other, thereby forming metal junction 20.

[0026] Via plugs 124 formed in the interlayer insulating film of wiring layer 123 provide electrical conductivity between metal portion 21 and wiring layer 122. Via plugs 344 formed in the interlayer insulating film of wiring layer 343 provide electrical conductivity between metal portion 22 and wiring layer 342. Metal junctions 20 where via plugs 124 and 344 are joined provide electrical connection between semiconductor element layer 11 and semiconductor element layer 23.

[0027] 3, for example, the wiring pattern of wiring layer 123 is electrically connected to the wiring pattern of wiring layer 122, which is the layer above it, through via plug 124. Furthermore, the wiring pattern of wiring layer 343 is electrically connected to the wiring pattern of wiring layer 342, which is the layer below it, through via plug 344. Note that via plugs are not essential, and the wiring pattern may be electrically connected to the wiring pattern of the upper or lower layer by directly contacting it.

[0028] 3, the wiring patterns of the wiring layer 123 and the wiring pattern of the wiring layer 343 electrically connect the semiconductor element layer 11 and the semiconductor element layer 33. It is not necessary for all of the wiring patterns of the wiring layer 123 and the wiring layer 343 to electrically connect the semiconductor element layer 11 and the semiconductor element layer 33, and some of the wiring patterns may be electrically connected to the semiconductor element layer 11 or the semiconductor element layer 33. It is also possible for some of the wiring patterns to be electrically connected to either of the wiring layers and not electrically connected to either the semiconductor element layer 11 or the semiconductor element layer 33.

[0029] A microlens ML is arranged on the light incident surface side of the semiconductor element layer 11 via an insulating material F. A color filter CF is arranged between the microlens ML and the insulating material F. The arrangement of the color filter CF can be selected appropriately. For example, a Bayer array may be used. A plurality of photoelectric conversion units may be arranged for one microlens ML.

[0030] As described above, this embodiment is a stacked solid-state imaging device made up of the pixel substrate 110 and the circuit substrate 150. The row selection circuit 180 and the row selection circuit 200 select a row of the pixel array 100, and the signal from the selected row is read out to the ADC 220 and the ADC 222 of the circuit substrate 150 via the metal junction 20.

[0031] 4 is a schematic diagram showing an example of the configuration of the ADC 220. The ADC 220 has a signal line 30, a current source 40, a ramp signal generating circuit 50, a comparator 60, a first memory 70, a second memory 80, and a counter 90. One CRT circuit has the current source 40, the comparator 60, the first memory 70, the second memory 80, and the counter 90. This one CRT circuit is arranged corresponding to one signal line 30. The present invention is not limited to this example, and one CRT circuit may be provided for multiple signal lines 30, or multiple CRT circuit circuits may be provided for one signal line 30.

[0032] 5 is a schematic diagram showing an example of the configuration of a pixel 10. The signal line 30 of the ADC 220 shown in FIG. 4 is electrically connected to the signal line 30 of the pixel shown in FIG. 3 by a metal junction 20. Each pixel of the pixel array 100 has a photodiode 400, a transfer transistor 410, a floating diffusion 420, a source follower transistor 430, and a selection transistor 440. The pixel 10 also has a GND (ground potential) node 450, a reset transistor 455, a gain switching transistor 456, and a power supply node 460.

[0033] 5, photocharges generated in a photodiode 400 are transferred to a floating diffusion 420 by turning on a transfer transistor 410, and are converted into a signal voltage by a parasitic capacitance associated with the floating diffusion 420. Note that in FIG. 5, the configuration is such that the conversion gain can be switched by switching a gain switching transistor 456 between an on state and an off state.

[0034] The converted signal voltage is output to the signal line 30 via the source follower transistor 430 and the selection transistor 440. The source follower transistor 430 forms a source follower together with the current source 40 in FIG. 4, and the signal voltage on the floating diffusion 420 is buffered by the source follower and appears on the signal line 30.

[0035] The comparator 60 compares the signal on the signal line 30 with the ramp signal output from the ramp generation circuit 50. The first memory 70 captures the count signal of the counter 90 at the timing when the comparator 60 inverts. This causes the signal from the pixel 10 to be AD converted. The digital signal from the first memory 70 is transferred to the second memory 80, and then output to the outside of the circuit board 150 via the logic circuits 230 and 232 and the IF (interface) circuits 240 and 242 in FIG. 2.

[0036] Although the present embodiment shows an example in which a common counter 90 is used for multiple circuits, a common count clock may be supplied and a counter may be provided for each circuit corresponding to each signal line. The technology of the present disclosure can also be applied to such a configuration.

[0037] Next, a description will be given of the supply of row selection signals from the row selection circuit 180 and the row selection circuit 200 to the pixel array 100. Fig. 6 is a schematic diagram showing the inter-substrate junction between the output circuit of the row selection circuit and the pixel substrate.

[0038] FIG. 6(a) shows a drive circuit 250 that outputs a pixel selection signal SEL, a drive circuit 260 that outputs a pixel transfer signal TX, a drive circuit 270 that outputs a pixel reset signal RES, and a drive circuit 280 that outputs a pixel gain switching signal FDINC, which are provided corresponding to one row of pixels 10.

[0039] Each output is supplied to the pixels 10 in a row of the pixel array 100 via inter-substrate junctions 290, 300, 310, and 320. The configuration shown in FIG. 6(a) is provided corresponding to one row of pixels 10, and this configuration is repeatedly arranged in each of the row selection circuits 180 and 200 corresponding to the number of pixel rows.

[0040] 6(b) shows the configuration of the drive circuit 270. The drive circuit 270 includes an N-type MOS transistor N and a P-type MOS transistor P. A voltage RESH, which is a power supply voltage, is supplied to one of the source and drain of the N-type MOS transistor N. The other of the source and drain of the N-type MOS transistor N is connected to one of the source and drain of the P-type MOS transistor P and the output node of the drive circuit 270.

[0041] A voltage RESL, which is another power supply voltage, is supplied to the other of the source and drain of the P-type MOS transistor P. A signal RESIN is input to the gates of the N-type MOS transistor N and the P-type MOS transistor P. When the signal RESIN is at a high level, a high-level signal having a signal level corresponding to the voltage value obtained by subtracting the threshold voltage of the N-type MOS transistor N from the voltage RESH is output as the control signal RES.

[0042] On the other hand, when the signal RESIN is at a low level, a low-level signal having a signal level corresponding to the voltage value obtained by subtracting the threshold voltage of the P-type MOS transistor P from the voltage RESL is output as the control signal RES. The other drive circuits 250, 260, and 280 also have a circuit configuration in which an N-type MOS transistor and a P-type MOS transistor are connected in series, similar to the drive circuit 270.

[0043] The output of the voltage generation circuit 500 in Fig. 2 is electrically connected to the row selection circuit 180 and the row selection circuit 200. As an example, it is electrically connected to RESL in Fig. 6. In this case, the plurality of functional elements to which the voltage RESL, which is the first voltage, is supplied are the plurality of drive circuits 270 and 280, respectively. In other words, the output of the voltage generation circuit 500 is a voltage corresponding to the low levels of the pixel reset signal RES and the pixel gain switching signal FDINC in Fig. 5.

[0044] In other words, the output of the voltage generating circuit 500 is used to generate signals that are input to the reset transistor and gain switching transistor of the pixel 10. In this way, by providing the voltage generating circuit 500 inside the circuit board 150, it is possible to reduce the number of voltage supply components that are provided outside the circuit board.

[0045] Furthermore, the low level of each signal output from the row selection circuits 180 and 200 to the pixel 10 may be a negative voltage. This negative voltage may be generated by a voltage generation circuit 500 provided inside the solid-state imaging device 1000. Specifically, the voltage RESL is set to a negative voltage in the range of −0.1 V to −1 V. This voltage RESL is generated by the voltage generation circuit 500. This voltage RESL is supplied to the row selection circuits 180 and 200 via a wiring section 510 external to the solid-state imaging device 1000. This allows the voltage RESL to be supplied with little potential fluctuation.

[0046] The voltage generating circuit 500 may be a circuit that generates only negative voltages. In this case, the positive voltages RESH, SELH, TXH, and FDINCH may be supplied from a voltage generating circuit provided outside the solid-state imaging device 1000.

[0047] 2, the voltage generation circuit 500 and the row selection circuit 200 are electrically connected using a wiring section 510 external to the solid-state imaging device 1000. Generally, the thickness of the wiring layer in the circuit board 150 is 0.1 μm to several μm, but the thickness of the internal wiring of the package that houses the solid-state imaging device 1000 is several hundred μm, so the sheet resistance of the wiring external to the solid-state imaging device 1000 is lower by two or more orders of magnitude. By making the connection as shown in FIG. 2, the impedance from the voltage generation circuit 500 to the row selection circuit 200 is reduced, and it is possible to suppress image quality degradation due to potential fluctuations in the wiring that supplies the power supply voltage (first voltage).

[0048] A comparative example is shown in Fig. 7. In Fig. 7, a second voltage generation circuit 501 is provided to supply a voltage to the row selection circuit 200. In this case, due to variations in the characteristics of the voltage generation circuit 500 and the second voltage generation circuit 501, the voltages supplied to the row selection circuits 180 and 200 do not completely match due to variations in the characteristics, etc. As a result, the voltages supplied to the pixels from the left and the voltages supplied to the pixels from the right do not match, which causes shading.

[0049] Another comparative example is shown in Fig. 8. In Fig. 8, voltage is supplied from the voltage generation circuit 500 to the row selection circuit 200 only through wiring sections inside the solid-state imaging device 1000, without going through wiring 510 external to the solid-state imaging device 1000. In this case, the long distance between the voltage generation circuit 500 and the row selection circuit 200 increases the parasitic resistance of the wiring that supplies the voltage, which can cause deterioration in image quality due to potential fluctuations.

[0050] In this embodiment, voltage is supplied to the row selection circuits 180 and 200 from the same voltage generation circuit 500, and the voltage is supplied to at least one of the row selection circuits 180 and 200 via wiring external to the solid-state imaging device 1000, thereby making it possible to suppress image quality degradation due to potential fluctuations in the lines supplying the voltage. Note that capacitance elements 520 and 521 provided outside the solid-state imaging device 1000 are connected to the wiring external to the solid-state imaging device 1000. In this way, it is possible to further suppress potential fluctuations in the wiring section 510 and suppress image quality degradation.

[0051] 9 shows a schematic diagram of an imaging module including a solid-state imaging device of this embodiment, viewed from above (in the normal direction to the light-receiving surface of the solid-state imaging device). In Fig. 9, a solid-state imaging device 1000 is composed of a pixel substrate 110 and a circuit board 150, and a resin frame 1010 is provided around the outer edge.

[0052] Fig. 10 is a cross-sectional view taken along line AA' in Fig. 9. As shown in Fig. 10, the imaging module 1100 has a transparent member 1020 and a printed circuit board 1030. The transparent member 1020 is fixed to the printed circuit board 1030 via a resin frame 1010. The imaging module 1100 also has bonding wires 1040 and 1060, and inner layer wiring 1050 as inner layer wiring of the printed circuit board 1030.

[0053] 2, the voltage output from the voltage generating circuit 500 is supplied again into the solid-state imaging device 1000 via the bonding wire 1040, inner layer wiring 1050, and bonding wire 1060 in FIG. 10, and is then supplied to the row selection circuit 200 in FIG. 2. Here, the wiring 510 outside the solid-state imaging device 1000 in FIG. 2 corresponds to the inner layer wiring 1050 in FIG. 10. Also, the bonding wire 5 in FIG. 3 corresponds to the bonding wires 1040 and 1060 in FIG. 10.

[0054] 10 shows an example in which inner layer wiring is used, but it is also possible to use surface layer wiring of the printed circuit board 1030. Also, in the example in Fig. 10, the inner layer wiring 1050 and the solid-state imaging device 1000 are arranged so as to have overlapping portions in a plan view seen from the top surface of the imaging module 1100, but this is not limiting.

[0055] However, by arranging the inner layer wiring 1050 so that it has overlapping portions in a plan view seen from the top of the solid-state imaging device 1000 and the imaging module 1100, the wiring path can be shortened. This reduces the impedance of the wiring that supplies voltage. When the semiconductor device is a solid-state imaging device, this is advantageous for suppressing image quality degradation. Even in semiconductor devices other than solid-state imaging devices, it is possible to suppress a decrease in the operational accuracy of functional elements to which voltage is supplied via wiring portions external to the semiconductor device.

[0056] Furthermore, the voltage generation circuit 500 may be provided on the pixel substrate 110. In this case, it is preferable to arrange the voltage generation circuit 500 on the same substrate as the row selection circuits 180 and 200. That is, when the row selection circuits 180 and 200 are provided on the pixel substrate 110, the voltage generation circuit 500 is also provided on the pixel substrate 110. Alternatively, when the row selection circuits 180 and 200 are provided on the circuit substrate 150, the voltage generation circuit 500 is also provided on the circuit substrate 150. In this way, the voltage generation circuit 500 can be electrically connected to the row selection circuits 180 and 200 without interposing a joint between the substrates.

[0057] In particular, it is preferable to arrange the voltage generating circuit 500 on the circuit board 150, as shown in FIG. 2. This simplifies the manufacturing process of the pixel substrate 110. Furthermore, heat caused by the operating power of the voltage generating circuit 500 is transmitted to the pixel array 100, which can cause shading in the image due to uneven heat. By arranging the voltage generating circuit 500 on the circuit board 150, it is possible to suppress shading caused by heat.

[0058] In the present embodiment, a structure including a pixel array and a circuit unit has been described by taking as an example a laminate in which a pixel substrate 110 and a circuit substrate 150 are laminated. However, the present invention is not limited to this example, and the solid-state imaging device 1000 may be a non-laminated structure in which the pixel array 100 shown in Fig. 1 and the functional blocks shown in Fig. 2 are provided on a single substrate.

[0059] (Second embodiment) 11 is a schematic diagram of a solid-state imaging device according to this embodiment. Only the differences from the first embodiment shown in FIG.

[0060] In this embodiment, there is only one row selection circuit 180. Voltage is supplied from the voltage generation circuit 500 to the row selection circuit 180 from two points, connection points a and b. By supplying voltage from two points in this manner, it is possible to suppress image quality degradation caused by the impedance of the wiring inside the row selection circuit 180.

[0061] 3, connection points a and b refer to portions that connect from a certain wiring layer to a wiring layer located relatively lower, or portions that contact the semiconductor layer of circuit board 150. Each of connection points a and b may include multiple contact points at one connection point, in which case the wiring layers are connected using multiple vias as contact points.

[0062] In addition, it is preferable that connection points a and b are provided near both ends of the plurality of row selection circuits 180, and that wiring is provided from connection points a and b to each row selection circuit from both ends of the plurality of row selection circuits 180 toward the center of the row selection circuit 180.

[0063] Furthermore, it is possible to reduce the impedance of the supply path and further suppress image quality degradation by supplying a voltage to the connection points a and b via the wiring section 510 external to the solid-state imaging device 1000. Therefore, it is preferable to supply a voltage to at least one of the connection points a and b via wiring external to the solid-state imaging device 1000.

[0064] Comparative examples are shown in Figures 12 to 14. In Figure 12, the voltage generation circuit 500 supplies voltage to the row selection circuit 180 from only one point, but in this case, image quality degradation due to the impedance of the wiring inside the row selection circuit 180 is likely to occur.

[0065] 13, voltages are supplied from two voltage generating circuits 500 and 501. In this case, the voltages supplied may differ due to variations in the characteristics of the voltage generating circuits 500 and 501. As a result, potential shading occurs in the vertical direction within the row selection circuit 180, which also causes deterioration in image quality.

[0066] In the comparative example of Figure 14, as in Figure 11, voltage is supplied from two locations from a single voltage generation circuit 500 to the row selection circuit 180, but because this is done via wiring 530 inside the solid-state imaging device 1000, image quality may deteriorate due to parasitic resistance of the wiring 530 inside the solid-state imaging device 1000.

[0067] As described above, by supplying voltage from a single voltage generation circuit 500 to two locations in the row selection circuit 180, and further supplying voltage to at least one of the locations via wiring external to the solid-state imaging device 1000, it is possible to suppress deterioration in image quality.

[0068] (Third embodiment) 15 is a schematic diagram of a solid-state imaging device according to this embodiment. Below, only the differences from FIG. 2 of the first embodiment will be described. This embodiment has three row selection circuits 180, 190, and 200. Furthermore, voltages are supplied to each of the row selection circuits 180, 190, and 200 from two locations via a wiring section 510 external to the solid-state imaging device 1000.

[0069] This configuration makes it possible to reduce the impedance of the voltage supply path to each of the row selection circuits 180, 190, and 200. In addition, by supplying voltage to each of the row selection circuits 180, 190, and 200 from two locations, it is also possible to reduce the influence of the wiring impedance inside each of the row selection circuits 180, 190, and 200.

[0070] (Fourth embodiment) In the first to third embodiments described above, the voltage is supplied from the voltage generating circuit 500 to the row selection circuit, but this is not limiting. For example, the voltage can be supplied to the ADC 220 as shown in Fig. 16. In this case, each of the multiple functional elements having the same function to which the first voltage is supplied is at least one of the current source 40, the comparator 60, the first memory 70, and the second memory 80 included in the circuit CRT of the ADC 220 shown in Fig. 4.

[0071] A functional element may be a combination of multiple circuit blocks. For example, in the case of a ground potential, the current source 40, the comparator 60, the first memory 70, and the second memory 80 may be supplied with the ground potential from a common wiring. In this case, each of the multiple functional elements having the same function and supplied with the ground potential as the first voltage may be the entire circuit CRT.

[0072] 16, the voltage generation circuit 500 supplies voltage to the multiple ADCs 220 from two locations, and one of the locations is supplied via wiring 510 external to the solid-state imaging device 1000. In this case, one of the two locations where the voltage is supplied is provided, for example, between the pad section 16 located on one end side of the solid-state imaging device 1000 and the ADC 220 located in the center of the multiple ADCs 220. One of the two locations where the voltage is supplied can be a via section that connects multiple layers of wiring that supply voltage to the ADCs 220.

[0073] Furthermore, it may be a via portion that is located within a range in which approximately 500 columns of ADCs 220 are provided as viewed from the pad portion 16 located on the one end side of the solid-state imaging device 1000, and that connects multiple layers of wiring that supply voltage to the ADCs 220. Similarly, the other of the two locations where voltage is supplied is provided, for example, between the pad portion 16 located on the other end side of the solid-state imaging device 1000 and the ADC 220 located in the center of the multiple ADCs 220. This other of the two locations where voltage is supplied may be a via portion that connects multiple layers of wiring that supply voltage to the ADCs 220.

[0074] Furthermore, it may be a via portion located within a range where approximately 500 rows of ADCs 220 are provided as viewed from the pad portion 16 located on the other end side of the solid-state imaging device 1000, and which connects multiple layers of wiring that supply voltage to the ADCs 220. It is preferably an ADC at both ends of the multiple ADCs 220, and is preferably wired to each ADC from both ends toward the center.

[0075] 4. This configuration can suppress potential fluctuations in the voltage supplied to the ADC 220, thereby suppressing degradation in the operation accuracy of the ADC 220.

[0076] 17, a voltage can also be supplied from a voltage generating circuit 500 to a pixel 10. In this case, for example, the voltage generating circuit 500 can supply a ground voltage supplied to a GND node 450 provided in the pixel 10 and a power supply voltage supplied to a power supply node 460 via a wiring unit 510. In this case, each of the multiple functional elements having the same function to which the first voltage is supplied corresponds to each of the multiple pixels 10.

[0077] 17, a power supply voltage is supplied from the voltage generating circuit 500 to the pixel substrate 110 via the inter-substrate junction 700. Furthermore, the power supply voltage is also supplied from the right side of the pixel substrate 110 via external wiring 510 and the inter-substrate junction 710 of the solid-state imaging device 1000. With this configuration, it is possible to suppress potential fluctuations in the voltage supplied to the pixel 10, and therefore, it is possible to suppress a decrease in the operational accuracy of the pixel 10.

[0078] The configuration of the solid-state imaging device is not limited to the above. For example, the number of signal lines 30 is not limited to one per pixel column, but may be two or more. A three-layer stack configuration is also possible. The pixel 10 is not limited to that shown in FIG. 5. For example, when there are multiple signal lines 30, a configuration having multiple selection transistors 440 is also possible. A configuration in which multiple photodiodes 400 share the floating diffusion 420 is also possible.

[0079] Although the above embodiments have been described focusing on solid-state imaging devices, the present disclosure can also be applied to storage devices equipped with memory (DRAM, SRAM, etc.). This is because one aspect of the technology of the present disclosure is that a structure has multiple functional elements and a voltage generation circuit that have the same functions, and the voltage generated by the voltage generation circuit is supplied to the multiple functional elements via wiring external to the structure. In a storage device, these multiple functional elements can be multiple memory cells, or they can be multiple drive elements included in a circuit unit that controls writing to or reading from these memory cells.

[0080] (Fifth embodiment) The fifth embodiment can be applied to any of the first to fourth embodiments. Fig. 18(a) is a schematic diagram illustrating a device 9191 equipped with a semiconductor device 930 of this embodiment. The imaging device of each of the above-mentioned embodiments can be used for the semiconductor device 930. The device 9191 equipped with the semiconductor device 930 will be described in detail.

[0081] As described above, the semiconductor device 930 can include a semiconductor device 910 having a semiconductor layer 10, as well as a package 920 that houses the semiconductor device 910. The package 920 can include a base to which the semiconductor device 910 is fixed, and a lid such as glass that faces the semiconductor device 910. The package 920 can further include bonding members such as bonding wires and bumps that connect terminals provided on the base to terminals provided on the semiconductor device 910.

[0082] The equipment 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a memory device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0083] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0084] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit provided in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0085] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operations.

[0086] Furthermore, the device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 990 in transportation equipment can be used as a moving device. The device 9191 as transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0087] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental impact, reducing costs, reducing size, and reducing weight.

[0088] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can also be improved. For example, by installing the semiconductor device 930 in a transport equipment, excellent performance can be obtained when photographing the exterior of the transport equipment or measuring the external environment. Therefore, when manufacturing and selling transport equipment, deciding to install the semiconductor device according to this embodiment in the transport equipment is advantageous in terms of improving the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0089] The photoelectric conversion system and the moving object of this embodiment will be described with reference to FIG.

[0090] 18(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 has a photoelectric conversion device 80. The photoelectric conversion device 80 is the imaging device described in any of the above embodiments.

[0091] The photoelectric conversion system 8 has an image processing unit 801 that performs image processing on the plurality of image data acquired by the photoelectric conversion device 80, and a parallax acquisition unit 802 that calculates parallax (phase difference between parallax images) from the plurality of image data acquired by the photoelectric conversion system 8. The photoelectric conversion system 8 also has a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance.

[0092] Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire distance information to an object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 804 may use any of this distance information to determine the possibility of a collision.

[0093] The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0094] The photoelectric conversion system 8 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, steering angle, etc. The photoelectric conversion system 8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The photoelectric conversion system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804.

[0095] For example, if the collision determination unit 804 determines that there is a high possibility of collision, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The warning device 830 warns the user by sounding an alarm or the like, displaying warning information on the screen of a car navigation system or the like, vibrating the seat belt or steering wheel, etc.

[0096] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 8. FIG. 18(c) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 850). A vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 8 or the photoelectric conversion device 80. This configuration can further improve the accuracy of distance measurement.

[0097] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, and control of automatic driving to prevent deviation from a lane. Furthermore, the photoelectric conversion system is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0098] The embodiments described above can be modified as appropriate within the scope of the technical concept. The disclosure of this specification includes not only what is described in this specification, but also all matters that can be understood from this specification and the drawings attached hereto.

[0099] Furthermore, the disclosure of this specification includes the complement of the concepts described in this specification. In other words, if this specification contains a statement that "A is greater than B," even if the statement that "A is not greater than B" is omitted, it can be said that this specification discloses that "A is not greater than B." This is because when a statement that "A is greater than B" is made, it is assumed that the case in which "A is not greater than B" is taken into consideration.

[0100] The disclosure of this embodiment includes the following configuration.

[0101] (Configuration 1) a structure including: a pixel array having a plurality of pixels arranged across a plurality of rows and a plurality of columns; a circuit unit that scans the plurality of pixels or processes signals output from the plurality of pixels; and a voltage generating circuit that generates a first voltage; a wiring portion provided outside the structure, The first voltage is supplied from the voltage generating circuit to the circuit section via the wiring section. A semiconductor device characterized by:

[0102] (Configuration 2) 2. The semiconductor device according to claim 1, wherein the structure has a connection portion for connection to the wiring portion.

[0103] (Configuration 3) The semiconductor device according to configuration 2, wherein the structure includes an insulating film, a recess is provided inside the insulating film, and the connection portion is a pad electrode provided inside the recess.

[0104] (Configuration 4) 4. The semiconductor device according to configuration 3, wherein the pad electrode is connected to a wiring containing a material mainly composed of gold.

[0105] (Configuration 5) 4. The semiconductor device according to configuration 3, wherein the pad electrode contains a material containing aluminum as a main component.

[0106] (Configuration 6) 3. The semiconductor device according to configuration 2, wherein the connection portion is a solder ball.

[0107] (Configuration 7) 7. The semiconductor device according to any one of configurations 1 to 6, wherein the circuit section includes a row selection circuit that selects pixels from which signals are to be read out from among the plurality of pixels on a row-by-row basis.

[0108] (Configuration 8) 8. The semiconductor device according to claim 1, wherein the voltage generating circuit supplies the first voltage to a plurality of the circuit sections.

[0109] (Configuration 9) the circuit unit is a circuit for scanning the plurality of pixels and includes a plurality of drive circuits for outputting signals for controlling the plurality of pixels; 9. The semiconductor device according to claim 1, wherein the voltage generating circuit supplies the first voltage to at least one of the plurality of drive circuits.

[0110] (Configuration 10) 10. The semiconductor device according to any one of configurations 1 to 9, comprising a capacitive element having a plurality of terminals, one of the plurality of terminals being supplied with the first voltage, and another of the plurality of terminals being supplied with a second voltage having a voltage value different from the first voltage, and the wiring portion being electrically connected to the one terminal.

[0111] (Configuration 11) 11. The semiconductor device according to any one of configurations 1 to 10, wherein the wiring portion has a portion that overlaps with the semiconductor device in a plan view from a normal direction to a light-receiving surface of the semiconductor device.

[0112] (Configuration 12) the structure includes a pixel substrate on which the pixel array is provided; a circuit board on which the circuit portion is provided, and a laminate in which the circuit portion and the circuit board are laminated. 12. The semiconductor device according to any one of configurations 1 to 11, characterized in that:

[0113] (Configuration 13) 13. The semiconductor device according to configuration 12, wherein the voltage generating circuit is provided on the circuit board.

[0114] (Configuration 14) 13. The semiconductor device according to configuration 12, wherein the circuit section is provided on the pixel substrate, and the voltage generating circuit is provided on the pixel substrate.

[0115] (Configuration 15) 13. The semiconductor device according to configuration 12, wherein the circuit section is provided on the circuit board, and the voltage generating circuit is provided on the circuit board.

[0116] (Configuration 16) 8. The semiconductor device according to configuration 7, wherein the circuit section includes a plurality of the row selection circuits.

[0117] (Configuration 17) the circuit unit includes a plurality of row selection circuits each configured to select pixels from which signals are to be read out from the plurality of pixels on a row-by-row basis; The pad electrodes are provided corresponding to the plurality of row selection circuits, respectively. 4. The semiconductor device according to configuration 3,

[0118] (Configuration 18) each of the plurality of pixels includes a photoelectric conversion unit that generates a signal charge, an amplification transistor having a first gate to which the signal charge is input, and a reset transistor that has a second gate and resets the first gate; 18. The semiconductor device according to any one of configurations 1 to 17, wherein the first voltage is used to generate a signal to be input to the second gate.

[0119] (Configuration 19) each of the plurality of pixels includes a photoelectric conversion unit that generates a signal charge; an amplification transistor having a first gate to which the signal charge is input; and a transistor that has a second gate and is connected to the first gate and changes a capacitance value connected to the first gate; 19. The semiconductor device according to any one of configurations 1 to 18, wherein the first voltage is used to generate a signal to be input to the second gate.

[0120] (Configuration 20) 20. The semiconductor device according to any one of configurations 1 to 19, wherein the first voltage is input to an AD converter that processes a signal from the pixel.

[0121] (Configuration 21) 21. The semiconductor device according to any one of configurations 1 to 20, wherein the first voltage is input as a power supply voltage for the pixel.

[0122] (Configuration 22) a structure including a pixel array having a plurality of pixels arranged across a plurality of rows and a plurality of columns, a circuit unit that scans the plurality of pixels, and a voltage generating circuit that generates a voltage; a wiring portion provided outside the structure, The voltage is supplied from the voltage generating circuit to the circuit unit via the wiring unit. A semiconductor device characterized by:

[0123] (Configuration 23) a structure including: a pixel array having a plurality of pixels arranged across a plurality of rows and a plurality of columns; a circuit unit for processing signals output from the plurality of pixels; and a voltage generating circuit for generating a voltage; a wiring portion provided outside the structure, The voltage is supplied from the voltage generating circuit to the circuit unit via the wiring unit. A semiconductor device characterized by:

[0124] (Configuration 24) a structure including a pixel array having a plurality of pixels arranged across a plurality of rows and a plurality of columns, and a voltage generating circuit that generates a first voltage; a wiring portion provided outside the structure, the first voltage is supplied from the voltage generating circuit to the pixel array via the wiring portion; A semiconductor device characterized by:

[0125] (Configuration 25) a structure including a plurality of functional elements each having the same function and a voltage generating circuit that generates a first voltage; a wiring portion provided outside the structure, The first voltage is supplied from the voltage generating circuit to the plurality of functional elements via the wiring portion. A semiconductor device characterized by:

[0126] (Configuration 26) An apparatus including the semiconductor device according to any one of configurations 1 to 25, an optical device corresponding to the semiconductor device; a control device for controlling the semiconductor device; a processing device that processes a signal output from the semiconductor device; a display device that displays information obtained by the semiconductor device; a storage device that stores information obtained by the semiconductor device; and and a mechanical device that operates based on information obtained by the semiconductor device. [Explanation of symbols]

[0127] 10 pixels 100 pixel array 150 Circuit Board 500 Voltage Generation Circuit 510 Wiring section

Claims

1. A structure comprising: a pixel array having multiple pixels arranged across multiple rows and multiple columns; a circuit unit that scans the multiple pixels or processes signals output from the multiple pixels; and a voltage generation circuit that generates a first voltage. The structure includes a wiring section provided on the outside of the aforementioned structure, The first voltage is supplied to the circuit section from the voltage generation circuit via the wiring section. The structure comprises a pixel substrate on which the pixel array is provided, The laminate has a circuit board on which the aforementioned circuit section is provided, and a laminate formed by stacking these components. A semiconductor device characterized by the following.

2. The structure has a connection portion for connecting to the wiring portion, The aforementioned connection portion includes a first connection portion, a second connection portion, and a third connection portion. The first voltage is supplied from the voltage generation circuit to the circuit section via the first connection section, the wiring section, and the second connection section in this order. The semiconductor device according to claim 1, characterized in that the first voltage is supplied from the voltage generation circuit to the circuit section via the first connection section, the wiring section, and the third connection section in this order.

3. The circuit section includes a first circuit and a second circuit. The aforementioned connection includes a fourth connection and a fifth connection, The first voltage is supplied from the voltage generation circuit to the first circuit via the first connection, the wiring, and the second connection in this order. The first voltage is supplied from the voltage generation circuit to the first circuit via the first connection, the wiring, and the third connection in this order. The first voltage is supplied from the voltage generation circuit to the second circuit via the first connection, the wiring, and the fourth connection in this order. The semiconductor device according to claim 2, characterized in that the first voltage is supplied from the voltage generation circuit to the second circuit via the first connection part, the wiring part, and the fifth connection part in this order.

4. The semiconductor device according to claim 3, characterized in that the voltage generation circuit is arranged between the first circuit and the second circuit in a plan view from the normal direction to the light-receiving surface of the semiconductor device.

5. The structure has a connection portion for connecting to the wiring portion, The semiconductor device according to claim 1, characterized in that the structure comprises an insulating film, a recess is provided inside the insulating film, and the connecting portion is a pad electrode provided inside the recess.

6. The semiconductor device according to claim 5, characterized in that the pad electrode is connected to wiring containing a material mainly composed of gold.

7. The semiconductor device according to claim 5, characterized in that the pad electrode contains a material mainly composed of aluminum.

8. The semiconductor device according to claim 1, characterized in that the circuit section includes a row selection circuit that selects pixels from the plurality of pixels to read out a signal, row by row.

9. The circuit section is a circuit for scanning the plurality of pixels and has a plurality of drive circuits that output signals to control the plurality of pixels. The semiconductor device according to claim 1, characterized in that the voltage generation circuit supplies the first voltage to at least one of the plurality of drive circuits.

10. The semiconductor device according to claim 1, comprising a capacitive element having a plurality of terminals, wherein one of the plurality of terminals is supplied with the first voltage, and another terminal of the plurality of terminals, which is supplied with a second voltage having a voltage value different from the first voltage, and the wiring portion is electrically connected to the one terminal.

11. The semiconductor device according to claim 1, characterized in that the wiring portion has a portion that overlaps with the semiconductor device when viewed in a plan view from the normal direction to the light-receiving surface of the semiconductor device.

12. The insulating film of the pixel substrate and the insulating film of the circuit board are in contact with each other. A semiconductor device according to claim 1, characterized by the above.

13. The semiconductor device according to claim 12, characterized in that a metal portion included in the insulating film of the pixel substrate and a metal portion included in the insulating film of the circuit board are in contact with each other.

14. The semiconductor device according to claim 12, characterized in that the voltage generation circuit is provided on the circuit board.

15. The semiconductor device according to claim 12, characterized in that the circuit section is provided on the pixel substrate and the voltage generation circuit is provided on the pixel substrate.

16. The semiconductor device according to claim 12, characterized in that the circuit section is provided on the circuit board and the voltage generation circuit is provided on the circuit board.

17. The semiconductor device according to claim 8, characterized in that the circuit section includes a plurality of row selection circuits.

18. The circuit section includes a plurality of row selection circuits, each having a configuration for selecting a pixel from the plurality of pixels on a row-by-row basis to read out a signal. The pad electrodes are provided in accordance with each of the plurality of row selection circuits. The semiconductor device according to claim 5, characterized in that

19. Each of the plurality of pixels includes a photoelectric conversion unit that generates a signal charge, an amplification transistor having a first gate to which the signal charge is input, and a reset transistor having a second gate that resets the first gate. The semiconductor device according to claim 1, characterized in that the first voltage is used to generate a signal input to the second gate.

20. Each of the plurality of pixels has a photoelectric conversion unit that generates a signal charge, an amplifying transistor having a first gate to which the signal charge is input, and a transistor having a second gate and connected to the first gate, which changes the capacitance value connected to the first gate. The semiconductor device according to claim 1, characterized in that the first voltage is used to generate a signal input to the second gate.

21. The semiconductor device according to claim 1, characterized in that the first voltage is input to an AD converter that processes signals from the pixels.

22. The semiconductor device according to claim 1, characterized in that the first voltage is input as the power supply voltage of the pixel.

23. A device comprising a semiconductor device according to any one of claims 1 to 22, Optical device corresponding to the aforementioned semiconductor device, Control device for controlling the aforementioned semiconductor device, A processing unit that processes the signal output from the aforementioned semiconductor device, A display device that displays information obtained by the aforementioned semiconductor device, A memory device for storing information obtained by the aforementioned semiconductor device, and The apparatus is characterized by further comprising at least one of the following: a semiconductor device, a mechanical device that operates based on information obtained from the semiconductor device.

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