Package and method for manufacturing the package

Abstract

A technology is provided that can efficiently form a groove that disables a temporary electrical path after electrolytic plating to electrically short-circuit multiple electrode parts for applying a current required for electrolytic plating in package manufacturing. [Solution] The insulator portion 720 of the frame portion FR has a bottom surface S3, an inner surface S1, a top surface S4, and an outer surface S2. The outer surface S2 includes a first region R1 spaced from the top surface S4 and a second region R2 located between the first region R1 and the top surface S4. The multiple electrode portions EL are spaced apart from one another on the outer surface S2, and include multiple first electrode portions EL1 and multiple second electrode portions EL2 located in the first region R1 and the second region R2 of the outer surface S2, respectively. The outer surface S2 of the insulator portion 720 is provided with a groove TR that separates the multiple first electrode portions EL1 from the multiple second electrode portions EL2. Each of the multiple electrode portions EL has an end that contacts the groove TR.

Description

[Technical Field]

[0001] The present disclosure relates to a package and a method for manufacturing the package, and more particularly to a package having a cavity for accommodating an electronic component and a method for manufacturing the same. [Background technology]

[0002] A wide variety of structures for housing electronic components have been disclosed.

[0003] For example, Japanese Patent Laid-Open Publication No. 2019-041072 (Patent Document 1) discloses a package having a base body with an upper surface including a recess and a frame surrounding the recess, at least a portion of the frame being an insulator, and a plurality of conductor layers located on the inner and outer surfaces of the frame in the insulator. An electronic component is housed in the recess and electrically connected to the conductor layers.

[0004] For example, Japanese Patent Application Laid-Open Publication No. 2002-231846 (Patent Document 2) discloses a semiconductor element storage substrate comprising an insulating substrate, a semiconductor element stored in a cavity on the upper surface of the insulating substrate, a lid joined to the upper surface of the insulating substrate to seal the semiconductor element, and a plurality of terminal electrodes formed on the bottom surface of the insulating substrate and electrically disconnected by an insulating groove. The plurality of terminal electrodes extend to the side surface of the insulating substrate, and the insulating groove is formed on the side surface of the insulating substrate. A plating layer is formed on the terminal electrodes by electroplating. At the time of electroplating, an electrically conductive portion short-circuits the plurality of terminal electrodes to simultaneously apply current to them. After electroplating, the short circuit is resolved by forming an insulating groove with a grinder.

[0005] For example, International Publication No. 2014 / 069123 (Patent Document 3) discloses a container for storing electronic components. It also discloses an application in which an electronic component storage container for use in a transmitter optical subassembly (TOSA) and an electronic component storage container for use in a receiver optical subassembly (ROSA) are arranged in close proximity. The electronic component storage container includes a container body in which electronic components are stored inside a recess formed by a bottom plate and side walls surrounding the center of the bottom plate in a polygonal shape, and a plurality of input / output terminals having conductors that electrically connect the inside and outside of the side walls. Among the conductors of the plurality of input / output terminals, a plurality of external terminals exposed from the insulator may be approximately parallel to the outer surface of the side walls. The plurality of external terminals may also be arranged in multiple rows, allowing for a high-density arrangement of the plurality of external terminals. A metal layer is deposited on the surfaces of the input / output terminals by plating for purposes such as preventing oxidation corrosion, improving wire bonding properties, reducing electrical resistance, and improving solderability. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2019-041072 [Patent Document 2] Japanese Patent Application Laid-Open No. 2002-231846 [Patent Document 3] International Publication No. 2014 / 069123 Summary of the Invention [Problem to be solved by the invention]

[0007] As disclosed in the above-mentioned International Publication No. 2014 / 069123, a plurality of external terminals (a plurality of electrode portions) coated with a metal layer by a plating method may be arranged in a plurality of rows. Typical plating methods include electroless plating and electrolytic plating. Electroless plating has disadvantages such as high cost and low adhesion strength of the plating layer. Therefore, it is often desirable to select electrolytic plating. To use electrolytic plating, as mentioned in the above-mentioned Japanese Patent Application Laid-Open No. 2002-231846, it is necessary to provide an electrical conductor (a temporary electrical path) that electrically shorts the plurality of terminal electrodes so that a current can be applied to them simultaneously during electrolytic plating, and to disable this temporary electrical path by forming a groove after electrolytic plating.

[0008] A method for efficiently performing the above-described disabling has not been fully explored to date when the electrodes are arranged in multiple rows, as disclosed in the above-mentioned International Publication No. 2014 / 069123, with the intention of increasing the density of the electrodes. Higher electrode density is increasingly required as packages become smaller and more highly integrated. For example, when integrating the above-mentioned TOSA and ROSA into a single small package, the number of electrodes required in one package increases and the area available for arranging the electrodes decreases, so there is a strong demand for higher electrode density. A TROSA does not have separate packages for the TOSA and ROSA, but has a package that houses both a group of circuit components for realizing the functions of the TOSA and a group of circuit components for realizing the functions of the ROSA.

[0009] The present disclosure has been made to solve the above-mentioned problems, and its purpose is to provide a technology that can efficiently form grooves that disable, after electrolytic plating, a temporary electrical path that electrically shorts multiple electrode portions for applying the current required for electrolytic plating in package manufacturing. [Means for solving the problem]

[0010] Aspect 1 is a package (801, 802) having a cavity (CV) for accommodating an electronic component (910, 920), the package comprising: a base portion (710) for supporting the electronic component (910, 920); and a frame portion (FR) attached to the base portion (710) and surrounding the cavity (CV) in an in-plane direction perpendicular to a thickness direction, the frame portion (FR) including an insulator portion (720), the insulator portion (720) having a bottom surface (S3) facing the base portion (710), an inner surface (S1) facing the cavity (CV), a top surface (S4) extending from the inner surface (S1) and opposite the bottom surface (S3), and an outer surface (S2) connecting the bottom surface (S3) and the top surface (S4), the outer surface (S2) being in contact with the top surface (S 4), and a second region (R2) located between the first region (R1) and the top surface (S4), and the package (801, 802) further comprises a plurality of electrode portions (EL) spaced apart from one another on the outer surface (S2) of the insulator portion (720), the plurality of electrode portions (EL) including a plurality of first electrode portions (EL1) and a plurality of second electrode portions (EL2) located in the first region (R1) and the second region (R2) of the outer surface (S2), respectively, and a groove (TR) is provided on the outer surface (S2) of the insulator portion (720) to separate the plurality of first electrode portions (EL1) and the plurality of second electrode portions (EL2), and each of the plurality of electrode portions (EL) has an end that contacts the groove (TR).

[0011] Aspect 2 is a package (801, 802) described in aspect 1, wherein the insulator portion (720) has a width dimension that is the dimension between the inner surface (S1) and the outer surface (S2) in the in-plane direction, and all of the grooves (TR) of the insulator portion (720) are located away from the position where the width dimension is smallest.

[0012] Aspect 3 is a package (801, 802) described in aspect 1 or 2, wherein the inner surface (S1) of the insulator portion (720) includes a first sidewall region (S1a), a second sidewall region (S1b), and a shelf-like region (S1c) connecting the first sidewall region (S1a) and the second sidewall region (S1b) to each other, the first sidewall region (S1a) is located between the shelf-like region (S1c) and the bottom surface (S3), the second sidewall region (S1b) is located between the shelf-like region (S1c) and the top surface (S4), and all of the grooves (TR) on the outer surface (S2) of the insulator portion (720) are located only between the shelf-like region (S1c) of the inner surface (S1) and the bottom surface (S3) in the thickness direction.

[0013] Aspect 4 is a package (801, 802) described in aspect 3, wherein at least one of the plurality of second electrode portions (EL2) is at least partially located between the shelf-like region (S1c) of the inner surface (S1) and the upper surface (S4) in the thickness direction.

[0014] Aspect 5 is a package (801, 802) described in any one of aspects 1 to 4, wherein the groove (TR) of the insulator portion (720) has a plurality of first portions (TR1) connecting the plurality of first electrode portions (EL1) and the plurality of second electrode portions (EL2) to each other, and a plurality of second portions (TR2) that are deeper than the first portions (TR1).

[0015] A sixth aspect is the package (801, 802) according to the fifth aspect, wherein the groove (TR) extends continuously so that the first portions (TR1) and the second portions (TR2) are alternately positioned.

[0016] A seventh aspect is a package (801) according to any one of the first to sixth aspects, wherein, with a direction along the outer surface (S2) of the insulator portion (720) among the in-plane directions as a length direction, each of the plurality of first electrode portions (EL1) has a first terminal portion (EL1a) and a first protruding portion (EL1b) protruding from the first terminal portion (EL1a) and having a width smaller than that of the first terminal portion (EL1a) in the length direction, and each of the plurality of second electrode portions (EL2) has a second terminal portion (EL2a) and a second protruding portion (EL2b) protruding from the second terminal portion (EL2a) and having a width smaller than that of the second terminal portion (EL2a) in the length direction. the plurality of first terminal portions (EL1a) include a pair of first terminal portions (EL1a) adjacent to each other in the length direction, the plurality of second terminal portions (EL2a) include a pair of second terminal portions (EL2a) adjacent to each other in the length direction, the plurality of second terminal portions (EL2a) include second terminal portions (EL2a) having portions facing each other in the thickness direction in a region on the outer surface between the pair of first terminal portions (EL1a), and the plurality of first terminal portions (EL1a) include first terminal portions (EL1a) having portions facing each other in the thickness direction in a region on the outer surface (S2) between the pair of second terminal portions (EL2a).

[0017] The eighth aspect is a package (811) having a cavity (CV) for accommodating an electronic component (910, 920), the package comprising: a base portion (710) for supporting the electronic component (910, 920); and a frame portion (FR) attached to the base portion (710) and surrounding the cavity (CV) in an in-plane direction perpendicular to the thickness direction, the frame portion (FR) including an insulator portion (720), the insulator portion (720) having a bottom surface (S3) facing the base portion (710) and a bottom surface (S4) facing the cavity (CV). The package has an inner surface (S1) facing the bottom surface (S3), an upper surface (S4) extending from the inner surface (S1) and opposite the bottom surface (S3), and an outer surface (S2) connecting the bottom surface (S3) and the upper surface (S4), wherein the outer surface (S2) includes a first region (R1) spaced apart from the upper surface (S4) and the bottom surface (S3), and a second region (R2) located between the first region (R1) and the upper surface (S4), and the package further includes a plurality of electrode portions (EL) spaced apart from each other on the outer surface (S2) of the insulator portion (720), The plurality of electrode portions (EL) include a first electrode portion (EL1) and a second electrode portion (EL2), and each of the plurality of second electrode portions (EL2) has a terminal portion (EL2a) and a protruding portion (EL2b) that protrudes from the terminal portion (EL2a) and has a width smaller than that of the terminal portion (EL2a) in the in-plane direction, and the plurality of first electrode portions (EL1) are located in the first region (R1) of the outer surface (S2), and the terminal portion (EL2a) of each of the plurality of second electrode portions (EL2) is located on the outer surface (S2). The protruding portion (EL2b) of each of the plurality of second electrode portions (EL2) crosses the first region (R1), a groove (TR) is provided on the outer surface (S2) of the insulator portion (720) to separate the bottom surface (S3) and the first region (R1), each of the plurality of first electrode portions (EL1) has an end that contacts the groove (TR), and the protruding portion (EL2b) of each of the plurality of second electrode portions (EL2) has an end that contacts the groove (TR).

[0018] Aspect 9 is a package (811) described in aspect 8, wherein the insulator portion (720) has a width dimension that is the dimension between the inner surface (S1) and the outer surface (S2) in the in-plane direction, and all of the grooves (TR) of the insulator portion (720) are located away from the position where the width dimension is smallest.

[0019] Aspect 10 is a package (811) described in aspect 8 or 9, wherein the inner surface (S1) of the insulator portion (720) includes a first sidewall region (S1a), a second sidewall region (S1b), and a shelf-like region (S1c) connecting the first sidewall region (S1a) and the second sidewall region (S1b) to each other, the first sidewall region (S1a) is located between the shelf-like region (S1c) and the bottom surface (S3), the second sidewall region (S1b) is located between the shelf-like region (S1c) and the top surface (S4), and all of the grooves (TR) on the outer surface (S2) of the insulator portion (720) are located only between the shelf-like region (S1c) of the inner surface (S1) and the bottom surface (S3) in the thickness direction.

[0020] Aspect 11 is a package (811) described in aspect 10, wherein at least a portion of the terminal portion (EL2a) of each of the second electrode portions (EL2) is located between the shelf-like region (S1c) of the inner surface (S1) and the upper surface (S4) in the thickness direction.

[0021] Aspect 12 is a package (811) described in any one of aspects 8 to 11, wherein the groove (TR) of the insulator portion (720) has a first edge (DG1) that contacts the end of each of the multiple first electrode portions (EL1) and the end of the protruding portion (EL2b) of each of the multiple second electrode portions (EL2), and a second edge (DG2) opposite the first edge (DG1) that is located between the first edge (DG1) and the bottom surface (S3) of the insulator portion (720), and the groove (TR) has multiple first portions (TR1) that connect the multiple electrode portions (EL) to the second edge (DG2) and multiple second portions (TR2) that are deeper than the first portions (TR1).

[0022] Aspect 13 is a package (811) according to aspect 12, wherein the groove (TR) extends continuously so that the plurality of first portions (TR1) and the plurality of second portions (TR2) are alternately positioned.

[0023] Aspect 14 is a package manufacturing method for manufacturing a package (801, 802, 811) described in any one of aspects 1 to 13, and includes the steps of forming an electrode pattern (EP) including portions that will become the multiple electrode portions (EL) on the outer surface (S2) of the insulator portion (720), applying electrolytic plating to the electrode pattern (EP), and performing laser processing to partially remove the electrode pattern (EP) so as to form the multiple electrode portions (EL), and the groove (TR) is formed on the outer surface (S2) of the insulator portion (720) by the laser processing.

[0024] It should be noted that the reference numerals in parentheses in the description of each embodiment above are used to facilitate understanding of each embodiment, and do not limit the present invention. [Effects of the Invention]

[0025] According to one aspect of the present disclosure, it is possible to efficiently form grooves that disable a temporary electrical path that electrically shorts a plurality of electrodes for applying a current required for electrolytic plating in package manufacturing after electrolytic plating, thereby improving package manufacturing efficiency. [Brief explanation of the drawings]

[0026] [Figure 1] FIG. 1 is a plan view schematically showing the configuration of a TROSA according to a first embodiment. [Figure 2] 2 is a cross-sectional view showing the configuration of the TROSA of FIG. 1 in a cross section perpendicular to the width direction. FIG. [Figure 3] FIG. 2 is a side view schematically showing the configuration of the TROSA of FIG. [Figure 4] 1 is a cross-sectional view schematically showing the configuration of a package in accordance with a first embodiment, taken along a cross section perpendicular to the width direction. [Figure 5] 5 is a cross-sectional view schematically showing the configuration of the package of FIG. 4 in a cross section perpendicular to the length direction. [Figure 6] FIG. 5 is a side view schematically showing the configuration of the package of FIG. 4. [Figure 7] FIG. 7 is an enlarged partial side view of a part of FIG. 6. [Figure 8] FIG. 5 is a flow chart schematically showing a method for manufacturing the package of FIG. [Figure 9] FIG. 9 is a side view schematically showing one step in FIG. 8. [Figure 10] FIG. 9 is a side view schematically showing one step in FIG. 8. [Figure 11] FIG. 9 is a side view schematically showing one step in FIG. 8. [Figure 12] FIG. 10 is a side view schematically illustrating the configuration of a package of a comparative example. [Figure 13] 13 is a cross-sectional view schematically showing the configuration of the package of FIG. 12 in a cross section perpendicular to the length direction. [Figure 14] 13 is a side view schematically showing a step in the method of manufacturing the package of FIG. 12. FIG. [Figure 15] 8 is a partial side view schematically showing the configuration of a package in a modified example of the first embodiment, in the same field of view as FIG. 7. FIG. [Figure 16] FIG. 10 is a side view schematically showing the configuration of a package in a second embodiment. [Figure 17] FIG. 17 is an enlarged partial side view of a part of FIG. 16. [Figure 18] 17 is a side view schematically showing a step in the method of manufacturing the package of FIG. 16. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0027] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that an XYZ Cartesian coordinate system is shown in some of the drawings to facilitate understanding of the relative directional relationships between the drawings. The X, Y, and Z directions in the drawings correspond to the length, width, and thickness directions in the specification, respectively. The XY in-plane directions in the drawings correspond to the in-plane directions in the specification. The terms "upper" and "lower" in the specification are used to distinguish relative directions, and do not imply limitations related to the direction of gravity unless otherwise specified. The upper and lower directions correspond to the positive and negative directions of the Z axis in the drawings, respectively. Furthermore, in the specification, a statement that member L is located between member M and member N in direction A means that the coordinates of each of members L to N in direction A are expressed as P. L ~P N When the coordinate P L is the coordinate P M and coordinate P N In other words, when only the coordinates in direction A are considered, member L is located between member M and member N.

[0028] <First Embodiment> Fig. 1 is a plan view schematically showing the configuration of TROSA 1000 (electronic device) in embodiment 1. Fig. 2 is a cross-sectional view schematically showing the configuration of TROSA 1000 in a cross section perpendicular to the width direction. Fig. 3 is a side view schematically showing the configuration of TROSA 1000.

[0029] The TROSA 1000 includes a package having a frame FR surrounding a cavity CV containing a transmitter 910 (electronic component), a receiver 920 (electronic component), and the cavity CV, and a lid 990 sealing the cavity CV. The transmitter 910 includes a group of circuit components so as to function as a TOSA. The receiver 920 includes a group of circuit components so as to function as a ROSA. The package 801 includes opposite end surface portions SEo and SEr, and opposite side surface portions SSt and SSr.

[0030] Optical connectors CNo and CNi are provided on the end surface portion SEo. The optical connector CNo is for outputting an optical signal from the transmitting unit 910. The optical connector CNi is for inputting an optical signal to the receiving unit 920. The optical connectors CNo and CNi are also collectively referred to as the optical connector CN. The end surface portion SEr is provided with an RF terminal ERi and an RF terminal ERo. The RF terminal ERi is for inputting an RF signal representing transmission data to the transmitting unit 910. The RF terminal ERo is for outputting an RF signal representing reception data from the receiving unit 920. The RF terminals ERi and ERo are also collectively referred to as the RF terminal ER.

[0031] The side surface portion SSt is provided with a plurality of terminals TDt for inputting and outputting DC signals related to the control of the transmitter 910. The plurality of terminals TDt may include power supply terminals for the transmitter 910. The side surface portion SSr is provided with a plurality of terminals TDr for inputting and outputting DC signals related to the control of the receiver 920. The plurality of terminals TDr may include power supply terminals for the receiver 920.

[0032] The package 801 has electrical wirings WIt, WIr, WIi, and WIo for interconnecting the outside and inside of the package 801. Each of the electrical wirings WIt, WIr, WIi, and WIo extends to penetrate the insulator portion 720 of the frame portion FR of the package 801. The electrical wirings WIi and WIo may be connected to a wiring portion 930 (FIG. 2) arranged in the cavity CV. Furthermore, the electrical wirings WIt and WIr may be connected to a wiring portion ET (see FIG. 5, described later) arranged in the cavity CV.

[0033] The receiving unit 920 (FIG. 2) includes a photoelectric conversion element 921 (semiconductor element) that converts optical signals into electrical signals, and an optical system OS. The receiving unit 920 may also include an element 922 (e.g., a semiconductor element such as an amplifier element) associated with the photoelectric conversion element 921, and a spacer 923 for aligning the optical axes between the photoelectric conversion element 921 and the optical system OS. The photoelectric conversion element 921, the element 922, and the wiring unit 930 are electrically connected by bonding wires 950 (electrical wiring). The receiving unit 920 and the wiring unit ET (see FIG. 5, described later in detail) may also be electrically connected by bonding wires (not shown). The transmitting unit 910 has a similar configuration. However, the photoelectric conversion element of the transmitting unit 910 is for converting electrical signals into optical signals. The spacer in the transmitting unit 910 typically includes a cooling element such as a Peltier element.

[0034] FIG. 4 is a cross-sectional view schematically showing the configuration of package 801 in a cross section perpendicular to the width direction. FIG. 5 is a cross-sectional view schematically showing the configuration of package 801 in a cross section perpendicular to the length direction. FIG. 6 is a side view schematically showing the configuration of package 801, specifically, a view showing the side surface portion SSr (FIG. 1). FIG. 7 is a partial side view showing an enlarged portion of FIG. 6. Note that in FIG. 7, a dot pattern is added to the electrode portion EL to make the drawing easier to see. Furthermore, the configuration of the side surface portion SSt (FIG. 1) of the package roughly corresponds to the configuration shown in the mirror image of FIGS. 6 and 7, and therefore is not shown.

[0035] The package 801 (FIG. 5) has a cavity CV for accommodating a transmitter 910 and a receiver 920. Therefore, the package 801 is a package for optical communications, or more broadly, a package for a semiconductor device. The package 801 includes a base portion 710, a frame portion FR, and a plurality of electrode portions EL.

[0036] The base portion 710 supports the transmitter 910 and the receiver 920. The base portion 710 may be made of metal, thereby improving heat dissipation. In other words, it can efficiently remove heat from the electronic components housed in the cavity CV. In particular, when the transmitter 910 is housed as an electronic component as in the first embodiment, a large amount of heat is generated therefrom, so the base portion 710 is required to have high heat dissipation properties. The metal of the base portion 710 may contain Cu, thereby improving heat dissipation. The metal of the base portion 710 may also contain a high-melting-point metal, such as W and / or Mo, which suppresses thermal expansion of the base portion 710 and thereby improves sealing reliability. The metal of the base portion 710 may contain, for example, both Cu and the high-melting-point metal, or may be essentially Cu.

[0037] The frame portion FR is attached to the base portion 710 and surrounds the cavity CV in an in-plane direction perpendicular to the thickness direction (an XY in-plane direction perpendicular to the Z direction). The frame portion FR includes an insulator portion 720. The insulator portion 720 is made of ceramic. The ceramic may be mainly composed of alumina. The ceramic may also include a glass component, such as Si oxide and / or Mn oxide. The frame portion FR may further include a metal portion 730.

[0038] The insulator portion 720 (FIG. 5) has an inner surface S1, an outer surface S2, a bottom surface S3, and a top surface S4 on each of the side surface SSt and side surface SSr of the package 801. The bottom surface S3 faces the base portion 710. A metallization layer 781 is formed on the bottom surface S3, and the metallization layer 781 and the base portion 710 may be joined with a brazing material (not shown). The inner surface S1 faces the cavity CV. The top surface S4 extends from the inner surface S1 and is opposite the bottom surface S3. A metallization layer 782 is formed on the top surface S4, and a lid 990 will be joined onto the metallization layer 782. The lid 990 (FIG. 2) may be attached onto a seal ring (not shown) that was previously attached to the metallization layer 782. The outer surface S2 connects the bottom surface S3 and the top surface S4. The outer surface S2 (FIG. 6) includes a first region R1 spaced from the upper surface S4 and a second region R2 located between the first region R1 and the upper surface S4.

[0039] The package 801 is provided with a plurality of electrode portions EL as terminals TDr (FIG. 1) provided on the side surface portion SSr. The plurality of electrode portions EL are arranged on the outer surface S2 of the insulator portion 720 and are spaced apart from one another on the outer surface S2. The plurality of electrode portions EL include a plurality of first electrode portions EL1 and a plurality of second electrode portions EL2 located in a first region R1 and a second region R2 of the outer surface S2, respectively. The plurality of first electrode portions EL1 may be arranged along the X direction on the first region R1. Similarly, the plurality of second electrode portions EL2 may be arranged along the X direction on the second region R2. Note that, as terminals TDt (FIG. 1) provided on the side surface portion SSt, a plurality of electrode portions EL are provided on the outer surface S2 opposite to the outer surface S2 shown in FIG. 3.

[0040] Each of the multiple first electrode portions EL1 may have a first terminal portion EL1a and a first protruding portion EL1b. The first protruding portion EL1b protrudes from the first terminal portion EL1a on the outer surface S2. The first protruding portion EL1b has a smaller width in the length direction (X direction) than the first terminal portion EL1a. Similarly, each of the multiple second electrode portions EL2 may have a second terminal portion EL2a and a second protruding portion EL2b. The second protruding portion EL2b protrudes from the second terminal portion EL2a on the outer surface S2. The second protruding portion EL2b has a smaller width in the length direction (X direction) than the second terminal portion EL2a. The length direction (X direction) is the direction along the outer surface S2 of the insulator portion 720 within the XY plane. The first protruding portion EL1b protrudes toward the second electrode portion EL2, and the second protruding portion EL2b protrudes toward the first electrode portion EL1.

[0041] The outer surface S2 of the insulator portion 720 is provided with a groove TR (FIG. 6) that separates the plurality of first electrode portions EL1 and the plurality of second electrode portions EL2. In the example shown in FIG. 6, the groove TR on the outer surface S2 is a single groove that extends continuously along a straight line perpendicular to the Z direction. Each of the plurality of electrode portions EL (FIG. 7) has an end that contacts the groove TR. In the example shown in FIG. 7, the end is the end of the first protruding portion EL1b for the first electrode portion EL1 and the end of the second protruding portion EL2b for the second electrode portion EL2.

[0042] The insulator portion 720 has a width dimension (horizontal dimension in FIG. 5) that is the dimension between the inner surface S1 and the outer surface S2 in the XY plane. All of the grooves TR of the insulator portion 720 may be positioned away from the position where the width dimension is minimum. Furthermore, the grooves TR of the insulator portion 720 may be positioned where the width dimension is maximum.

[0043] The inner surface S1 (FIG. 5) of the insulator portion 720 may include a first sidewall region S1a, a second sidewall region S1b, and a shelf-like region S1c connecting the first sidewall region S1a and the second sidewall region S1b. The first sidewall region S1a is located between the shelf-like region S1c and the bottom surface S3. The second sidewall region S1b is located between the shelf-like region S1c and the top surface S4. The shelf-like region S1c is approximately parallel to the XY in-plane direction. Each of the first sidewall region S1a and the second sidewall region S1b is approximately perpendicular to the XY in-plane direction. Each of the first sidewall region S1a and the second sidewall region S1b is approximately parallel to the ZX plane. The shelf-like region S1c is a region for providing the wiring portion ET. All of the grooves TR on the outer surface S2 of the insulator portion 720 may be located only between the shelf region S1c of the inner surface S1 and the bottom surface S3 in the thickness direction (Z direction), with the upper surfaces of the grooves TR not coinciding with the shelf region S1c and the lower surfaces of the grooves TR not coinciding with the bottom surface S3.

[0044] Dimensions related to the package 801 are exemplified below. Referring to FIG. 5, the width dimension (dimension in the Y direction) between the outer surface S2 of the insulator portion 720 and the second sidewall region S1b is 0.5 mm or more and 2 mm or less. The width dimension between the first sidewall region S1a and the second sidewall region S1b of the insulator portion 720, in other words, the width dimension of the shelf-like region S1c, is 0.5 mm or more and 2 mm or less. The thickness dimension (dimension in the Z direction) of the package 801 is 4 mm or more and 5 mm or less. The width dimension between one outer surface S2 of the insulator portion 720 and the opposite outer surface S2 is 5 mm or more and 30 mm or less. Referring to FIG. 4, ignoring the optical connector CN and the base portion 710, the length dimension (dimension in the X direction) of the package 801 is 10 mm or more and 40 mm or less.

[0045] At least one of the plurality of second electrode portions EL2 may be at least partially located between the shelf region S1c of the inner surface S1 and the upper surface S4 in the thickness direction (Z direction). Furthermore, at least one of the plurality of second electrode portions EL2 may be located partially, but not entirely, between the shelf region S1c of the inner surface S1 and the upper surface S4 in the thickness direction (Z direction). For example, the upper portion of the second electrode portion EL2 illustrated in FIG. 5 is located between the shelf region S1c of the inner surface S1 and the upper surface S4 in the Z direction. Furthermore, each of the plurality of second electrode portions EL2 may be at least partially located between the shelf region S1c of the inner surface S1 and the upper surface S4 in the thickness direction (Z direction). Furthermore, each of the plurality of second electrode portions EL2 may be located partially, but not entirely, between the shelf region S1c of the inner surface S1 and the upper surface S4 in the thickness direction (Z direction).

[0046] The groove TR (FIG. 7) of the insulator portion 720 has a plurality of first portions TR1 that connect the plurality of first electrode portions EL1 and the plurality of second electrode portions EL2 to each other, and a plurality of second portions TR2 that are deeper than the first portions TR1. Note that the depth of the groove TR corresponds to the dimension in the Y direction in FIG. 7. The groove TR may extend continuously so that the plurality of first portions TR1 and the plurality of second portions TR2 are positioned alternately.

[0047] The plurality of first terminal portions EL1a include a pair of first terminal portions EL1a adjacent to each other in the length direction (X direction) (for example, a pair of first terminal portions EL1a sandwiching an interval N1 in FIG. 7). Similarly, the plurality of second terminal portions EL2a include a pair of second terminal portions EL2a adjacent to each other in the length direction (X direction) (for example, a pair of second terminal portions EL2a sandwiching an interval N2 in FIG. 7). The plurality of first terminal portions EL1a include a first terminal portion EL1a (the left first terminal portion EL1a in FIG. 7) having portions facing each other in the thickness direction (Z direction) in a region between the pair of second terminal portions EL2a on the outer surface S2. Similarly, the plurality of second terminal portions EL2a include a second terminal portion EL2a (the second terminal portion EL2a located at the center in the lateral direction in FIG. 7) having portions facing each other in the thickness direction (Z direction) in a region between the pair of first terminal portions EL1a on the outer surface S2.

[0048] The first terminal portions EL1a may include portions on the outer surface S2 that face the second terminal portions EL2a in the thickness direction (Z direction). Similarly, the second terminal portions EL2a may include portions on the outer surface S2 that face the first terminal portions EL1a in the thickness direction (Z direction).

[0049] The insulator portion 720 (FIG. 4) of the frame portion FR has an inner surface S5 and an outer surface S6 at the end surface SEr of the package 801. The inner surface S5 faces the cavity CV. The outer surface S6 connects the bottom surface S3 and the top surface S4.

[0050] The inner surface S5 may include a sidewall region S5a, a sidewall region S5b, and a shelf-like region S5c connecting the sidewall regions S5a and S5b. The sidewall region S5a is located between the shelf-like region S5c and the bottom surface S3. The sidewall region S5b is located between the shelf-like region S5c and the top surface S4. The shelf-like region S5c is approximately parallel to the XY in-plane direction. Each of the sidewall regions S5a and S5b is approximately perpendicular to the XY in-plane direction. Each of the sidewall regions S5a and S5b is approximately parallel to the ZX plane. The shelf-like region S5c is a region for arranging the wiring portion 930.

[0051] The outer surface S6 may include a sidewall region S6a, a sidewall region S6b, and a shelf-like region S6c connecting the sidewall regions S6a and S6b. The sidewall region S6a is located between the shelf-like region S6c and the bottom surface S3. The sidewall region S6b is located between the shelf-like region S6c and the top surface S4. The shelf-like region S6c is approximately parallel to the XY plane. Each of the sidewall regions S6a and S6b is approximately perpendicular to the XY plane. Each of the sidewall regions S6a and S6b is also approximately parallel to the ZX plane. The RF terminal ER may be disposed on the shelf-like region S6c. The RF terminal ER and the wiring portion 930 are electrically connected to each other by electrical wirings WIi and WIo (see FIG. 1) that penetrate the insulator portion 720.

[0052] The metal portion 730 (FIG. 4) of the frame portion FR is disposed on the end surface portion SEo of the package 801. Referring to FIG. 6, a metallized layer 783 is formed on the end surface of the insulator portion 720 facing the metal portion 730. The metal portion 730 and the metallized layer 783 may be joined by a brazing material (not shown). Also referring to FIG. 4, the metal portion 730 and the base portion 710 may be joined by a brazing material (not shown). The metal portion 730 may be provided with a through hole for the optical connector CN (FIG. 1). In the example shown in FIG. 4, the optical connector CN is attached to the through hole. The optical connector CN may have a metal pipe 731 attached to the through hole. The optical connector CN may further have a light-transmitting member 732 that closes the through hole together with the metal pipe 731.

[0053] Fig. 8 is a flow diagram that schematically shows a manufacturing method for manufacturing the package 801. Figs. 9 to 11 are side views that schematically show steps in the manufacturing method.

[0054] 9, in step P10 (FIG. 8), insulator section 720 is formed. Electrical wirings WIt, WIr, WIi, and WIo (see FIG. 1) are provided inside insulator section 720. In this manner, a configuration including an insulator section and electrical wirings disposed therein can be formed using, for example, known multilayer ceramic technology.

[0055] Referring to FIG. 10, in step P20 (FIG. 8), an electrode pattern EP is formed on the outer surface S2 of the insulator portion 720. The electrode pattern EP may have a plurality of first terminal portions EL1a, a plurality of second terminal portions EL2a, and a plurality of bridge portions ELb between the plurality of first terminal portions EL1a and the plurality of second terminal portions EL2a. Referring to FIG. 7, the bridge portions ELb (FIG. 10) may have portions that will remain as the first protruding portions EL1b and the second protruding portions EL2b, and portions that will be removed as the first portions TR1 of the grooves TR. Each bridge portion ELb (FIG. 10) may extend on the outer surface S2 along an imaginary straight line that is parallel to the thickness direction (Z direction). In this case, a pair of first protruding portions EL1b and second protruding portions EL2b formed from each bridge portion ELb will also extend on the outer surface S2 along the imaginary straight line. The electrode pattern EP may be formed by printing an electrode paste on the outer surface S2 of the insulator portion 720 and then firing the printed electrode paste. An electrode pattern similar to the electrode pattern EP may also be formed on the outer surface S2 opposite to the outer surface S2 shown in FIG. 10. The RF terminal ER and the metallization layers 781-783 may also be formed by a similar method. As a modified example, one or more of the components described herein may be formed by firing simultaneously with the firing process for forming the insulator portion 720. In this modified example, the metallization layers 781-783 may be formed separately after the firing process. Of the above-mentioned electrode paste, at least the portion in contact with the insulator portion 720 may be a mixed paste of metal and ceramic.

[0056] 10, the electrode pattern EP may be a single pattern. In other words, the single pattern may include the plurality of first terminal portions EL1a, the plurality of second terminal portions EL2a, and the plurality of bridge portions ELb. As a result, under a design in which at least one of the plurality of first terminal portions EL1a, EL2a is at the reference potential of the package 801 (FIG. 6) (ground potential in the operating state of the TROSA1000 (FIG. 2)), the electrode pattern EP has the reference potential. As a modified example, a plurality of electrode patterns EP having the reference potential may be formed.

[0057] Referring to FIG. 11, in step P30 (FIG. 8), the base portion 710 and the optical connector CN are attached. This attachment is performed by brazing, for example. Through the steps up to this point, a work-in-progress 801L immediately prior to the electrolytic plating step is obtained. As a variant, the base portion 710 may be a sintered body, in which case an unsintered member that will become the insulator portion 720 and an unsintered member that will become the base portion 710 may be stacked and then fired simultaneously. The two unsintered members may be stacked directly on top of each other, or may be stacked via a mixed paste of metal and ceramic.

[0058] In step P40 (FIG. 8), electrolytic plating is applied to the work-in-progress 801L. Specifically, while the work-in-progress 801L is immersed in a plating solution, a voltage is applied to a portion of the work-in-progress 801L that has a reference potential. Typically, an electrode pin for applying the voltage is brought into contact with the base portion 710, which is a member having a reference potential. As described above, since the electrode pattern EP has a reference potential, this voltage application causes electrolytic plating to be applied to the electrode pattern EP. At the same time, electrolytic plating is also applied to the metallized layers 781-783 and the metal pipe 731, which have the reference potential. As the plating process, for example, Ni plating is first performed, followed by Au plating or PdAu plating.

[0059] Referring also to FIG. 6, after the above-described electrolytic plating, in step P50 (FIG. 8), laser processing is performed to partially remove the electrode pattern EP (FIG. 11) so as to form a plurality of electrode portions EL (FIG. 6). Specifically, grooves TR are formed in the outer surface S2 of the insulator portion 720 by laser processing. Similar laser processing is performed on the outer surface S2 opposite to the outer surface S2. This results in the package 801 (FIG. 6).

[0060] Fig. 12 is a side view schematically showing the configuration of a comparative example package 800. Fig. 13 is a cross-sectional view schematically showing the configuration of package 800 in a cross section perpendicular to the longitudinal direction. Fig. 14 is a side view schematically showing a work-in-progress 800L immediately before the electrolytic plating step in the manufacturing method of package 800.

[0061] 14, work-in-progress 800L is provided with protruding portions EW1 as electrical paths extending from each of the plurality of first terminal portions EL1a to the metallized layer 781, and protruding portions EW2 as electrical paths extending from each of the plurality of second terminal portions EL2a to the metallized layer 782. With this configuration, the potentials of the plurality of first terminal portions EL1a, the plurality of second terminal portions EL2a, the plurality of protruding portions EW1, and the plurality of protruding portions EW2 are set to the reference potential. Therefore, electrolytic plating can be applied to these members.

[0062] 12 and 13, after the electrolytic plating, laser processing is performed to form a plurality of first electrode portions EL1 and a plurality of second electrode portions EL2. Specifically, grooves TRA and TRB are formed in the outer surface S2 of the insulator portion 720 by laser processing. The grooves TRA separate each of the protruding portions EW1 (FIG. 14) into a first protruding portion EL1b from the first terminal portion EL1a and a protruding portion EW1 from the metallization layer 781. The grooves TRB separate each of the protruding portions EW2 (FIG. 14) into a second protruding portion EL2b from the second terminal portion EL2a and a protruding portion EW2 from the metallization layer 782. Similar laser processing is performed on the outer surface S2 opposite to the outer surface S2 shown in FIG. 14. This results in a package 800.

[0063] 12, the comparative example requires laser processing to form grooves TRA and TRB in the upper and lower regions of outer surface S2 that are separated by first electrode portion EL1 and second electrode portion EL2. This laser processing is more complicated than the laser processing in the first embodiment, which only requires forming grooves TR (FIG. 6).

[0064] Fig. 15 is a partial side view showing the configuration of a package 802 which is a modification of the package 801 (Fig. 7) in the first embodiment. In Fig. 15, a dot pattern is added to the electrode portion EL to make the drawing easier to see. In this modification, unlike the package 801 (Fig. 7), a plurality of first terminal portions EL1a and a plurality of second terminal portions EL2a face each other exactly along the Z direction.

[0065] According to the package 801 of the first embodiment, referring to FIG. 10, a temporary electrical path for electrically shorting the plurality of electrode portions EL is disposed between the plurality of first electrode portions EL1 and the plurality of second electrode portions EL2 on the outer surface S2 of the insulator portion 720 to apply a current required for electrolytic plating during the manufacture of the package 801. Referring to FIG. 6, after electrolytic plating, grooves TR are formed separating the plurality of first electrode portions EL1 and the plurality of second electrode portions EL2, thereby cutting the electrical path and eliminating the short-circuit state. In this case, the grooves TR need to be formed only between the plurality of first electrode portions EL1 and the plurality of second electrode portions EL2, so the grooves TR can be formed efficiently. This improves the manufacturing efficiency of the package 801.

[0066] Furthermore, the adjacent first electrode portion EL1 and second electrode portion EL2 are separated by a groove TR, which prevents the solder on the first electrode portion EL1 and the solder on the second electrode portion EL2 from unintentionally connecting to each other when external wiring is soldered to each of the first electrode portion EL1 and the second electrode portion EL2.

[0067] Furthermore, unlike the second embodiment described below, there is no need to provide a second protruding portion EL2b (FIG. 17: second embodiment) between adjacent first electrode portions EL1 on the outer surface S2. This prevents the solder on adjacent first electrode portions EL1 from unintentionally connecting to each other on the second protruding portion EL2b between them when external wiring is soldered to the multiple first electrode portions EL1.

[0068] All of the grooves TR (FIG. 5) may be located away from the thinnest point between the inner surface S1 and the outer surface S2 of the insulator portion 720. This prevents cracks from occurring between the inner surface S1 and the outer surface S2 of the insulator portion 720 due to the grooves TR. If the grooves TR are located at the thickest point between the inner surface S1 and the outer surface S2 of the insulator portion 720, cracks are further prevented from occurring.

[0069] All of the grooves TR (FIG. 5) may be located only between the shelf region S1c of the inner surface S1 and the bottom surface S3 in the thickness direction. This allows the dimension between the grooves TR on the outer surface S2 of the insulator 720 and the inner surface S1 of the insulator 720 to be larger than when the grooves TR are located between the shelf region S1c of the inner surface S1 and the top surface S4 in the thickness direction. This prevents cracks from occurring between the inner surface S1 and the outer surface S2 of the insulator 720 due to the grooves TR.

[0070] At least one of the second electrode portions EL2 (FIG. 5) may be at least partially located between the shelf region S1c of the inner surface S1 and the upper surface S4 in the thickness direction, thereby ensuring a larger area of ​​the outer surface S2 of the insulator portion 720 where the second electrode portions can be arranged.

[0071] The grooves TR (FIG. 7) may have a plurality of first portions TR1 connecting the plurality of first electrode portions EL1 and the plurality of second electrode portions EL2 to each other, and a plurality of second portions TR2 deeper than the first portions TR1. This allows the grooves TR of the insulator portion 720 to have the first portions TR1 that cut off the electrical path and the second portions TR2 that are not covered by the electrical path and are therefore deeper, when forming the grooves TR by laser processing to disable a temporary electrical path that electrically connects the plurality of electrode portions EL, including the plurality of first electrode portions EL1 and the plurality of second electrode portions EL2, on the outer surface S2 for the convenience of electrolytic plating. This allows the grooves TR to be formed at positions outside the electrical path. This facilitates control of the position at which the grooves TR are formed.

[0072] Furthermore, the groove TR may extend continuously so that a plurality of first portions TR1 and a plurality of second portions TR2 are alternately positioned. This allows the plurality of first portions TR1 for cutting the electrical path to be formed by simply forming one continuous groove TR. This improves the manufacturing efficiency of the package 801.

[0073] The plurality of second terminal portions EL2a may include second terminal portions EL2a having portions facing each other in the thickness direction (Z direction) in a region on the outer surface S2 between the pair of first terminal portions EL1a, and the plurality of first terminal portions EL1a may include first terminal portions EL1a having portions facing each other in the thickness direction (Z direction) in a region on the outer surface S2 between the pair of second terminal portions EL2a. This allows external wiring connected to first terminal portions EL1a having portions facing each other in the thickness direction (Z direction) in a region on the outer surface S2 between the pair of second terminal portions EL2a to extend along the thickness direction (Z direction) toward the upper surface S4 without being interfered with by the pair of second terminal portions EL2a. Alternatively, an external wiring connected to the second terminal portion EL2a having a portion facing the pair of first terminal portions EL1a in the thickness direction (Z direction) on the outer surface S2 in the region between the pair of first terminal portions EL1a can be extended along the thickness direction (Z direction) toward the bottom surface S3 without being interfered with by the pair of first terminal portions EL1a, thereby preventing an increase in capacitance due to extending the external wiring to avoid the interference.

[0074] The plurality of first terminal portions EL1a may include portions on the outer surface S2 that face the second terminal portions EL2a in the thickness direction (Z direction). Similarly, the plurality of second terminal portions EL2a may include portions on the outer surface S2 that face the first terminal portions EL1a in the thickness direction (Z direction). This allows the electrode portions EL to be arranged more densely.

[0075] According to the manufacturing method of the first embodiment, a plurality of electrode portions EL (FIG. 6) can be efficiently formed by laser processing from the electrolytically plated electrode pattern EP (FIG. 10).

[0076] Each bridge portion ELb (FIG. 10) may extend on the outer surface S2 along an imaginary straight line parallel to the thickness direction (Z direction). This allows the total length of the multiple bridge portions ELb to be shortened. This also reduces the amount of gold required for gold plating the bridge portions ELb. In this case, the first protruding portion EL1b (FIG. 7) and the second protruding portion EL2b (FIG. 7) formed from the bridge portions ELb also extend on the outer surface S2 along the imaginary straight line. Therefore, when such first protruding portion EL1b (FIG. 7) and second protruding portion EL2b (FIG. 7) are used, the manufacturing method for reducing the amount of gold, as described above, can be applied.

[0077] <Embodiment 2> Fig. 16 is a side view schematically showing the configuration of a package 811 in embodiment 2. Fig. 17 is a partial side view showing an enlarged portion of Fig. 16. In Fig. 17, a dot pattern is added to the electrode portion EL to make the drawing easier to see. The following mainly describes the differences between package 801 in embodiment 1 and package 811 in embodiment 1 described above.

[0078] 17, in the second embodiment, the first protruding portion EL1b of the first electrode portion EL1 and the second protruding portion EL2b of the second electrode portion EL2 each protrude toward the bottom surface S3 on the outer surface S2 of the insulator portion 720. The second protruding portion EL2b of each of the plurality of second electrode portions EL2 traverses the first region R1.

[0079] In the second embodiment, the groove TR separates the bottom surface S3 and the first region R1 on the outer surface S2. Each of the first electrode portions EL1 has an end that contacts the groove TR. Specifically, each of the first protruding portions EL1b has an end that contacts the groove TR. Furthermore, each of the second protruding portions EL2b of the second electrode portions EL2 has an end that contacts the groove TR.

[0080] At least a part of the second terminal portion EL2a of each of the second electrode portions EL2 may be located between the shelf-like region S1c (see FIG. 5) of the inner surface S1 and the upper surface S4 in the thickness direction.

[0081] The groove TR of the insulator portion 720 has a first edge DG1 and a second edge DG2. The first edge DG1 contacts an end of each of the multiple first electrode portions EL1. Specifically, the first edge DG1 contacts an end of the first protruding portion EL1b of each of the multiple first electrode portions EL1. The first edge DG1 contacts an end of the second protruding portion EL2b of each of the multiple second electrode portions EL2. The second edge DG2 opposite to the first edge DG1 is located between the first edge DG1 and the bottom surface S3 of the insulator portion 720. The groove TR may have multiple first portions TR1 connecting the multiple electrode portions EL to the second edge DG2 and multiple second portions TR2 deeper than the first portions TR1. The groove TR may extend continuously so that the multiple first portions TR1 and the multiple second portions TR2 are alternately positioned.

[0082] On the outer surface S2, a plurality of protruding portions EW1 and a plurality of protruding portions EW2 may be provided from the metallized layer 781 so as to connect the second edge DG2 of the groove TR and the metallized layer 781 on the bottom surface S3 to each other. The protruding portion EW2 protrudes toward the second protruding portion EL2b. The protruding portion EW1 may protrude toward the first electrode portion EL1, specifically toward the first protruding portion EL1b. The protruding portions EW1 and EW2 are electrolytically plated, similar to the first electrode portion EL1 and the second electrode portion EL2.

[0083] FIG. 18 is a side view schematically showing a step in the manufacturing method of the package 811. In the manufacturing method of the package 811, a work in progress 811L (FIG. 18) is formed instead of the work in progress 801L (FIG. 11: embodiment 1). In the work in progress 811L, the electrode pattern EP has connecting portions EC1 and EC2 instead of the bridge portion ELb (FIG. 11: embodiment 1). The connecting portions EC1 and EC2 connect the first terminal portion EL1a and the second terminal portion EL2a to the metallized layer 781 on the bottom surface S3, respectively. This sets the potential of the electrode pattern EP to the reference potential. Therefore, electrolytic plating can be applied to the electrode pattern EP. Next, electrolytic plating is applied to the work in progress 811L in substantially the same manner as in the case of embodiment 1 described above.

[0084] After the electrolytic plating, laser processing is performed to partially remove the electrode pattern EP (FIG. 18) so as to form a plurality of electrode portions EL (FIG. 17), thereby obtaining the package 811. Specifically, grooves TR are formed in the outer surface S2 of the insulator portion 720 by laser processing. As a result of this laser processing, second protruding portions EL2b are formed from the connecting portions EC2 (FIG. 18). Protruding portions EW2 may also be formed from the connecting portions EC2 (FIG. 18). Furthermore, first protruding portions EL1b and EW1 (FIG. 17) may be formed from the connecting portions EC1 (FIG. 18).

[0085] Note that the configuration other than the above is substantially the same as the configuration of the first embodiment described above, and therefore the same or corresponding elements are given the same reference numerals and description thereof will not be repeated.

[0086] According to the second embodiment, a temporary electrical path for electrically shorting the plurality of electrode portions EL to apply a current required for electrolytic plating in manufacturing the package 811 is disposed between the bottom surface S3 and the first region R1 on the outer surface S2 of the insulator portion 720, and after electrolytic plating, a groove TR is formed separating the bottom surface S3 and the first region R1 to cut the electrical path, thereby eliminating the short-circuit state. In this case, the groove TR needs to be formed only between the bottom surface S3 and the first region R1, so the groove TR can be formed efficiently. This improves the manufacturing efficiency of the package 811.

[0087] Furthermore, in the above-described first embodiment (FIG. 11), at least one of the first terminal portion EL1a and the second terminal portion EL2a is a terminal portion having a reference ionization potential (also referred to as a reference potential terminal portion) in the design of the package 801. However, the other terminal portions are temporarily connected to the reference potential terminal portion during electrolytic plating, thereby applying a reference potential. Therefore, during the electrolytic plating process, the potential of the terminals of the many terminal portions connected to the reference potential terminal portion deviates slightly from the reference potential due to a voltage drop caused by the current flowing through these many connected terminal portions. This leads to variations in plating thickness. In contrast, according to the second embodiment, the first terminal portion EL1a and the second terminal portion EL2a are each connected to the metallized layer 781 without passing through other terminal portions, thereby applying a reference potential. This allows for a more uniform plating thickness.

[0088] At least a part of the second terminal portion EL2a of each second electrode portion EL2 may be located between the shelf-like region S1c of the inner surface S1 and the upper surface S4 in the thickness direction, thereby ensuring a larger area of ​​the outer surface S2 of the insulator portion 720 where multiple second terminal portions EL2a can be arranged.

[0089] The grooves TR may have a plurality of first portions TR1 connecting the plurality of electrode portions EL to the second edge DG2 and a plurality of second portions TR2 deeper than the first portions TR1. This allows the grooves TR of the insulator portion 720 to have the first portions TR1 that cut off the electrical path and the second portions TR2 that are not covered by the electrical path and are therefore deeper when forming the grooves TR by laser processing to disable a temporary electrical path that electrically connects the plurality of electrode portions EL, including the plurality of first electrode portions EL1 and the plurality of second electrode portions EL2, on the outer surface for the convenience of electrolytic plating. This allows the grooves TR to be formed at positions outside the electrical path. This facilitates control of the position at which the grooves TR are formed.

[0090] The groove TR may extend continuously so that a plurality of first portions TR1 and a plurality of second portions TR2 are alternately positioned. This allows the plurality of first portions TR1 for cutting the electrical path to be formed by simply forming one continuous groove TR. This improves the manufacturing efficiency of the package 811.

[0091] Note that the description of the effects based on the same features as those of the first embodiment will be omitted.

[0092] <Additional Notes> In the above embodiments, the case where both the transmitter 910 and the receiver 920 are housed as electronic components has been described, but the electronic component housed in the package may be either the transmitter 910 or the receiver 920. Alternatively, the electronic component housed in the package may be a semiconductor element other than the transmitter and receiver. [Explanation of symbols]

[0093] 710: Base 720: Insulator 781~783: Metallized layer 801, 802, 811: Package 910: Transmitter (electronic components) 920: Receiver (electronic parts) 1000: TROSA (electronic equipment) CV: Cavity DG1: First Edge DG2: Second Edge EL: Electrode part EL1: 1st electrode part EL1a: 1st terminal part EL1b: 1st protruding part EL2: 2nd electrode part EL2a: 2nd terminal part EL2b: 2nd protruding part EP: Electrode pattern FR: Frame R1: 1st area R2: 2nd area S1: Inner surface S1a: 1st side wall area S1b: 2nd side wall area S1c: shelf area S2: External surface S3: Bottom S4: Top surface TR: Groove TR1 : 1st part TR2 : 2nd part

Claims

1. A package having a cavity for housing an electronic component, a base portion for supporting the electronic component; a frame portion attached to the base portion and surrounding the cavity in an in-plane direction perpendicular to a thickness direction, the frame portion including an insulator portion, the insulator portion having a bottom surface facing the base portion, an inner surface facing the cavity, a top surface extending from the inner surface and opposite the bottom surface, and an outer surface connecting the bottom surface and the top surface, the outer surface including a first region separated from the top surface and a second region located between the first region and the top surface, the package further comprising: a plurality of electrode portions spaced apart from one another on the outer surface of the insulator portion, the plurality of electrode portions including a plurality of first electrode portions and a plurality of second electrode portions located in the first region and the second region of the outer surface, respectively; A package, wherein a groove is provided on the outer surface of the insulator portion to separate the plurality of first electrode portions from the plurality of second electrode portions, and each of the plurality of electrode portions has an end that contacts the groove.

2. 10. The package of claim 1, A package wherein the insulator portion has a width dimension that is the dimension between the inner surface and the outer surface in the in-plane direction, and all of the grooves in the insulator portion are located away from the position where the width dimension is smallest.

3. 3. The package of claim 1 or 2, the inner surface of the insulator portion includes a first sidewall region, a second sidewall region, and a shelf region connecting the first sidewall region and the second sidewall region, the first sidewall region being located between the shelf region and the bottom surface, and the second sidewall region being located between the shelf region and the top surface; a package in which all of the grooves on the outer surface of the insulator are located only between the shelf-like region of the inner surface and the bottom surface in the thickness direction.

4. 4. The package of claim 3, At least one of the plurality of second electrode portions is at least partially located between the shelf-like region of the inner surface and the top surface in the thickness direction.

5. 3. The package of claim 1 or 2, The groove of the insulator portion has a plurality of first portions that connect the plurality of first electrode portions and the plurality of second electrode portions to each other, and a plurality of second portions that are deeper than the first portions.

6. 6. The package of claim 5, The groove extends continuously so that the first portions and the second portions alternate with each other.

7. 3. The package of claim 1 or 2, The direction along the outer surface of the insulator portion among the in-plane directions is defined as a length direction, each of the plurality of first electrode portions has a first terminal portion and a first protruding portion that protrudes from the first terminal portion and has a width smaller than that of the first terminal portion in the longitudinal direction; and each of the plurality of second electrode portions has a second terminal portion and a second protruding portion that protrudes from the second terminal portion and has a width smaller than that of the second terminal portion in the longitudinal direction; the plurality of first terminal portions include a pair of first terminal portions adjacent to each other in the longitudinal direction, and the plurality of second terminal portions include a pair of second terminal portions adjacent to each other in the longitudinal direction, the plurality of second terminal portions include second terminal portions having portions on the outer surface facing each other in the thickness direction in a region between the pair of first terminal portions, and the plurality of first terminal portions include first terminal portions having portions on the outer surface facing each other in the thickness direction in a region between the pair of second terminal portions.

8. A package having a cavity for housing an electronic component, a base portion for supporting the electronic component; a frame portion attached to the base portion and surrounding the cavity in an in-plane direction perpendicular to a thickness direction, the frame portion including an insulator portion, the insulator portion having a bottom surface facing the base portion, an inner surface facing the cavity, a top surface extending from the inner surface and opposite the bottom surface, and an outer surface connecting the bottom surface and the top surface, the outer surface including a first region spaced apart from the top surface and the bottom surface, and a second region located between the first region and the top surface, the package further comprising: the insulating body portion has a plurality of electrode portions spaced apart from one another on the outer surface thereof, the plurality of electrode portions including a first electrode portion and a second electrode portion, each of the plurality of second electrode portions having a terminal portion and a protruding portion protruding from the terminal portion and having a width smaller than that of the terminal portion in the in-plane direction, the plurality of first electrode portions being located in the first region of the outer surface, the terminal portion of each of the plurality of second electrode portions being located in the second region of the outer surface, and the protruding portion of each of the plurality of second electrode portions traversing the first region; a groove is provided on the outer surface of the insulator portion to separate the bottom surface and the first region, each of the plurality of first electrode portions has an end that contacts the groove, and the protruding portion of each of the plurality of second electrode portions has an end that contacts the groove.

9. 9. The package of claim 8, A package wherein the insulator portion has a width dimension that is the dimension between the inner surface and the outer surface in the in-plane direction, and all of the grooves in the insulator portion are located away from the position where the width dimension is smallest.

10. 10. The package of claim 8 or 9, the inner surface of the insulator portion includes a first sidewall region, a second sidewall region, and a shelf region connecting the first sidewall region and the second sidewall region, the first sidewall region being located between the shelf region and the bottom surface, and the second sidewall region being located between the shelf region and the top surface; a package in which all of the grooves on the outer surface of the insulator are located only between the shelf-like region of the inner surface and the bottom surface in the thickness direction.

11. 11. The package of claim 10, At least a portion of the terminal portion of each of the second electrode portions is located between the shelf-like region of the inner surface and the top surface in the thickness direction.

12. 10. The package of claim 8 or 9, the groove of the insulator portion has a first edge contacting the end of each of the plurality of first electrode portions and the end of the protruding portion of each of the plurality of second electrode portions, and a second edge opposite to the first edge and positioned between the first edge and the bottom surface of the insulator portion; The groove has a plurality of first portions that connect the plurality of electrode portions to the second edge, and a plurality of second portions that are deeper than the first portions.

13. 13. The package of claim 12, The groove extends continuously so that the first portions and the second portions alternate with each other.

14. A method for manufacturing a package according to any one of claims 1, 2, 8 and 9, comprising the steps of: forming an electrode pattern including portions to be the plurality of electrode portions on the outer surface of the insulator portion; a step of electroplating the electrode pattern; and performing laser processing to partially remove the electrode pattern so as to form the plurality of electrode portions, wherein the grooves are formed in the outer surface of the insulator portion by the laser processing.

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