Semiconductor Devices

Abstract

A highly reliable semiconductor device is provided by reducing the force applied when bonding wires. [Solution] The semiconductor device comprises a first conductive layer 191 formed on the element formation surface of a semiconductor chip 12, a second conductive layer 192 formed on the first conductive layer, a first wire connected to the second conductive layer and made of a material primarily composed of copper, and a third conductive layer 193 formed between the first and second conductive layers and containing a material harder than copper, wherein the thickness of the second conductive layer is smaller than the thickness of the first conductive layer, and the thickness of the third conductive layer is smaller than the thickness of either the first or second conductive layer, the element structure including the transistor cell 14 includes a recess (source trench 18) formed in the semiconductor chip and a conductive embedded body (contact plug 11) embedded in the recess, the first conductive layer covers the recess, and the semiconductor chip is formed of a semiconductor material such as Si or SiC.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device comprising an insulating substrate having a first electrode and a second electrode, a semiconductor element bonded to the first electrode by a sintered metal layer, a joint consisting of a sintered copper layer provided on the semiconductor element and a metal-containing layer covering the surface of the sintered copper layer, a metal sintered layer provided on the second electrode, and a metal wire having one end bonded to the joint and the other end bonded to the second electrode via the metal sintered layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-147967 Summary of the Invention [Means for solving the problem]

[0004] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor chip having an element formation surface on which an element structure is formed, a first conductive layer formed on the element formation surface of the semiconductor chip, a second conductive layer formed on the first conductive layer, a first wire connected to the second conductive layer and made of a material primarily composed of copper, and a third conductive layer formed between the first conductive layer and the second conductive layer and containing a material harder than copper. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a partial enlarged view of the semiconductor device of FIG. [Figure 3] FIG. 3 is a partial enlarged view of the semiconductor device of FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. [Figure 5] FIG. 5 is a view showing a VV cross section of FIG. [Figure 6] FIG. 6 is a diagram for explaining the bonded state of the first wire. [Figure 7] FIG. 7 is a diagram for explaining the bonded state of the second wire. [Figure 8] 8A and 8B are diagrams showing a part of the manufacturing process of the semiconductor device. [Figure 9] 9A and 9B are diagrams showing the next steps of FIGS. 8A and 8B, respectively. [Figure 10] 10A and 10B are diagrams showing the next steps of FIGS. 9A and 9B, respectively. [Figure 11] 11A and 11B are diagrams showing the next steps of FIGS. 10A and 10B, respectively. [Figure 12] 12A and 12B are diagrams showing the next steps of FIGS. 11A and 11B, respectively. [Figure 13] 13A and 13B are diagrams showing the next steps of FIGS. 12A and 12B, respectively. [Figure 14] 14A and 14B are diagrams showing the next steps of FIGS. 13A and 13B, respectively. [Figure 15] 15A and 15B are diagrams showing the next steps of FIGS. 14A and 14B, respectively. [Figure 16] 16A and 16B are diagrams showing the next steps of FIGS. 15A and 15B, respectively. [Figure 17] 17A and 17B are diagrams showing the next steps of FIGS. 16A and 16B, respectively. [Figure 18] 18A and 18B are diagrams showing the next steps of FIGS. 17A and 17B, respectively. [Figure 19] FIG. 19 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0006] <Embodiments of the present disclosure> First, embodiments of the present disclosure will be listed and described.

[0007] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor chip having an element formation surface on which an element structure is formed, a first conductive layer formed on the element formation surface of the semiconductor chip, a second conductive layer formed on the first conductive layer, a first wire connected to the second conductive layer and made of a material primarily composed of copper, and a third conductive layer formed between the first conductive layer and the second conductive layer and containing a material harder than copper.

[0008] With this configuration, the force applied when joining the first wire to the second conductive layer is alleviated by the third conductive layer, thereby reducing the stress load on the element structure and providing a highly reliable semiconductor device.

[0009] The semiconductor device according to an embodiment of the present disclosure may include a fourth conductive layer formed between the semiconductor chip and the first conductive layer, the fourth conductive layer including a material harder than copper.

[0010] According to this configuration, by forming the fourth conductive layer, the first conductive layer, the third conductive layer, and the second conductive layer in this order from the semiconductor chip side, it is possible to reduce stress (for example, film stress) applied to the semiconductor chip, thereby mitigating warpage of the semiconductor chip and providing a highly reliable semiconductor device.

[0011] In the semiconductor device according to the embodiment of the present disclosure, the fourth conductive layer may contain the same material as the third conductive layer.

[0012] In the semiconductor device according to the embodiment of the present disclosure, the third conductive layer may have a thickness equal to or less than a thickness of the fourth conductive layer.

[0013] With this configuration, the thickness of the third conductive layer, which is closer to the second conductive layer (the bonding portion of the first wire) out of the third and fourth conductive layers, is at least the same as or relatively thinner than the thickness of the fourth conductive layer, making the third conductive layer more susceptible to damage by the impact when bonding the first wire. This allows the stress when bonding the first wire to be dispersed, thereby providing a semiconductor device with higher reliability.

[0014] In a semiconductor device according to one embodiment of the present disclosure, the element structure may include a recess formed in the semiconductor chip and a conductive filler embedded in the recess, and the first conductive layer may cover the recess.

[0015] When a recess is formed in an element structure, the shape of the recess may be inherited by the first conductive layer and the second conductive layer. This may increase the load due to stress when bonding the first wire compared to when the recess is not inherited. The semiconductor device according to this embodiment is effective even for structures that are prone to large load due to such stress, and as a result, a highly reliable semiconductor device can be provided.

[0016] In a semiconductor device according to one embodiment of the present disclosure, the element structure may include a first region of a first conductivity type and a second region of a second conductivity type in contact with the first region, each exposed in the recess, and the embedded body may be electrically connected to the first region and the second region.

[0017] A semiconductor device according to one embodiment of the present disclosure may further include an insulating layer formed between the semiconductor chip and the first conductive layer, a recess that penetrates the insulating layer and reaches partway through the thickness of the semiconductor chip, a fourth conductive layer formed to conform to the inner surface of the recess and the upper surface of the insulating layer and containing a material harder than copper, and a conductive embedment embedded in the recess via the fourth conductive layer.

[0018] When a recess is formed in a semiconductor chip, the shape of the recess may be inherited by the first conductive layer and the second conductive layer. This increases the load due to stress when bonding the first wire compared to when the recess is not inherited, and may cause cracks in the insulating layer. The semiconductor device according to this embodiment is effective even for structures that are prone to large loads due to such stress, and as a result, a highly reliable semiconductor device can be provided.

[0019] Furthermore, by forming the fourth conductive layer, the first conductive layer, the third conductive layer, and the second conductive layer in this order from the semiconductor chip side, it is possible to reduce stress (for example, film stress) applied to the semiconductor chip, thereby mitigating warpage of the semiconductor chip.

[0020] In the semiconductor device according to the embodiment of the present disclosure, the recesses may be arranged at a pitch of 1 μm or less.

[0021] In a miniaturized structure in which multiple recesses are arranged at a pitch of 1 μm or less, the load due to stress when bonding the first wire tends to be large, but the semiconductor device of this embodiment can solve this problem.

[0022] A semiconductor device according to one embodiment of the present disclosure may include a fifth conductive layer formed on the element forming surface of the semiconductor chip and separated from the first conductive layer, a sixth conductive layer formed on the fifth conductive layer, a second wire connected to the sixth conductive layer, and a seventh conductive layer formed between the fifth conductive layer and the sixth conductive layer and including a material harder than copper.

[0023] In the semiconductor device according to the embodiment of the present disclosure, the diameter of the second wire may be the same as the diameter of the first wire.

[0024] According to this configuration, the first wire and the second wire can be bonded to the second conductive layer and the sixth conductive layer, respectively, using the same bonding device, thereby providing a semiconductor device that can be manufactured efficiently and at low cost.

[0025] In the semiconductor device according to the embodiment of the present disclosure, the second wire may include a wire made of a material containing copper as a main component.

[0026] In a semiconductor device according to one embodiment of the present disclosure, the element structure may include a gate electrode, and a first impurity region and a second impurity region formed in the semiconductor chip and conducting through a channel formed by application of a voltage to the gate electrode, wherein the first wire is electrically connected to the first impurity region through the second conductive layer and the first conductive layer, and the second wire is electrically connected to the gate electrode through the sixth conductive layer and the fifth conductive layer.

[0027] In the semiconductor device according to the embodiment of the present disclosure, the third conductive layer may contain at least one of Ti and W.

[0028] In the semiconductor device according to the embodiment of the present disclosure, the third conductive layer may have a thickness of 700 Å or less.

[0029] In the semiconductor device according to the embodiment of the present disclosure, the first conductive layer and the second conductive layer may be formed of the same material.

[0030] In the semiconductor device according to the embodiment of the present disclosure, the first conductive layer and the second conductive layer may contain AlCu.

[0031] In the semiconductor device according to the embodiment of the present disclosure, the second conductive layer may have a thickness of not less than 2 μm and not more than 4.5 μm.

[0032] In a semiconductor device according to one embodiment of the present disclosure, the second conductive layer may have a first thickness at the junction with the first wire and a second thickness greater than the first thickness around the periphery of the junction.

[0033] Detailed Description of Embodiments of the Present Disclosure Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following detailed description, there are a plurality of components with names each having an ordinal number, but the ordinal numbers do not necessarily match the ordinal numbers of the components described in the claims.

[0034] [First embodiment] 1 is a schematic plan view of a semiconductor device 1 according to a first embodiment of the present disclosure. For clarity, in FIG. 1, a package 4 is shown by an imaginary line (broken line), and other components are shown by solid lines.

[0035] The semiconductor device 1 includes a lead frame 2 , a semiconductor element 3 , and a package 4 .

[0036] The lead frame 2 is formed in the shape of a metal plate. The lead frame 2 is formed by punching, cutting, bending, etc. from a thin metal plate made of Cu or the like that is rectangular in plan view. Therefore, the main component of the material of the lead frame 2 is Cu. However, the material of the lead frame 2 is not limited to this.

[0037] The lead frame 2 may include a die pad portion 21, a first lead portion 22, a second lead portion 23, and a third lead portion 24. In this embodiment, the first lead portion 22, the second lead portion 23, and the third lead portion 24 may be referred to as a source lead portion, a gate lead portion, and a drain lead portion, respectively. Furthermore, the first lead portion 22, the second lead portion 23, and the third lead portion 24 have portions that are exposed from the package 4 and are connected to an external circuit of the semiconductor device 1, and therefore may be referred to as a first terminal (source terminal), a second terminal (gate terminal), and a third terminal (drain terminal).

[0038] In a plan view, the die pad portion 21 has a rectangular shape having a pair of first sides 211A, 211B extending in a first direction X and a pair of second sides 212A, 212B extending in a direction intersecting the first direction X (in this embodiment, a direction perpendicular to the first direction X).

[0039] The first lead portion 22, the second lead portion 23, and the third lead portion 24 are arranged around the die pad portion 21. In this embodiment, the first lead portion 22, the second lead portion 23, and the third lead portion 24 are arranged adjacent to first sides 211A and 211B of the die pad portion 21. More specifically, the first lead portion 22 and the second lead portion 23 are arranged adjacent to one first side 211A of the die pad portion 21, and the third lead portion 24 is arranged adjacent to the other first side 211B of the die pad. In other words, the first lead portion 22 and the second lead portion 23 are arranged on the opposite side of the die pad portion 21 from the third lead portion 24.

[0040] The first lead portion 22 is formed away from the die pad portion 21. The first lead portion 22 may include a first pad portion 221 and a first lead 222. In a plan view, the first pad portion 221 is formed in a substantially rectangular shape extending along the first side 211A of the die pad portion 21. The first lead 222 is formed integrally with the first pad portion 221 and extends from the first pad portion 221 in a direction intersecting the longitudinal direction of the first pad portion 221. A plurality of first leads 222 (three in this embodiment) are formed. The multiple first leads 222 are arranged at intervals from one another along the longitudinal direction of the common first pad portion 221 and are connected to the common first pad portion 221.

[0041] The second lead portion 23 is formed apart from the die pad portion 21 and the first lead portion 22. The second lead portion 23 may include a second pad portion 231 and a second lead 232. The second pad portion 231 is formed in a substantially rectangular shape extending along a first side 211A of the die pad portion 21. The second lead 232 is formed integrally with the second pad portion 231 and extends from the second pad portion 231 in a direction intersecting the longitudinal direction of the second pad portion 231. The second lead 232 is connected to the second pad portion 231 in a one-to-one relationship. In this embodiment, the second lead portion 23 is disposed near one end of one first side 211A of the die pad portion 21 (one corner of the die pad portion 21), and the first lead portion 22 extends from that end toward the other end along the first side 211A of the die pad portion 21.

[0042] Unlike the first lead portion 22 and the second lead portion 23, the third lead portion 24 is formed integrally with the die pad portion 21. The third lead portion 24 extends from the other first side 211B of the die pad portion 21 in a direction intersecting the other first side 211B. A plurality of third lead portions 24 (four in this embodiment) are formed. The plurality of third lead portions 24 are arranged at intervals along the first side 211B of the die pad portion 21.

[0043] The semiconductor element 3 is disposed on the die pad portion 21 of the lead frame 2 and is supported by the die pad portion 21. In a plan view, the semiconductor element 3 has a rectangular shape that is smaller than the die pad portion 21 and has a pair of first sides 31A, 31B and a pair of second sides 32A, 32B. In this embodiment, the semiconductor element 3 is disposed on the die pad portion 21 so that the first sides 31A, 31B are parallel to the first sides 211A, 211B of the die pad portion 21 and the second sides 32A, 32B are parallel to the second sides 212A, 212B of the die pad portion 21. A first distance D1 between the first sides 211A, 211B of the die pad portion 21 and the first sides 31A, 31B of the semiconductor element 3 is narrower than a second distance D2 between the second sides 212A, 212B of the die pad portion 21 and the second sides 32A, 32B of the semiconductor element 3. For example, the first distance D1 may be equal to or less than half the second distance D2.

[0044] A conductive region 5 and an insulating region 6 are formed on one surface (the upper surface in this embodiment) of the semiconductor element 3. The conductive region 5 is partially covered by the insulating region 6. In FIG. 1, the portion of the conductive region 5 that is covered by the insulating region 6 is shown as a hatched region, and the portion exposed from the insulating region 6 is shown as a white region. The conductive region 5 is a region to which a first wire 8 and a second wire 10, which will be described later, are connected, and may also be referred to as an electrode region.

[0045] The conductive region 5 is formed over almost the entire upper surface of the semiconductor element 3. The conductive region 5 may include a first conductive region 51 and a second conductive region 52. The first conductive region 51 and the second conductive region 52 are formed to be separated from each other.

[0046] A plurality of first conductive regions 51 are formed. The plurality of first conductive regions 51 are formed adjacent to one another in the direction along the second sides 32A and 32B of the semiconductor element 3, and a gap region 61 is formed between adjacent first conductive regions 51. The region surrounding the first conductive region 51 may be an outer periphery region 63. In other words, if the region where the first conductive region 51 is formed is referred to as an active region, the outer periphery region 63 may be the outer periphery region 63 surrounding the active region. In this embodiment, each first conductive region 51 is formed in a rectangular shape in a plan view that is elongated along the first sides 31A and 31B of the semiconductor element 3. A portion of the first conductive region 51 is exposed from the insulating region 6 as a first pad 7.

[0047] A first wire 8 is connected to the first pad 7. In this embodiment, the first wire 8 is a so-called Cu wire, which is mainly composed of Cu. Examples of wires mainly composed of Cu include wires made of Cu alone (e.g., Cu with a purity of 99.99% or more), Cu alloy wires in which Cu is alloyed with other alloy components, and wires in which a Cu alone wire or a Cu alloy wire is coated with a conductive layer. Examples of alloy components of Cu alloy wire include Ag, Au, Al, Ni, Be, Fe, Ti, Pd, Zn, and Sn. Examples of coating components of conductive-layer-coated Cu wires include Pd. Note that, as a modified example, an Au wire or an Al wire may be used as the first wire 8. When an Au wire is used as the bonding wire, Au is expensive and its cost is unstable due to price fluctuations. In addition, in a high-temperature environment, the wire is prone to peeling due to the growth of compounds between gold and aluminum. In addition, when an Al wire is used as the bonding wire, aluminum has a relatively low melting point and is prone to recrystallization in a high-temperature environment. A semiconductor device with higher reliability than that using Au wires or Al wires can be provided by using Cu wires as the first wires 8. When the first wires 8 are Cu wires, for example, they may have a diameter of φ118 μm or more and φ150 μm or less.

[0048] The first wire 8 connects the first pad 7 and the first pad portion 221 of the first lead portion 22. The first wire 8 may include a long wire 81 and a short wire 82 that is shorter than the long wire 81. The long wire 81 may be connected to the first pad 7 of a pair of adjacent first pads 7 that is farther from the first lead portion 22. On the other hand, the short wire 82 may be connected to the first pad 7 of the pair of first pads 7 that is closer to the first lead portion 22.

[0049] A plurality of long wires 81 and a plurality of short wires 82 may be provided, and may be arranged alternately along the longitudinal direction of the first pad portion 221. Furthermore, the bonding portion 811 of the long wire 81 on the first pad portion 221 side and the bonding portion 821 of the short wire 82 on the first pad portion 221 side are respectively arranged offset to one side and the other side in the longitudinal direction of the first pad portion 221. This allows the bonding portion 811 of the long wire 81 and the bonding portion 821 of the short wire 82 to be arranged offset from each other, preventing them from contacting each other. As a result, the space required for the first lead portion 22 can be saved.

[0050] The second conductive region 52 may integrally include a pad region 521 and a finger region 522. The pad region 521 is formed in the outer periphery region 63 and is arranged at one corner of the semiconductor element 3 in this embodiment. The finger region 522 is formed in the outer periphery region 63 from the pad region 521 along the periphery of the semiconductor element 3. In this embodiment, the finger region 522 is formed along the first sides 31A and 31B and the second sides 32A and 32B of the semiconductor element 3 so as to surround the first conductive region 51. The finger region 522 may also be formed in the gap region 61 between adjacent first conductive regions 51. As a result, each first conductive region 51 is individually surrounded by the finger region 522.

[0051] The finger region 522 is covered by the insulating region 6 , while a part of the pad region 521 is exposed from the insulating region 6 as a second pad 9 .

[0052] A second wire 10 is connected to the second pad 9. The second wire 10 may be made of the same material as the first wire 8. That is, in this embodiment, the second wire 10 may be made of a so-called Cu wire, which is mainly composed of Cu, but as a variant, an Au wire or an Al wire may also be used. The second wire 10 may also have the same diameter as the first wire 8. That is, in the case of a Cu wire, the second wire 10 may have a diameter of φ218 μm or more and φ250 μm or less.

[0053] The second wire 10 connects the second pad 9 and the second pad portion 231 of the second lead portion 23. The second wire 10 may have a length shorter than the short wire 82 of the first wire 8.

[0054] The package 4 covers the semiconductor element 3, the first wire 8, the second wire 10, and part of the lead frame 2, and may also be called a sealing resin. The package 4 is made of an insulating material. In this embodiment, the package 4 is made of, for example, black epoxy resin.

[0055] Fig. 2 is a partially enlarged view showing the planar structure below the first pad 7 in Fig. 1. Fig. 3 is a partially enlarged view showing the planar structure below the second pad 9 in Fig. 1. Fig. 4 is a view showing a cross section taken along line IV-IV in Fig. 2. Fig. 5 is a view showing a cross section taken along line VV in Fig. 3. In Fig. 3, for clarity, the first conductive region 51 and the second conductive region 52 are shown by two-dot chain lines or dashed lines.

[0056] The semiconductor device 1 includes a semiconductor chip 12, a first impurity region 121 (source), a second impurity region 122 (body), a third impurity region 123 (drain), a gate trench 15 (first recess), a gate insulating film 16, a gate electrode 13 (first embedded body), an interlayer insulating film 17 (insulating layer), a source trench 18 (second recess), a contact plug 11 (second embedded body), a conductive layer 19, and an insulating film 62.

[0057] The semiconductor chip 12 forms the outer shape of the semiconductor element 3 and is, for example, a structure in which a single crystal semiconductor material is formed into a chip shape (rectangular parallelepiped shape). The semiconductor chip 12 is formed of a semiconductor material such as Si or SiC. The semiconductor chip 12 has a first main surface 12A and a second main surface 12B opposite to the first main surface 12A. The first main surface 12A is a device surface on which functional devices are formed. The second main surface 12B is a non-device surface on which functional devices are not formed. In this embodiment, the semiconductor chip 12 may include at least one of a semiconductor substrate and an epitaxial layer.

[0058] 4 and 5, the first impurity region 121 is a p-type impurity region selectively formed in the surface layer portion of the first main surface 12A of the semiconductor chip 12 below the first conductive region 51. The p-type impurity concentration of the first impurity region 121 is 1×10 18 cm -3 More than 1×10 20 cm -3 In this embodiment, the first impurity region 121 may be referred to as a p-type source region.

[0059] The second impurity region 122 is an n-type impurity region formed in the surface layer portion of the first main surface 12A of the semiconductor chip 12. The second impurity region 122 is formed so as to be spaced apart from the first main surface 12A toward the second main surface 12B and to be in contact with the first impurity region 121. In other words, the second impurity region 122 faces the first main surface 12A with the first impurity region 121 in between. The n-type impurity concentration of the second impurity region 122 is 1×10 15 cm -3 More than 1×10 19 cm -3 5, the second impurity region 122 may be referred to as an n-type body region. In this embodiment, the second impurity region 122 may be referred to as an n-type body region. As shown in FIG. 5, the second impurity region 122 is exposed from the first main surface 12A of the semiconductor chip 12 below the second conductive region 52.

[0060] The third impurity region 123 is a p-type impurity region formed in the surface layer portion of the second main surface 12B of the semiconductor chip 12. The third impurity region 123 is formed in contact with the second impurity region 122, over the entire surface layer portion of the second main surface 12B, and is exposed from the second main surface 12B. The p-type impurity concentration of the third impurity region 123 is lower than the p-type impurity concentration of the first impurity region 121, and is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The thickness of the third impurity region 123 may be 1 μm or more and 500 μm or less. In this embodiment, the third impurity region 123 may also be referred to as a p-type drift region or a p-type drain region.

[0061] The gate trench 15 (first recess) is a trench that penetrates the first impurity region 121 and the second impurity region 122 and reaches the third impurity region 123. As shown in FIGS. 2 and 3 , the gate trench 15 surrounds the first impurity region 121, the second impurity region 122, and the third impurity region 123, thereby defining a transistor cell 14 including these regions 121, 122, and 123. In this embodiment, as shown in FIGS. 2 and 3 , the transistor cell 14 is selectively formed in the region below the first conductive region 51, avoiding the region below the second conductive region 52. That is, the transistor cell 14 is covered by the first conductive region 51 but not covered by the second conductive region 52.

[0062] The arrangement pattern of the transistor cells 14 is staggered in Figures 2 and 3. Although not shown, the arrangement pattern of the transistor cells 14 may also be a matrix or stripe pattern. Each transistor cell 14 is formed in a quadrangular shape in the plan view shown in Figures 2 and 3, and in this embodiment, it is formed in a rectangular shape.

[0063] The gate trenches 15 are formed between the plurality of transistor cells 14 arranged as described above. As shown in Fig. 4, the pitch P1 between adjacent gate trenches 15 is, for example, 1 µm or less. As shown in Figs. 2 and 3, when the gate trenches 15 are connected to each other so as to surround each of the plurality of transistor cells 14, the pitch P1 of the gate trenches 15 may be, for example, the distance between the gate trenches 15 facing each other across one transistor cell 14.

[0064] 4 and 5, the gate insulating film 16 covers the inner surface of the gate trench 15. The gate insulating film 16 also covers the first main surface 12A of the semiconductor chip 12. The gate insulating film 16 is formed of an insulating material containing, for example, SiO2, SiN, or the like.

[0065] The gate electrode 13 is accommodated in a gate trench 15. This structure allows for miniaturization and lower on-resistance compared to a planar structure. Furthermore, the gate electrode 13 is insulated from the semiconductor chip 12 by a gate insulating film 16, thereby preventing leakage current. The gate electrode 13 is made of a conductive material containing polysilicon and the like. Since polysilicon has a melting point nearly equal to that of single-crystal silicon, using polysilicon as the gate electrode 13 eliminates temperature-related process limitations after the formation of the gate electrode 13.

[0066] The gate electrode 13 faces the second impurity region 122 via the gate insulating film 16. In the second impurity region 122, a side portion of the gate trench 15 facing the gate electrode 13 is a channel region 124. When a voltage is applied to the gate electrode 13, carriers (electrons in this embodiment) are induced in the channel region 124, thereby establishing electrical continuity between the first impurity region 121 and the third impurity region 123. That is, in the semiconductor device 1, the transistor cell 14 and the gate electrode 13 form an element structure.

[0067] 4, the gate electrode 13 may have an upper surface 131 below the first conductive region 51 that is flush with the first main surface 12A of the semiconductor chip 12 or recessed toward the second main surface 12B. On the other hand, the gate electrode 13 may have an upper surface 132 below the second conductive region 52 that is flush with the first main surface 12A of the semiconductor chip 12 or recessed toward the second main surface 12B.

[0068] An interlayer insulating film 17 is formed on the first main surface 12A of the semiconductor chip 12 so as to cover the gate insulating film 16 and the gate electrode 13. The interlayer insulating film 17 insulates the gate electrode 13 from the first conductive layer 191. Therefore, the gate electrode 13 is configured to be covered by the gate insulating film 16 and the interlayer insulating film 17. The interlayer insulating film 17 is made of an insulating material containing SiO2, SiN, or the like.

[0069] 2 and 3, a source trench 18 (second recess) is formed in each transistor cell 14. In this embodiment, one source trench 18 is formed in each transistor cell 14, but a plurality of source trenches 18 may be formed in each transistor cell 14. The source trench 18 is formed in a long rectangular shape in plan view along the longitudinal direction of the transistor cell 14, which has a rectangular shape in plan view.

[0070] 4 and 5, source trench 18 is a groove portion that penetrates interlayer insulating film 17, gate insulating film 16, and first impurity region 121 and reaches second impurity region 122. Source trench 18 is formed in a tapered shape such that an opening width W1 gradually narrows toward the depth direction of source trench 18. Furthermore, as shown in FIG. 4, pitch P2 between adjacent source trenches 18 is the same as pitch P1 between gate trenches 15, and is, for example, 1 μm or less.

[0071] The contact plug 11 is buried in the source trench 18 via the first barrier layer 194. With this configuration, it is possible to provide a semiconductor device 1 with improved reliability by mitigating electric field concentration at the bottom of the gate trench 15.

[0072] The first barrier layer 194 prevents the material forming the contact plug 11 from diffusing into the interlayer insulating film 17. In this embodiment, the contact plug 11 contains W (tungsten), and the first barrier layer 194 may contain a material containing Ti (for example, a single layer structure of Ti or a stacked structure of Ti and TiN). The thickness of the first barrier layer 194 is, for example, not less than 500 Å and not more than 700 Å.

[0073] The first barrier layer 194 has one and the other surfaces formed to conform to the inner surface of the source trench 18 and the upper surface of the interlayer insulating film 17, and is in direct conduction with the first impurity region 121 and the second impurity region 122. The first barrier layer 194 is also continuous across the upper region of the gate trench 15, which is the boundary between adjacent transistor cells 14.

[0074] The contact plug 11 is electrically connected to the first impurity region 121 and the second impurity region 122 via the first barrier layer 194. The contact plug 11 has an upper surface 111 that is recessed toward the first main surface 12A of the semiconductor chip 12 with respect to the upper surface of the interlayer insulating film 17.

[0075] Furthermore, a second barrier layer 198 is formed on the interlayer insulating film 17. The second barrier layer 198 may include a material containing Ti (for example, a single layer structure of Ti or a laminated structure of Ti and TiN). The thickness of the second barrier layer 198 is the same as that of the first barrier layer 194, and is, for example, not less than 500 Å and not more than 700 Å.

[0076] The second barrier layer 198 has one and the other surfaces formed to conform to the upper surface of the interlayer insulating film 17, and is in direct electrical contact with the gate electrode 13 at a position not shown. Furthermore, as shown in FIG. 5, the second barrier layer 198 has an edge 27 on the interlayer insulating film 17 that faces the edge 26 of the first barrier layer 194 with a gap therebetween.

[0077] The conductive layer 19 is formed on the interlayer insulating film 17. The conductive layer 19 has a plurality of portions that are separated from one another on the interlayer insulating film 17. In this embodiment, the conductive layer 19 may include a first conductive portion 200 and a second conductive portion 201 as the plurality of portions. The first conductive portion 200 and the second conductive portion 201 have upper surfaces formed as the above-described first conductive region 51 and second conductive region 52, respectively. Furthermore, the first conductive portion 200 and the second conductive portion 201 may be referred to as a source electrode layer and a gate electrode layer, or a source electrode film and a gate electrode film, based on the objects to which they are electrically connected, or may be referred to as a first electrode and a second electrode using ordinal numbers.

[0078] As shown in FIGS. 4 and 5 , the first conductive unit 200 has multiple layers stacked in this order starting from the interlayer insulating film 17. In this embodiment, the first conductive unit 200 may include a first conductive layer 191, a second conductive layer 192, and a third conductive layer 193. The first conductive layer 191, the second conductive layer 192, and the third conductive layer 193 are formed across the entire first conductive unit 200 in an in-plane direction perpendicular to the stacking direction of the first conductive unit 200, and are each exposed at an end face 28 of the first conductive unit 200. In other words, the boundaries between the first conductive layer 191, the second conductive layer 192, and the third conductive layer 193 are exposed at the end face 28. The end face 28 may be flush with an edge 26 of the first barrier layer 194.

[0079] The first conductive layer 191 is formed on the interlayer insulating film 17 so as to cover the contact plug 11. The first conductive layer 191 is in contact with the upper surface 111 of the contact plug 11 above the source trench 18 and is in contact with the first barrier layer 194 on the interlayer insulating film 17. Therefore, a portion of the first barrier layer 194 is sandwiched between the interlayer insulating film 17 and the first conductive layer 191. The first conductive layer 191 is electrically connected to the first impurity region 121 and the second impurity region 122 via the first barrier layer 194 and the contact plug 11. The first conductive layer 191 is made of a material containing Al, for example, AlCu in this embodiment. The thickness of the first conductive layer 191 may be, for example, 2.5 μm or less.

[0080] The second conductive layer 192 is formed on the first conductive layer 191 with the third conductive layer 193 interposed therebetween. The second conductive layer 192 is a surface conductive layer forming the outermost surface of the first conductive section 200 and is the layer to which the first wire 8 described above is connected. Therefore, the upper surface of the second conductive layer 192 is exposed as the first pad 7. The second conductive layer 192 is electrically connected to the first impurity region 121 and the second impurity region 122 via the first barrier layer 194, the contact plug 11, the third conductive layer 193, and the first conductive layer 191. The second conductive layer 192 is made of the same material as the first conductive layer 191 (e.g., a material containing Al), and in this embodiment, is made of AlCu. The thickness of the second conductive layer 192 is smaller than the thickness of the first conductive layer 191, and may be, for example, 2 μm to 4.5 μm.

[0081] Third conductive layer 193 is formed between first conductive layer 191 and second conductive layer 192, and is sandwiched between first conductive layer 191 and second conductive layer 192. Third conductive layer 193 is made of a material harder than Cu (copper), for example, containing at least one of Ti and W, and in this embodiment, third conductive layer 193 has a layered structure (Ti / TiN) in which Ti and TiN are stacked in this order from the boundary with first conductive layer 191. The thickness of third conductive layer 193 is equal to or less than the thickness of first barrier layer 194, and is, for example, 700 Å or less.

[0082] As described above, the upper surface 111 of the contact plug 11 is recessed with respect to the upper surface of the interlayer insulating film 17. Therefore, a recess 202 may be formed in the upper surface of the first conductive layer 191 at a position facing the upper surface 111 in the stacking direction of the first conductive unit 200. Furthermore, a recess 203 may be formed in the upper surface of the second conductive layer 192 at a position facing the upper surface 111 in the stacking direction of the first conductive unit 200. Furthermore, a recess 204 may be formed in the upper surface of the third conductive layer 193 at a position facing the upper surface 111 in the stacking direction of the first conductive unit 200.

[0083] In other words, a part of the interface between the first conductive layer 191 and the third conductive layer 193 may selectively protrude toward the source trench 18. Also, a part of the interface between the third conductive layer 193 and the second conductive layer 192 may selectively protrude toward the source trench 18.

[0084] As described above, the first conductive section 200 has a structure in which the third conductive layer 193 is sandwiched between the first conductive layer 191 and the second conductive layer 192. Therefore, in this embodiment, the third conductive layer 193 may be referred to as a first intermediate layer, the first conductive layer 191 may be referred to as a first lower conductive layer, and the second conductive layer 192 may be referred to as a second upper conductive layer. Furthermore, the third conductive layer 193 relieves stress when a Cu wire is connected to the second conductive layer 192, as will be described later, and therefore may be referred to as a first relaxation layer (buffer layer) or a first stress relaxation layer.

[0085] As shown in FIG. 5 , the second conductive unit 201 has multiple layers stacked in this order starting from the interlayer insulating film 17. In this embodiment, the second conductive unit 201 may include a fourth conductive layer 195, a fifth conductive layer 196, and a sixth conductive layer 197. The fourth conductive layer 195, the fifth conductive layer 196, and the sixth conductive layer 197 are formed across the entire second conductive unit 201 in an in-plane direction perpendicular to the stacking direction of the second conductive unit 201, and are each exposed at an end face 29 of the second conductive unit 201. In other words, the boundaries between the fourth conductive layer 195, the fifth conductive layer 196, and the sixth conductive layer 197 are exposed at the end face 29. The end face 29 may be flush with an edge 27 of the second barrier layer 198. The end face 29 of the second conductive unit 201 faces the end face 28 of the first conductive unit 200 across a space.

[0086] The fourth conductive layer 195 is formed on the interlayer insulating film 17. The fourth conductive layer 195 contacts the gate electrode 13 at a position not shown, and contacts the second barrier layer 198 on the interlayer insulating film 17. Therefore, a portion of the second barrier layer 198 is sandwiched between the interlayer insulating film 17 and the fourth conductive layer 195. The fourth conductive layer 195 is electrically connected to the gate electrode 13 via the second barrier layer 198. The fourth conductive layer 195 is made of a material containing Al, for example, AlCu in this embodiment. The thickness of the fourth conductive layer 195 is the same as that of the first conductive layer 191, and may be, for example, 2.5 μm or less.

[0087] The fifth conductive layer 196 is formed on the fourth conductive layer 195 via the sixth conductive layer 197. The fifth conductive layer 196 is a surface conductive layer forming the outermost surface of the second conductive portion 201 and is the layer to which the second wire 10 is connected. Therefore, the upper surface of the fifth conductive layer 196 is exposed as the second pad 9. The fifth conductive layer 196 is electrically connected to the gate electrode 13 via the second barrier layer 198, the fourth conductive layer 195, and the sixth conductive layer 197. The fifth conductive layer 196 is made of the same material as the fourth conductive layer 195 (e.g., a material containing Al), and in this embodiment, is made of AlCu. The thickness of the fifth conductive layer 196 is smaller than the thickness of the fourth conductive layer 195, and may be, for example, 2 μm or more and 4.5 μm or less. The thickness of the fifth conductive layer 196 may be the same as the thickness of the second conductive layer 192.

[0088] Sixth conductive layer 197 is formed between fourth conductive layer 195 and fifth conductive layer 196 and is sandwiched between fourth conductive layer 195 and fifth conductive layer 196. Sixth conductive layer 197 is made of a material harder than Cu (copper), for example, containing at least one of Ti and W. In this embodiment, sixth conductive layer 197 has a layered structure (Ti / TiN) in which Ti and TiN are stacked in this order from the boundary with fourth conductive layer 195. The thickness of sixth conductive layer 197 is equal to or less than the thickness of second barrier layer 198, for example, 700 Å or less. Alternatively, the thickness of sixth conductive layer 197 may be the same as the thickness of third conductive layer 193.

[0089] As described above, the second conductive portion 201 has a structure in which the sixth conductive layer 197 is sandwiched between the fourth conductive layer 195 and the fifth conductive layer 196. Therefore, in this embodiment, the sixth conductive layer 197 may be referred to as a second intermediate layer, the fourth conductive layer 195 may be referred to as a second lower conductive layer, and the fifth conductive layer 196 may be referred to as a second upper conductive layer. Furthermore, the sixth conductive layer 197 relieves stress when a Cu wire is connected to the fifth conductive layer 196, as will be described later, and therefore may also be referred to as a second relaxation layer (buffer layer) or a second stress relaxation layer.

[0090] Furthermore, the fourth conductive layer 195, the fifth conductive layer 196 and the sixth conductive layer 197 may have a flat upper surface without recesses 202-204 formed thereon, unlike the first conductive layer 191, the second conductive layer 192 and the third conductive layer 193, respectively.

[0091] The insulating film 62 is formed on the interlayer insulating film 17 so as to cover the conductive layer 19. At the boundary between the first conductive portion 200 and the second conductive portion 201, the insulating film 62 integrally covers the end face 28 of the first conductive portion 200, the edge 26 of the first barrier layer 194, the upper surface of the interlayer insulating film 17, the edge 27 of the second barrier layer 198, and the end face 29 of the second conductive portion 201. The insulating film 62 is formed of an insulating material, such as SiN. The insulating film 62 protects the outermost surface of the semiconductor chip 12, and may be referred to as a surface protective film or a surface insulating film. The insulating film 62 has an upper surface formed as the insulating region 6 described above. The insulating film 62 also has a first opening 621 that exposes a portion of the first conductive portion 200 as the first pad 7 and a second opening 622 that exposes a portion of the second conductive portion 201 as the second pad 9. The first pad 7 may include a recess 203 in the second conductive layer 192.

[0092] Fig. 6 is a diagram showing the bonded state of the first wire 8 of the semiconductor device 1 according to the first embodiment of the present disclosure. Fig. 7 is a diagram showing the bonded state of the second wire 10 of the semiconductor device 1 according to the first embodiment of the invention. For clarity, Figs. 6 and 7 show only the configurations shown in Figs. 4 and 5 that are necessary to explain the bonded state of the first wire 8 and the second wire 10.

[0093] The bonded state of the first wires 8 of the semiconductor device 1 according to the first embodiment will be described with reference to FIG.

[0094] A first wire 8 is bonded to the second conductive layer 192. The first wire 8 has a bonding portion 83 that contacts the second conductive layer 192. The bonding portion 83 is formed by so-called ball bonding. The bonding portion 83 is bonded to the second conductive layer 192 at a distance from a boundary 85 between the second conductive layer 192 and the third conductive layer 193 in the stacking direction of the first conductive section 200. Therefore, a part of the second conductive layer 192 is interposed between a bonding surface 84 of the bonding portion 83 and the boundary 85, and the bonding portion 83 is not in direct contact with the third conductive layer 193.

[0095] Furthermore, the bonding surface 84 of the first wire 8 has a diameter φ3 that is larger than the diameter φ1 of the first wire 8. The diameter φ3 of the bonding surface 84 is, for example, 150 μm or more and 160 μm or less. As a result, in the stacking direction of the first conductive section 200, the bonding surface 84 of the first wire 8 may cover 100 to 200 contact plugs 11 (source trenches 18). Note that in FIG. 6, for clarity, the source trenches 18 are shown at a larger ratio than the first wire 8.

[0096] Additionally, the second conductive layer 192 is selectively recessed in an area in contact with the bonding surface 84 of the first wire 8, and the periphery thereof is selectively raised. In this embodiment, the second conductive layer 192 may include a bonding portion 86 sandwiched between the bonding surface 84 of the first wire 8 and the third conductive layer 193, and a raised portion 87 formed around the bonding portion 86. The thickness T1 of the bonding portion 86 (the distance from the boundary 85 to the bonding surface 84) is smaller than the thickness T2 of the raised portion 87 (the distance from the boundary 85 to the top of the raised portion 87).

[0097] Next, the bonded state of the second wire 10 of the semiconductor device 1 according to the first embodiment will be described with reference to FIG.

[0098] A second wire 10 is bonded to the fifth conductive layer 196. The second wire 10 has a bonding portion 88 that contacts the fifth conductive layer 196. The bonding portion 88 is formed by so-called ball bonding. The bonding portion 88 is bonded to the fifth conductive layer 196 at a distance from a boundary 89 between the fifth conductive layer 196 and the sixth conductive layer 197 in the stacking direction of the second conductive portion 201. Therefore, a part of the fifth conductive layer 196 is interposed between a bonding surface 90 of the bonding portion 88 and the boundary 89, and the bonding portion 88 is not in direct contact with the sixth conductive layer 197.

[0099] The bonding surface 90 of the second wire 10 has a diameter φ4 that is larger than the diameter φ2 of the second wire 10. The diameter φ4 of the bonding surface 90 is, for example, not less than 150 μm and not more than 160 μm.

[0100] Furthermore, the fifth conductive layer 196 has a selective recess in the region that contacts the bonding surface 90 of the second wire 10, and a selective protrusion around the recess. In this embodiment, the fifth conductive layer 196 may include a bonding portion 91 sandwiched between the bonding surface 90 of the second wire 10 and the sixth conductive layer 197, and a protrusion 92 formed around the bonding portion 91. A thickness T3 of the bonding portion 91 (the distance from the boundary 89 to the bonding surface 90) is smaller than a thickness T4 of the protrusion 92 (the distance from the boundary 89 to the top of the protrusion 92).

[0101] As described above, according to the semiconductor device 1, a Cu wire is used as the first wire 8. For example, when an Au wire is used as the bonding wire, Au is expensive and its cost is unstable due to price fluctuations, and in high-temperature environments, the wire is prone to peeling due to compound growth between gold and aluminum. Furthermore, when an Al wire is used as the bonding wire, aluminum has a relatively low melting point and is prone to recrystallization in high-temperature environments. By using a Cu wire as the first wire, it is possible to provide a semiconductor device with higher reliability than when an Au wire or an Al wire is used.

[0102] On the other hand, the first wire 8 is joined to the second conductive layer 192 by solid-state bonding such as solid-state diffusion bonding, friction welding, ultrasonic bonding, etc. Therefore, stress is applied to the element structure including the transistor cell 14 due to heat generated when the first wire 8 (Cu wire) is solid-state bonded to the second conductive layer 192, a load applied in the stacking direction of the conductive layer 19, and a load due to vibration applied in a direction perpendicular to the stacking direction of the conductive layer 19.

[0103] In this regard, in this embodiment, a third conductive layer 193 is formed between the first conductive layer 191 and the second conductive layer 192 below the first conductive region 51. As a result, the force applied when the first wire 8 (Cu wire) is joined to the second conductive layer 192 is alleviated by the third conductive layer 193. This makes it possible to alleviate the stress load on the element structure including the transistor cell 14, thereby providing a highly reliable semiconductor device 1.

[0104] Furthermore, when recesses such as source trenches 18 are formed on the first main surface 12A of the semiconductor chip 12 as in this embodiment, the shape of the recesses may be inherited by the first conductive layer 191 and the second conductive layer 192. For example, as shown in FIGS. 4 and 5 , a contact plug 11 formed by filling the source trench 18 with a conductive material may have a recessed upper surface 111. The shape of the upper surface 111 may be inherited by the first conductive layer 191 as a recess 202 and further by the second conductive layer 192 as a recess 203. When the recesses 202 and 203 are formed in this manner, the load due to stress during bonding of the Cu wire becomes larger than when no recesses are formed, which may cause cracks to occur in the interlayer insulating film 17 directly below the conductive layer 19. The semiconductor device 1 according to this embodiment is effective even for a structure that is prone to such large stress loads, and as a result, a highly reliable semiconductor device 1 can be provided.

[0105] Furthermore, in a miniaturized structure in which multiple source trenches 18 are arranged at a pitch P2 of 1 μm or less, the load due to stress when bonding the Cu wire tends to be large, but the semiconductor device 1 according to this embodiment can also solve this problem.

[0106] Furthermore, with regard to the thickness of third conductive layer 193 and first barrier layer 194, which are multiple conductive layers harder than Cu (copper), upper third conductive layer 193, which is relatively close to bonding surface 84 of first wire 8, is formed thinner than lower first barrier layer 194, which is farther from bonding surface 84 than third conductive layer 193. This makes third conductive layer 193 more susceptible to damage due to an impact when bonding first wire 8. As a result, stress when bonding first wire 8 can be dispersed throughout first conductive layer 191, making it possible to provide a semiconductor device with higher reliability.

[0107] Furthermore, in the semiconductor device 1, the conductive layer on the semiconductor chip 12 has a layered structure in which a first barrier layer 194 (Ti / TiN), a first conductive layer 191 (AlCu), a third conductive layer 193 (Ti / TiN), and a second conductive layer 192 (AlCu) are layered in this order. In other words, layers made of two types of conductive material are alternately layered on the semiconductor chip 12. This allows stresses within these conductive layers to be canceled out, thereby reducing stress (e.g., film stress) applied to the semiconductor chip 12. This reduces warpage of the semiconductor chip 12, thereby providing a highly reliable semiconductor device 1.

[0108] Similarly, a sixth conductive layer 197 is also formed below the second conductive region 52 between the fourth conductive layer 195 and the fifth conductive layer 196. This allows the sixth conductive layer 197 to mitigate the force applied when the second wire 10 (Cu wire) is joined to the fifth conductive layer 196.

[0109] Next, a method for manufacturing the semiconductor device 1 will be described with reference to Figures 8A, 8B to 18A and 18B. Figures 8A, 8B to 18A and 18B are longitudinal cross-sectional views showing some of the manufacturing steps of the semiconductor device 1 in the order of steps. Figures 8A to 18A are longitudinal cross-sectional views of a portion corresponding to line IV-IV in Figure 2. Figures 8B to 18B are longitudinal cross-sectional views of a portion corresponding to line VV in Figure 3.

[0110] 8A and 8B, in manufacturing the semiconductor device 1, first, a semiconductor wafer (not shown) is prepared. Next, a p-type epitaxial layer 60 is formed on the semiconductor wafer. A first main surface of the epitaxial layer and a second main surface opposite thereto may correspond to the first main surface 12A and the second main surface 12B, respectively. Next, p-type impurities and n-type impurities are selectively implanted into a surface layer portion of the first main surface 12A of the epitaxial layer 60, thereby forming a p-type first impurity region 121 and an n-type second impurity region 122. Furthermore, a p-type third impurity region 123 is formed in the remaining region of the epitaxial layer 60. In this way, a semiconductor chip 12 including the epitaxial layer 60 is formed.

[0111] 9A and 9B, the gate trench 15 is formed. For example, a photoresist (not shown) is formed on the first main surface 12A of the semiconductor chip 12, and the gate trench 15 is selectively formed by etching via the photoresist.

[0112] 10A and 10B, the first main surface 12A of the semiconductor chip 12 and the inner surface of the gate trench 15 are oxidized by heat treatment such as thermal oxidation. As a result, a gate insulating film 16 is formed on the first main surface 12A and the inner surface of the gate trench 15.

[0113] 11A and 11B, gate electrode 13 is formed. A polysilicon film is formed on gate insulating film 16 by, for example, a CVD method. Thereafter, unnecessary portions of the polysilicon film are removed by etching or the like, thereby forming gate electrode 13.

[0114] Next, with reference to FIGS. 12A and 12B, interlayer insulating film 17 is formed on first main surface 12A so as to cover gate insulating film 16 and gate electrode 13, for example, by a CVD method.

[0115] Next, with reference to FIGS. 13A and 13B, interlayer insulating film 17, gate insulating film 16, first impurity region 121, and second impurity region 122 are partially etched to form source trench 18.

[0116] Next, referring to FIGS. 14A and 14B, a first barrier material layer 300 is formed. The first barrier material layer 300 is formed by depositing an electrode material using, for example, a sputtering method. The first barrier material layer 300 includes, for example, a material containing Ti. The first barrier material layer 300 may have a laminated structure of a Ti film and a TiN film by first forming a Ti film by a sputtering method on the Ti film. The first barrier material layer 300 is continuously formed between the inner surface of the source trench 18 and the upper surface of the interlayer insulating film 17 so as to be in contact with these surfaces.

[0117] 15A and 15B, contact plugs 11 are formed in the source trenches 18. For example, an electrode material is deposited on the first barrier material layer 300 by using a CVD method or the like. Thereafter, unnecessary portions of the electrode material are removed by etching or the like, and the electrode material remaining in the source trenches 18 is formed as contact plugs 11. The contact plugs 11 include, for example, a material containing W.

[0118] 16A and 16B, a first conductive material layer 301 is formed. For example, the first conductive material layer 301 is formed by depositing an electrode material on the first barrier material layer 300 and the contact plug 11 using a sputtering method or the like. The first conductive material layer 301 may contain, for example, AlCu.

[0119] 17A and 17B, a second barrier material layer 302 is formed. The second barrier material layer 302 includes, for example, a material containing Ti. The second barrier material layer 302 may have a laminated structure of a Ti film and a TiN film, formed by first forming a Ti film by sputtering and then forming a TiN film on the Ti film by sputtering. Using the same material for the second barrier material layer 302 as for the first barrier material layer 300 allows for the reuse of materials, thereby improving the productivity of the semiconductor device 1.

[0120] 18A and 18B, the second conductive material layer 303 is formed. For example, the second conductive material layer 303 is formed by depositing an electrode material on the second barrier material layer 302 using a sputtering method or the like. The second conductive material layer 303 may contain, for example, AlCu. By using the same material for the second conductive material layer 303 as for the first conductive material layer 301, it is possible to reuse the material, thereby improving the productivity of the semiconductor device 1.

[0121] 18B, second conductive material layer 303, second barrier material layer 302, first conductive material layer 301, and first barrier material layer 300 are selectively etched to separate these layers 300-303 into a plurality of regions. This forms first conductive portion 200 and second conductive portion 201 of conductive layer 19. Thereafter, an insulating material is deposited to cover conductive layer 19, and the insulating material is selectively etched to form insulating film 62 having first opening 621 and second opening 622.

[0122] Next, a drain electrode layer (not shown) is formed on the back surface of the semiconductor wafer by vapor deposition, sputtering, plating, or the like, and then a plurality of semiconductor devices 1 are cut out from the semiconductor wafer. The semiconductor device 1 is manufactured through the steps including those described above.

[0123] [Second embodiment] Next, a cross-sectional structure of a semiconductor device 20 according to a second embodiment of the present disclosure will be described with reference to Fig. 19. Fig. 19 is a schematic cross-sectional view of the semiconductor device 20 according to the second embodiment of the present disclosure.

[0124] The semiconductor device 1 of the first embodiment described above has a MISFET having a trench gate structure as an element structure, but the semiconductor device 20 has a MISFET having a planar gate structure.

[0125] In the semiconductor device 20, the second impurity region 122 is selectively formed in a surface layer portion of the first main surface 12A of the semiconductor chip 12 below the first conductive region 51. The multiple second impurity regions 122 are formed at intervals from one another. The first impurity region 121 is formed in a surface layer portion of the second impurity region 122 at an interval from the periphery of the second impurity region 122 to the inside of the second impurity region 122. The first impurity region 121 is formed, for example, in a ring shape. A portion of the second impurity region 122 is exposed from the first main surface 12A through the central portion of the first impurity region 121 as a contact portion 125. In the second impurity region 122, a region between the periphery of the first impurity region 121 and the periphery of the second impurity region 122 is a channel region 126.

[0126] In this manner, each second impurity region 122 and the first impurity region 121 within the second impurity region 122 form a transistor cell 25 of the semiconductor device 20. The arrangement pattern of the transistor cells 25 may also be a staggered pattern, a matrix pattern, a stripe pattern, or the like, as in the first embodiment.

[0127] The third impurity region 123 is formed in a surface layer portion of the second main surface 12B of the semiconductor chip 12 so as to contact the second impurity region 122. A portion of the third impurity region 123 is exposed from the first main surface 12A via a gap between adjacent second impurity regions 122.

[0128] The gate insulating film 16 is formed on the first main surface 12A of the semiconductor chip 12 so as to cover the channel region 126. The gate insulating film 16 extends across adjacent second impurity regions 122. The gate electrode 13 is formed on the gate insulating film 16 and faces the channel region 126 with the gate insulating film 16 interposed therebetween.

[0129] The interlayer insulating film 17 is formed on the first main surface 12A of the semiconductor chip 12 so as to cover the gate electrode 13. The interlayer insulating film 17 has contact holes 127 formed therein to expose the first impurity region 121 and the second impurity region 122 (contact portions 125).

[0130] The first barrier layer 194 has one and the other surfaces formed to conform to the inner surface of the contact hole 127 and the upper surface of the interlayer insulating film 17, and is in direct electrical contact with the first impurity region 121 and the second impurity region 122.

[0131] The first conductive layer 191 is formed on the first barrier layer 194. The first conductive layer 191 is electrically connected to the first impurity region 121 and the second impurity region 122 via the first barrier layer 194.

[0132] The second conductive layer 192 is formed on the first conductive layer 191 with the third conductive layer 193 interposed therebetween. The second conductive layer 192 is a surface conductive layer forming the outermost surface of the first conductive section 200, and is the layer to which the above-mentioned first wire 8 is connected. Therefore, the upper surface of the second conductive layer 192 is exposed as the first pad 7. The second conductive layer 192 is electrically connected to the first impurity region 121 and the second impurity region 122 via the first barrier layer 194, the third conductive layer 193, and the first conductive layer 191.

[0133] The third conductive layer 193 is formed between the first conductive layer 191 and the second conductive layer 192 and is sandwiched between the first conductive layer 191 and the second conductive layer 192 .

[0134] As described above, the contact hole 127 is formed in the interlayer insulating film 17. Therefore, a recess 205 may be formed in the upper surface of the first conductive layer 191 at a position facing the contact hole 127 in the stacking direction of the first conductive unit 200. Furthermore, a recess 206 may be formed in the upper surface of the second conductive layer 192 at a position facing the contact hole 127 in the stacking direction of the first conductive unit 200. Furthermore, a recess 207 may be formed in the upper surface of the third conductive layer 193 at a position facing the upper surface 111 in the stacking direction of the first conductive unit 200.

[0135] As described above, in this semiconductor device 20 as well, the third conductive layer 193 is formed between the first conductive layer 191 and the second conductive layer 192 below the first conductive region 51. As a result, the force applied when the first wire 8 (Cu wire) is joined to the second conductive layer 192 is alleviated by the third conductive layer 193. This makes it possible to alleviate the stress load on the element structure including the transistor cell 25, thereby providing a highly reliable semiconductor device 20.

[0136] Furthermore, when the recesses 205 to 207 are formed in the first conductive part 200, the load due to stress when bonding the Cu wire increases compared to when no recesses are formed, and cracks may occur in the interlayer insulating film 17 directly below the conductive layer 19. The semiconductor device 20 according to this embodiment is effective even for a structure that is prone to a large load due to such stress, and as a result, a highly reliable semiconductor device 20 can be provided.

[0137] Furthermore, in the semiconductor device 20, the conductive layer on the semiconductor chip 12 has a layered structure in which a first barrier layer 194 (Ti / TiN), a first conductive layer 191 (AlCu), a third conductive layer 193 (Ti / TiN), and a second conductive layer 192 (AlCu) are layered in this order. In other words, layers made of two types of conductive material are alternately layered on the semiconductor chip 12. This allows stresses within these conductive layers to be canceled out, thereby reducing stress (e.g., film stress) applied to the semiconductor chip 12. This reduces warpage of the semiconductor chip 12, thereby providing a highly reliable semiconductor device 20.

[0138] Although one embodiment of the present disclosure has been described above, the present disclosure can be embodied in other forms.

[0139] For example, it is possible to adopt a configuration in which the conductivity types of the semiconductor portions of the semiconductor devices 1 and 20 are reversed. For example, in the semiconductor devices 1 and 20, the p-type portions may be n-type, and the n-type portions may be p-type.

[0140] In addition, in the above-described embodiments, a MISFET was used as an example of the element structure of the semiconductor devices 1 and 20, but the element structure of the semiconductor devices 1 and 20 may also be, for example, an IGBT (Insulated Gate Bipolar Transistor), a pn diode, a Schottky barrier diode, etc.

[0141] In addition, various design modifications can be made within the scope of the claims.

[0142] This application corresponds to Patent Application No. 2020-126710 filed with the Japan Patent Office on July 27, 2020, the entire disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0143] 1: semiconductor device, 3: semiconductor element, 8: first wire, 10: second wire, 11: contact plug, 12: semiconductor chip, 12A: first main surface, 12B: second main surface, 13: gate electrode, 14: transistor cell, 15: gate trench, 16: gate insulating film, 17: interlayer insulating film, 18: source trench, 19: conductive layer, 20: semiconductor device, 25: transistor cell, 51: first conductive region, 52: second conductive region, 83: junction, 84: junction surface, 85: boundary, 86: junction, 87: protrusion, 88: junction, 89: boundary, 90: junction surface, 91: junction, 92: protrusion, 111: upper surface, 121: first impurity region, 122: second impurity region, 123: third impurity region, 124: channel region, 126: channel region, 191: first conductive layer, 192: second conductive layer, 193: third conductive layer, 194: first barrier layer, 195: fourth conductive layer, 196: fifth conductive layer, 197: sixth conductive layer, 198: second barrier layer, 200: first conductive portion, 201: second conductive portion, 202: recess, 203: recess, 204: recess, 205: recess, 206: recess, 207: recess, P1: pitch, P2: pitch, T1: thickness, T2: thickness, T3: thickness, T4: thickness, φ1: diameter, φ2: diameter, φ3: diameter, φ4: diameter

Claims

1. a semiconductor chip having an element formation surface on which an element structure is formed; a first conductive layer formed on the element forming surface of the semiconductor chip; a second conductive layer formed on the first conductive layer; a first wire connected to the second conductive layer and made of a material primarily composed of copper; a third conductive layer formed between the first conductive layer and the second conductive layer and including a material harder than copper; the thickness of the second conductive layer is smaller than the thickness of the first conductive layer; the thickness of the third conductive layer is smaller than the thickness of either the first conductive layer or the second conductive layer; the element structure includes a recess formed in the semiconductor chip and a conductive embedding body embedded in the recess; the first conductive layer covers the recess; the semiconductor chip includes a semiconductor region made of a semiconductor material; The recessed portion includes a groove portion provided in the semiconductor region.

2. The semiconductor device according to claim 1 , further comprising a fourth conductive layer formed between said semiconductor chip and said first conductive layer, said fourth conductive layer including a material harder than copper.

3. The semiconductor device according to claim 2 , wherein said fourth conductive layer includes the same material as said third conductive layer.

4. 4. The semiconductor device according to claim 2, wherein the thickness of said third conductive layer is equal to or less than the thickness of said fourth conductive layer.

5. the element structure includes a first region of a first conductivity type and a second region of a second conductivity type in contact with the first region, each of the first region and the second region being exposed in the recess; 5. The semiconductor device according to claim 1, wherein the embedded body is electrically connected to the first region and the second region.

6. an insulating layer formed between the semiconductor chip and the first conductive layer; a recess that penetrates the insulating layer and reaches a partway through the thickness of the semiconductor chip; a fourth conductive layer formed to conform to the inner surface of the recess and the upper surface of the insulating layer, the fourth conductive layer including a material harder than copper; a conductive embedding body embedded in the recess via the fourth conductive layer, the semiconductor chip includes a semiconductor region made of a semiconductor material; The semiconductor device according to claim 1 , wherein said recessed portion reaches said semiconductor region through said element formation surface.

7. 7. The semiconductor device according to claim 1, wherein a plurality of said recesses are arranged at a pitch of 1 μm or less.

8. a fifth conductive layer formed on the element forming surface of the semiconductor chip and separated from the first conductive layer; a sixth conductive layer formed on the fifth conductive layer; a second wire connected to the sixth conductive layer; 5. The semiconductor device according to claim 1, further comprising: a seventh conductive layer formed between said fifth conductive layer and said sixth conductive layer, said seventh conductive layer including a material harder than copper.

9. The semiconductor device according to claim 8 , wherein the diameter of said second wire is the same as the diameter of said first wire.

10. The semiconductor device according to claim 8 , wherein the second wire includes a wire made of a material containing copper as a main component.

11. The device structure is A gate electrode; a first impurity region and a second impurity region formed in the semiconductor chip and conducting through a channel formed by application of a voltage to the gate electrode; the first wire is electrically connected to the first impurity region via the second conductive layer and the first conductive layer; 11. The semiconductor device according to claim 8, wherein the second wire is electrically connected to the gate electrode via the sixth conductive layer and the fifth conductive layer.

12. 12. The semiconductor device according to claim 1, wherein the third conductive layer contains at least one of Ti and W.

13. 13. The semiconductor device according to claim 1, wherein the third conductive layer has a thickness of 700 Å or less.

14. 14. The semiconductor device according to claim 1, wherein the first conductive layer and the second conductive layer are formed of the same material.

15. The semiconductor device according to claim 14 , wherein the first conductive layer and the second conductive layer contain AlCu.

16. 16. The semiconductor device according to claim 1, wherein the second conductive layer has a thickness of 2 μm or more and 4.5 μm or less.

17. A semiconductor device according to any one of claims 1 to 16, wherein the second conductive layer has a first thickness at the joint with the first wire and a second thickness greater than the first thickness around the periphery of the joint.

18. A semiconductor device according to any one of claims 1 to 17, wherein in the stacking direction of the first conductive layer, the second conductive layer and the third conductive layer, a bonding surface where the first wire connects to the second conductive layer covers a plurality of the recesses.

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