solar cells

Abstract

To provide a solar cell capable of improving performance. [Solution] The solar cell includes a semiconductor substrate (11), a first conductivity type semiconductor layer (25), a thin-film electrode layer (28), a lower metal electrode layer (29l), and an upper metal electrode layer (29u) arranged in a first region (7) on the back surface of the substrate (11), and a second conductivity type semiconductor layer (35), a thin-film electrode layer (38), a lower metal electrode layer (39l), and an upper metal electrode layer (39u) arranged in a second region (8) on the back surface of the substrate (11), the upper metal electrode layers (29u, 39u) being plated metal layers. When the semiconductor substrate (11) is of the first conductivity type, a plated metal film (50) is arranged on the periphery of the lower metal electrode layer (29l) in the first region (7), and no plated metal film is arranged on the periphery of the lower metal electrode layer (39l) in the second region (8). When the semiconductor substrate (11) is of the second conductivity type, a plated metal film (50) is arranged on the periphery of the lower metal electrode layer (39l) in the second region (8), and no plated metal film is arranged on the periphery of the lower metal electrode layer (29l) in the first region (7).

Description

[Technical Field]

[0001] The present invention relates to a back electrode type (back contact type) solar cell. [Background technology]

[0002] Solar cells using semiconductor substrates include double-sided electrode solar cells in which electrodes are formed on both the light-receiving surface and the back surface, and back-surface electrode solar cells in which electrodes are formed only on the back surface. In double-sided electrode solar cells, electrodes are formed on the light-receiving surface, which blocks sunlight. On the other hand, back-surface electrode solar cells do not have electrodes on the light-receiving surface, so they have a higher sunlight reception rate than double-sided electrode solar cells. Patent Document 1 discloses a back-surface electrode solar cell.

[0003] The solar cell described in Patent Document 1 includes a semiconductor substrate (photoelectric conversion layer), a first conductivity type semiconductor layer and a first electrode layer stacked in this order on the back surface of the semiconductor substrate, and a second conductivity type semiconductor layer and a second electrode layer stacked in this order on another part of the back surface of the semiconductor substrate. The first electrode layer and the second electrode layer are separated from each other to prevent short circuits. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-131586 Summary of the Invention [Problem to be solved by the invention]

[0005] Generally, each of the first and second electrode layers includes a transparent electrode layer (thin film electrode layer) and a metal electrode layer. The metal electrode layer can be formed relatively easily and separately, for example, by a screen printing method using silver paste. On the other hand, the transparent electrode layer must be formed separately by, for example, a photolithography method using a mask, and the formation process is relatively complicated.

[0006] Furthermore, further performance improvements are required for back electrode solar cells. In this regard, the present inventors have devised a method for improving the performance of solar cells by increasing the reflection on the back surface and increasing the re-entry of light into the photoelectric conversion layer.

[0007] An object of the present invention is to provide a solar cell that can improve its performance. [Means for solving the problem]

[0008] The solar cell of the present invention is a back electrode type solar cell comprising: a semiconductor substrate; a first conductivity type semiconductor layer arranged in a first region that is a part of one main surface side of the semiconductor substrate; a second conductivity type semiconductor layer arranged in a second region that is another part of the one main surface side of the semiconductor substrate; a first thin-film electrode layer, a first lower-layer metal electrode layer, and a first upper-layer metal electrode layer corresponding to the first conductivity type semiconductor layer; and a second thin-film electrode layer, a second lower-layer metal electrode layer, and a second upper-layer metal electrode layer corresponding to the second conductivity type semiconductor layer, wherein the first thin-film electrode layer, the first lower-layer metal electrode layer, and the first upper-layer metal electrode layer are strip-shaped, the second thin-film electrode layer, the second lower-layer metal electrode layer, and the second upper-layer metal electrode layer are strip-shaped, and the first upper-layer metal electrode layer and the second upper-layer metal electrode layer are plated metal layers. When the semiconductor substrate is of a first conductivity type, a plated metal film is disposed on the periphery of the first lower-layer metal electrode layer in the first region, and a plated metal film is not disposed on the periphery of the second lower-layer metal electrode layer in the second region.When the semiconductor substrate is of a second conductivity type, a plated metal film is disposed on the periphery of the second lower-layer metal electrode layer in the second region, and a plated metal film is not disposed on the periphery of the first lower-layer metal electrode layer in the first region. [Effects of the Invention]

[0009] According to the present invention, the performance of solar cells can be improved. [Brief explanation of the drawings]

[0010] [Figure 1]1 is a side view illustrating an example of a solar cell module according to an embodiment of the present invention. [Figure 2] 1 is a view of the solar cell according to the first embodiment as seen from the back surface side. [Figure 3] 3 is a cross-sectional view of the solar cell of FIG. 2 taken along line III-III. [Figure 4] FIG. 3 is an enlarged view of part IV in the solar cell of FIG. 2. [Figure 5A] 3A to 3C are diagrams illustrating a semiconductor layer forming step in the method for manufacturing a solar cell according to the first embodiment. [Figure 5B] 3A to 3C are diagrams illustrating a thin conductive film forming step in the solar cell manufacturing method according to the first embodiment. [Figure 5C] 3A to 3C are diagrams illustrating a lower metal electrode layer forming step in the method for manufacturing the solar cell according to the first embodiment. [Figure 5D] 3A to 3C are diagrams illustrating a thin-film electrode layer forming step in the method for manufacturing a solar cell according to the first embodiment. [Figure 5E] 5A to 5C are diagrams illustrating an upper metal electrode layer forming step in the method for manufacturing the solar cell according to the first embodiment. [Figure 6A] 1 shows the results of observing the metal electrode layer and the space between the metal electrode layers on the back side of the solar cell of the example at 100x magnification using an SEM. [Figure 6B] This is the result of observing the portion A between the metal electrode layers in FIG. 6A using an SEM at a magnification of 450 times. [Figure 6C] This is the result of observing the portion B between the metal electrode layers in FIG. 6B using an SEM at a magnification of 5000 times. [Figure 7A] 7 shows the results of observing the portion VII in FIG. 4, which includes the metal electrode layer and the space between the metal electrode layers on the back side of the solar cell of the example, at a magnification of 20 times using a laser microscope. [Figure 7B] This is the result of observing the portion A between the metal electrode layers in FIG. 7A using a laser microscope at a magnification of 100 times. [Figure 8] 1 shows the measurement results of performance characteristics of the solar cell of the example. [Figure 9] FIG. 10 is a view of the solar cell according to the second embodiment as seen from the back surface side. [Figure 10] 10 is a cross-sectional view of the solar cell of FIG. 9 taken along line XX. [Figure 11] FIG. 10 is an enlarged view of a portion XI in the solar cell of FIG. [Figure 12A] 10A to 10C are diagrams illustrating a semiconductor layer forming step in a method for manufacturing a solar cell according to a second embodiment. [Figure 12B] 10A to 10C are diagrams illustrating a thin-film conductive film forming step in the solar cell manufacturing method according to the second embodiment. [Figure 12C] 10A to 10C are diagrams illustrating a thin-film electrode layer forming step in the solar cell manufacturing method according to the second embodiment. [Figure 12D] 10A to 10C are diagrams illustrating a thin-film electrode layer forming step in the solar cell manufacturing method according to the second embodiment. [Figure 12E] 10A to 10C are diagrams illustrating a thin-film electrode layer forming step in the solar cell manufacturing method according to the second embodiment. [Figure 12F] FIG. 10 is a diagram showing a lower metal electrode layer forming step in the method for manufacturing a solar cell according to the second embodiment. [Figure 12G] FIG. 10 is a diagram showing an upper metal electrode layer forming step in the method for manufacturing a solar cell according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] An example of an embodiment of the present invention will be described below with reference to the accompanying drawings. The same or equivalent parts in each drawing are designated by the same reference numerals. For convenience, hatching and reference numerals may be omitted. In such cases, reference should be made to other drawings.

[0012] (solar cell module) 1 is a side view showing an example of a solar cell module according to this embodiment. The solar cell module 100 includes a plurality of solar cells 1 arranged two-dimensionally.

[0013] The solar cells 1 are connected in series and / or parallel by the wiring members 2. Specifically, the wiring members 2 are connected to busbar portions (described later) in the electrode layers of the solar cells 1 via conductive adhesive members. The wiring members 2 are, for example, known interconnectors such as tabs. Examples of conductive adhesive members that can be used include conductive films such as resin films containing metal fine particles, conductive pastes containing metal fine particles, and solder pastes containing solder particles. Among these, solder pastes are preferred from the viewpoints of adhesion and low contact resistance.

[0014] The solar cell 1 and wiring member 2 are sandwiched between a light-receiving surface protection member 3 and a back surface protection member 4. A liquid or solid sealing material 5 is filled between the light-receiving surface protection member 3 and the back surface protection member 4, thereby sealing the solar cell 1 and wiring member 2. The light-receiving surface protection member 3 is, for example, a glass substrate, and the back surface protection member 4 is, for example, a glass substrate or a metal plate. The sealing material 5 is, for example, a transparent resin. Hereinafter, a first embodiment and a second embodiment of the solar cell (hereinafter referred to as solar cell) 1 will be described in detail.

[0015] [First embodiment] (solar cells) Figure 2 is a view of the solar cell according to the first embodiment as seen from the back surface side. The solar cell 1 shown in Figure 2 is a back electrode type solar cell. The solar cell 1 includes a semiconductor substrate 11 having two main surfaces, and the main surface of the semiconductor substrate 11 has a first conductivity type region 7 (hereinafter also referred to as the first region) and a second conductivity type region 8 (hereinafter also referred to as the second region).

[0016] The first conductivity type region 7 has a so-called comb shape and includes a plurality of finger portions 7f corresponding to the teeth of the comb and busbar portions 7b corresponding to supports for the teeth of the comb. The busbar portions 7b extend in a first direction (X direction) along one side of the semiconductor substrate 11, and the finger portions 7f extend from the busbar portions 7b in a second direction (Y direction) that intersects with the first direction.

[0017] Similarly, the second conductivity type region 8 has a so-called comb shape and includes a plurality of finger portions 8f corresponding to the teeth of the comb and busbar portions 8b corresponding to supports for the teeth of the comb. The busbar portions 8b extend in a first direction (X direction) along one side of the semiconductor substrate 11 opposite the other side, and the finger portions 8f extend in a second direction (Y direction) from the busbar portions 8b.

[0018] The finger portions 7f and the finger portions 8f are strip-shaped and extend in the second direction (Y direction), and are provided alternately in the first direction (X direction). The first conductivity type regions 7 and the second conductivity type regions 8 may be formed in stripes.

[0019] Fig. 3 is a cross-sectional view of the solar cell of Fig. 2 taken along line III-III, and Fig. 4 is an enlarged view of portion IV of the solar cell of Fig. 2. As shown in Fig. 3, solar cell 1 includes a passivation layer 13 laminated on the light-receiving surface side of semiconductor substrate 11, which is the light-receiving principal surface. Solar cell 1 also includes a passivation layer 23, a first-conductivity-type semiconductor layer 25, and a first electrode layer 27 laminated in this order on a first-conductivity-type region 7, which is part of the back surface side, which is the principal surface (one principal surface) of semiconductor substrate 11 opposite the light-receiving surface. Solar cell 1 also includes a passivation layer 33, a second-conductivity-type semiconductor layer 35, and a second electrode layer 37 laminated in this order on a second-conductivity-type region 8, which is another part of the back surface side of semiconductor substrate 11.

[0020] The semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate obtained by doping a crystalline silicon material with an n-type dopant. The semiconductor substrate 11 may also be a p-type semiconductor substrate obtained by doping a crystalline silicon material with a p-type dopant. An example of an n-type dopant is phosphorus (P). An example of a p-type dopant is boron (B). The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light-receiving surface side and generates photocarriers (electrons and holes).

[0021] By using crystalline silicon as the material for the semiconductor substrate 11, dark current is relatively small, and a relatively high output (stable output regardless of illuminance) can be obtained even when the intensity of incident light is low.

[0022] The semiconductor substrate 11 may have a pyramidal fine uneven structure called a texture structure on the back side, which increases the recovery efficiency of light that passes through the semiconductor substrate 11 without being absorbed.

[0023] Furthermore, semiconductor substrate 11 may have a pyramidal fine uneven structure called a texture structure on the light-receiving surface side, which reduces the reflection of incident light on the light-receiving surface and improves the light trapping effect in semiconductor substrate 11.

[0024] Passivation layer 13 is formed on the light-receiving surface side of semiconductor substrate 11. Passivation layer 23 is formed in first conductivity type region 7 on the back surface side of semiconductor substrate 11. Passivation layer 33 is formed in second conductivity type region 8 on the back surface side of semiconductor substrate 11. Passivation layers 13, 23, and 33 are formed of, for example, an intrinsic (i-type) amorphous silicon material. Passivation layers 13, 23, and 33 suppress recombination of carriers generated in semiconductor substrate 11 and increase carrier collection efficiency.

[0025] An anti-reflection layer made of a material such as SiO, SiN, or SiON may be provided on passivation layer 13 on the light-receiving surface side of semiconductor substrate 11.

[0026] The first conductivity type semiconductor layer 25 is formed on the passivation layer 23, i.e., in the first conductivity type region 7 on the back surface side of the semiconductor substrate 11. The first conductivity type semiconductor layer 25 is formed of, for example, an amorphous silicon material. The first conductivity type semiconductor layer 25 is a p-type semiconductor layer obtained by doping, for example, an amorphous silicon material with a p-type dopant (for example, the above-mentioned boron (B)).

[0027] The second conductivity type semiconductor layer 35 is formed on the passivation layer 33, i.e., in the second conductivity type region 8 on the back surface side of the semiconductor substrate 11. The second conductivity type semiconductor layer 35 is formed of, for example, an amorphous silicon material. The second conductivity type semiconductor layer 35 is, for example, an n-type semiconductor layer in which an amorphous silicon material is doped with an n-type dopant (for example, the above-mentioned phosphorus (P)). The first conductivity type semiconductor layer 25 may be an n-type semiconductor layer, and the second conductivity type semiconductor layer 35 may be a p-type semiconductor layer.

[0028] The first conductivity type semiconductor layer 25 and the passivation layer 23, and the second conductivity type semiconductor layer 35 and the passivation layer 33 form strips extending in the second direction (Y direction) and are arranged alternately in the first direction (X direction). Parts of the second conductivity type semiconductor layer 35 and the passivation layer 33 may overlap parts of the adjacent first conductivity type semiconductor layer 25 and the passivation layer 23 (not shown).

[0029] The first electrode layer 27 corresponds to the first conductivity type semiconductor layer 25, specifically, is formed on the first conductivity type semiconductor layer 25 in the first conductivity type region 7 on the back surface side of the semiconductor substrate 11. The second electrode layer 37 corresponds to the second conductivity type semiconductor layer 35, specifically, is formed on the second conductivity type semiconductor layer 35 in the second conductivity type region 8 on the back surface side of the semiconductor substrate 11. The first electrode layer 27 has a first thin-film electrode layer 28 and a first metal electrode layer 29 stacked in this order on the first conductivity type semiconductor layer 25. The second electrode layer 37 has a second thin-film electrode layer 38 and a second metal electrode layer 39 stacked in this order on the second conductivity type semiconductor layer 35.

[0030] The first metal electrode layer 29 has a two-layer structure of a first lower metal electrode layer 29l and a first upper metal electrode layer 29u, and the second metal electrode layer 39 has a two-layer structure of a second lower metal electrode layer 39l and a second upper metal electrode layer 39u.

[0031] The first thin-film electrode layer 28 and the second thin-film electrode layer 38 may be transparent electrode layers made of a transparent conductive material, or may be layers made of a non-transparent conductive material. Examples of transparent conductive materials include ITO (Indium Tin Oxide: a composite oxide of indium oxide and tin oxide). Examples of non-transparent conductive materials include a metal thin film (e.g., a copper thin film).

[0032] The first lower metal electrode layer 29l and the second lower metal electrode layer 39l are formed of a conductive paste material containing a particulate metal material such as silver, copper, or aluminum, an insulating material such as resin, and a solvent. The first upper metal electrode layer 29u and the second upper metal electrode layer 39u are formed of a plated metal layer such as copper.

[0033] The first electrode layer 27 and the second electrode layer 37 are strip-shaped extending in the second direction (Y direction) and are alternately arranged in the first direction (X direction). That is, the first thin-film electrode layer 28 and the second thin-film electrode layer 38 are strip-shaped extending in the second direction (Y direction) and are alternately arranged in the first direction (X direction). Furthermore, the first lower-layer metal electrode layer 29l and the second lower-layer metal electrode layer 39l are strip-shaped extending in the second direction (Y direction) and are alternately arranged in the first direction (X direction). Furthermore, the first upper-layer metal electrode layer 29u and the second upper-layer metal electrode layer 39u are strip-shaped extending in the second direction (Y direction) and are alternately arranged in the first direction (X direction). The first thin-film electrode layer 28 and the second thin-film electrode layer 38 are separated from each other, the first lower metal electrode layer 29l and the second lower metal electrode layer 39l are also separated from each other, and the first upper metal electrode layer 29u and the second upper metal electrode layer 39u are also separated from each other.

[0034] The width in the first direction (X direction) of the first thin-film electrode layer 28 is narrower than the width in the first direction (X direction) of the first lower-layer metal electrode layer 29l, and the width in the first direction (X direction) of the second thin-film electrode layer 38 is narrower than the width in the first direction (X direction) of the second lower-layer metal electrode layer 39l.

[0035] An insulating film 40 is formed on the periphery of the first lower metal electrode layer 29l and the periphery of the second lower metal electrode layer 39l, where the insulating material in the conductive paste material of the first lower metal electrode layer 29l and the second lower metal electrode layer 39l is unevenly distributed (details will be described later).

[0036] A part of the first conductivity type semiconductor layer 25 and a part of the second conductivity type semiconductor layer 35 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l are covered with the insulating film 40. More specifically, the valleys of the uneven structure (textured structure) of the first conductivity type semiconductor layer 25 and the valleys of the uneven structure of the second conductivity type semiconductor layer 35 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l are covered with the insulating film 40. On the other hand, the tops of the uneven structure of the first conductivity type semiconductor layer 25 and the tops of the uneven structure of the second conductivity type semiconductor layer 35 between the first metal electrode layer 29l and the second metal electrode layer 39 are not covered with the insulating film 40.

[0037] Thin-film conductive films 48 made of the same material as the first thin-film electrode layer 28 and the second thin-film electrode layer 38 are arranged in island shapes (discontinuously) between the first conductivity-type semiconductor layer 25 and the insulating film 40 and between the second conductivity-type semiconductor layer 35 and the insulating film 40. More specifically, thin-film conductive films 48 are arranged in island shapes between the valleys of the uneven structure of the first conductivity-type semiconductor layer 25 and the insulating film 40 and between the valleys of the uneven structure of the second conductivity-type semiconductor layer 35 and the insulating film 40.

[0038] When the semiconductor substrate 11 is of a second conductivity type (e.g., n-type), a plated metal film 50 is arranged in an island shape around the periphery of the second lower metal electrode layer 39l in the second conductivity type region 8. On the other hand, no plated metal film is arranged around the periphery of the first lower metal electrode layer 29l in the first conductivity type region 7. The periphery of the second lower metal electrode layer 39l is in a range of 100 μm to 300 μm from the end of the second lower metal electrode layer 39l, and the periphery of the first lower metal electrode layer 29l is in a range of 100 μm to 300 μm from the end of the first lower metal electrode layer 29l.

[0039] In other words, when the semiconductor substrate 11 is of the second conductivity type (e.g., n-type), a portion of the second conductivity type semiconductor layer 35 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l is covered with the plated metal film 50, and the plated metal film 50 is in contact with the island-shaped thin-film conductive film 48. On the other hand, the first conductivity type semiconductor layer 25 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l is not covered with the plated metal film.

[0040] More specifically, when the semiconductor substrate 11 is of the second conductivity type (e.g., n-type), the tops of the concave-convex structure of the second conductivity type semiconductor layer 35 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l are covered with the plated metal film 50, and the plated metal film 50 is in contact with the thin-film conductive film 48 arranged in islands in the valleys of the concave-convex structure of the second conductivity type semiconductor layer 35. On the other hand, the tops of the concave-convex structure of the first conductivity type semiconductor layer 25 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l are not covered with the plated metal film.

[0041] On the other hand, when the semiconductor substrate 11 is of the first conductivity type (for example, p-type) (not shown), the plated metal film 50 is arranged in an island shape around the periphery of the first lower metal electrode layer 29l in the first conductivity type region 7. On the other hand, no plated metal film is arranged around the periphery of the second lower metal electrode layer 39l in the second conductivity type region 8.

[0042] In other words, when the semiconductor substrate 11 is of a first conductivity type (e.g., p-type) (not shown), a portion of the first conductivity type semiconductor layer 25 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l is covered with a plated metal film 50, and the plated metal film 50 is in contact with the island-shaped thin-film conductive film 48. On the other hand, the second conductivity type semiconductor layer 35 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l is not covered with a plated metal film.

[0043] More specifically, when the semiconductor substrate 11 is of a first conductivity type (e.g., p-type) (not shown), the tops of the concave-convex structure of the first conductivity type semiconductor layer 25 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l are covered with a plated metal film 50, and the plated metal film 50 is in contact with the thin-film conductive film 48 arranged in islands in the valleys of the concave-convex structure of the first conductivity type semiconductor layer 25. On the other hand, the tops of the concave-convex structure of the second conductivity type semiconductor layer 35 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l are not covered with a plated metal film.

[0044] Next, a method for manufacturing a solar cell according to the first embodiment will be described with reference to Figures 5A to 5E. Figure 5A is a diagram showing a semiconductor layer formation step in the method for manufacturing a solar cell according to the first embodiment, and Figure 5B is a diagram showing a thin-film conductive layer formation step in the method for manufacturing a solar cell according to the first embodiment. Figure 5C is a diagram showing a lower-layer metal electrode layer formation step in the method for manufacturing a solar cell according to the first embodiment, and Figure 5D is a diagram showing a thin-film electrode layer formation step in the method for manufacturing a solar cell according to the first embodiment. Figure 5E is a diagram showing an upper-layer metal electrode layer formation step in the method for manufacturing a solar cell according to the first embodiment. Figures 5A to 5E show the back side of semiconductor substrate 11, and the front side of semiconductor substrate 11 is omitted.

[0045] First, as shown in FIG. 5A, a passivation layer 23 and a first conductivity type semiconductor layer 25 are formed on a portion of the back surface side of a semiconductor substrate 11 having an uneven structure (textured structure) on at least the back surface side, specifically in the first conductivity type region 7 (semiconductor layer formation process).

[0046] For example, a passivation film and a first conductivity type semiconductor film may be formed on the entire back surface of semiconductor substrate 11 by CVD or PVD, and then passivation layer 23 and first conductivity type semiconductor layer 25 may be patterned by etching using a mask or a metal mask generated by photolithography. Note that examples of etching solutions for p-type semiconductor films include acidic solutions such as hydrofluoric acid containing ozone and a mixture of nitric acid and hydrofluoric acid, and examples of etching solutions for n-type semiconductor films include alkaline solutions such as an aqueous solution of potassium hydroxide.

[0047] Alternatively, when a passivation layer and a first conductivity type semiconductor layer are stacked on the back side of the semiconductor substrate 11 using a CVD method or a PVD method, the passivation layer 23 and the first conductivity type semiconductor layer 25 may be deposited and patterned simultaneously using a mask.

[0048] Next, a passivation layer 33 and a second conductivity type semiconductor layer 35 are formed on another part of the back surface side of the semiconductor substrate 11, specifically on the second conductivity type region 8 (semiconductor layer forming step).

[0049] For example, as described above, a passivation film and a second conductivity type semiconductor film may be formed on the entire back surface of semiconductor substrate 11 using a CVD method or a PVD method, and then passivation layer 33 and second conductivity type semiconductor layer 35 may be patterned using an etching method that uses a mask or a metal mask generated using photolithography technology.

[0050] Alternatively, when a passivation layer and a second conductivity type semiconductor layer are stacked on the back side of the semiconductor substrate 11 using a CVD method or a PVD method, the passivation layer 33 and the second conductivity type semiconductor layer 35 may be deposited and patterned simultaneously using a mask.

[0051] In this semiconductor layer forming step, a passivation layer 13 (not shown) may be formed on the entire light-receiving surface side of the semiconductor substrate 11.

[0052] 5B, a thin-film conductive film 28Z is formed on and across the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 (thin-film conductive film forming process). The thin-film conductive film 28Z can be formed by, for example, a CVD method or a PVD method.

[0053] Next, as shown in FIG. 5C, a first lower metal electrode layer 29l is formed on the first conductivity type semiconductor layer 25 in the first conductivity type region 7 via the thin-film conductive film 28Z, and a second lower metal electrode layer 39l is formed on the second conductivity type semiconductor layer 35 in the second conductivity type region 8 via the thin-film conductive film 28Z (lower metal electrode layer formation process).

[0054] The first lower metal electrode layer 29l and the second lower metal electrode layer 39l are formed by printing a printing material (e.g., ink). Methods for forming the first lower metal electrode layer 29l and the second lower metal electrode layer 39l include screen printing, inkjet printing, gravure coating, and dispenser methods. Among these, screen printing is preferred.

[0055] The printing material contains particulate (e.g., spherical) metal material in an insulating material. For example, the weight ratio of the metal material contained in the printing material is 85% or more and 95% or less of the total printing material. The printing material may contain a solvent or the like to adjust viscosity or coatability.

[0056] Examples of insulating materials include matrix resins, etc. More specifically, the insulating resin is preferably a polymer compound, and particularly preferably a thermosetting resin or an ultraviolet-curing resin, and representative examples thereof include epoxy, urethane, polyester, and silicone-based resins.

[0057] Examples of the metal material include silver, copper, aluminum, etc. Among these, a silver paste containing silver particles is preferred.

[0058] Next, after printing the first lower metal electrode layer 29l and the second lower metal electrode layer 39l, the insulating resin in the first lower metal electrode layer 29l and the second lower metal electrode layer 39l is cured by a heat treatment or an ultraviolet irradiation treatment. At this time, the insulating resin material seeps out to the peripheries of the first lower metal electrode layer 29l and the second lower metal electrode layer 39l, and an insulating film 40 made of the insulating material unevenly distributed around the peripheries of the first lower metal electrode layer 29l and the second lower metal electrode layer 39l is formed.

[0059] At this time, the valleys of the uneven structure (textured structure) of the thin-film conductive film 28Z between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l are covered with the insulating film 40. On the other hand, the peaks of the uneven structure of the thin-film conductive film 28Z between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l are not covered with the insulating film 40 and are exposed.

[0060] The first lower metal electrode layer 29l and the second lower metal electrode layer 39l formed from the conductive paste may contain urethane bonds. For example, compared to epoxy resin, urethane resin shrinks less during crosslinking and is less likely to crack. Resistance to cracking in the resin prevents the etching solution from seeping into the metal electrode layer, preventing peeling of the metal electrode layer and deterioration of long-term reliability due to etching of the thin conductive film underneath the metal electrode layer.

[0061] 5D, the thin-film conductive film 28Z is patterned by etching using the first lower-layer metal electrode layer 29l and its peripheral insulating film 40, and the second lower-layer metal electrode layer 39l and its peripheral insulating film 40 as a mask, thereby forming the first thin-film electrode layer 28 and the second thin-film electrode layer 38 that are separated from each other (thin-film electrode layer forming step). The etching method may be, for example, wet etching, and the etching solution may be an acid solution such as hydrochloric acid (HCl).

[0062] At this time, etching of the thin-film conductive film 28Z progresses from the peaks to the valleys of the textured structure between the first lower-layer metal electrode layer 29l and the second lower-layer metal electrode layer 39l. Here, to separate the first thin-film electrode layer 28 and the second thin-film electrode layer 38, the thin-film conductive film between them need only be discontinuous, and the thin-film conductive film 48 may remain in the shape of islands in the valleys of the textured structure. When the thin-film conductive film 48 remains in the shape of islands in the valleys of the textured structure, the insulating film 40 in the valleys of the textured structure remains on the first-conductivity-type semiconductor layer 25 and the second-conductivity-type semiconductor layer 35.

[0063] 5E, a first upper metal electrode layer 29u is formed on the first lower metal electrode layer 29l in the first conductivity-type region 7, and a second upper metal electrode layer 39u is formed on the second lower metal electrode layer 39l in the second conductivity-type region 8 by electroplating (upper metal electrode layer forming step). As a result, a first metal electrode layer 29 composed of the first lower metal electrode layer 29l and the first upper metal electrode layer 29u is obtained, and a first electrode layer 27 composed of the first thin-film electrode layer 28 and the first metal electrode layer 29 is obtained. Furthermore, a second metal electrode layer 39 composed of the second lower metal electrode layer 39l and the second upper metal electrode layer 39u is obtained, and a second electrode layer 37 composed of the second thin-film electrode layer 38 and the second metal electrode layer 39 is obtained.

[0064] At this time, if the semiconductor substrate 11 is of the second conductivity type (e.g., n-type), it is considered that, in the electrolytic plating method, the current flowing through the second lower metal electrode layer 39l also flows through the second conductivity type semiconductor layer 35 and the semiconductor substrate 11 to the thin-film conductive film 48 arranged in islands around the second lower metal electrode layer 39l in the second conductivity type region 8, and plated metal film 50 grows from the thin-film conductive film 48. As a result, plated metal film 50 is formed in islands around the second lower metal electrode layer 39l in the second conductivity type region 8.

[0065] On the other hand, when the semiconductor substrate 11 is of the second conductivity type (e.g., n-type), a pn junction exists between the first conductivity type semiconductor layer 25 and the semiconductor substrate 11, and therefore, in the electrolytic plating method, the current flowing in the first lower metal electrode layer 29l does not flow through the first conductivity type semiconductor layer 25 and the semiconductor substrate 11 to the thin-film conductive film 48 arranged in islands around the first lower metal electrode layer 29l in the first conductivity type region 7, and even if it does flow, the current is small, and it is thought that the plated metal film 50 does not grow from the thin-film conductive film 48. As a result, a plated metal film is not formed around the first lower metal electrode layer 29l in the first conductivity type region 7.

[0066] More specifically, when the semiconductor substrate 11 is of the second conductivity type (e.g., n-type), the tops of the concave-convex structure of the second conductivity type semiconductor layer 35 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l are covered with the plated metal film 50, and the plated metal film 50 is in contact with the thin-film conductive film 48 arranged in islands in the valleys of the concave-convex structure of the second conductivity type semiconductor layer 35. On the other hand, the tops of the concave-convex structure of the first conductivity type semiconductor layer 25 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l are not covered with the plated metal film.

[0067] On the other hand, when the semiconductor substrate 11 is of the first conductivity type (for example, p-type) (not shown), the plated metal film 50 is formed in an island shape around the periphery of the first lower metal electrode layer 29l in the first conductivity type region 7. On the other hand, no plated metal film is formed around the periphery of the second lower metal electrode layer 39l in the second conductivity type region 8.

[0068] More specifically, when the semiconductor substrate 11 is of a first conductivity type (e.g., p-type) (not shown), the tops of the concave-convex structure of the first conductivity type semiconductor layer 25 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l are covered with a plated metal film 50, and the plated metal film 50 is in contact with the thin-film conductive film 48 arranged in islands in the valleys of the concave-convex structure of the first conductivity type semiconductor layer 25. On the other hand, the tops of the concave-convex structure of the second conductivity type semiconductor layer 35 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l are not covered with a plated metal film. Through the above steps, the back electrode type solar cell 1 of the first embodiment is completed.

[0069] Here, for example, the method for manufacturing a solar cell includes a thin-film electrode layer forming step after the thin-film conductive film forming step and before the lower metal electrode layer forming step. In the thin-film electrode layer forming step, the thin-film conductive film is patterned using, for example, photolithography to form the first thin-film electrode layer and the second thin-film electrode layer that are separated from each other. - A resist is applied onto the thin conductive film, By exposing the resist to light, openings are formed in the resist, forming a first thin-film electrode layer and a second thin-film electrode layer separated from each other by etching the thin-film conductive film exposed in the opening using the resist as a mask; Remove the resist.

[0070] In contrast, the solar cell manufacturing method of this embodiment includes a lower-layer metal electrode layer forming step and a thin-film electrode layer forming step, in this order, after the thin-film conductive film forming step. In the thin-film electrode layer forming step, the first lower-layer metal electrode layer 29l and the second lower-layer metal electrode layer 39l formed in the lower-layer metal electrode layer forming step are used as masks to pattern the thin-film conductive film 28Z, thereby forming the first thin-film electrode layer 28 and the second thin-film electrode layer 38, which are separated from each other. As a result, the solar cell manufacturing method of this embodiment does not require the use of photolithography using a mask, as in the conventional method, and can simplify and shorten the formation of the thin-film electrode layers. As a result, it is possible to reduce the cost of solar cells and solar cell modules.

[0071] Here, if the thin-film conductive film 28Z is patterned using the first lower-layer metal electrode layer 29l and the second lower-layer metal electrode layer 39l as a mask, the thin-film conductive film 28Z below the first lower-layer metal electrode layer 29l and the second lower-layer metal electrode layer 39l will also be etched when the thin-film conductive film 28Z is etched, which may result in peeling off of the first thin-film electrode layer 28 and the first lower-layer metal electrode layer 29l, and the second thin-film electrode layer 38 and the second lower-layer metal electrode layer 39l.

[0072] In this regard, according to the solar cell manufacturing method of the present embodiment, in the lower-layer metal electrode layer forming step, a printing material containing a particulate metal material, an insulating material, and a solvent is printed and cured to form insulating film 40 in which the insulating material is unevenly distributed around the periphery of first lower-layer metal electrode layer 29l and the periphery of second lower-layer metal electrode layer 39l, and in the thin-film electrode layer forming step, thin-film conductive film 28Z is patterned using first lower-layer metal electrode layer 29l and the insulating film 40 around its periphery and second lower-layer metal electrode layer 39l and the insulating film 40 around its periphery as masks. This suppresses etching of thin-film conductive film 28Z below first lower-layer metal electrode layer 29l and second lower-layer metal electrode layer 39l, and suppresses peeling of first thin-film electrode layer 28 and first lower-layer metal electrode layer 29l and second thin-film electrode layer 38 and second lower-layer metal electrode layer 39l.

[0073] In the solar cell 1 manufactured by such a manufacturing method, the band width of the first thin-film electrode layer 28 is narrower than the band width of the first lower-layer metal electrode layer 29l, the band width of the second thin-film electrode layer 38 is narrower than the band width of the second lower-layer metal electrode layer 39l, and an insulating film 40 is formed around the periphery of the first lower-layer metal electrode layer 29l and the periphery of the second lower-layer metal electrode layer 39l, where the insulating material in the printing material of the first lower-layer metal electrode layer 29l and the second lower-layer metal electrode layer 39l is unevenly distributed. In a solar cell manufactured by the above-described method of manufacturing a solar cell using photolithography, the band width of the thin-film electrode layer is generally wider than the band width of the metal electrode layer.

[0074] Furthermore, in the solar cell 1 manufactured by the manufacturing method of this embodiment, a part of the first conductivity type semiconductor layer 25 and a part of the second conductivity type semiconductor layer 35 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l are covered with the insulating film 40. More specifically, the valleys of the uneven structure (textured structure) of the first conductivity type semiconductor layer 25 and the valleys of the uneven structure of the second conductivity type semiconductor layer 35 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l are covered with the insulating film 40.

[0075] Furthermore, thin-film conductive films 48 made of the same material as the first thin-film electrode layer 28 and the second thin-film electrode layer 38 are arranged in island shapes (discontinuously) between the first conductivity-type semiconductor layer 25 and the insulating film 40 and between the second conductivity-type semiconductor layer 35 and the insulating film 40. More specifically, the thin-film conductive films 48 are arranged in island shapes between the valleys of the uneven structure of the first conductivity-type semiconductor layer 25 and the insulating film 40 and between the valleys of the uneven structure of the second conductivity-type semiconductor layer 35 and the insulating film 40. This reduces the exposed areas of the first conductivity-type semiconductor layer 25 and the second conductivity-type semiconductor layer 35. This suppresses deterioration of the solar cell and the solar cell module, improving the reliability (e.g., long-term durability) of the solar cell and the solar cell module.

[0076] Furthermore, according to the manufacturing method of the solar cell of this embodiment, in the upper metal electrode layer formation process, the first upper metal electrode layer 29u, which is a plated metal layer, is formed on the first lower metal electrode layer 29l in the first conductivity type region 7 by electroplating, and the second upper metal electrode layer 39u, which is a plated metal layer, is formed on the second lower metal electrode layer 39l in the second conductivity type region 8 by electroplating. At this time, when the semiconductor substrate 11 is of the second conductivity type (e.g., n-type), the plated metal film 50 is formed in an island shape around the periphery of the second lower metal electrode layer 39l in the second conductivity type region 8. On the other hand, no plated metal film is formed around the periphery of the first lower metal electrode layer 29l in the first conductivity type region 7. On the other hand, when the semiconductor substrate 11 is of the first conductivity type (for example, p-type) (not shown), the plated metal film 50 is formed in an island shape around the periphery of the first lower metal electrode layer 29l in the first conductivity type region 7. On the other hand, no plated metal film is formed around the periphery of the second lower metal electrode layer 39l in the second conductivity type region 8.

[0077] In the solar cell 1 manufactured by such a manufacturing method, the first metal electrode layer 29 and the second metal electrode layer 39 include plated metal layers, so that the resistance of the first electrode layer 27 and the second electrode layer 37 can be reduced compared to when the first metal electrode layer 29 and the second metal electrode layer 39 are formed from a printing material such as silver paste. Furthermore, since the first metal electrode layer 29 and the second metal electrode layer 39 include plated metal layers, it is possible to reduce the use of relatively expensive printing materials such as silver paste, thereby enabling the solar cell 1 and solar cell module 100 to be produced at lower prices.

[0078] Furthermore, in the solar cell 1 manufactured by the manufacturing method of this embodiment, for example, when the semiconductor substrate 11 is of a second conductivity type (e.g., n-type), the plated metal film 50 is arranged in an island shape around the periphery of the second lower metal electrode layer 39l in the second conductivity type region 8. This increases reflection on the back surface side and re-incidence into the photoelectric conversion layer, thereby enabling the performance of the solar cell 1 and the solar cell module 100 to be improved.

[0079] Furthermore, in the solar cell 1 manufactured by the manufacturing method of this embodiment, for example, when the semiconductor substrate 11 is of a second conductivity type (e.g., n-type), a portion of the second conductivity type semiconductor layer 35 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l is covered with a plated metal film 50, and the plated metal film 50 is in contact with the thin-film conductive film 48 arranged in an island shape. More specifically, the peaks of the uneven structure of the second conductivity type semiconductor layer 35 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l are covered with the plated metal film 50, and the plated metal film 50 is in contact with the thin-film conductive film 48 arranged in an island shape in the valleys of the uneven structure of the second conductivity type semiconductor layer 35. This increases reflection on the back surface side and increases re-entry into the photoelectric conversion layer, resulting in improved performance of the solar cell 1 and the solar cell module 100.

[0080] On the other hand, in the solar cell 1 manufactured by the manufacturing method of this embodiment, when the semiconductor substrate 11 is of the second conductivity type (e.g., n-type), for example, no plated metal film is disposed around the periphery of the first lower metal electrode layer 29l in the first conductivity type region 7. This makes it possible to avoid a short circuit between the first electrode layer 27 and the second electrode layer 37.

[0081] Furthermore, in the solar cell 1 manufactured by the manufacturing method of this embodiment, for example, when the semiconductor substrate 11 is of a second conductivity type (e.g., n-type), the first conductivity type semiconductor layer 25 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l is not covered with a plated metal film. More specifically, the top of the uneven structure of the first conductivity type semiconductor layer 25 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l is not covered with a plated metal film. This makes it possible to avoid a short circuit between the first electrode layer 27 and the second electrode layer 37.

[0082] The above-mentioned effects will be verified below. (Verification example 1) A passivation layer 23, a first conductivity-type semiconductor layer 25, a passivation layer 33, a second conductivity-type semiconductor layer 35, and a thin-film conductive film (transparent conductive film) 28Z were formed on the back surface of a semiconductor substrate 11 having a pyramidal texture structure on the back surface. Then, using a screen printing method using silver paste, a first lower metal electrode layer 29l was formed on the first conductivity-type semiconductor layer 25 via the thin-film conductive film 28Z, and a second lower metal electrode layer 39l was formed on the second conductivity-type semiconductor layer 35 via the thin-film conductive film 28Z. Then, the first lower metal electrode layer 29l and the second lower metal electrode layer 39l were heat-treated in an oven at 180°C for one hour. As a result, the insulating material (resin material) in the printing material seeped out onto the periphery of the first lower metal electrode layer 29l and the periphery of the second lower metal electrode layer 39l, and an insulating film (resin film) 40 was formed on the periphery of the first lower metal electrode layer 29l and the periphery of the second lower metal electrode layer 39l.

[0083] The back side of the solar cell fabricated as described above, before patterning of the thin-film conductive film (transparent conductive film), was observed using an SEM (field emission scanning electron microscope S4800, manufactured by Hitachi High-Technologies Corporation). The results are shown in Figures 6A to 6C. Figure 6A shows the metal electrode layer and the space between the metal electrode layers on the back side of the solar cell of the verification example, observed using an SEM at 100x magnification. Figure 6B shows the area A between the metal electrode layers in Figure 6A, observed using an SEM at 450x magnification. Figure 6C shows the area B between the metal electrode layers in Figure 6B, observed using an SEM at 5000x magnification.

[0084] 6A to 6C, it was confirmed that an insulating film (resin film) 40 (black portion) made of an insulating material (resin material) unevenly distributed was formed on the periphery of the first lower-layer metal electrode layer 29l and the periphery of the second lower-layer metal electrode layer 39l. It was also confirmed that the valleys of the uneven structure (textured structure) of the thin-film conductive film (transparent conductive film) 28Z between the first lower-layer metal electrode layer 29l and the second lower-layer metal electrode layer 39l were covered with the insulating film 40 (black portion). On the other hand, it was confirmed that the tops of the uneven structure of the thin-film conductive film 28Z between the first lower-layer metal electrode layer 29l and the second lower-layer metal electrode layer 39l were not covered with the insulating film (resin film) 40 and were exposed. Therefore, it is expected that etching of the thin-film conductive film 28Z will proceed from the top to the bottom of the uneven structure during the subsequent etching in the thin-film electrode layer formation process.

[0085] Next, the back side of the solar cell on which the thin-film conductive film (transparent conductive film) had been patterned was observed using an SEM, with the lower metal electrode layer as a mask, and it was confirmed that the insulating film (resin film) 40 remained unpeeled in the valleys of the uneven structure between the first metal electrode layer 29 and the second metal electrode layer 39. Furthermore, a check for short circuits between the electrodes was performed, and it was confirmed that there were no short circuits between the electrode layers. Since the insulating film 40 was not peeled off and there were no short circuits between the electrode layers, it is expected that the thin-film conductive film (transparent conductive film) 48 remains in island shapes between the valleys of the uneven structure of the first conductivity-type semiconductor layer 25 and the insulating film 40, and between the valleys of the uneven structure of the second conductivity-type semiconductor layer 35 and the insulating film 40, thereby maintaining the insulating film 40.

[0086] (Verification example 2) Next, by electrolytic plating, a first upper metal electrode layer 29u was formed on the first lower metal electrode layer 29l, and a second upper metal electrode layer 39u was formed on the second lower metal electrode layer 39l. The electrolytic plating conditions were as follows: (Electrolytic Plating Conditions for First Upper Metal Electrode Layer 29u on P-Type Semiconductor Layer 25) First, current 500mA, time 20s Then, current 3350mA, time 280s ·Charge amount 945C (Electrolytic Plating Conditions for Second Upper Metal Electrode Layer 39u on N-Type Semiconductor Layer 35) First, current 500mA, time 20s Then, current 3350mA, time 280s ·Charge amount 945C

[0087] The back side of the solar cell fabricated as described above was observed using a laser microscope (LEXT OLS4100, manufactured by Olympus Corporation). The results are shown in Figures 7A and 7B. Figure 7A shows the result of observing part VII in Figure 4, which includes the metal electrode layer and the space between the metal electrode layers on the back side of the solar cell of the verification example, using a laser microscope at 20x magnification. Figure 7B shows the result of observing part A between the metal electrode layers in Figure 7A using a laser microscope at 100x magnification.

[0088] 7A and 7B, when the semiconductor substrate 11 is of the second conductivity type (e.g., n-type), it was confirmed that the plated metal film 50 is arranged in an island shape around the periphery of the second lower metal electrode layer 39l in the second conductivity type region 8. It was also confirmed that the above-mentioned insulating film (resin film) 40 (black portion) is arranged in the portion other than the plated metal film 50. This suggests that the tops of the uneven structure of the second conductivity type semiconductor layer 35 are covered with the plated metal film 50.

[0089] On the other hand, it was confirmed that no plated metal film was disposed around the periphery of the first lower metal electrode layer 29l in the first conductivity type region 7. This suggests that the tops of the uneven structure of the first conductivity type semiconductor layer 25 in the first conductivity type region 7 are not covered with a plated metal film.

[0090] (Verification example 3) Next, the performance characteristics of the solar cells of Example 1 and Comparative Example 1 were measured. As Example 1, a solar cell shown in Figures 3 and 4 was used, which had a first metal electrode layer 29 made of a first lower metal electrode layer 29l (Ag paste) and a first upper metal electrode layer 29u (Cu plating), and a second metal electrode layer 39 made of a second lower metal electrode layer 39l (Ag paste) and a second upper metal electrode layer 39u (Cu plating), both of which were prepared as described above.

[0091] As Comparative Example 1, a solar cell was used which had a first metal electrode layer 29 consisting only of a first lower metal electrode layer 29l (Ag paste) and a second metal electrode layer 39 consisting only of a second lower metal electrode layer 39l (Ag paste) before the first upper metal electrode layer 29u (Cu plated) and the second upper metal electrode layer 39u (Cu plated) were formed in Example 1.

[0092] The measurements were performed using a pulse solar simulator with an AM1.5 spectral distribution, emitting simulated sunlight at 100mW / cm at 25°C. 2 The performance characteristics (open circuit voltage Voc, short circuit current Isc, fill factor FF, and conversion efficiency Eff) of the solar cells of the above examples and comparative examples were measured. The measurement results are shown in FIG. In FIG. 8, the output characteristic result of Comparative Example 1 was set as the standard (1.00) and the measurement results of Example 1 were compared to evaluate the correlation of the outputs.

[0093] As shown in FIG. 8, in Example 1, the fill factor FF increased, and as a result, since the first metal electrode layer 29 and the second metal electrode layer 39 include a plated metal layer, it is possible to reduce the resistance of the first electrode layer 27 and the second electrode layer 37.

[0094] Furthermore, the short-circuit current Isc increased in Example 1. This shows that, for example, when the semiconductor substrate 11 is of the second conductivity type (e.g., n-type), the plated metal film 50 is arranged in an island shape around the periphery of the second lower metal electrode layer 39l in the second conductivity type region 8, increasing reflection on the back surface side and re-incidence into the photoelectric conversion layer, thereby enabling the performance of the solar cell 1 and the solar cell module 100 to be improved.

[0095] [Second embodiment] (solar cells) Fig. 9 is a view of the solar cell according to the second embodiment as seen from the back surface side, Fig. 10 is a cross-sectional view of the solar cell of Fig. 9 taken along line XX, and Fig. 11 is an enlarged view of part XI in the solar cell of Fig. 9. Note that the uneven structure (textured structure) on the back surface side and front surface side is not shown in Fig. 10 and Figs. 12A to 12G described below.

[0096] 10 and 11, the solar cell 1 of the second embodiment differs from the solar cell 1 of the first embodiment in that the width of the first thin-film electrode layer 28 is wider than the width of the first lower-layer metal electrode layer 29l, and the first thin-film electrode layer 28 is disposed around the periphery of the first lower-layer metal electrode layer 29l. The solar cell 1 of the second embodiment also differs from the solar cell 1 of the first embodiment in that the width of the second thin-film electrode layer 38 is wider than the width of the second lower-layer metal electrode layer 39l, and the second thin-film electrode layer 38 is disposed around the periphery of the second lower-layer metal electrode layer 38l.

[0097] Furthermore, the solar cell 1 of the second embodiment differs from the solar cell 1 of the first embodiment in that the first lower-layer metal electrode layer 29l and the second lower-layer metal electrode layer 39l are formed by a sputtering method instead of a printing method using a conductive paste material containing a particulate metal material, an insulating material such as resin, and a solvent. In this case, insulating material (resin film) 40, which is formed by unevenly distributing the insulating material (resin material) in the conductive paste material of the first lower-layer metal electrode layer 29l and the second lower-layer metal electrode layer 39l, is not formed in an island-like (discontinuous) pattern around the periphery of the first lower-layer metal electrode layer 29l and the periphery of the second lower-layer metal electrode layer 39l.

[0098] The solar cell 1 of the second embodiment also differs from the solar cell 1 of the first embodiment in that it includes a thin-film electrode layer formation step after the thin-film conductive film formation step and before the lower-layer metal electrode layer formation step, in which the thin-film conductive film is patterned using photolithography to form first and second thin-film electrode layers that are separated from each other. In this case, thin-film conductive films 48 made of the same material as the first and second thin-film electrode layers 28 and 38 are not formed in an island shape (discontinuously) around the periphery of the first lower-layer metal electrode layer 29l and the periphery of the second lower-layer metal electrode layer 39l.

[0099] Furthermore, when the semiconductor substrate 11 is of a second conductivity type (e.g., n-type), a plated metal film 50 is disposed in a planar (continuous) manner on the second thin-film electrode layer 38 in the peripheral portion of the second lower metal electrode layer 39l in the second conductivity type region 8. On the other hand, no plated metal film is disposed on the first thin-film electrode layer 28 in the peripheral portion of the first lower metal electrode layer 29l in the first conductivity type region 7.

[0100] In other words, when the semiconductor substrate 11 is of the second conductivity type (e.g., n-type), a portion of the second conductivity type semiconductor layer 35 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l is covered with the plated metal film 50, and the plated metal film 50 is in contact with the planarly arranged thin-film electrode layer 38. On the other hand, the first conductivity type semiconductor layer 25 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l is not covered with the plated metal film.

[0101] On the other hand, when the semiconductor substrate 11 is of the first conductivity type (for example, p-type) (not shown), a plated metal film 50 is disposed in a planar (continuous) manner on the first thin-film electrode layer 28 in the peripheral portion of the first lower metal electrode layer 29l in the first conductivity type region 7. On the other hand, no plated metal film is disposed on the second thin-film electrode layer 38 in the peripheral portion of the second lower metal electrode layer 39l in the second conductivity type region 8.

[0102] In other words, when the semiconductor substrate 11 is of a first conductivity type (e.g., p-type) (not shown), a portion of the first conductivity type semiconductor layer 25 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l is covered with a plated metal film 50, and the plated metal film 50 is in contact with the planarly arranged thin-film electrode layer 28. On the other hand, the second conductivity type semiconductor layer 35 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l is not covered with a plated metal film.

[0103] Next, a method for manufacturing a solar cell according to the second embodiment will be described with reference to Figures 12A to 12G. Figure 12A is a diagram showing a semiconductor layer formation step in the method for manufacturing a solar cell according to the second embodiment. Figure 12B is a diagram showing a thin-film conductive layer formation step in the method for manufacturing a solar cell according to the second embodiment, and Figures 12C to 12E are diagrams showing a thin-film electrode layer formation step in the method for manufacturing a solar cell according to the second embodiment. Figure 12F is a diagram showing a lower-layer metal electrode layer formation step in the method for manufacturing a solar cell according to the second embodiment, and Figure 12G is a diagram showing an upper-layer metal electrode layer formation step in the method for manufacturing a solar cell according to the second embodiment. Figures 12A to 12G show the back side of semiconductor substrate 11, and the front side of semiconductor substrate 11 is omitted.

[0104] First, as shown in FIG. 12A, a passivation layer 23 and a first conductivity type semiconductor layer 25 are formed on a part of the back surface side of the semiconductor substrate 11, specifically on the first conductivity type region 7 (semiconductor layer forming step).

[0105] For example, as described above, a passivation film and a first conductivity type semiconductor film may be formed on the entire back surface side of semiconductor substrate 11 using a CVD method or a PVD method, and then passivation layer 23 and first conductivity type semiconductor layer 25 may be patterned using an etching method that uses a mask or a metal mask generated using photolithography technology.

[0106] Alternatively, when a passivation layer and a first conductivity type semiconductor layer are stacked on the back side of the semiconductor substrate 11 using a CVD method or a PVD method, the passivation layer 23 and the first conductivity type semiconductor layer 25 may be deposited and patterned simultaneously using a mask.

[0107] Next, a passivation layer 33 and a second conductivity type semiconductor layer 35 are formed on another part of the back surface side of the semiconductor substrate 11, specifically on the second conductivity type region 8 (semiconductor layer forming step).

[0108] For example, as described above, a passivation film and a second conductivity type semiconductor film may be formed on the entire back surface of semiconductor substrate 11 using a CVD method or a PVD method, and then passivation layer 33 and second conductivity type semiconductor layer 35 may be patterned using an etching method that uses a mask or a metal mask generated using photolithography technology.

[0109] Alternatively, when a passivation layer and a second conductivity type semiconductor layer are stacked on the back side of the semiconductor substrate 11 using a CVD method or a PVD method, the passivation layer 33 and the second conductivity type semiconductor layer 35 may be deposited and patterned simultaneously using a mask.

[0110] In this semiconductor layer forming step, a passivation layer 13 (not shown) may be formed on the entire light-receiving surface side of the semiconductor substrate 11.

[0111] 12B, a thin-film conductive film 28Z is formed on and across the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 (thin-film conductive film forming process). The thin-film conductive film 28Z can be formed by, for example, a CVD method or a PVD method.

[0112] Next, as shown in Figures 12C to 12E, the thin-film conductive film 28Z at the boundary between the first-conductivity-type semiconductor layer 25 and the second-conductivity-type semiconductor layer 35 is removed to form a first thin-film electrode layer 28 in the first-conductivity-type region 7 and a second thin-film electrode layer 38 in the second-conductivity-type region 8 (thin-film electrode layer formation process).

[0113] 12C, for example, a resist 90 is formed using photolithography in the first conductivity type region 7 and the second conductivity type region 8 of the semiconductor substrate 11. In the photolithography technique, a resist is applied onto the thin-film conductive film 28Z, and the resist is exposed to light to form an opening in the resist.

[0114] 12D, the thin-film conductive film 28Z is patterned by an etching method using a resist 90. In the etching method, the thin-film conductive film 28Z exposed in the openings is etched using the resist 90 as a mask, thereby forming the first thin-film electrode layer 28 and the second thin-film electrode layer 38 that are separated from each other. The etching method may be, for example, a wet etching method, and the etching solution may be an acidic solution such as hydrochloric acid (HCl).

[0115] 12E, the resist 90 is peeled off and removed. Examples of a solution for removing the resist 90 include an alkaline aqueous solution such as an aqueous potassium hydroxide solution, and an organic solvent.

[0116] 12F, a first lower metal electrode layer 29l is formed on the first conductivity type semiconductor layer 25 and the first thin-film electrode layer 28 in the first conductivity type region 7, and a second lower metal electrode layer 39l is formed on the second conductivity type semiconductor layer 35 and the second thin-film electrode layer 38 in the second conductivity type region 8 (lower metal electrode layer forming step). The first lower metal electrode layer 29l and the second lower metal electrode layer 39l may be formed by sputtering or by printing the above-mentioned printing material.

[0117] 12G, a first upper metal electrode layer 29u is formed on the first lower metal electrode layer 29l in the first conductivity-type region 7, and a second upper metal electrode layer 39u is formed on the second lower metal electrode layer 39l in the second conductivity-type region 8 by electroplating (upper metal electrode layer forming step). As a result, a first metal electrode layer 29 composed of the first lower metal electrode layer 29l and the first upper metal electrode layer 29u is obtained, and a first electrode layer 27 composed of the first thin-film electrode layer 28 and the first metal electrode layer 29 is obtained. Furthermore, a second metal electrode layer 39 composed of the second lower metal electrode layer 39l and the second upper metal electrode layer 39u is obtained, and a second electrode layer 37 composed of the second thin-film electrode layer 38 and the second metal electrode layer 39 is obtained.

[0118] At this time, if the semiconductor substrate 11 is of the second conductivity type (e.g., n-type), it is considered that in the electrolytic plating method, the current flowing in the second lower metal electrode layer 39l also flows through the second conductivity type semiconductor layer 35 and the semiconductor substrate 11 to the second thin-film electrode layer 38 disposed in the periphery of the second lower metal electrode layer 39l in the second conductivity type region 8, and a plated metal film 50 grows from the second thin-film electrode layer 38. As a result, the plated metal film 50 is formed in a planar shape on the second thin-film electrode layer 38 in the periphery of the second lower metal electrode layer 39l in the second conductivity type region 8.

[0119] On the other hand, when the semiconductor substrate 11 is of the second conductivity type (e.g., n-type), a pn junction exists between the first conductivity type semiconductor layer 25 and the semiconductor substrate 11, and therefore, in the electrolytic plating method, the current flowing through the first lower metal electrode layer 29l does not flow through the first conductivity type semiconductor layer 25 and the semiconductor substrate 11 to the first thin-film electrode layer 28 disposed around the first lower metal electrode layer 29l in the first conductivity type region 7, and even if it does flow, the current is small and it is thought that a plated metal film 50 does not grow from the first thin-film electrode layer 28. As a result, a plated metal film is not formed on the first thin-film electrode layer 28 around the first lower metal electrode layer 29l in the first conductivity type region 7.

[0120] On the other hand, when the semiconductor substrate 11 is of the first conductivity type (for example, p-type) (not shown), a plated metal film 50 is formed in a planar shape on the first thin-film electrode layer 28 in the peripheral portion of the first lower metal electrode layer 29l in the first conductivity type region 7. On the other hand, no plated metal film is formed on the second thin-film electrode layer 38 in the peripheral portion of the second lower metal electrode layer 39l in the second conductivity type region 8. Through the above steps, the back electrode type solar cell 1 of the second embodiment is completed.

[0121] In the solar cell 1 of the second embodiment, for example, when the semiconductor substrate 11 is of the second conductivity type (e.g., n-type), a plated metal film 50 is disposed around the periphery of the second lower metal electrode layer 39l in the second conductivity type region 8. In other words, a portion of the second conductivity type semiconductor layer 35 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l is covered with the plated metal film 50. This increases reflection on the back surface side and re-entries light into the photoelectric conversion layer, thereby enabling the performance of the solar cell 1 and the solar cell module 100 to be improved.

[0122] Furthermore, in the solar cell 1 of the second embodiment, for example, when the semiconductor substrate 11 is of the second conductivity type (e.g., n-type), no plated metal film is disposed around the periphery of the first lower metal electrode layer 29l in the first conductivity type region 7. In other words, the first conductivity type semiconductor layer 25 between the first lower metal electrode layer 29l and the second lower metal electrode layer 39l is not covered with a plated metal film. This makes it possible to avoid a short circuit between the first electrode layer 27 and the second electrode layer 37.

[0123] In the above-described thin-film electrode layer forming step, when the first thin-film electrode layer 28 and the second thin-film electrode layer 38 are formed by removing the thin-film conductive film 28Z at the boundary between the first conductivity-type semiconductor layer 25 and the second conductivity-type semiconductor layer 35 using an etching method that uses the resist 90, depending on the degree of etching, the thin-film conductive film may remain in island shapes (discontinuous) on the first thin-film electrode layer 28 and the second thin-film electrode layer 38 between the first thin-film electrode layer 28 and the second thin-film electrode layer 38. For example, the thin-film conductive film may remain in island shapes (discontinuous) in the valleys of the uneven structure (texture structure) between the first thin-film electrode layer 28 and the second thin-film electrode layer 38.

[0124] In this case, in the upper metal electrode layer formation process using electrolytic plating, a plated metal film is formed in an island shape (discontinuous) or a planar shape (continuous) on the first conductivity type semiconductor layer 25 or the second conductivity type semiconductor layer 35 between the first thin film electrode layer 28 and the second thin film electrode layer 38.

[0125] For example, similarly to the above, when the semiconductor substrate 11 is of the second conductivity type (e.g., n-type), it is conceivable that, in the electrolytic plating method, the current flowing through the second lower metal electrode layer 39l also flows through the second conductivity type semiconductor layer 35 and the semiconductor substrate 11 to the thin-film conductive film arranged in islands on the second conductivity type semiconductor layer 35 between the first thin-film electrode layer 28 and the second thin-film electrode layer 38, causing a plated metal film to grow from the thin-film conductive film. As a result, the plated metal film 50 is formed in islands or in a planar shape on the second conductivity type semiconductor layer 35 between the first thin-film electrode layer 28 and the second thin-film electrode layer 38.

[0126] On the other hand, when semiconductor substrate 11 is of the second conductivity type (e.g., n-type), a pn junction exists between first conductivity type semiconductor layer 25 and semiconductor substrate 11, and therefore, in the electrolytic plating method, the current flowing through first lower metal electrode layer 29l does not flow through first conductivity type semiconductor layer 25 and semiconductor substrate 11 to the thin-film conductive film arranged in an island shape on first conductivity type semiconductor layer 25 between first thin-film electrode layer 28 and second thin-film electrode layer 38, and even if it does flow, the current is small, and it is thought that a plated metal film does not grow from the thin-film conductive film. As a result, a plated metal film is not formed on first conductivity type semiconductor layer 25 between first thin-film electrode layer 28 and second thin-film electrode layer 38.

[0127] More specifically, when the semiconductor substrate 11 is of the second conductivity type (e.g., n-type), the tops of the concave-convex structure of the second conductivity type semiconductor layer 35 between the first thin-film electrode layer 28 and the second thin-film electrode layer 38 are covered with the plated metal film 50 (island-shaped). Alternatively, the thin-film conductive film in the valleys of the concave-convex structure of the second conductivity type semiconductor layer 35 between the first thin-film electrode layer 28 and the second thin-film electrode layer 38 is covered with the plated metal film 50 (island-shaped). Alternatively, the thin-film conductive film in the tops and valleys of the concave-convex structure of the second conductivity type semiconductor layer 35 between the first thin-film electrode layer 28 and the second thin-film electrode layer 38 is covered with the plated metal film 50 (flat-shaped). On the other hand, the first conductivity type semiconductor layer 25 between the first thin-film electrode layer 28 and the second thin-film electrode layer 38 is not covered with the plated metal film.

[0128] On the other hand, when the semiconductor substrate 11 is of the first conductivity type (for example, p-type) (not shown), the plated metal film 50 is formed in an island or planar shape on the first conductivity type semiconductor layer 25 between the first thin-film electrode layer 28 and the second thin-film electrode layer 38. On the other hand, the plated metal film is not formed on the second conductivity type semiconductor layer 35 between the first thin-film electrode layer 28 and the second thin-film electrode layer 38.

[0129] More specifically, when the semiconductor substrate 11 is of a first conductivity type (for example, p-type) (not shown), The tops of the concave-convex structure of the first conductivity-type semiconductor layer 25 between the first thin-film electrode layer 28 and the second thin-film electrode layer 38 are covered with the plated metal film 50 (island-shaped). Alternatively, the thin-film conductive film in the valleys of the concave-convex structure of the first conductivity-type semiconductor layer 25 between the first thin-film electrode layer 28 and the second thin-film electrode layer 38 is covered with the plated metal film 50 (island-shaped). Alternatively, the thin-film conductive film in the tops and valleys of the concave-convex structure of the first conductivity-type semiconductor layer 25 between the first thin-film electrode layer 28 and the second thin-film electrode layer 38 is covered with the plated metal film 50 (flat). On the other hand, the second conductivity-type semiconductor layer 35 between the first thin-film electrode layer 28 and the second thin-film electrode layer 38 is not covered with the plated metal film.

[0130] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various modifications and variations are possible. For example, in the above-described embodiments, a heterojunction solar cell 1 is illustrated as shown in Figures 3 and 10, but the present invention is not limited to heterojunction solar cells and can be applied to various solar cells such as homojunction solar cells.

[0131] Furthermore, in the above-described embodiment, the solar cell has been illustrated as having a crystalline silicon substrate, but the solar cell is not limited to this, and may have, for example, a gallium arsenide (GaAs) substrate. [Explanation of symbols]

[0132] 1. Solar cells 2 Wiring materials 3 Photosensitive surface protection member 4 Back protection material 5. Encapsulating material 7 First conductivity type region (first region) 8 Second conductivity type region (second region) 7b, 8b busbar section 7f,8f finger part 11 Semiconductor substrate 13,23,33 Passivation layer 25 First conductivity type semiconductor layer 27 1st electrode layer 28 First thin film electrode layer 28Z Thin Conductive Film 29 First metal electrode layer 29l 1st lower metal electrode layer 29u 1st upper metal electrode layer 35 Second conductivity type semiconductor layer 37 Second electrode layer 38 Second thin film electrode layer 39 Second metal electrode layer 39l Second lower metal electrode layer 39u 2nd upper metal electrode layer 40 Insulating film 48 Thin Conductive Film 50 Plated metal film 100 solar cell modules

Claims

1. A back electrode type solar cell comprising: a semiconductor substrate; a first conductivity type semiconductor layer disposed in a first region which is a part of one main surface side of the semiconductor substrate; a second conductivity type semiconductor layer disposed in a second region which is another part of the one main surface side of the semiconductor substrate; a first thin-film electrode layer, a first lower-layer metal electrode layer, and a first upper-layer metal electrode layer corresponding to the first conductivity type semiconductor layer; and a second thin-film electrode layer, a second lower-layer metal electrode layer, and a second upper-layer metal electrode layer corresponding to the second conductivity type semiconductor layer, the first thin-film electrode layer, the first lower metal electrode layer, and the first upper metal electrode layer are strip-shaped; the second thin-film electrode layer, the second lower metal electrode layer, and the second upper metal electrode layer are strip-shaped; the first upper metal electrode layer and the second upper metal electrode layer are plated metal layers, When the semiconductor substrate is of a first conductivity type, a plated metal film is disposed on a peripheral portion of the first lower-layer metal electrode layer in the first region, and a plated metal film is not disposed on a peripheral portion of the second lower-layer metal electrode layer in the second region; When the semiconductor substrate is of a second conductivity type, a plated metal film is disposed on a peripheral portion of the second lower-layer metal electrode layer in the second region, and a plated metal film is not disposed on a peripheral portion of the first lower-layer metal electrode layer in the first region. Solar cell.

2. a width of the first thin-film electrode layer is wider than a width of the first lower-layer metal electrode layer, and the first thin-film electrode layer is disposed on the periphery of the first lower-layer metal electrode layer; a width of the second thin-film electrode layer is wider than a width of the second lower-layer metal electrode layer, and the second thin-film electrode layer is disposed on the periphery of the second lower-layer metal electrode layer; When the semiconductor substrate is of a first conductivity type, the plated metal film is disposed on the first thin-film electrode layer in a peripheral portion of the first lower-layer metal electrode layer in the first region, When the semiconductor substrate is of a second conductivity type, the plated metal film is disposed on the second thin-film electrode layer in the peripheral portion of the second lower-layer metal electrode layer in the second region. The solar cell according to claim 1 .

3. the width of the first thin-film electrode layer is narrower than the width of the first lower metal electrode layer; the width of the second thin-film electrode layer is narrower than the width of the second lower metal electrode layer; the first lower-layer metal electrode layer and the second lower-layer metal electrode layer are layers formed by printing and curing a printing material containing a particulate metal material, an insulating material, and a solvent; an insulating film formed on a periphery of the first lower-layer metal electrode layer and a periphery of the second lower-layer metal electrode layer, the insulating material being unevenly distributed in the printing material of the first lower-layer metal electrode layer and the second lower-layer metal electrode layer; The solar cell according to claim 1 .

4. When the semiconductor substrate is of a first conductivity type, the plated metal film is arranged in an island shape around the periphery of the first lower-layer metal electrode layer in the first region, When the semiconductor substrate is of a second conductivity type, the plated metal film is arranged in an island shape around the periphery of the second lower-layer metal electrode layer in the second region. The solar cell according to claim 3 .

5. a portion of the first conductivity type semiconductor layer and a portion of the second conductivity type semiconductor layer between the first lower metal electrode layer and the second lower metal electrode layer are covered with the insulating film; When the semiconductor substrate is of a first conductivity type, a portion of the first conductivity type semiconductor layer between the first lower-layer metal electrode layer and the second lower-layer metal electrode layer is covered with the plated metal film, and a portion of the second conductivity type semiconductor layer between the first lower-layer metal electrode layer and the second lower-layer metal electrode layer is not covered with the plated metal film, When the semiconductor substrate is of a second conductivity type, a portion of the second conductivity type semiconductor layer between the first lower-layer metal electrode layer and the second lower-layer metal electrode layer is covered with the plated metal film, and a portion of the first conductivity type semiconductor layer between the first lower-layer metal electrode layer and the second lower-layer metal electrode layer is not covered with the plated metal film. The solar cell according to claim 4 .

6. thin-film conductive films made of the same material as the first thin-film electrode layer and the second thin-film electrode layer are arranged in an island shape between the first conductive type semiconductor layer and the insulating film and between the second conductive type semiconductor layer and the insulating film, the plated metal film is in contact with the thin conductive film arranged in an island shape; The solar cell according to claim 5 .

7. At least one of the two main surfaces of the semiconductor substrate has an uneven structure, a valley portion of the first conductivity type semiconductor layer and a valley portion of the second conductivity type semiconductor layer between the first lower-layer metal electrode layer and the second lower-layer metal electrode layer are covered with the insulating film, a top portion of the first conductivity type semiconductor layer and a top portion of the second conductivity type semiconductor layer between the first lower metal electrode layer and the second lower metal electrode layer are not covered with the insulating film; When the semiconductor substrate is of a first conductivity type, a top portion of the first conductivity type semiconductor layer between the first lower-layer metal electrode layer and the second lower-layer metal electrode layer is covered with the plated metal film, and a top portion of the second conductivity type semiconductor layer between the first lower-layer metal electrode layer and the second lower-layer metal electrode layer is not covered with the plated metal film, When the semiconductor substrate is of a second conductivity type, a top portion of the second conductivity type semiconductor layer between the first lower-layer metal electrode layer and the second lower-layer metal electrode layer is covered with the plated metal film, and a top portion of the first conductivity type semiconductor layer between the first lower-layer metal electrode layer and the second lower-layer metal electrode layer is not covered with the plated metal film. The solar cell according to claim 4 .

8. thin-film conductive films made of the same material as the first thin-film electrode layer and the second thin-film electrode layer are arranged in an island shape between the valley portions of the first conductive type semiconductor layer and the insulating film and between the valley portions of the second conductive type semiconductor layer and the insulating film, the plated metal film is in contact with the thin conductive film arranged in an island shape; The solar cell according to claim 7 .

Images