Super-junction semiconductor device

Abstract

An object of the present invention is to provide a super-junction semiconductor device that can reduce the difference in breakdown voltage between termination regions with different structures. [Solution] The semiconductor device comprises a first semiconductor layer 2 of the first conductivity type provided on the front surface of a semiconductor substrate 1 of a first conductivity type, the first semiconductor layer 2 having a lower impurity concentration than the semiconductor substrate 1; a second semiconductor layer 70 of the first conductivity type provided on the front surface of the first semiconductor layer 2, the second semiconductor layer 70 having a lower impurity concentration than the first semiconductor layer 2; and a parallel pn region 20 in which first column regions 3 of the first conductivity type and second column regions 3 of the second conductivity type provided in the second semiconductor layer 70 are repeatedly arranged alternately in a direction parallel to the front surface, the depths of the first column regions 3 and second column regions 4 of the parallel pn region 20 becoming shallower in stages as they approach the terminal portion, and a part of the parallel pn region 20 located at the bottom or outermost position is formed in a ring shape at a fixed distance from the active region 50 and is connected to parallel columns of the same conductivity type.

Description

[Technical Field]

[0001] This disclosure relates to super-junction semiconductor devices. [Background technology]

[0002] Conventionally, in super-junction semiconductor devices, a technique is known in which the depths from the surface of the n-type column region and the p-type column region of the parallel pn region become gradually shallower as they move outward (see, for example, Patent Document 1 below). Another technique is known in which an uppermost p-type layer ring and a central p-type layer ring are provided in a portion of the parallel pn region of the termination region (see, for example, Patent Document 2 below). Another technique is known in which n-type columns and p-type columns are provided in an annular shape in the edge termination region to surround the active region (see, for example, Patent Document 3 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-135674 [Patent Document 2] Japanese Patent Application Publication No. 2019-021788 [Patent Document 3] Japanese Patent Application Publication No. 2023-132670 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional super junction semiconductor devices, the termination region can be divided into two types of structures: one in which the pn column region is parallel to the drift layer, and one in which the pn column region is horizontally aligned. However, each structure has different depletion layer expansion patterns and electric field distributions, which makes the design more complex. This disclosure aims to provide a super junction semiconductor device that can reduce the difference in breakdown voltage between termination regions with different structures. [Means for solving the problem]

[0005] To solve the above-mentioned problems and achieve the object of the present disclosure, a super-junction semiconductor device according to the present disclosure has the following features: It is a semiconductor device having an active region through which current flows, and a termination structure disposed outside the active region and having a breakdown voltage structure surrounding the periphery of the active region. The termination structure includes: a first semiconductor layer of a first conductivity type provided on a front surface of a semiconductor substrate of a first conductivity type and having a lower impurity concentration than the semiconductor substrate; a second semiconductor layer of the first conductivity type provided on the front surface of the first semiconductor layer and having a lower impurity concentration than the first semiconductor layer; and a parallel pn region in the second semiconductor layer, in which first column regions of the first conductivity type and second column regions of the second conductivity type are repeatedly arranged alternately in a direction parallel to the front surface. The depths of the first column regions and the second column regions of the parallel pn region become shallower stepwise toward the termination portion, and a portion of the parallel pn region located at the bottom or outermost position is formed in a ring shape at a fixed distance from the active region and is connected to parallel columns of the same conductivity type.

[0006] According to the disclosure above, by connecting a portion of the parallel pn region to parallel columns of the same conductivity type, it is possible to uniformize the expansion of the depletion layer and the electric field distribution of the termination structures with different structures, thereby reducing the difference in breakdown voltage between the structures. Furthermore, by connecting parallel columns of the same conductivity type, the current paths of excess carriers discharged during avalanche operation and reverse recovery operation are dispersed, thereby suppressing current concentration. [Effects of the Invention]

[0007] The super-junction semiconductor device according to the present disclosure has the advantage of being able to reduce the difference in breakdown voltage between termination regions with different structures. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a top view of an SJ-MOSFET according to an embodiment. [Figure 2] 2 is a cross-sectional view taken along the line AA' showing a first structure of the SJ-MOSFET according to the embodiment. FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along the line BB′ showing a first structure of the SJ-MOSFET according to the embodiment. [Figure 4] FIG. 2 is a cross-sectional view taken along the line CC' showing a first structure of the SJ-MOSFET according to the embodiment. [Figure 5] FIG. 2 is a DD′ plan view showing a first structure of the SJ-MOSFET according to the embodiment. [Figure 6] FIG. 2 is a plan view taken along the line EE′ showing a first structure of the SJ-MOSFET according to the embodiment. [Figure 7] FIG. 2 is a plan view taken along the line FF′ showing a first structure of the SJ-MOSFET according to the embodiment. [Figure 8] FIG. 37 is a plan view taken at a depth EE' in the cross-sectional views of FIGS. 34 to 36, illustrating an image of the path of hole carriers remaining in the termination region during the reverse recovery process of a conventional SJ-MOSFET. [Figure 9] 5 is a plan view taken at a depth EE' in the cross-sectional views of FIGS. 2 to 4, illustrating an image of the path of hole carriers remaining in the termination region during the reverse recovery process of the SJ-MOSFET according to the embodiment. FIG. [Figure 10] FIG. 2 is a cross-sectional view taken along the line AA′ showing a second structure of the SJ-MOSFET according to the embodiment. [Figure 11] FIG. 5 is a cross-sectional view taken along the line BB′ showing a second structure of the SJ-MOSFET according to the embodiment. [Figure 12] FIG. 4 is a cross-sectional view taken along the line CC' showing a second structure of the SJ-MOSFET according to the embodiment. [Figure 13] FIG. 13 is a diagram showing a planar structure at a depth GG' in the cross-sectional view of the second structure shown in FIGS. [Figure 14] FIG. 2 is a cross-sectional view taken along the line AA′ showing a third structure of an SJ-MOSFET according to an embodiment. [Figure 15] FIG. 10 is a cross-sectional view taken along the line BB′ showing a third structure of an SJ-MOSFET according to an embodiment. [Figure 16] FIG. 10 is a cross-sectional view taken along the line CC' showing a third structure of an SJ-MOSFET according to an embodiment. [Figure 17]FIG. 10 is a cross-sectional view taken along the line AA′ showing a fourth structure of an SJ-MOSFET according to an embodiment. [Figure 18] FIG. 10 is a cross-sectional view taken along the line BB' showing a fourth structure of an SJ-MOSFET according to an embodiment. [Figure 19] FIG. 10 is a cross-sectional view taken along the line CC' showing a fourth structure of an SJ-MOSFET according to an embodiment. [Figure 20] FIG. 10 is a plan view taken along the line HH′ showing a fourth structure of an SJ-MOSFET according to an embodiment. [Figure 21] FIG. 10 is a plan view taken along line II' showing a fourth structure of an SJ-MOSFET according to an embodiment. [Figure 22] FIG. 10 is a cross-sectional view taken along the line AA′ showing a fifth structure of an SJ-MOSFET according to an embodiment. [Figure 23] FIG. 10 is a cross-sectional view taken along the line BB′ showing a fifth structure of an SJ-MOSFET according to an embodiment. [Figure 24] FIG. 10 is a cross-sectional view taken along the line CC' showing a fifth structure of an SJ-MOSFET according to an embodiment. [Figure 25] FIG. 10 is a cross-sectional view taken along the line AA′ showing a sixth structure of an SJ-MOSFET according to an embodiment. [Figure 26] FIG. 10 is a cross-sectional view taken along the line BB′ showing a sixth structure of an SJ-MOSFET according to an embodiment. [Figure 27] FIG. 10 is a cross-sectional view taken along the line CC' showing a sixth structure of an SJ-MOSFET according to an embodiment. [Figure 28] FIG. 10 is a cross-sectional view taken along the line AA′ showing a seventh structure of an SJ-MOSFET according to an embodiment. [Figure 29] FIG. 10 is a cross-sectional view taken along the line BB′ showing a seventh structure of an SJ-MOSFET according to an embodiment. [Figure 30] FIG. 10 is a cross-sectional view taken along the line CC' showing a seventh structure of an SJ-MOSFET according to an embodiment. [Figure 31] FIG. 1 is a DD′ plan view showing the structure of a conventional SJ-MOSFET. [Figure 32] FIG. 1 is a plan view taken along the line E-E′ showing the structure of a conventional SJ-MOSFET. [Figure 33] FIG. 1 is a plan view taken along the line FF' showing the structure of a conventional SJ-MOSFET. [Figure 34] FIG. 1 is a cross-sectional view taken along the line A-A' showing the structure of a conventional SJ-MOSFET. [Figure 35] FIG. 1 is a cross-sectional view taken along the line BB' showing the structure of a conventional SJ-MOSFET. [Figure 36] FIG. 1 is a cross-sectional view taken along the line CC' showing the structure of a conventional SJ-MOSFET. DETAILED DESCRIPTION OF THE INVENTION

[0009] <Summary of Embodiments of the Present Disclosure> To solve the above-mentioned problems and achieve the object of the present disclosure, a super-junction semiconductor device according to the present disclosure has the following features: It is a semiconductor device having an active region through which current flows, and a termination structure disposed outside the active region and having a breakdown voltage structure surrounding the periphery of the active region. The termination structure includes: a first semiconductor layer of a first conductivity type provided on a front surface of a semiconductor substrate of a first conductivity type and having a lower impurity concentration than the semiconductor substrate; a second semiconductor layer of the first conductivity type provided on the front surface of the first semiconductor layer and having a lower impurity concentration than the first semiconductor layer; and a parallel pn region in the second semiconductor layer, in which first column regions of the first conductivity type and second column regions of the second conductivity type are repeatedly arranged alternately in a direction parallel to the front surface. The depths of the first column regions and the second column regions of the parallel pn region become shallower stepwise toward the termination portion, and a portion of the parallel pn region located at the bottom or outermost position is formed in a ring shape at a fixed distance from the active region and is connected to parallel columns of the same conductivity type.

[0010] According to the disclosure above, by connecting a portion of the parallel pn region to parallel columns of the same conductivity type, it is possible to uniformize the expansion of the depletion layer and the electric field distribution of the termination structures with different structures, thereby reducing the difference in breakdown voltage between the structures. Furthermore, by connecting parallel columns of the same conductivity type, the current paths of excess carriers discharged during avalanche operation and reverse recovery operation are dispersed, thereby suppressing current concentration.

[0011] Furthermore, the super-junction semiconductor device according to the present disclosure is characterized in that, in the above disclosure, a first semiconductor region of a first conductivity type is provided at the outermost side of the parallel pn region and is connected to the parallel first column region.

[0012] Furthermore, the super-junction semiconductor device according to the present disclosure is characterized in that, in the above disclosure, a second semiconductor region of a second conductivity type is provided at the bottom of the parallel pn region and connected to the parallel second column region.

[0013] Furthermore, the super junction semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the second semiconductor region is provided at the bottom of the first column region inside a portion where the first column region becomes gradually shallower.

[0014] Furthermore, the super-junction semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the second semiconductor region is provided at the bottom of the first column region sandwiched between the first column regions of the same depth.

[0015] Furthermore, the super junction semiconductor device according to the present disclosure, in the above disclosure, is characterized in that the active region includes the semiconductor substrate, the first semiconductor layer provided on a front surface of the semiconductor substrate, the second semiconductor layer provided on a front surface of the first semiconductor layer, and the parallel pn region provided in the second semiconductor layer, and the depths of the first column region and the second column region of the parallel pn region in the termination structure are shallower than the depths of the first column region and the second column region of the parallel pn region in the active region.

[0016] Furthermore, in the super-junction semiconductor device disclosed above, the depths of the first column region and the second column region become shallower in three or more stages toward the terminal end.

[0017] <Findings underlying this disclosure> First, we will explain the issues with conventional super-junction semiconductor devices. MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are widely used as semiconductor devices for power conversion. Super-junction MOSFETs (SJ: Super-junction MOSFETs), which have pn column regions arranged in parallel with the drift layer, have lower on-resistance than regular MOSFETs, which allows for device miniaturization and high-speed operation, and are therefore used in a variety of applications.

[0018] FIG. 31 is a D-D' plan view showing the structure of a conventional SJ-MOSFET. FIG. 32 is an E-E' plan view showing the structure of a conventional SJ-MOSFET. FIG. 33 is an F-F' plan view showing the structure of a conventional SJ-MOSFET. FIG. 34 is an A-A' cross-sectional view showing the structure of a conventional SJ-MOSFET. FIG. 35 is a B-B' cross-sectional view showing the structure of a conventional SJ-MOSFET. FIG. 36 is a C-C' cross-sectional view showing the structure of a conventional SJ-MOSFET. The plan views of FIGS. 31 to 33 show the planar structures at depths D-D', E-E', and F-F' in the cross-sectional views of FIGS. 34 to 36, respectively, and the cross-sectional views of FIGS. 34 to 36 show the cross-sectional structures at positions A-A', B-B', and C-C' in the plan views of FIGS. 31 to 33, respectively. 31 to 36, the element structure of the active region 150 does not include the MOS gate (insulated gate made of metal-oxide film-semiconductor) structure on the front surface side of the semiconductor substrate 180.

[0019] As shown in Figures 31 to 36, a conventional SJ-MOSFET has a high impurity concentration n ++ An n-type semiconductor substrate 101 is provided with an n-type buffer layer 102, and multiple epitaxial layers are stacked on the n-type buffer layer 102. - A type drift layer 170 is provided. - From the surface of the drift layer 170 to ++A p-type column region 104 and an n-type column region 103 are provided facing a semiconductor substrate 101. The p-type column region 104 and the n-type column region 103 are connected to each other. ++ An n-type buffer layer 102 is provided between the p-type semiconductor substrate 101 and the n-type column region 104. ++ The semiconductor substrate 101 may be in contact with the substrate.

[0020] Also, n - The drift layer 170 has a parallel structure (hereinafter referred to as parallel pn region 120) in which p-type regions (hereinafter referred to as p-type column regions 104) and n-type regions (hereinafter referred to as n-type column regions 103) that extend in a direction perpendicular to the substrate main surface and have narrow widths in a plane parallel to the substrate main surface are alternately and repeatedly arranged in a plane parallel to the substrate main surface. The p-type column regions 104 and n-type column regions 103 that make up the parallel pn region 120 are regions with increased impurity concentrations corresponding to the n-type buffer layer 102. In the parallel pn region 120, by making the impurity concentrations contained in the p-type column regions 104 and the n-type column regions 103 approximately equal, a pseudo-non-doped layer is created in the off state, thereby achieving a high breakdown voltage.

[0021] In the SJ-MOSFET, the parallel pn region 120 on the side of the active region 150 where the element is formed and through which current flows when the element is in the on state is provided with p + A mold base region (not shown) is provided. + Inside the type base region, n + A p-type source region (not shown) is provided. + A gate insulating film (not shown) is provided over the surfaces of the n-type base region and the n-type column region 103. A gate electrode (not shown) is provided on the surface of the gate insulating film, and an interlayer insulating film (not shown) is provided to cover the gate electrode. + A source electrode (not shown) is provided on the n-type source region. ++ A drain electrode (not shown) is provided on the back surface of the n-type semiconductor substrate 101. ++ The semiconductor substrate 101 corresponds to the drain region.

[0022] The termination region 160 of the SJ-MOSFET, which surrounds the active region 150, has n - In the type drift layer 170, the parallel pn region 120 is provided similarly to the active region 150, and n - A mold termination R region 130 is provided. - The type termination R region 130 is - From the surface of the drift layer 170 to - The n-type buffer layer 102 is formed so as to extend to the depth of the lower surface of the n-type drift layer 170. - Outside the n-type termination R region 130, the n-type region 115 - The n-type region 115 is provided to surround the n-type termination R region 130. - From the surface of the drift layer 170 to - The n-type region 115 is formed to a depth below the n-type drift layer 170 and is in contact with the n-type buffer layer 102. The n-type region 115 may have the same impurity concentration as the n-type buffer layer 102. The surface of the n-type region 115 has an n-type impurity layer 115a that functions as a channel stopper. + The mold region (not shown) is n - The parallel pn region 120 and the n + An oxide film is provided on the n-type region. ++ A drain electrode (not shown) is provided on the back surface of the semiconductor substrate 101 .

[0023] In this way, SJ-MOSFETs for power conversion have p + Source electrode connected to the base region, n-type ++ The mainstream structure is a vertical structure with a drain electrode connected to the semiconductor substrate 101. When a voltage is applied between the drain and source, + A depletion layer spreads between the n-type base region and the n-type drift layer 102, maintaining the breakdown voltage. The depletion layer spreads not only vertically from the source electrode side to the drain electrode side but also horizontally, so it is necessary to devise a termination structure in the termination region 160 to control the spread of the depletion layer. Since the characteristics of the device are mainly determined by the characteristics of the active region 150, it is common to maintain the breakdown voltage of the termination region 160 higher than that of the active region 150 in order to maximize the performance of the device.

[0024] The magnitude of the breakdown voltage is determined by the width of the depletion layer, which depends on the impurity concentration; the lower the impurity concentration and the wider the depletion layer, the higher the breakdown voltage that can be maintained. If the depletion layer that spreads laterally reaches the termination region 160, punch-through occurs and the breakdown voltage cannot be maintained, so it is necessary to stop the spread of the depletion layer in the termination region 160. If the spread of the depletion layer is stopped suddenly, an avalanche current will occur due to electric field concentration, leading to the destruction of the element, and if it is stopped gradually, the width of the termination region 160 will increase and the element will become larger, so it is necessary to suppress the spread of the depletion layer in a balanced manner. In an SJ-MOSFET, - Since the pn column region 120 parallel to the type drift layer 170 is also disposed in the termination region 160, it is important to adjust the shape and concentration of the pn junction.

[0025] In the termination region 160 of a conventional SJ-MOSFET, n - These structures can be broadly divided into two types: a structure in which the pn column region 120 is in a parallel relationship with the type drift layer 170, and a structure in which the pn column region 120 is in a horizontal relationship. The way the depletion layer spreads and the electric field distribution differ in each region, which creates the problem of complicated design.

[0026] (Embodiment) Preferred embodiments of the super-junction semiconductor device according to the present disclosure, which solve the problems of the conventional super-junction semiconductor device described above, will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate higher and lower impurity concentrations than layers and regions without these symbols, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted. Furthermore, the terms "same" or "equivalent" should preferably be interpreted as including variations within 5% to account for variations in manufacturing.

[0027] The super-junction semiconductor device according to the present disclosure will be described taking an SJ-MOSFET fabricated (manufactured) using silicon (Si) as an example. FIG. 1 is a top view of an SJ-MOSFET according to an embodiment. FIG. 2 is an A-A' cross-sectional view showing a first structure of an SJ-MOSFET according to an embodiment. FIG. 3 is a B-B' cross-sectional view showing the first structure of an SJ-MOSFET according to an embodiment. FIG. 4 is a C-C' cross-sectional view showing the first structure of an SJ-MOSFET according to an embodiment. FIG. 5 is a D-D' plan view showing the first structure of an SJ-MOSFET according to an embodiment. FIG. 6 is an E-E' plan view showing the first structure of an SJ-MOSFET according to an embodiment. FIG. 7 is an F-F' plan view showing the first structure of an SJ-MOSFET according to an embodiment. The cross-sectional view of FIG. 2 shows the cross-sectional structure taken along A-A' in FIG. 1. The cross-sectional views of FIGS. 3 and 4 show the cross-sectional structures taken along B-B' and C-C' in FIG. 2, respectively. The plan views of FIGS. 5 to 7 show enlarged planar structures of region Z in FIG. 1 at depths DD', EE', and FF' in the cross-sectional views of FIGS. 2 to 4, respectively.

[0028] The SJ-MOSFET according to the embodiment has a front surface (p +The SJ-MOSFET has a MOS (Metal Oxide Semiconductor) gate on the surface (the surface facing the base region 5). As shown in FIG. 1, this SJ-MOSFET has an active region 50 and a termination region 60 surrounding the active region 50. The active region 50 is a region through which current flows when the SJ-MOSFET is on. The termination region 60 is a region that relieves the electric field on the front surface side of the semiconductor substrate 80 and maintains a breakdown voltage. A gate wiring 22 is provided in the termination region 60 so as to surround the active region 50. Furthermore, an oxide film 13 and a channel stopper electrode 23, which will be described later, are provided in the termination region 60. The active region 50 is a region surrounded by the edge of the outermost source electrode 10 on each side of the SJ-MOSFET shown in FIG. 1. The active region 50 is provided with a source electrode 10 and a gate pad 11 connected to the gate wiring 22. The gate wiring 22 and the gate pad 11 are electrically insulated from the source electrode 10. A surface protection film (not shown) such as polyimide may be provided on the surface of the SJ-MOSFET according to the embodiment. The surface protection film has openings that expose the surfaces of the source electrode 10 and the gate pad 11. Furthermore, the SJ-MOSFET according to the embodiment may be provided with a temperature detection diode (not shown), a current sensor (not shown), and the like.

[0029] 2 shows a cross-sectional view taken along the line A-A' in FIG. 1. In the active region 50 of FIG. 2, only four unit cells (functional units of the device) are shown, and other unit cells adjacent to these are not shown. ++ The n-type semiconductor substrate (first conductivity type semiconductor substrate) 1 is, for example, a silicon single crystal substrate doped with phosphorus (P). The n-type buffer layer (first conductivity type first semiconductor layer) 2 is an n ++ The n-type buffer layer 2 is a low-concentration n-type layer doped with, for example, phosphorus at an impurity concentration lower than that of the n-type semiconductor substrate 1. On the n-type buffer layer 2, a plurality of epitaxial layers are stacked. - A first conductivity type drift layer (second semiconductor layer) 70 is provided. - The n-type drift layer 70 has a lower impurity concentration than the n-type buffer layer 2, and is, for example, a low-concentration n-type drift layer doped with phosphorus. - Hereafter, n++ a semiconductor substrate 1, an n-type buffer layer 2, and an n - The semiconductor substrate 80 includes the n-type drift layer 70. A MOS gate (insulated gate made of metal-oxide-semiconductor) structure (device structure) is formed on the front surface side of the semiconductor substrate 80. ++ A drain electrode (not shown) is provided on the back surface of the n-type semiconductor substrate 1. ++ The semiconductor substrate 1 corresponds to the drain region.

[0030] The parallel pn region 20 is provided in the active region 50 of the semiconductor substrate 80. In the parallel pn region 20, n-type column regions 3 and p-type column regions 4 are alternately and repeatedly arranged. The n-type column regions 3 and the p-type column regions 4 are arranged in a direction from the surface of the semiconductor substrate 80 to the n-type column region 3. ++ The n-type column region 3 and the p-type column region 4 are provided toward the n-type semiconductor substrate layer 1. - The n-type column region 3 and the p-type column region 4 are formed in the n-type drift layer 70. ++ An n-type buffer layer 2 is provided between the n-type semiconductor substrate 1 and the n-type column region 3 and the p-type column region 4. ++ The semiconductor substrate 1 may be in contact with the substrate.

[0031] In addition, the surface layer of the p-type column region 4 is + A type base region 5 is provided, and p + The surface layer of the base region 5 is + A p-type source region 6 is optionally provided. + Type base region 5, n + A gate electrode 8 is provided on the surface of the portion sandwiched between the n-type source region 6 and the n-type column region 3, with a gate insulating film 7 interposed therebetween. The gate electrode 8 may also be provided on the surface of the n-type column region 3 with the gate insulating film 7 interposed therebetween. + The surface layer of the base region 5 is + A source region 6 may be selectively provided. + The region sandwiched between the source regions 6 is p + p type base region 5 with a higher impurity concentration ++A contact region (not shown) may also be provided. + Type base region 5, n + Type source region 6 and p ++ The mold contact regions (not shown) may be provided in a stripe pattern along the depth direction of FIG.

[0032] The interlayer insulating film 9 is provided on the front surface side of the semiconductor substrate 80 so as to cover the gate electrode 8. The source electrode 10 is connected to the n-type semiconductor substrate 8 through a contact hole opened in the interlayer insulating film 9. + Type source region 6 and p + In contact with the base region 5, + Type source region 6 and p + It is electrically connected to the mold base region 5 .

[0033] The source electrode 10 is electrically insulated from the gate electrode 8 by an interlayer insulating film 9. A protective film (not shown), such as a passivation film made of polyimide, is selectively provided on the source electrode 10.

[0034] The termination region 60 of the SJ-MOSFET is provided with a parallel pn region 20, similar to the active region 50. The impurity concentration of the parallel pn region 20 in the termination region 60 may be lower than or the same as the impurity concentration of the parallel pn region 20 provided in the active region 50. Furthermore, the impurity concentration of the parallel pn region 20 in the termination region 60 may decrease the further it is from the active region 50. The impurity concentration of the parallel pn region 20 in the termination region 60 may be 1 / 2 to 1 / 3 times the impurity concentration of the parallel pn region 20 in the active region 50. The outermost n-type column region of the parallel pn region 20 provided in the termination region 60 is an n-type annular region (first semiconductor region of the first conductivity type) 31.

[0035] The n-type column region 3 and the p-type column region 4 of the parallel pn region 20 of the termination region 60 are - The depth from the surface of the n-type drift layer 70 becomes shallower stepwise toward the outside. - A mold termination R region 30 is provided.

[0036] Furthermore, in the parallel pn region 20, which becomes shallower stepwise outward, there are portions of the adjacent p-type column region 4 and n-type column region 3 where the p-type column region 4 is deeper than the n-type column region 3. A p-type annular region (second semiconductor region of the second conductivity type) 32 is provided at the bottom of the p-type column region 4, which is deeper than the n-type column region 3.

[0037] The impurity concentration of the p-type annular region 32 may be the same as or lower than the p-type column region 4. Outside the parallel pn region 20, an n-type buffer layer 20 having a lower impurity concentration than the n-type buffer layer 2 is provided. - A type termination R region 30 is provided to surround the parallel pn region 20. - The type termination R region 30 is n - The surface of the drift layer 70 is - The n-type buffer layer 2 is formed so as to extend to the bottom surface of the n-type drift layer 70 and is in contact with the top surface of the n-type buffer layer 2. - The impurity concentration of the n-type termination R region 30 is lower than the impurity concentration of the n-type column region 3 in the termination region 60, and may be the same as the impurity concentration of the n-type column region 3 in the termination region 60.

[0038] n - Outside the type termination R region 30, - The n-type region 15 has a higher impurity concentration than the type termination R region 30. The n-type region 15 has an n - The surface of the drift layer 70 is - The n-type region 15 is formed to a depth equal to the bottom surface of the n-type drift layer 70 and is in contact with the top surface of the n-type buffer layer 2. The impurity concentration of the n-type region 15 is the same as the impurity concentration of the n-type buffer layer 2.

[0039] The surface of the n-type region 15 is provided with a p + Type region 27 and p + Type region 21 is n - It is provided so as to surround the mold termination R region 30. + The type region 27 is n - The surface of the drift layer 70 is ++The p-type semiconductor substrate layer 1 is provided facing the n-type region 14, which will be described later. + The bottom of the p-type region 27 is located within the n-type region 15. + The depth of the n-type region 27 may be deeper than the n-type region 14, and the p-type region 27 may be deeper than the n-type region 14. + The depth may be the same as that of the p well region 26. + The impurity concentration of the type region 27 is p + It may have the same impurity concentration as the type well region 26 .

[0040] p + The type region 21 is n - The surface of the drift layer 70 is ++ The p-type semiconductor substrate layer 1 is provided. + The type region 21 is p + The mold region 27 is provided on the surface thereof, and the bottom and side surfaces are p + It is in contact with the mold area 27. + The impurity concentration of the p-type region 21 is + The impurity concentration in the active region 50 may be higher than or equal to that in the dopant region 27. ++ When a contact region (not shown) is provided, p + The impurity concentration of the p-type region 21 is ++ The impurity concentration may be the same as that of the p-type contact region (not shown). + The p-type region 21 is the p-type region of the active region 50. ++ It may be provided to the same depth as the mold contact region (not shown).

[0041] The surface of the parallel pn region 20 of the termination region 60 is + The p-type well region 26 and the n-type region 14 are provided. + The p well region 26 is provided across the active region 50 and the termination region 60. In the first structure, + The well region 26 is a p-type well of the active region 50. + The p + The well region 26 is a p-type well of the active region 50. + It may be provided to a position deeper than the bottom of the mold base region 5. + The impurity concentration of the well region 26 is p+ The impurity concentration is the same as that of the base region 5. + The impurity concentration of the well region 26 is p + The impurity concentration may be lower than that of the base region 5 .

[0042] The impurity concentration of the n-type region 14 is lower than or equal to the impurity concentration of the n-type column region 3 of the active region 50. - The impurity concentration is higher than or equal to that of the type termination R region 30. + n-type well region 26, n-type region 14, p + Type region 21 and p + An oxide film 13 is provided on the surface of the type region 27. In the termination region 60, a gate wiring 22 electrically connected to the gate electrode 8 and a p + A channel stopper electrode 23 is provided which is electrically connected to the mold region 21 .

[0043] 3 and 4 are B-B' and C-C' cross sections taken in the depth direction relative to the A-A' cross section in Fig. 2. Fig. 3 is a cross section of the n-type column region 3, which corresponds to the B-B' cross section in Figs. 5 to 7 described later. Fig. 4 is a cross section of the p-type column region 4, which corresponds to the C-C' cross section in Figs. 5 to 7 described later.

[0044] 3 and 4, the n-type column region 3 and the p-type column region 4 are provided in a stripe pattern. + Type well region 26, p + Type region 21 and p + The p-type region 27 is provided in a ring shape on the surface layer of the semiconductor substrate 80. + Type well region 26 and p + Between the n-type region 27 and the n-type region 14 is provided. + n-type well region 26, n-type region 14, p + Type region 21 and p + An oxide film 13 is provided on the upper surface of the mold region 27. On the upper surface of the oxide film 13, a gate wiring 22 that is electrically connected to the gate electrode 8 is provided.

[0045] Furthermore, an annular channel stopper electrode 23 is provided on the upper surface of the oxide film 13. The channel stopper electrode 23 is connected to the p + p through type region 21 + The p-type annular region 32 is electrically connected to the n-type region 27. The p-type annular region 32 is formed in a ring shape. In the termination region 60, the p-type annular region 32 formed closest to the active region 50 has its bottom surface in contact with the n-type buffer layer 2 and its side surface in contact with the n-type buffer layer 2. - The termination region 60 is in contact with the p-type termination R region 30. In the termination region 60, the p-type annular region 32 provided on the outside has a bottom surface and a side surface that are n-type. - It is in contact with the mold termination R region 30 .

[0046] 5 is a plan view taken at a depth D-D' in FIGS. 2 to 4. In this embodiment, in termination region 60, a portion of parallel pn region 20 located at the bottom or outermost position is formed in an annular shape at a fixed distance from active region 50 and is connected to parallel columns of the same conductivity type. This makes it possible to homogenize the electric field distribution in termination region 60, which has a different structure. The columns of the same conductivity type are n-type column regions 3 if the annularly formed region is n-type, and p-type column regions 4 if it is p-type.

[0047] In this embodiment, the n-type annular region 31 is provided to surround the parallel pn region 20. The n-type column region 3 of the parallel pn region 20, which is provided in a stripe shape, contacts the annular n-type annular region 31. The impurity concentration of the n-type annular region 31 is the same as the impurity concentration of the n-type column region 3 of the termination region 60. The impurity concentration of the n-type annular region 31 may be lower than the impurity concentration of the n-type column region 3 of the active region 50. - The impurity concentration is higher than that of the type termination R region 30.

[0048] 6 and 7 are plan views taken at depths E-E' and F-F' in Figures 2 to 4, respectively. As a region formed in an annular shape, an annular p-type annular region 32 is provided at the bottom of the parallel pn region 20, surrounding the parallel pn region 20, and is connected to the parallel p-type column region 4. Here, the p-type annular region 32 is provided at the bottom of the p-type column region 4, inside the portion where the n-type column region 3 becomes shallower in stages.

[0049] 6 shows the annular p-type region 32 provided at the outermost position in the termination region 60 of FIGS. 2 to 4. The p-type region 32 is provided in an annular shape, and its lower surface is n - 6. The p-type annular region 32 is in contact with the n-type buffer layer 2 at its bottom surface.

[0050] In the termination region 60, depletion occurs in a fan shape from the source electrode 10 of the active region 50 in the center, extending vertically toward the drain electrode and horizontally toward the edge of the device. - In a termination structure in which the parallel pn region 20 is parallel to the type drift layer 70, the depletion layer easily spreads because the direction of propagation of the depletion layer coincides with the pn junction surface. However, in a termination structure in which the parallel pn region 20 is perpendicular to the type drift layer 70, as shown in Figures 3 and 4, the pn junction blocks the direction of propagation of the depletion layer. As a result, in a termination structure in which the parallel pn region 20 is perpendicular to the type drift layer 70, the depletion layer does not easily spread, which can result in a difference in breakdown voltage between the two structures. In this embodiment, by connecting portions of the parallel pn region 20 to parallel columns of the same conductivity type, the depletion layer spreads more uniformly and the electric field distribution in the different termination structures can be uniformed, thereby reducing the difference in breakdown voltage between the structures. Furthermore, by connecting parallel columns of the same conductivity type, the current paths of excess carriers discharged during avalanche operation and reverse recovery operation can be dispersed, suppressing current concentration.

[0051] Fig. 8 is a plan view at a depth E-E' in the cross-sectional views of Figs. 34 to 36 showing an image of the path of hole carriers remaining in the termination region during the reverse recovery process of a conventional SJ-MOSFET. Fig. 9 is a plan view at a depth E-E' in the cross-sectional views of Figs. 2 to 4 showing an image of the path of hole carriers remaining in the termination region during the reverse recovery process of an SJ-MOSFET according to an embodiment.

[0052] As shown in FIG. 8, in the conventional SJ-MOSFET, the striped p-type column regions 104 are formed independently or in the p-type region near the surface. + Although there is a connection between the p-type well region and the RESURF structure, the paths of the hole carriers 140 are difficult to disperse on the back surface side. For this reason, the hole carriers 140 tend to concentrate in the p-type column region 104, which is close to a structure in a parallel relationship with the parallel pn region 120, and the hole current tends to concentrate, which raises concerns about a decrease in reverse recovery capability.

[0053] 9, in the SJ-MOSFET according to the embodiment, the provision of the p-type annular region 32 increases the number of paths for connecting the p-type column regions 4 on the back surface side as well, thereby dispersing the paths of the hole carriers 40. Therefore, when the holes 40 pass through the p-type annular region 32, the hole carriers 40 do not concentrate in the p-type column region 4, which has a structure similar to that of the parallel pn region 20, and the hole current can be dispersed. Although FIG. 9 shows the effect of the p-type annular region 32, the n-type annular region 31 can also disperse the hole current.

[0054] Furthermore, by connecting adjacent columns, the electric field distribution in the termination region 60 can be made uniform, and n - This has the effect of reducing the difference in breakdown voltage of the termination portion in the direction perpendicular to and parallel to the stripe of the parallel pn region 20 in parallel relation to the type drift layer 70.

[0055] FIG. 10 is an A-A' cross-sectional view showing a second structure of an SJ-MOSFET according to an embodiment. FIG. 11 is a B-B' cross-sectional view showing the second structure of an SJ-MOSFET according to an embodiment. FIG. 12 is a C-C' cross-sectional view showing the second structure of an SJ-MOSFET according to an embodiment. FIG. 13 is a diagram showing a planar structure at a depth G-G' in the cross-sectional views of the second structure shown in FIGS. 10 to 12. In the second structure, a ring-shaped p-type annular region 32 surrounding the active region 50 is provided at the bottom of the p-type column region 4 provided on the outermost side of the active region 50.

[0056] In the second structure, similar to the first structure, the n-type column region 3 and the p-type column region 4 of the parallel pn region 20 of the termination region 60 are arranged in a manner such that the n-type column region 3 and the p-type column region 4 ... - The depth from the surface of the n-type drift layer 70 becomes shallower in stages. The second structure differs from the first structure in that the p-type annular region 32 is provided in the active region 50. In the first structure, the depths of the n-type column regions 3 and p-type column regions 4 in the parallel pn region 20 were the same as the depths of the n-type column regions 3 and p-type column regions 4 in the active region 50 up to the middle of the termination region 60. On the other hand, in the second structure, the depths of the n-type column regions 3 and p-type column regions 4 in the parallel pn region 20 in the termination region 60 are shallower than the depths of the n-type column regions 3 and p-type column regions 4 in the active region 50.

[0057] In the second structure, the p-type annular region 32 of the active region 50 is provided at the bottom of the p-type column region 4 located at the outermost part of the active region 50. The bottom surface of the p-type annular region 32 provided in the active region 50 is in contact with the buffer layer 2. The side surface of the p-type annular region 32 provided in the active region 50 is - The n-type column region 3 and the p-type column region 4 of the termination region 60 are in contact with the n-type termination R region 30. -The first structure and the second structure have the same number of p-type annular regions 32, and the same number of n-type column regions 3 and p-type column regions 4 in the termination region 60. By providing the p-type annular regions 32 in the active region 50, the second structure has an increased number of n-type column regions 3 and p-type column regions 4 in the termination region 60 that have the same depth, compared to the first structure.

[0058] In this way, in the termination region 60, the number of n-type column regions 3 and p-type column regions 4 at the same depth is increased compared to the first structure, so that the change in the electric field distribution in the termination region 60 becomes gentler and electric field concentration is less likely to occur. Also, all of the n-type column regions 3 and p-type column regions 4 in the termination region 60 are provided shallower than the n-type column regions 3 and p-type column regions 4 in the active region 50, and the lower surface is - By contacting the p-type termination R region 30, it is possible to obtain the effect of preventing the electric field from concentrating on the p-type column region 4 (p-type annular region 32) provided on the outermost side of the active region .

[0059] FIG. 14 is an A-A' cross-sectional view showing a third structure of an SJ-MOSFET according to an embodiment. FIG. 15 is a B-B' cross-sectional view showing a third structure of an SJ-MOSFET according to an embodiment. FIG. 16 is a C-C' cross-sectional view showing a third structure of an SJ-MOSFET according to an embodiment. Plan views of the third structure are omitted. The cross-sectional views of FIGS. 14 to 16 show cross-sectional structures at positions A-A', B-B', C-C', and G-G' in the plan views of FIGS. 5 to 7 and FIG. 13, respectively.

[0060] 10 to 13, the depths of the n-type column regions 3 and p-type column regions 4 of the parallel pn region 20 in the termination region 60 are shallower in two stages, as in the second structure. That is, the depths of the n-type column regions 3 and p-type column regions 4 in the termination region 60 are of two types: shorter than the depths of the n-type column regions 3 and p-type column regions 4 in the active region 50, and even shorter. On the other hand, in the third structure of FIGS. 14 to 16, the depths of the n-type column regions 3 and p-type column regions 4 of the parallel pn region 20 in the termination region 60 are shallower in three stages. That is, the depths of the n-type column regions 3 and p-type column regions 4 in the termination region 60 are of three types: shorter than the depths of the n-type column regions 3 and p-type column regions 4 in the active region 50, even shorter, and the shortest. The p-type annular region 32 is provided at the bottom of the p-type column region 4 inside the portion where the n-type column region 3 becomes gradually shallower, so that the third structure has three p-type annular regions 32. The p-type annular regions 32 have the effect of dispersing the concentration of hole current, so the third structure, which has more p-type annular regions 32, can further disperse the hole current than the first and second structures, and the n - This can further reduce the difference in breakdown voltage of the termination portion in the directions perpendicular and parallel to the stripe of the parallel pn region 20 that is in a parallel relationship with the type drift layer 70.

[0061] 14 to 16, the innermost p-type annular region 32 is provided at the bottom of the outermost p-type column region 4 of the active region 50 so as to surround the active region. Furthermore, the depths of the n-type column region 3 and the p-type column region 4 become shallower in three stages, but may be four or more stages.

[0062] 17 to 21 are diagrams illustrating a fourth structure of an SJ-MOSFET according to an embodiment. FIG. 17 is an A-A' cross-sectional view illustrating the fourth structure of an SJ-MOSFET according to an embodiment. FIG. 18 is a B-B' cross-sectional view illustrating the fourth structure of an SJ-MOSFET according to an embodiment. FIG. 19 is a C-C' cross-sectional view illustrating the fourth structure of an SJ-MOSFET according to an embodiment. FIG. 20 is an H-H' cross-sectional view illustrating the fourth structure of an SJ-MOSFET according to an embodiment. FIG. 21 is an I-I' cross-sectional view illustrating the fourth structure of an SJ-MOSFET according to an embodiment. In the fourth structure, the D-D', E-E', H-H', and I-I' planes illustrated in FIGS. 19 to 21 correspond to the plan views of FIGS. 2, 3, 17, and 18, respectively. The cross-sectional views of FIGS. 19 to 21 illustrate cross-sectional structures at positions A-A', B-B', and C-C' in the plan views of FIGS. 1, 2, 17, and 18, respectively.

[0063] In the third structure of FIGS. 14 to 16, the p-type annular regions 32 are provided at the bottom of the p-type column regions 4 inside the portions where the n-type column regions 3 become shallower in stages, but in the fourth structure of FIGS. 17 to 21, the p-type annular regions 32 are also provided outside the portions where the n-type column regions 3 become shallower in stages, for example, at the bottom of the p-type column regions 4 sandwiched between n-type column regions 3 of the same depth. For this reason, while the p-type annular regions 32 are provided in three locations in the third structure of FIGS. 14 to 16, the p-type annular regions 32 are provided in five locations in the fourth structure of FIGS. 17 to 21. Note that the locations where the p-type annular regions 32 are provided are not limited to those described above, and more p-type annular regions 32 may be provided. The fourth structure, which has more p-type annular regions 32, can distribute the hole current more effectively than the first, second, and third structures, and the n - This can further reduce the difference in breakdown voltage of the termination portion in the directions perpendicular and parallel to the stripe of the parallel pn region 20 that is in a parallel relationship with the type drift layer 70.

[0064] FIG. 22 is an A-A' cross-sectional view showing a fifth structure of an SJ-MOSFET according to an embodiment. FIG. 23 is a B-B' cross-sectional view showing a fifth structure of an SJ-MOSFET according to an embodiment. FIG. 24 is a C-C' cross-sectional view showing a fifth structure of an SJ-MOSFET according to an embodiment. Plan views are omitted for the fifth structure. The cross-sectional views of FIGS. 22 to 24 show cross-sectional structures at positions A-A', B-B', and C-C' in the plan views of FIGS. 2 to 4, respectively.

[0065] The fifth structure is a structure in which a field plate electrode 24 is added to the first structure in the termination region 60. The field plate electrode 24 is connected to a p-type MOSFET provided on the surface of the n-type column region 3 through a contact hole provided in the oxide film 13. + It is electrically connected to the type well region 26. Furthermore, in addition to the first structure, structures in which the field plate electrode 24 is added to the second to fourth structures are also possible.

[0066] FIG. 25 is an A-A' cross-sectional view showing a sixth structure of an SJ-MOSFET according to an embodiment. FIG. 26 is a B-B' cross-sectional view showing a sixth structure of an SJ-MOSFET according to an embodiment. FIG. 27 is a C-C' cross-sectional view showing a sixth structure of an SJ-MOSFET according to an embodiment. Plan views are omitted for the sixth structure. The cross-sectional views of FIGS. 25 to 27 show cross-sectional structures at positions A-A', B-B', and C-C' in the plan views of FIGS. 2 to 4, respectively.

[0067] The sixth structure is a structure in which a resurf structure 25 is added to the first structure in the termination region 60. The resurf structure 25 is p + Outside the well region 26, + It is a ring-shaped p-type region that contacts the p-type well region 26 and is provided on the surface of the parallel pn region 20. In addition to the first structure, a structure in which the RESURF structure 25 is added to the second to fourth structures is also possible.

[0068] FIG. 28 is an A-A' cross-sectional view showing a seventh structure of an SJ-MOSFET according to an embodiment. FIG. 29 is a B-B' cross-sectional view showing a seventh structure of an SJ-MOSFET according to an embodiment. FIG. 30 is a C-C' cross-sectional view showing a seventh structure of an SJ-MOSFET according to an embodiment. Plan views are omitted for the seventh structure. The cross-sectional views of FIGS. 28 to 30 show cross-sectional structures at positions A-A', B-B', and C-C' in the plan views of FIGS. 2 to 4, respectively.

[0069] The seventh structure is a structure in which a field plate electrode 24 and a resurf structure 25 are added to the first structure in termination region 60. The field plate electrode 24 is the same as in the fifth structure, and the resurf structure 25 is the same as in the sixth structure. Furthermore, in addition to the first structure, structures in which a field plate electrode 24 and a resurf structure 25 are added to any of the second to fourth structures are also possible.

[0070] Furthermore, the super-junction semiconductor device according to the embodiment can be fabricated, for example, by forming the p-type column region 4 of the termination region 60 inside the n-type drift region 2 by ion implantation using a different mask to form the p-type annular region 32, and then forming the n-type annular region 31 on the surface of the n-type drift region 2 by ion implantation. Other structures can be fabricated in the same manner as when fabricating a MOSFET with a breakdown voltage of, for example, 1200 V.

[0071] As described above, according to the embodiment, by connecting a portion of the parallel pn region to parallel columns of the same conductivity type, it is possible to uniformize the expansion of the depletion layer and the electric field distribution of the termination structures with different structures and reduce the difference in breakdown voltage between the structures. Furthermore, by connecting parallel columns of the same conductivity type, the current paths of excess carriers discharged during avalanche operation and reverse recovery operation are dispersed, thereby suppressing current concentration.

[0072] In the above, the present disclosure has been described using an example in which a MOS gate structure is configured on the first main surface of a silicon substrate, but the present disclosure is not limited to this and various changes are possible in the type of semiconductor (e.g., silicon carbide (SiC)), the surface orientation of the substrate main surface, and the like. Furthermore, the embodiments of the present disclosure have been described using a planar MOSFET as an example, but the present disclosure is not limited to this and is applicable to semiconductor devices with various configurations, such as MOS semiconductor devices such as trench IGBTs and trench MOSFETs. Furthermore, in each embodiment of the present disclosure, the first conductivity type is n-type and the second conductivity type is p-type, but the present disclosure is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0073] As described above, the super-junction semiconductor device according to the present disclosure is useful as a high-voltage semiconductor device used in power conversion devices and power supply devices for various industrial machines. [Explanation of symbols]

[0074] 1, 101 n ++ semiconductor substrate 2, 102 n-type buffer layer 3, 103 n-type column region 4, 104 p-type column region 5 p + Type-based domain 6n + Type Source Area 7 Gate insulating film 8 gate electrode 9 Interlayer insulating film 10 Source electrode 11 Gate Pad 13 Oxide film 14 n-type region 15, 115 n-type region 20, 120 parallel pn regions 21n + type area 22 Gate wiring 23 Channel stopper electrode 24 Field plate electrode 25 Resurf structure 26 pages + Mold well area 27 pages + type area 30, 130 n - Mold end R area 31 n-type annular region 32 p-type annular region 40, 140 hole career 50, 150 active area 60, 160 termination area 70, 170 n - Mold drift layer 80, 180 Semiconductor substrate

Claims

1. A semiconductor device having an active region through which a current flows, and a termination structure portion disposed outside the active region and having a breakdown voltage structure surrounding the active region, The termination structure includes: a first semiconductor layer of the first conductivity type provided on a front surface of a semiconductor substrate of the first conductivity type and having a lower impurity concentration than the semiconductor substrate; a second semiconductor layer of the first conductivity type provided on a front surface of the first semiconductor layer and having a lower impurity concentration than the first semiconductor layer; a parallel pn region in which first column regions of a first conductivity type and second column regions of a second conductivity type provided in the second semiconductor layer are repeatedly and alternately arranged in a direction parallel to the front surface; and the parallel pn region has a depth of the first column region and a depth of the second column region that gradually become shallower toward a terminal portion; A super-junction semiconductor device characterized in that a part of the parallel pn region located at the bottom or outermost position is formed in an annular shape at a certain distance from the active region and is connected to parallel columns of the same conductivity type.

2. 2. The super-junction semiconductor device according to claim 1, wherein a first semiconductor region of a first conductivity type is provided on the outermost side of said parallel pn region and is connected to said parallel first column region.

3. 2. The super-junction semiconductor device according to claim 1, wherein a second semiconductor region of a second conductivity type is provided at the bottom of said parallel pn region and connected to said second column region in parallel.

4. 4. The super-junction semiconductor device according to claim 3, wherein the second semiconductor region is provided at the bottom of the first column region inside a portion where the first column region becomes shallower in a stepwise manner.

5. 5. The super-junction semiconductor device according to claim 4, wherein the second semiconductor region is provided at the bottom of the first column regions sandwiched between the first column regions of the same depth.

6. In the active region, the semiconductor substrate; the first semiconductor layer provided on a front surface of the semiconductor substrate; the second semiconductor layer provided on a front surface of the first semiconductor layer; the parallel pn region provided in the second semiconductor layer; and 2. The super-junction semiconductor device of claim 1, wherein the depth of the first column region and the second column region of the parallel pn region of the termination structure is shallower than the depth of the first column region and the second column region of the parallel pn region of the active region.

7. 2. The super-junction semiconductor device according to claim 1, wherein the depths of the first column region and the second column region become shallower in three or more steps toward the terminal portion.

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