Chip package and its substrate

Abstract

The present invention provides a chip package and its substrate. [Solution] A chip package (100) includes a substrate (110), a chip (120), and a heat sink (130). The substrate (110) includes a carrier (111), a circuit layer (112), and a solder resist layer (113). The circuit layer (112) is mounted on the carrier (111) and includes a plurality of circuit lines (L). The solder resist layer (113) covers the circuit layer (112), and the solder resist layer (113) includes a first opening (113a), a first shielding portion (113b), and a second opening (113c). The first shielding portion (113b) is located between the first opening (113a) and the second opening (113c), and inner leads (L1) of each circuit line (L) are exposed through the first opening (113a). The first shielding portion (113b) covers first conductive portions (L2) of each circuit line (L), and second conductive portions (L3) of each circuit line (L) are exposed through the second opening (113c).

Description

[Technical Field]

[0001] The present invention relates to a chip package and its substrate, and more particularly to a chip package and its substrate in which a heat sink contacts the circuit layer of the substrate to enhance heat conduction and flexibility. [Background technology]

[0002] The higher the processing speed of an integrated circuit, the higher the temperature of the chip. To reduce the temperature of the chip, a heat sink is installed on the chip to dissipate heat. Summary of the Invention [Problem to be solved by the invention]

[0003] However, as chips become smaller, the heat sink cannot keep up with the rate at which the chip heats up, resulting in insufficient efficiency, which can damage the chip or affect its computing speed.

[0004] Therefore, the present inventors believed that the above drawbacks could be improved, and as a result of extensive research, they came up with the proposal of the present invention, which effectively improves the above problems through rational design.

[0005] As a result of extensive research, the present inventors have found that the above object can be achieved by employing the following configuration, and have thus completed the present invention.

[0006] The present invention was developed through extensive research by the inventors in light of the above-mentioned problems, and its purpose is to provide a chip package that improves the heat dissipation efficiency of the chip package by covering the substrate and chip with a heat sink and attaching the heat sink to the circuit layer exposed through the opening in the solder resist layer. [Means for solving the problem]

[0007] In order to solve the above problems, the chip package of the present invention employs the following measures. The chip package of the present invention includes a substrate, a chip, and a heat sink. The substrate includes a carrier, a circuit layer, and a solder resist layer. The circuit layer is mounted on the carrier and includes a plurality of circuit lines. Each of the circuit lines includes an inner lead, a first conductive portion, a second conductive portion, and an outer lead. The first conductive portion is located between the inner lead and the second conductive portion, and the second conductive portion is located between the first conductive portion and the outer lead. The solder resist layer covers the circuit layer, and the solder resist layer has a first opening, a first shielding portion, and a second opening. The first shielding portion is located between the first opening and the second opening. The inner lead is exposed from the first opening, the first shielding portion covers the first conductive portion, and the second conductive portion is exposed from the second opening. The chip is mounted on the substrate and electrically connected to the inner leads, and the heat sink covers the substrate and the chip. The heat sink has a heat dissipation layer and an insulating adhesive layer, and the heat dissipation layer is attached to the second conductive portion exposed from the second opening by the insulating adhesive layer.

[0008] To achieve the above object, a substrate according to the present invention includes a carrier, a circuit layer, and a solder resist layer. The circuit layer is mounted on the carrier and includes a plurality of circuit lines. Each of the circuit lines includes an inner lead, a first conductive portion, a second conductive portion, and an outer lead, with the first conductive portion located between the inner lead and the second conductive portion, and the second conductive portion located between the first conductive portion and the outer lead. The solder resist layer covers the circuit layer, and the solder resist layer includes a first opening, a first shielding portion, and a second opening, with the first shielding portion located between the first opening and the second opening. The inner lead for electrical connection to a chip is exposed from the first opening, and the first shielding portion covers the first conductive portion. The second conductive portion is exposed from the second opening, and a heat dissipation layer of a heat sink is attached to the second conductive portion exposed from the second opening by an insulating adhesive layer. [Effects of the Invention]

[0009] As described above, the present invention has the following advantages. The heat dissipation layer of the present invention is attached to the second conductive portion exposed from the second opening by an insulating adhesive layer, and heat generated during chip operation is conducted to the heat sink by the second conductive portion, thereby improving the heat dissipation efficiency of the chip package.

[0010] At least the following points will become clear from the description and drawings to be described later. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a plan view showing a chip package according to an embodiment of the present invention; [Figure 2] 1 is a cross-sectional view showing a chip package according to an embodiment of the present invention; [Figure 3] FIG. 10 is a plan view showing a chip package according to another embodiment of the present invention. [Figure 4]FIG. 10 is a plan view showing a chip package according to yet another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0012] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0013] 1 and 2, a chip package 100 includes a substrate 110, a chip 120, and a heat sink 130. The substrate 110 includes a carrier 111, a circuit layer 112, and a solder resist layer 113. The material of the carrier 111 may be polyimide or other flexible material. The circuit layer 112 is mounted on the carrier 111, and the solder resist layer 113 covers the circuit layer 112. The chip 120 is mounted on the substrate 110 and electrically connected to the circuit layer 112, and the heat sink 130 covers the substrate 110 and the chip 120.

[0014] 1 and 2, the circuit layer 112 has a plurality of circuit lines L, and each circuit line L has an inner lead L1, a first conductive portion L2, a second conductive portion L3, and an outer lead L4. The first conductive portion L2 is located between the inner lead L1 and the second conductive portion L3, and the second conductive portion L3 is located between the first conductive portion L2 and the outer lead L4. In this embodiment, each circuit line L further has a third conductive portion L5, which is located between the second conductive portion L3 and the outer lead L4.

[0015] As shown in FIGS. 1 and 2, the solder resist layer 113 has a first opening 113a, a first shielding portion 113b, and at least one second opening 113c. The first shielding portion 113b is located between the first opening 113a and the second opening 113c. In this embodiment, the first shielding portion 113b surrounds the first opening 113a, and the second opening 113c surrounds the first opening 113a and the first shielding portion 113b. In another embodiment, the second opening 113c is located on a side of the first opening 113a (see FIG. 4). When the solder resist layer 113 has multiple second openings 113c, these second openings 113c do not have to be connected to each other and may be located on different sides of the first opening 113a.

[0016] 1 and 2, the inner lead L1 is exposed from the first opening 113a, the first shielding portion 113b covers the first conductive portion L2, and the second opening 113c exposes the second conductive portion L3. In this embodiment, the solder resist layer 113 further includes a second shielding portion 113d, and the second opening 113c is located between the first shielding portion 113b and the second shielding portion 113d. The second shielding portion 113d covers the third conductive portion L5 but does not cover the outer lead L4. The outer lead L4 is used for electrical connection to an external electronic element (not shown, e.g., a panel).

[0017] 1 and 2, the chip 120 is installed in the first opening 113a and electrically connected to the inner lead L1. Preferably, a filler 140 is filled between the chip 120 and the substrate 110. The heat sink 130 has a heat dissipation layer 131 and an insulating adhesive layer 132. The heat dissipation layer 131 is attached to the second conductive portion L3 exposed from the second opening 113c by the insulating adhesive layer 132. Therefore, heat generated during operation of the chip 120 is conducted to the heat sink 130 attached to the second conductive portion L3 by the inner lead L1, the first conductive portion L2, and the second conductive portion L3. The increased area of ​​the heat sink 130 in contact with the heat source (e.g., the chip 120 and the circuit layer 112) improves the thermal conduction effect of the chip package 100. In this embodiment, the heat dissipation layer 131 is attached to the first shielding portion 113b and the second shielding portion 113d by an insulating adhesive layer 132, and warping occurs at the edges of the first shielding portion 113b or the second shielding portion 113d located on both sides of the second opening 113c, preventing the solder resist layer 113 from peeling off.

[0018] 1, 3, and 4, the area of ​​the second opening 113c is smaller than the area of ​​the heat sink 130, allowing the heat sink 130 to completely cover the second opening 113c. The heat dissipation layer 131 is attached to the first shielding portion 113b and the second shielding portion 113d by an insulating adhesive layer 132, preventing moisture from entering the second opening 113c. The area and shape of the second opening 113c differ between FIGS. 1, 3, and 4, and can be adjusted based on different heat dissipation requirements. The shape of the second opening 113c may be rectangular, triangular, or trapezoidal.

[0019] 2, along the direction Y, there is a first thickness D1 between the first conductive portion L2 and the heat dissipation layer 131, and there is a second thickness D2 between the second conductive portion L3 and the heat dissipation layer 131. In this embodiment, the second thickness D2 is thinner than the first thickness D1. When the chip package 100 is applied to a curved electronic product (such as a curved panel), the second thickness D2 being thinner than the first thickness D1 increases the flexibility of the chip package 100, thereby reducing the shear stress generated between the chip 120 and the inner leads L1 and preventing the chip 120 from detaching from the inner leads L1, resulting in a disconnection.

[0020] 2, in this embodiment, heat dissipation layer 131 is attached to chip 120 and filler 140 by insulating adhesive layer 132. In other embodiments, heat dissipation layer 131 is attached directly to chip 120.

[0021] The present embodiment has been described above, but the above-described embodiment merely illustrates some of the application examples of the present invention, and is not intended to limit the technical scope of the present invention to the specific configurations of the above-described embodiment. [Explanation of symbols]

[0022] 100 chip packages 110 Substrate 111 Career 112 Circuit layer 113 Solder resist layer 113a 1st opening 113b 1st shielding part 113c 2nd opening 113d 2nd shielding part 120 chips 130 Heatsink 131 Heat dissipation layer 132 Insulating adhesive layer 140 Filling material D1 First thickness D2 Second thickness L circuit line L1 inner lead L2 1st conductive part L3 2nd conductive part L4 outer lead L5 3rd conductive part Y direction

Claims

1. a substrate comprising a carrier, a circuit layer, and a solder resist layer, the circuit layer being mounted on the carrier, the circuit layer having a plurality of circuit lines, each of the circuit lines having an inner lead, a first conductive portion, a second conductive portion, and an outer lead, the first conductive portion being located between the inner lead and the second conductive portion, the second conductive portion being located between the first conductive portion and the outer lead, the solder resist layer covering the circuit layer, the solder resist layer having a first opening, a first shielding portion, and a second opening, the first shielding portion being located between the first opening and the second opening, the inner lead being exposed from the first opening, the first shielding portion covering the first conductive portion, and the second conductive portion being exposed from the second opening; a chip mounted on the substrate and electrically connected to the inner leads; a heat sink covering the substrate and the chip, the heat sink having a heat dissipation layer and an insulating adhesive layer, the heat dissipation layer being attached to the second conductive portion exposed from the second opening by the insulating adhesive layer.

2. 2. The chip package of claim 1, wherein the area of ​​the second opening is smaller than the area of ​​the heat sink, and the heat sink completely covers the second opening.

3. 2. The chip package of claim 1, wherein each of the circuit lines further includes a third conductive portion, the third conductive portion being located between the second conductive portion and the outer lead, the solder resist layer further includes a second shielding portion, the second opening being located between the first shielding portion and the second shielding portion, the second shielding portion covering the third conductive portion and exposing the outer lead.

4. 4. The chip package according to claim 3, wherein the heat dissipation layer is attached to the first shielding portion and the second shielding portion by the insulating adhesive layer.

5. 5. The chip package of claim 1, wherein a first thickness is provided between the first conductive portion and the heat dissipation layer, and a second thickness is provided between the second conductive portion and the heat dissipation layer, the second thickness being thinner than the first thickness.

6. The chip package of claim 5 , wherein the second opening surrounds the first opening and the first shielding portion.

7. The chip package according to claim 6 , wherein the first shielding portion encloses the first opening.

8. Career and a circuit layer disposed on the carrier and having a plurality of circuit lines, each of the circuit lines having an inner lead, a first conductive portion, a second conductive portion, and an outer lead, the first conductive portion being located between the inner lead and the second conductive portion, and the second conductive portion being located between the first conductive portion and the outer lead; a substrate covering the circuit layer, having a first opening, a first shielding portion, and a second opening, the first shielding portion being located between the first opening and the second opening, the inner lead for electrically connecting to a chip being exposed from the first opening, the first shielding portion covering the first conductive portion, the second conductive portion being exposed from the second opening, and a heat dissipation layer of a heat sink comprising a solder resist layer attached to the second conductive portion by an insulating adhesive layer.

9. 9. The substrate of claim 8, wherein each of the circuit lines further has a third conductive portion located between the second conductive portion and the outer lead, the solder resist layer further has a second shielding portion, the second opening is located between the first shielding portion and the second shielding portion, the second shielding portion covers the third conductive portion, and the outer lead is exposed.

10. The substrate according to claim 9 , wherein the first shielding portion and the second shielding portion are used to attach the heat dissipation layer by the insulating adhesive layer.

11. The substrate according to claim 8 , wherein the second opening encloses the first opening and the first shielding portion.

12. The substrate according to claim 11 , wherein the first shielding portion surrounds the first opening.

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