Semiconductor Devices

Abstract

A plurality of first semiconductor chips and a plurality of second semiconductor chips are appropriately arranged. [Solution] A semiconductor device comprising: a wiring board having a wiring layer provided therein; a plurality of first semiconductor chips stacked on the wiring board in a shifted manner and having connection terminals on the surface facing the wiring board; and a second semiconductor chip provided on the side of the wiring board where the connection terminals and the wiring board are electrically connected, and having a function different from that of the first semiconductor chip.

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor device. [Background technology]

[0002] In a semiconductor device, multiple chips are stacked, and terminals extend from each chip in the stacking direction. In a semiconductor device, it is desirable to appropriately arrange other chips in addition to the multiple chips. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 9,640,513 [Patent Document 2] U.S. Patent No. 9,917,072 [Patent Document 3] Japanese Patent Application Laid-Open No. 2017-5187 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a semiconductor device in which a plurality of first chips and second chips can be appropriately arranged. [Means for solving the problem]

[0005] This embodiment is a semiconductor device comprising a wiring board having a wiring layer provided therein, a plurality of first semiconductor chips stacked on the wiring board in a shifted manner and having connection terminals on the surface facing the wiring board, and a second semiconductor chip provided on the side of the wiring board where the connection terminals and the wiring board are electrically connected, and having a function different from that of the first semiconductor chip. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 3 is a cross-sectional view showing a first modified example of the semiconductor device according to the first embodiment. [Figure 3] FIG. 10 is a cross-sectional view showing a second modified example of the semiconductor device in the first embodiment. [Figure 4] FIG. 10 is a cross-sectional view showing a third modified example of the semiconductor device in the first embodiment. [Figure 5] FIG. 10 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 6] FIG. 10 is a cross-sectional view showing a first modified example of the semiconductor device according to the second embodiment. [Figure 7] FIG. 10 is a cross-sectional view showing a second modified example of the semiconductor device according to the second embodiment. [Figure 8] FIG. 10 is a cross-sectional view showing a third modified example of the semiconductor device according to the second embodiment. [Figure 9] FIG. 10 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Figure 10] FIG. 11 is a cross-sectional view showing a first modified example of the semiconductor device according to the third embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing a second modified example of the semiconductor device according to the third embodiment. [Figure 12] FIG. 11 is a cross-sectional view showing a third modified example of the semiconductor device according to the third embodiment. [Figure 13] FIG. 10 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. [Figure 14] FIG. 10 is a cross-sectional view showing a modified example of the semiconductor device according to the fourth embodiment. [Figure 15] FIG. 10 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. [Figure 16] FIG. 10 is a cross-sectional view showing a semiconductor device according to a sixth embodiment. [Figure 17] FIG. 13 is a cross-sectional view showing a semiconductor device according to a seventh embodiment. [Figure 18] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 19] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 20] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 21] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 22] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 23] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 24] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 25] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 26] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 27] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 28] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 29] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first modified example of the first embodiment. [Figure 30] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first modified example of the first embodiment. [Figure 31] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first modified example of the first embodiment. [Figure 32] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first modified example of the first embodiment. [Figure 33] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first modified example of the first embodiment. [Figure 34] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first modified example of the first embodiment. [Figure 35]10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first modified example of the first embodiment. [Figure 36] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first modified example of the first embodiment. [Figure 37] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first modified example of the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, the present embodiment will be described with reference to the accompanying drawings. To facilitate understanding of the description, the same components in the drawings will be denoted by the same reference numerals as much as possible, and duplicated descriptions will be omitted.

[0008] A semiconductor device 2 according to a first embodiment will be described with reference to Fig. 1. Fig. 1 is a cross-sectional view of the semiconductor device 2. As shown in Fig. 1, the semiconductor device 2 includes a wiring substrate 21, a spacer 22, a first semiconductor chip 23, a support 24, loop wires 25, vertical wires 26, metal bumps 27, a second semiconductor chip 28, metal balls 29, and a molded resin layer 30. The metal bumps 27 have a convex shape extending upward from the wiring substrate 21 toward the first semiconductor chip 23. The metal bumps 27 are provided inside the molded resin layer 30.

[0009] First semiconductor chips 23 are provided on wiring substrate 21. The first semiconductor chips 23 are, for example, memory chips of NAND flash memory. A plurality of first semiconductor chips 23 are stacked. In the example shown in FIG. 1, eight first semiconductor chips 23 are divided into two sets of four and stacked, but the total number, number of sets, and number of stacked chips are not limited to this. The first semiconductor chips 23 are stacked while being shifted so that a portion of each faces wiring substrate 21.

[0010] A second semiconductor chip 28 is flip-chip mounted on the wiring substrate 21. The second semiconductor chip 28 is, for example, a semiconductor chip equipped with an arbitrary LSI. The second semiconductor chip 28 is mounted on the wiring substrate 21 via metal bumps.

[0011] The first semiconductor chips 23, which are divided into two groups and mounted, are arranged with a shift so that they are closer to the second semiconductor chip 28. The first semiconductor chip 23 arranged closest to the wiring substrate 21 is arranged furthest from the second semiconductor chip 28. On the first semiconductor chip 23 arranged closest to the wiring substrate 21, another first semiconductor chip 23 is arranged with a shift so that it is closer to the second semiconductor chip 28. The first semiconductor chip 23 arranged farthest from the wiring substrate 21 is arranged closest to the second semiconductor chip 28.

[0012] A die attach film (DAF) is provided between the stacked first semiconductor chips 23. The stacked first semiconductor chips 23 are electrically connected to each other by loop wires 25. Metal bumps 27 are provided on the wiring substrate 21. The first semiconductor chip 23 arranged closest to the wiring substrate 21 and the metal bump 27 are electrically connected by vertical wires 26.

[0013] A spacer 22 is provided between the wiring board 21 and the first semiconductor chip 23, which is arranged closest to the wiring board 21. A die attach film (DAF) is provided between the spacer 22 and the first semiconductor chip 23. An adhesive layer (not shown) is provided between the wiring board 21 and the spacer 22.

[0014] A support body 24 is provided on the first semiconductor chip 23, which is disposed farthest from the wiring board 21. Between the support body 24 and the first semiconductor chip 23, a die attach film (DAF) is provided.

[0015] A molded resin layer 30 is provided on the wiring substrate 21. The molded resin layer 30 covers the spacer 22, the first semiconductor chip 23, the support 24, the loop wires 25, the vertical wires 26, and the metal bumps 27.

[0016] Metal balls 29 are provided on the surface of wiring board 21 opposite to the surface on which first semiconductor chip 23 is mounted.

[0017] The spacer 22 included in the semiconductor device 2 described with reference to FIG. 1 is an optional component. As in the semiconductor device 2a shown in FIG. 2, the spacer 22 may not be provided. The support 24 included in the semiconductor device 2 described with reference to FIG. 1 is an optional component. As in the semiconductor device 2b shown in FIG. 3, the support 24 may not be provided. When the support 24 is not provided, the first semiconductor chip 23a disposed farthest from the wiring substrate 21 is formed thicker than the other first semiconductor chips 23. As in the semiconductor device 2c shown in FIG. 4, the spacer 22 and the support 24 may not be provided. In this case, too, the first semiconductor chip 23a disposed farthest from the wiring substrate 21 is formed thicker than the other first semiconductor chips 23.

[0018] A semiconductor device 2A according to the second embodiment will be described with reference to Fig. 5. Fig. 5 is a cross-sectional view of the semiconductor device 2A. As shown in Fig. 5, the semiconductor device 2A includes a wiring substrate 21, a spacer 22, a first semiconductor chip 23, a support 24, loop wires 25, vertical wires 26 and 26a, metal bumps 27 and 27a, a second semiconductor chip 28, metal balls 29, and a molded resin layer 30.

[0019] First semiconductor chips 23 are provided on wiring substrate 21. The first semiconductor chips 23 are, for example, memory chips of NAND flash memory. A plurality of first semiconductor chips 23 are stacked. In the example shown in FIG. 5, eight first semiconductor chips 23 are divided into two sets of four and stacked, but the total number, number of sets, and number of stacked chips are not limited to this. The first semiconductor chips 23 are stacked while being shifted so that a portion of each faces wiring substrate 21.

[0020] A second semiconductor chip 28 is flip-chip mounted on the wiring substrate 21. The second semiconductor chip 28 is, for example, a semiconductor chip equipped with an arbitrary LSI. The second semiconductor chip 28 is mounted on the wiring substrate 21 via metal bumps.

[0021] The first semiconductor chips 23, which are divided into two groups and mounted, are arranged with a shift so that they are closer to the second semiconductor chip 28. The first semiconductor chip 23 arranged closest to the wiring substrate 21 is arranged furthest from the second semiconductor chip 28. On the first semiconductor chip 23 arranged closest to the wiring substrate 21, another first semiconductor chip 23 is arranged with a shift so that it is closer to the second semiconductor chip 28. The first semiconductor chip 23 arranged farthest from the wiring substrate 21 is arranged closest to the second semiconductor chip 28.

[0022] A die attach film (DAF) is provided between the stacked first semiconductor chips 23. The stacked first semiconductor chips 23 are divided into a plurality of sets and electrically connected to each other by loop wires 25. In the case of FIG. 5, two stacked first semiconductor chips 23 form one set and are connected to each other by loop wires 25. Metal bumps 27, 27a are provided on the wiring substrate 21. The first semiconductor chip 23 arranged closest to the wiring substrate 21 is electrically connected to the metal bump 27 by a vertical wire 26. The first semiconductor chip 23 stacked third from the wiring substrate 21 is electrically connected to the metal bump 27a by a vertical wire 26a.

[0023] A spacer 22 is provided between the wiring board 21 and the first semiconductor chip 23, which is arranged closest to the wiring board 21. A die attach film (DAF) is provided between the spacer 22 and the first semiconductor chip 23. An adhesive layer (not shown) is provided between the wiring board 21 and the spacer 22.

[0024] A support body 24 is provided on the first semiconductor chip 23, which is disposed farthest from the wiring board 21. Between the support body 24 and the first semiconductor chip 23, a die attach film (DAF) is provided.

[0025] A molded resin layer 30 is provided on the wiring substrate 21. The molded resin layer 30 covers the spacer 22, the first semiconductor chip 23, the support 24, the loop wire 25, the vertical wires 26 and 26a, and the metal bumps 27 and 27a.

[0026] Metal balls 29 are provided on the surface of wiring board 21 opposite to the surface on which first semiconductor chip 23 is mounted.

[0027] The spacer 22 included in the semiconductor device 2A described with reference to FIG. 5 is an optional component. As in the semiconductor device 2Aa shown in FIG. 6, the spacer 22 may not be provided. The support 24 included in the semiconductor device 2A described with reference to FIG. 5 is an optional component. As in the semiconductor device 2Ab shown in FIG. 7, the support 24 may not be provided. If the support 24 is not provided, the first semiconductor chip 23a disposed farthest from the wiring substrate 21 is formed thicker than the other first semiconductor chips 23. As in the semiconductor device 2Ac shown in FIG. 8, the spacer 22 and the support 24 may not be provided. In this case, too, the first semiconductor chip 23a disposed farthest from the wiring substrate 21 is formed thicker than the other first semiconductor chips 23.

[0028] A semiconductor device 2B according to the third embodiment will be described with reference to Fig. 9. Fig. 9 is a cross-sectional view of the semiconductor device 2B. As shown in Fig. 9, the semiconductor device 2B includes a wiring substrate 21, a spacer 22, a first semiconductor chip 23, a support 24, vertical wires 26, 26a, 26b, and 26c, metal bumps 27, 27a, 27b, and 27c, a second semiconductor chip 28, metal balls 29, and a molded resin layer 30.

[0029] First semiconductor chips 23 are provided on wiring substrate 21. The first semiconductor chips 23 are, for example, memory chips of NAND-type flash memory. A plurality of first semiconductor chips 23 are stacked. In the example shown in FIG. 9, eight first semiconductor chips 23 are divided into two sets of four and stacked, but the total number, number of sets, and number of stacked chips are not limited to this. The first semiconductor chips 23 are stacked while being shifted so that a portion of each faces wiring substrate 21.

[0030] A second semiconductor chip 28 is flip-chip mounted on the wiring substrate 21. The second semiconductor chip 28 is, for example, a semiconductor chip equipped with an arbitrary LSI. The second semiconductor chip 28 is mounted on the wiring substrate 21 via metal bumps.

[0031] The first semiconductor chips 23, which are divided into two groups and mounted, are arranged with a shift so that they are closer to the second semiconductor chip 28. The first semiconductor chip 23 arranged closest to the wiring substrate 21 is arranged furthest from the second semiconductor chip 28. On the first semiconductor chip 23 arranged closest to the wiring substrate 21, another first semiconductor chip 23 is arranged with a shift so that it is closer to the second semiconductor chip 28. The first semiconductor chip 23 arranged farthest from the wiring substrate 21 is arranged closest to the second semiconductor chip 28.

[0032] A die attach film (DAF) is provided between the stacked first semiconductor chips 23. Metal bumps 27, 27a, 27b, and 27c are provided on the wiring substrate 21. The first semiconductor chip 23 arranged closest to the wiring substrate 21 and metal bump 27 are electrically connected by vertical wire 26. The first semiconductor chip 23 stacked second from the wiring substrate 21 side and metal bump 27b are electrically connected by vertical wire 26b. The first semiconductor chip 23 stacked third from the wiring substrate 21 side and metal bump 27a are electrically connected by vertical wire 26a. The first semiconductor chip 23 stacked fourth from the wiring substrate 21 side and metal bump 27c are electrically connected by vertical wire 26c.

[0033] A spacer 22 is provided between the wiring board 21 and the first semiconductor chip 23, which is arranged closest to the wiring board 21. A die attach film (DAF) is provided between the spacer 22 and the first semiconductor chip 23. An adhesive layer (not shown) is provided between the wiring board 21 and the spacer 22.

[0034] A support body 24 is provided on the first semiconductor chip 23, which is disposed farthest from the wiring board 21. Between the support body 24 and the first semiconductor chip 23, a die attach film (DAF) is provided.

[0035] A molded resin layer 30 is provided on the wiring substrate 21. The molded resin layer 30 covers the spacer 22, the first semiconductor chip 23, the support 24, the vertical wires 26, 26a, 26b, and 26c, and the metal bumps 27, 27a, 27b, and 27c.

[0036] Metal balls 29 are provided on the surface of wiring board 21 opposite to the surface on which first semiconductor chip 23 is mounted.

[0037] The spacer 22 included in the semiconductor device 2B described with reference to FIG. 9 is an optional component. As in the semiconductor device 2Ba shown in FIG. 10, the spacer 22 may not be provided. The support 24 included in the semiconductor device 2B described with reference to FIG. 9 is an optional component. As in the semiconductor device 2Bb shown in FIG. 11, the support 24 may not be provided. When the support 24 is not provided, the first semiconductor chip 23a disposed farthest from the wiring substrate 21 is formed thicker than the other first semiconductor chips 23. As in the semiconductor device 2Bc shown in FIG. 12, the spacer 22 and the support 24 may not be provided. In this case, too, the first semiconductor chip 23a disposed farthest from the wiring substrate 21 is formed thicker than the other first semiconductor chips 23.

[0038] A semiconductor device 2C according to the fourth embodiment will be described with reference to Fig. 13. Fig. 13 is a cross-sectional view of the semiconductor device 2C. As shown in Fig. 13, the semiconductor device 2C includes a wiring substrate 21, a spacer 22, a first semiconductor chip 23, a support 24, loop wires 25, metal bumps 31, a second semiconductor chip 28, metal balls 29, and a molded resin layer 30.

[0039] A first semiconductor chip 23 is provided on the wiring substrate 21. The first semiconductor chip 23 is, for example, a memory chip of a NAND flash memory. A plurality of the first semiconductor chips 23 are stacked. In the example shown in FIG. 13, eight first semiconductor chips 23 are divided into two sets of four and stacked, but the total number, the number of sets, and the number of stacked chips are not limited to this. The first semiconductor chips 23 are stacked while being shifted so that a portion of each faces the wiring substrate 21.

[0040] A second semiconductor chip 28 is flip-chip mounted on the wiring substrate 21. The second semiconductor chip 28 is, for example, a semiconductor chip equipped with an arbitrary LSI. The second semiconductor chip 28 is mounted on the wiring substrate 21 via metal bumps.

[0041] The first semiconductor chips 23, which are divided into two groups and mounted, are arranged with a shift so that they are closer to the second semiconductor chip 28. The first semiconductor chip 23 arranged closest to the wiring substrate 21 is arranged furthest from the second semiconductor chip 28. On the first semiconductor chip 23 arranged closest to the wiring substrate 21, another first semiconductor chip 23 is arranged with a shift so that it is closer to the second semiconductor chip 28. The first semiconductor chip 23 arranged farthest from the wiring substrate 21 is arranged closest to the second semiconductor chip 28.

[0042] A die attach film (DAF) is provided between the stacked first semiconductor chips 23. The stacked first semiconductor chips 23 are electrically connected to one another by loop wires 25. Metal bumps 31 are provided on the wiring substrate 21. Loop wires 25 that connect the first semiconductor chip 23 arranged closest to the wiring substrate 21 to the first semiconductor chip 23 stacked thereon are electrically connected to the metal bumps 31. The loop wires 25 are connected to the metal bumps 31 at the midpoint of the loop.

[0043] A spacer 22 is provided between the first semiconductor chip 23, which is arranged closest to the wiring board 21, and the wiring board 21. A die attach film (DAF) is provided between the spacer 22 and the first semiconductor chip 23.

[0044] A support body 24 is provided on the first semiconductor chip 23, which is disposed farthest from the wiring board 21. Between the support body 24 and the first semiconductor chip 23, a die attach film (DAF) is provided.

[0045] A molded resin layer 30 is provided on the wiring substrate 21. The molded resin layer 30 covers the spacer 22, the first semiconductor chip 23, the support 24, the loop wires 25, and the metal bumps 31.

[0046] Metal balls 29 are provided on the surface of wiring board 21 opposite to the surface on which first semiconductor chip 23 is mounted.

[0047] The support 24 of the semiconductor device 2C described with reference to Fig. 13 is an optional component. The support 24 may not be provided, as in the semiconductor device 2Cb shown in Fig. 14. When the support 24 is not provided, the first semiconductor chip 23a disposed farthest from the wiring substrate 21 is formed thicker than the other first semiconductor chips 23.

[0048] In the above-described embodiment, an example in which the first semiconductor chips 23 are arranged symmetrically with respect to an axis has been described, but the arrangement of the first semiconductor chips 23 is not limited to this. A semiconductor device 2D according to a fifth embodiment will be described with reference to FIG. 15. FIG. 15 is a cross-sectional view of the semiconductor device 2D. As shown in FIG. 15, the semiconductor device 2D includes a wiring substrate 21, spacers 22, 22a, a first semiconductor chip 23, loop wires 25, vertical wires 26, 26a, metal bumps 27, a second semiconductor chip 28, metal balls 29, and a molded resin layer 30.

[0049] First semiconductor chips 23 are provided on wiring substrate 21. The first semiconductor chips 23 are, for example, memory chips of NAND-type flash memory. A plurality of first semiconductor chips 23 are stacked. In the example shown in FIG. 15, eight first semiconductor chips 23 are divided into two sets of four and stacked, but the total number, the number of sets, and the number of stacked chips are not limited to this. The first semiconductor chips 23 are stacked while being shifted so that a portion of each faces wiring substrate 21.

[0050] A second semiconductor chip 28 is flip-chip mounted on the wiring substrate 21. The second semiconductor chip 28 is, for example, a semiconductor chip equipped with an arbitrary LSI. The second semiconductor chip 28 is mounted on the wiring substrate 21 via metal bumps.

[0051] The first semiconductor chips 23, which are divided into two groups and mounted, are arranged with a shift so that they are closer to the second semiconductor chip 28. The first semiconductor chip 23 arranged closest to the wiring substrate 21 is arranged furthest from the second semiconductor chip 28. On the first semiconductor chip 23 arranged closest to the wiring substrate 21, another first semiconductor chip 23 is arranged with a shift so that it is closer to the second semiconductor chip 28. The first semiconductor chip 23 arranged farthest from the wiring substrate 21 is arranged closest to the second semiconductor chip 28.

[0052] A die attach film (DAF) is provided between the stacked first semiconductor chips 23. The stacked second semiconductor chips 28 are electrically connected to each other by loop wires 25. Metal bumps 27 are provided on the wiring substrate 21. The first semiconductor chip 23 arranged closest to the wiring substrate 21 and the metal bumps 27 are electrically connected by vertical wires 26, 26a.

[0053] Spacers 22 and 22a are provided between the wiring board 21 and the first semiconductor chip 23, which is arranged closest to the wiring board 21. A die attach film (DAF) is provided between the spacers 22 and 22a and the first semiconductor chip 23. The spacer 22a is thicker than the spacer 22. An adhesive layer (not shown) is provided between the wiring board 21 and the spacers 22 and 22a. The first semiconductor chip 23 disposed on the spacer 22a is connected to the metal bumps 27 by vertical wires 26a, which are longer than the vertical wires 26.

[0054] 15, the first semiconductor chips 23 disposed farthest from the wiring substrate 21 are arranged to overlap each other on the second semiconductor chip 28.

[0055] A molded resin layer 30 is provided on the wiring substrate 21. The molded resin layer 30 covers the spacer 22, the first semiconductor chip 23, the loop wires 25, the vertical wires 26 and 26a, and the metal bumps 27.

[0056] Metal balls 29 are provided on the surface of wiring board 21 opposite to the surface on which first semiconductor chip 23 is mounted.

[0057] A semiconductor device 2E according to the sixth embodiment will be described with reference to Fig. 16. Fig. 16 is a cross-sectional view of the semiconductor device 2E. As shown in Fig. 16, the semiconductor device 2E includes a wiring substrate 21, a spacer 22, a first semiconductor chip 23, loop wires 25, vertical wires 26, metal bumps 27, a second semiconductor chip 28, metal balls 29, and a molded resin layer 30.

[0058] A first semiconductor chip 23 is provided on the wiring substrate 21. The first semiconductor chip 23 is, for example, a memory chip of a NAND flash memory. A plurality of the first semiconductor chips 23 are stacked. In the example shown in FIG. 16, eight first semiconductor chips 23 are divided into two sets, one of which is stacked two by two, and the other of which is stacked six by six. The first semiconductor chips 23 are stacked while being shifted so that a portion of each faces the wiring substrate 21.

[0059] A second semiconductor chip 28 is flip-chip mounted on the wiring substrate 21. The second semiconductor chip 28 is, for example, a semiconductor chip equipped with an arbitrary LSI. The second semiconductor chip 28 is mounted on the wiring substrate 21 via metal bumps.

[0060] The first semiconductor chips 23, which are divided into two groups and mounted, are arranged with a shift so that they are closer to the second semiconductor chip 28. The first semiconductor chip 23 arranged closest to the wiring substrate 21 is arranged furthest from the second semiconductor chip 28. On the first semiconductor chip 23 arranged closest to the wiring substrate 21, another first semiconductor chip 23 is arranged with a shift so that it is closer to the second semiconductor chip 28. The first semiconductor chip 23 arranged farthest from the wiring substrate 21 is arranged closest to the second semiconductor chip 28.

[0061] A die attach film (DAF) is provided between the stacked first semiconductor chips 23. The stacked second semiconductor chips 28 are electrically connected to each other by loop wires 25. Metal bumps 27 are provided on the wiring substrate 21. The first semiconductor chip 23 arranged closest to the wiring substrate 21 and the metal bumps 27 are electrically connected by vertical wires 26, 26a.

[0062] A spacer 22 is provided between the wiring board 21 and the first semiconductor chip 23, which is arranged closest to the wiring board 21. A die attach film (DAF) is provided between the spacer 22 and the first semiconductor chip 23. An adhesive layer (not shown) is provided between the wiring board 21 and the spacer chip 22.

[0063] 16, the first semiconductor chips 23 arranged farthest from the wiring substrate 21 are arranged to overlap each other on the second semiconductor chip 28.

[0064] A molded resin layer 30 is provided on the wiring substrate 21. The molded resin layer 30 covers the spacer 22, the first semiconductor chip 23, the loop wires 25, the vertical wires 26 and 26a, and the metal bumps 27.

[0065] Metal balls 29 are provided on the surface of wiring board 21 opposite to the surface on which first semiconductor chip 23 is mounted.

[0066] A semiconductor device 2F according to the seventh embodiment will be described with reference to Fig. 17. Fig. 17 is a cross-sectional view of the semiconductor device 2F. As shown in Fig. 17, the semiconductor device 2F includes a wiring substrate 21, a spacer 22, a first semiconductor chip 23, a support 24, loop wires 25, vertical wires 26, metal bumps 27, a second semiconductor chip 28, metal balls 29, and a molded resin layer 30.

[0067] The semiconductor device 2F differs from the semiconductor device 2 in the first embodiment in the mounting mode of the second semiconductor chip .

[0068] A second semiconductor chip 28 is mounted by wire bonding on wiring board 21. Second semiconductor chip 28 is, for example, a semiconductor chip equipped with an arbitrary LSI. Second semiconductor chip 28 is mounted on wiring board 21 via wires 32.

[0069] Next, a manufacturing method of the semiconductor device 2 will be described with reference to FIGS. 18 to 23. As shown in FIG. 18, a support 24, a first semiconductor chip 23, and a spacer 22 are prepared. The first semiconductor chip 23 is placed on the support 24 with a die attach film (DAF) interposed therebetween. In this embodiment, a pair of first semiconductor chips 23 are placed. Then, the next first semiconductor chip 23 is placed on the placed first semiconductor chip 23 with a die attach film (DAF) interposed therebetween. The newly placed first semiconductor chip 23 is positioned outward relative to the first semiconductor chip 23 on the support 24 side. Similarly, the next first semiconductor chip 23 and the first semiconductor chip 23 after that are placed on the first semiconductor chip 23 with a die attach film (DAF) interposed therebetween. Finally, a spacer 22 is placed on the first semiconductor chip 23 placed on the top layer with a die attach film (DAF) interposed therebetween to form a stack.

[0070] 19, stacked first semiconductor chips 23 are electrically connected to each other by loop wires 25. Vertical wires 26 are provided on the first semiconductor chip 23 arranged on the top layer.

[0071] 20, metal bumps 27 and a second semiconductor chip 28 are provided on wiring board 21. Second semiconductor chip 28 is flip-chip mounted on wiring board 21. Second semiconductor chip 28 is mounted on wiring board 21 via the metal bumps. Adhesive 50 is applied to the wiring board 21 at a position where the laminate shown in FIG. 19 will be placed.

[0072] As shown in Fig. 21, the laminate shown in Fig. 19 is placed upside down on the wiring board 21 prepared in Fig. 20. In this placement, the vertical wires 26 are positioned so as to bond to the metal bumps 27. The wiring board 21 and the spacers 22 are bonded together via an adhesive 50.

[0073] As shown in FIG. 22, a molding resin layer 30 is formed so as to cover the spacer 22, the first semiconductor chip 23, the support 24, the loop wires 25, the vertical wires 26, and the metal bumps 27.

[0074] As shown in FIG. 23, metal balls 29 are provided on the surface of wiring board 21 opposite to the surface on which first semiconductor chip 23 is mounted, and semiconductor device 2 is formed.

[0075] Another method for manufacturing the semiconductor device 2 will be described with reference to Figures 24 to 28. The formation of the laminate is partially similar to the description given with reference to Figures 18 and 19. The difference is that while spacers 22 are arranged in Figures 18 and 19, in the another manufacturing method to be described below, the spacers 22 are arranged on the wiring board 21 side.

[0076] 24, metal bumps 27 and a second semiconductor chip 28 are provided on wiring substrate 21. Second semiconductor chip 28 is flip-chip mounted on wiring substrate 21. Second semiconductor chip 28 is mounted on wiring substrate 21 via the metal bumps. Spacers 22 are provided via die attach films (DAF) at positions on wiring substrate 21 where the laminate will be placed. As shown in FIG. 25, adhesive 50 is applied onto spacers 22.

[0077] 26, the stack shown in FIG. 19, minus the spacers 22, is placed upside down on the wiring board 21 prepared in FIG. 25. In this placement, the stack is positioned so that the vertical wires 26 are bonded to the metal bumps 27. The spacers 22 and the first semiconductor chip 23 are bonded via adhesive 50.

[0078] As shown in FIG. 27, a molding resin layer 30 is formed so as to cover the spacer 22, the first semiconductor chip 23, the support 24, the loop wires 25, the vertical wires 26, and the metal bumps 27.

[0079] As shown in FIG. 28, metal balls 29 are provided on the surface of wiring board 21 opposite to the surface on which first semiconductor chip 23 is mounted, and semiconductor device 2 is formed.

[0080] Next, a method for manufacturing the semiconductor device 2a will be described with reference to Figures 29 to 33. The formation of the stack is partially similar to the description given with reference to Figures 18 and 19. The difference is that while spacers 22 are arranged in Figures 18 and 19, the semiconductor device 2a does not have the spacers 22, and therefore the spacers 22 are not arranged.

[0081] 29, metal bumps 27 and a second semiconductor chip 28 are provided on wiring substrate 21. Second semiconductor chip 28 is flip-chip mounted on wiring substrate 21. Second semiconductor chip 28 is mounted on wiring substrate 21 via the metal bumps.

[0082] As shown in Fig. 30, the laminate shown in Fig. 19, minus the spacers 22, is placed upside down on the wiring board 21 prepared in Fig. 29. In this placement, the vertical wires 26 are positioned so as to bond to the metal bumps 27. The wiring board 21 and the laminate are bonded by thermocompression bonding.

[0083] As shown in FIG. 31, an underfill material (UF) 51 is filled between the wiring board 21 and the first semiconductor chip 23 and second semiconductor chip 28 that constitute the laminate.

[0084] As shown in FIG. 32, a molding resin layer 30 is formed so as to cover the first semiconductor chip 23, the support body 24, the loop wires 25, the vertical wires 26, and the metal bumps 27.

[0085] As shown in FIG. 33, metal balls 29 are provided on the surface of wiring board 21 opposite to the surface on which first semiconductor chip 23 is mounted, to form semiconductor device 2a.

[0086] Another method for manufacturing the semiconductor device 2a will be described with reference to Figures 34 to 37. The formation of the stack is partially similar to that described with reference to Figures 18 and 19. The difference is that while spacers 22 are arranged in Figures 18 and 19, the semiconductor device 2a does not have spacers 22, and therefore, no spacers 22 are arranged.

[0087] 34, metal bumps 27 are provided on wiring board 21. Non-conductive paste (NCP) 52 is applied to the positions on wiring board 21 where the laminate will be placed and the positions where second semiconductor chip 28 will be placed. The non-conductive paste (NCP) is a thermosetting paste made of epoxy resin or the like.

[0088] As shown in Fig. 35, the laminate shown in Fig. 19, minus the spacers 22, is placed upside down on the wiring board 21 prepared in Fig. 34. In this placement, the vertical wires 26 are positioned so as to bond to the metal bumps 27. The wiring board 21 and the laminate are bonded by thermocompression bonding.

[0089] As shown in FIG. 36, a molding resin layer 30 is formed so as to cover the first semiconductor chip 23, the support body 24, the loop wires 25, the vertical wires 26, and the metal bumps 27.

[0090] As shown in FIG. 37, metal balls 29 are provided on the surface of wiring board 21 opposite to the surface on which first semiconductor chip 23 is mounted, to form semiconductor device 2a.

[0091] The present embodiment has been described above with reference to specific examples. However, the present disclosure is not limited to these specific examples. Design modifications to these specific examples made by a person skilled in the art as appropriate are also included within the scope of the present disclosure as long as they comprise the features of the present disclosure. The elements of the above-described specific examples, as well as their arrangement, conditions, shape, etc., are not limited to those exemplified and can be modified as appropriate. The elements of the above-described specific examples can be combined in various ways as appropriate, as long as no technical contradictions arise. [Explanation of symbols]

[0092] 2: Semiconductor device 21: Wiring board 22: Spacer 23: First semiconductor chip 24:Support 25: Loop wire 26: Vertical wire 27: Metal bump 28: Second semiconductor chip 29: Metal ball 30: Mold resin layer

Claims

1. a wiring substrate having a wiring layer provided therein; a plurality of first semiconductor chips stacked on the wiring substrate in a shifted manner, the first semiconductor chips having connection terminals on surfaces facing the wiring substrate; a second semiconductor chip provided on the wiring substrate on a side where the connection terminal and the wiring substrate are electrically connected, the second semiconductor chip having a function different from that of the first semiconductor chip; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein said plurality of first semiconductor chips are electrically connected to one another, and said connection terminals provided on some of said first semiconductor chips are electrically connected to said wiring substrate.

3. 2. The semiconductor device according to claim 1, wherein the plurality of first semiconductor chips are divided into a plurality of groups and provided on the wiring substrate, and the heights of the stacked plurality of first semiconductor chips are different in the groups.

4. 2. The semiconductor device according to claim 1, wherein the position where the plurality of first semiconductor chips are provided overlaps the position where the second semiconductor chip is provided.

5. 2. The semiconductor device according to claim 1, wherein a first resin covering the first semiconductor chip and the second semiconductor chip on the wiring substrate is different from a second resin in contact with the wiring substrate and the first semiconductor chip.

6. The semiconductor device according to claim 1 , further comprising a spacer provided between said plurality of first semiconductor chips and said wiring substrate.

7. 7. The semiconductor device according to claim 6, wherein a first resin covering the first semiconductor chip and the second semiconductor chip on the wiring substrate is different from a third resin in contact with the spacer and the first semiconductor chip.

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