Semiconductor Devices
The semiconductor device addresses on-resistance and switching loss by optimizing layer configurations with varying impurity concentrations and trench structures, achieving reduced capacitances and improved performance.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2026-01-14
- Publication Date
- 2026-03-11
AI Technical Summary
Existing semiconductor devices with trench gate structures face challenges in reducing on-resistance and switching loss.
The semiconductor device incorporates a specific layer configuration with a first current spreading layer having a lower impurity concentration than a second current spreading layer, and a high-concentration layer in contact with the trench, which reduces on-resistance and switching loss by optimizing impurity concentrations and trench structure.
This configuration effectively reduces gate-drain and drain-source capacitances, leading to decreased switching loss and improved mass productivity while maintaining low on-resistance.
Smart Images
Figure 2026043040000001_ABST
Abstract
Description
[Technical Field]
[0001] The present invention relates to a semiconductor device having a trench gate structure. [Background technology]
[0002] Conventionally, a semiconductor device has been proposed in which a MOSFET (an abbreviation for metal oxide semiconductor field effect transistor) having a trench gate structure is formed (see, for example, Patent Document 1). + On a type substrate, an n-type substrate with a lower impurity concentration than the substrate is - A p-type buffer layer is formed, and a low-concentration layer having a lower impurity concentration than the buffer layer is formed on the buffer layer. A p-type first deep layer and an n-type first current spreading layer are formed on the low-concentration layer, extending in one direction as the longitudinal direction. The first deep layers and first current spreading layers are alternately arranged in a direction intersecting the longitudinal direction, with the first current spreading layers located between adjacent first deep layers.
[0003] An n-type current spreading layer and a p-type second deep layer are disposed on the first deep layer and the first current spreading layer. A p-type base layer is disposed on the first current spreading layer and the second deep layer. The second deep layer is disposed so as to connect the first deep layer and the base layer.
[0004] The surface of the base layer is + A source region of a silicon nitride semiconductor is formed in the base layer. A plurality of trenches are formed through the source region and the base layer to reach the current spreading layer, and a gate insulating film and a gate electrode are formed in each trench in this order, thereby forming a trench gate structure. [Prior art documents] [Patent documents]
[0005] [Patent Document 1] Japanese Patent Application Publication No. 2019-016775 Summary of the Invention [Problem to be solved by the invention]
[0006] In the semiconductor device described above, there is a demand for reducing the on-resistance and the switching loss.
[0007] In view of the above, an object of the present invention is to provide a semiconductor device that can reduce on-resistance and switching loss. [Means for solving the problem]
[0008] Claim 1 for achieving the above object is a semiconductor device having a trench gate structure, comprising: a first impurity region (11) of a first conductivity type or a second conductivity type; a low-concentration layer (13) of the first conductivity type arranged on the first impurity region and having a lower impurity concentration than the first impurity region; a first deep layer (15) of the second conductivity type arranged on the low-concentration layer and having a plurality of linear portions extending in one direction intersecting with the stacking direction of the first impurity region and the low-concentration layer; a first current spreading layer (14) of the first conductivity type arranged on the low-concentration layer and having linear portions sandwiched between the first deep layers; a second current spreading layer (17) of the first conductivity type arranged on the first current spreading layer; a second deep layer (18) of the second conductivity type arranged on the first deep layer; the second current spreading layer has a higher impurity concentration than the first current spreading layer, and a high-concentration layer (31) having a higher impurity concentration than the second current spreading layer is disposed in the second current spreading layer, and the high-concentration layer is disposed away from the base layer and has a portion in contact with a side surface of the trench.
[0009] This allows the on-resistance to be reduced while the capacitances are reduced, thereby reducing switching loss.
[0010] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]
[0011] [Figure 1] 1 is a perspective cross-sectional view of a SiC semiconductor device according to a first embodiment. [Figure 2] FIG. 10 is a diagram showing the results of a simulation regarding the relationship between the on-resistance and the gate-drain capacitance. [Figure 3] FIG. 10 is a diagram showing the results of a simulation regarding the relationship between the on-resistance and the drain-source capacitance. [Figure 4] FIG. 10 is a perspective cross-sectional view of a SiC semiconductor device according to a second embodiment. [Figure 5] FIG. 4 is a diagram showing a simulation result regarding current density in an on-state in the SiC semiconductor device of the first embodiment. [Figure 6] FIG. 4 is a diagram showing a simulation result regarding the electron density in the on-state in the SiC semiconductor device of the first embodiment. [Figure 7] FIG. 10 is a perspective cross-sectional view of a SiC semiconductor device according to a third embodiment. [Figure 8] FIG. 10 is a perspective cross-sectional view of a SiC semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION
[0012] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, parts that are identical or equivalent to each other will be denoted by the same reference numerals.
[0013] (First embodiment) A first embodiment will be described with reference to the drawings. In this embodiment, a silicon carbide (hereinafter also referred to as SiC) semiconductor device in which an inversion MOSFET with a trench gate structure is formed will be described as an example. Note that, although the configuration of a cell region in the SiC semiconductor device in which the MOSFET is formed will be described below, an actual SiC semiconductor device has an outer periphery region in which an FLR (abbreviation for Field Limiting Ring) structure or the like is formed so as to surround the cell region. Furthermore, the SiC semiconductor device of this embodiment is suitable for use, for example, as a device mounted on a vehicle such as an automobile and used to drive various electronic devices for the vehicle.
[0014] In the following description, one direction in the surface direction of the substrate 11 (described later) is referred to as the X-axis direction, a direction intersecting the one direction in the surface direction of the substrate is referred to as the Y-axis direction, and a direction perpendicular to the X-axis direction and the Y-axis direction is referred to as the Z-axis direction. In this embodiment, the X-axis direction and the Y-axis direction are perpendicular to each other. In addition, the Z-axis direction in this embodiment corresponds to the thickness direction of the semiconductor substrate 10 (described later) and also corresponds to the stacking direction of the substrate 11 and the low-concentration layer 13 (described later).
[0015] As shown in Fig. 1, the SiC semiconductor device is configured using a semiconductor substrate 10. Specifically, the SiC semiconductor device is configured using an n-type SiC semiconductor device. + In this embodiment, the substrate 11 has an off-angle of 0 to 8° with respect to the (0001) Si plane, and has an n-type impurity concentration of 1.0×10 19 / cm 3 The substrate 11 has a thickness of about 300 μm. In this embodiment, the substrate 11 constitutes the drain region, and corresponds to the first impurity region.
[0016] On the surface of the substrate 11, a n-type SiC substrate is formed. - An n-type buffer layer 12 is formed on the surface of the substrate 11. The buffer layer 12 is formed by epitaxial growth on the surface of the substrate 11. The buffer layer 12 has an n-type impurity concentration that is between that of the substrate 11 and a low-concentration layer 13, which will be described later, and has a thickness of about 1 μm.
[0017] On the surface of the buffer layer 12, for example, an n-type impurity concentration of 5.0 to 20.0×10 15 / cm 3 The thickness is about 10 to 15 μm, and the n - A low-concentration layer 13 of a mold is formed. The impurity concentration of this low-concentration layer 13 may be constant in the Z-axis direction, but it is preferable to provide a gradient in the concentration distribution so that the low-concentration layer 13 has a higher concentration on the substrate 11 side than on the side away from the substrate 11. For example, the low-concentration layer 13 has an impurity concentration of 2.0×10 in a portion about 3 to 5 μm from the surface of the substrate 11.15 / cm 3 It is preferable that the internal resistance of the low concentration layer 13 is set to be higher than that of other portions. By adopting such a configuration, the internal resistance of the low concentration layer 13 can be reduced, and the on-resistance can be reduced.
[0018] A first current spreading layer 14 and a first deep layer 15 are formed in the surface portion of the low-concentration layer 13. In this embodiment, the first current spreading layer 14 and the first deep layer 15 each extend along the X-axis direction and have linear portions arranged alternately and repeatedly in the Y-axis direction. That is, the first current spreading layer 14 and the first deep layer 15 are configured in stripes extending along the X-axis direction in the normal direction to the surface of the substrate 11, and are arranged alternately along the Y-axis direction. Note that the normal direction to the surface of the substrate 11 can also be referred to as when viewed from the normal direction to the surface of the substrate 11. The normal direction to the surface of the substrate 11 is also the direction along the stacking direction of a drift layer 19 and a base layer 21 (described later) and is the direction along the Z-axis direction.
[0019] The first current spreading layer 14 is of n-type with a higher impurity concentration than the low concentration layer 13, and has a thickness of 0.3 to 1.5 μm. In this embodiment, the first current spreading layer 14 has an n-type impurity concentration of 5.0×10 16 ~1.0×10 17 / cm 3 The first deep layer 15 has a p-type impurity concentration of about 2.0×10 17 ~2.0×10 18 / cm 3 It is said to be about that level.
[0020] Moreover, the first deep layer 15 of this embodiment is formed shallower than the first current spreading layer 14. That is, the first deep layer 15 is formed so that its bottom is located within the first current spreading layer 14. In other words, the first deep layer 15 is formed so that the first current spreading layer 14 is located between the first deep layer 15 and the low concentration layer 13. Note that such first current spreading layer 14 and first deep layer 15 are formed, for example, by ion-implanting appropriate impurities into the surface layer portion of the low concentration layer 13.
[0021] On the first current spreading layer 14 and the first deep layer 15, a second current spreading layer 17, a second deep layer 18, a base layer 21, a source region 22, a contact region 23, and the like are formed.
[0022] The second current spreading layer 17 is of n-type and has a higher impurity concentration than the low-concentration layer 13, and is formed so as to be connected to the first current spreading layer 14. Therefore, in this embodiment, the low-concentration layer 13, the first current spreading layer 14, and the second current spreading layer 17 are connected, and these layers form the drift layer 19. The second current spreading layer 17 has a thickness of 0.5 to 2.0 μm and an n-type impurity concentration of 1.0×10 17 ~3.0×10 17 cm 3 However, the impurity concentration of the second current spreading layer 17 in this embodiment is adjusted to be higher than the impurity concentration of the first current spreading layer 14, using the impurity concentration of the first current spreading layer 14 as a reference.
[0023] The second deep layer 18 is of p-type and has the same thickness as the second current spreading layer 17. The second deep layer 18 is formed so as to be connected to the first deep layer 15. The second deep layer 18 of this embodiment has a p-type impurity concentration of 2.0×10 17 ~2.0×10 18 / cm 3 It is said to be about that level.
[0024] The second current spreading layer 17 and the second deep layer 18 extend in a direction intersecting the longitudinal direction of the striped portion of the first current spreading layer 14 and the first deep layer 15. In this embodiment, the second current spreading layer 17 and the second deep layer 18 extend in the Y-axis direction as their longitudinal direction, and are laid out such that multiple layers are alternately arranged in the X-axis direction. The formation pitch of the second current spreading layer 17 and the second deep layer 18 matches the formation pitch of a trench gate structure described later, and the second deep layers 18 are formed to sandwich a trench 25 described later.
[0025] Such second current spreading layer 17 and second deep layer 18 are constructed, for example, by placing an n-type layer of SiC that constitutes the second current spreading layer 17, and then ion-implanting p-type impurities into a predetermined region of the n-type layer to form the second deep layer 18.
[0026] The base layer 21 is of p-type and is formed on the second current spreading layer 17 and the second deep layer 18. Therefore, the first deep layer 15 is connected to the base layer 21 via the second deep layer 18. The base layer 21 has a p-type impurity concentration of, for example, 5.0×10 16 ~2.0×10 19 / cm 3 The thickness is said to be about 2.0 μm.
[0027] The source region 22 is + The contact region 23 is a p + The source region 22 is formed in a surface layer portion of the base layer 21. Specifically, the source region 22 is formed so as to contact the side surface of a trench 25, which will be described later, and the contact region 23 is formed on the opposite side of the source region 22 from the trench 25, which will be described later. In this embodiment, the source region 22 has an n-type impurity concentration (i.e., surface concentration) in the surface layer portion of the source region 22 of, for example, 1.0×10 21 / cm 3The contact region 23 has a p-type impurity concentration in the surface layer (i.e., surface concentration) of, for example, 1.0×10 21 / cm 3 The thickness is set to about 0.3 μm. In this embodiment, the source region 22 corresponds to the second impurity region.
[0028] In this embodiment, as described above, the semiconductor substrate 10 is configured to include the substrate 11, buffer layer 12, low-concentration layer 13, first current spreading layer 14, first deep layer 15, second current spreading layer 17, second deep layer 18, base layer 21, source region 22, contact region 23, etc. Since the semiconductor substrate 10 is configured as described above, it can be said that the semiconductor substrate 10 is configured of SiC. Furthermore, in this embodiment, one surface 10a of the semiconductor substrate 10 is configured by the source region 22 and the contact region 23, and the other surface 10b of the semiconductor substrate 10 is configured by the substrate 11.
[0029] In the semiconductor substrate 10, a trench 25 having a width of, for example, 1.4 to 2.0 μm is formed so that the trench 25 penetrates the source region 22, the base layer 21, etc., from the one surface 10a side to reach the second current spreading layer 17, and the bottom surface is located within the second current spreading layer 17. The trench 25 is formed so as not to reach the first current spreading layer 14 and the first deep layer 15. In other words, the trench 25 is formed so that the first current spreading layer 14 and the first deep layer 15 are located below the bottom surface and apart from the trench 25.
[0030] 1, a plurality of trenches 25 are actually formed extending along the Y-axis direction and arranged at equal intervals in the X-axis direction to form stripes. That is, in this embodiment, the trenches 25 are formed so that their longitudinal direction is perpendicular to the longitudinal direction of the first deep layer 15. The trenches 25 are also formed so as to be sandwiched between the second deep layers 18 in the stacking direction of the drift layer 19 and the base layer 21.
[0031] A gate insulating film 26 is formed on the inner wall surface of the trench 25, and a gate electrode 27 made of doped poly-Si or the like is formed on the gate insulating film 26. This forms a trench gate structure. Although not particularly limited, the gate insulating film 26 is formed by thermally oxidizing the inner wall surface of the trench 25 or by performing a CVD (short for chemical vapor deposition) method. The gate insulating film 26 has a thickness of about 100 nm on both the side and bottom sides of the trench 25.
[0032] The gate insulating film 26 is also formed on surfaces other than the inner wall surfaces of the trench 25. Specifically, the gate insulating film 26 is formed so as to cover a portion of the one surface 10a of the semiconductor substrate 10. More specifically, the gate insulating film 26 is formed so as to cover a portion of the surface of the source region 22. In other words, the gate insulating film 26 has contact holes 26a that expose the source region 22 and the contact region 23 in a portion different from the portion where the gate electrode 27 is disposed.
[0033] An interlayer insulating film 28 is formed on one surface 10a of the semiconductor substrate 10 so as to cover the gate electrode 27, the gate insulating film 26, etc. The interlayer insulating film 28 is made of BPSG (abbreviation of borophosphosilicate glass) or the like.
[0034] A contact hole 28a is formed in the interlayer insulating film 28, communicating with the contact hole 26a and exposing the source region 22 and the contact region 23. The contact hole 28a formed in the interlayer insulating film 28 is formed to communicate with the contact hole 26a formed in the gate insulating film 26, and functions together with the contact hole 26a as a single contact hole. For this reason, hereinafter, the contact holes 26a and 28a are collectively referred to as contact holes 26b. The contact holes 26b may have any pattern, including, for example, a pattern in which multiple squares are arranged, a pattern in which rectangular lines are arranged, or a pattern in which lines are lined up. In this embodiment, the contact holes 26b are linear along the longitudinal direction of the trench 25.
[0035] An upper electrode 29 is formed on the interlayer insulating film 28. The upper electrode 29 is electrically connected to the source region 22 and the contact region 23 through the contact hole 26b. In this embodiment, the upper electrode 29 corresponds to the first electrode.
[0036] The upper electrode 29 of this embodiment is made of a plurality of metals, such as Ni / Al. The portion of the plurality of metals that contacts the portion that constitutes the n-type SiC (i.e., the source region 22) is made of a metal that can make ohmic contact with the n-type SiC. Furthermore, the portion of the plurality of metals that contacts at least the p-type SiC (i.e., the base layer 21) is made of a metal that can make ohmic contact with the p-type SiC.
[0037] A lower electrode 30 electrically connected to the substrate 11 is formed on the other surface 10b of the semiconductor substrate 10. In this embodiment, the lower electrode 30 corresponds to the second electrode.
[0038] In the SiC semiconductor device of this embodiment, an n-channel inversion type trench gate MOSFET is configured with such a structure. - type, n type, n+ The first conductivity type corresponds to p-type, p + The type corresponds to the second conductivity type.
[0039] The above is the configuration of the SiC semiconductor device according to this embodiment. Next, the operation and effects of the SiC semiconductor device will be described.
[0040] First, in the SiC semiconductor device, in the off state before a gate voltage equal to or higher than the threshold voltage is applied to the gate electrode 27, no inversion layer is formed in the base layer 21. Therefore, even if a positive voltage, for example, 1600 V, is applied to the lower electrode 30, electrons do not flow from the source region 22 into the base layer 21, and the SiC semiconductor device enters an off state in which no current flows between the upper electrode 29 and the lower electrode 30.
[0041] Furthermore, when the SiC semiconductor device is in an off state, an electric field is applied between the gate and drain, which can cause electric field concentration at the bottom of the gate insulating film 26. However, in the above-described SiC semiconductor device, the first deep layer 15 and the first current spreading layer 14 are provided at a position deeper than the trench 25. Therefore, the depletion layer formed between the first deep layer 15 and the first current spreading layer 14 suppresses the rise of equipotential lines due to the influence of the drain voltage, making it difficult for a high electric field to penetrate into the gate insulating film 26. Therefore, in this embodiment, it is possible to suppress breakdown of the gate insulating film 26.
[0042] When a gate voltage equal to or higher than the threshold voltage, for example, 20 V, is applied to gate electrode 27, an inversion layer is formed on the surface of base layer 21 that contacts trench 25. As a result, a current flows between upper electrode 29 and lower electrode 30, and the SiC semiconductor device is turned on. In this embodiment, electrons that have passed through the inversion layer pass through second current spreading layer 17, first current spreading layer 14, and low-concentration layer 13 and flow to substrate 11, so that drift layer 19 having second current spreading layer 17, first current spreading layer 14, and low-concentration layer 13 can be said to be configured.
[0043] In this embodiment, the impurity concentration of the second current spreading layer 17 is set higher than the impurity concentration of the first current spreading layer 14. Therefore, compared to when the impurity concentration of the second current spreading layer 17 is set the same as that of the first current spreading layer 14, the resistance value of the second current spreading layer 17 can be lowered, and the on-resistance can be reduced.
[0044] Furthermore, the gate-drain capacitance Cgd (i.e., the feedback capacitance Crss) depends on the capacitance of the gate insulating film 26 and the extension of the depletion layer of the PN junction formed between the second current spreading layer 17 and the second deep layer 18, etc. In this case, if the impurity concentration of the first current spreading layer 14 is equal to or higher than the impurity concentration of the second current spreading layer 17, the depletion layer may be more likely to penetrate into the first deep layer 15 and extend, compared to when the impurity concentration of the second current spreading layer 17 is higher than the impurity concentration of the first current spreading layer 14. In other words, if the impurity concentration of the first current spreading layer 14 is equal to or higher than the impurity concentration of the second current spreading layer 17, the gate-drain capacitance Cgd may be large. For this reason, in this embodiment, the impurity concentration of the first current spreading layer 14 is set lower than the impurity concentration of the second current spreading layer 17.
[0045] Here, the SiC semiconductor device in which the impurity concentration of the second current spreading layer 17 is lower than the impurity concentration of the first current spreading layer 14 is referred to as the SiC semiconductor device of the first comparative example. Also, the SiC semiconductor device in which the impurity concentration of the second current spreading layer 17 is the same as the impurity concentration of the first current spreading layer 14 is referred to as the SiC semiconductor device of the second comparative example.
[0046] In this case, as shown in FIG. 2, in the SiC semiconductor device of the first comparative example, it is confirmed that when the impurity concentration of the second current spreading layer 17 is increased to decrease the on-resistance, the gate-drain capacitance Cgd gradually increases. In the SiC semiconductor device of the second comparative example, it is confirmed that when the impurity concentration of the second current spreading layer 17 is increased to decrease the on-resistance, the gate-drain capacitance Cgd increases sharply. In contrast, in the SiC semiconductor device of this embodiment, it is confirmed that the gate-drain capacitance Cgd can also be reduced even if the impurity concentration of the second current spreading layer 17 is increased to decrease the on-resistance. Note that FIG. 2 shows the results when the current density is 831 A / cm 2 The figure shows the simulation results when the drain-source voltage Vds is set to 10 V and the ambient temperature is set to 25°C.
[0047] Furthermore, as shown in FIG. 3, in the SiC semiconductor device of the first comparative example, it is confirmed that the drain-source capacitance Cds gradually increases when the impurity concentration of the second current spreading layer 17 is increased to decrease the on-resistance. In the SiC semiconductor device of the second comparative example, it is confirmed that the drain-source capacitance Cds increases sharply when the impurity concentration of the second current spreading layer 17 is increased to decrease the on-resistance. In contrast, in the SiC semiconductor device of this embodiment, it is confirmed that the drain-source capacitance Cds can also be reduced even when the impurity concentration of the second current spreading layer 17 is increased to decrease the on-resistance. Note that FIG. 3 shows the results when the current density is 831 A / cm 2 The figure shows the simulation results when the drain-source voltage Vds is set to 10 V and the ambient temperature is set to 25°C.
[0048] As described above, in the SiC semiconductor device of this embodiment, the gate-drain capacitance Cgd and the drain-source capacitance Cds can be reduced, and therefore the output capacitance Coss can be reduced, thereby enabling a reduction in switching loss.
[0049] In the SiC semiconductor device of the second comparative example, depending on the on-resistance, the gate-drain capacitance Cgd and the drain-source capacitance Cds may be lower than those of the SiC semiconductor device of this embodiment. However, in the SiC semiconductor device of the second comparative example, as shown in FIG. 2, the gate-drain capacitance Cgd increases sharply with the on-resistance, and as shown in FIG. 3, the drain-source capacitance Cds may increase sharply with the on-resistance. Therefore, the SiC semiconductor device of the second comparative example is prone to large fluctuations in characteristics due to manufacturing variations, which may reduce mass productivity. In contrast, in the SiC semiconductor device of this embodiment, changes in the gate-drain capacitance Cgd and the drain-source capacitance Cds due to changes in on-resistance are small, so mass productivity is not reduced.
[0050] Furthermore, in the SiC semiconductor device of this embodiment, a parasitic diode is formed that includes the n-type drift layer 19, etc., the p-type base layer 21, the second deep layer 18, the first deep layer 15, etc. In the SiC semiconductor device of this embodiment configured as described above, even if the impurity concentration of the second current spreading layer 17 is increased so as to reduce the on-resistance, the drain-source capacitance Cds (i.e., the junction capacitance of the parasitic diode) can be reduced. Therefore, according to this embodiment, it is possible to reduce the on-resistance and switching loss while also suppressing an increase in recovery loss.
[0051] According to the present embodiment described above, the impurity concentration of the second current spreading layer 17 is set higher than the impurity concentration of the first current spreading layer 14. This makes it possible to reduce the gate-drain capacitance Cgd and the drain-source capacitance Cds while reducing the on-resistance, thereby reducing switching loss. Furthermore, because the impurity concentration of the second current spreading layer 17 is set higher than the impurity concentration of the first current spreading layer 14, recovery loss can also be reduced.
[0052] (Second embodiment) A second embodiment will be described. This embodiment is the same as the first embodiment except that a high concentration layer is added. As the other features are the same as the first embodiment, a description thereof will be omitted here.
[0053] 4, in the SiC semiconductor device of this embodiment, a high-concentration layer 31 is formed so as to be in contact with the bottom of the trench 25. The high-concentration layer 31 has an n-type impurity layer having a higher impurity concentration than the second current spreading layer 17. + For example, the impurity concentration is 7.0 × 10 17 ~2.0×10 18 cm / 3 In addition, the high concentration layer 31 of this embodiment is formed to be wider than the width of the trench 25.
[0054] Next, the operation and effects of the SiC semiconductor device of this embodiment will be described.
[0055] First, in a SiC semiconductor device such as that of the first embodiment, a pn junction is formed between the n-type first current spreading layer 14, second current spreading layer 17, etc. and the p-type first deep layer 15, second deep layer 18, and base layer 21. In the on state, a depletion layer D resulting from the pn junction expands, as shown in FIGS. 5 and 6. Note that FIGS. 5 and 6 are schematic diagrams of the vicinity of trench 25, and are cross-sectional views of a portion in which the first current spreading layer 14 is taken as the XZ plane. In FIGS. 5 and 6, the region surrounded by dotted lines constitutes the depletion layer D.
[0056] In this case, if the depletion layer D extends toward the trench 25, the path through which current can flow in the second current spreading layer 17 becomes narrower, which causes an increase in on-resistance. For this reason, in this embodiment, the high-concentration layer 31 is formed so as to be in contact with the bottom of the trench 25. This makes it possible to prevent the depletion layer D from extending toward the trench 25, thereby improving the current capability. In this case, the high-concentration layer 31 in this embodiment is wider than the width of the trench 25. This makes it possible to further prevent the depletion layer D from extending toward the trench 25.
[0057] Furthermore, in the SiC semiconductor device described above, a parasitic diode is formed. In this case, when the parasitic diode operates, the formation of the high-concentration layer 31 makes it difficult for holes to be injected from the base layer 21 into the second current spreading layer 17. Therefore, it is possible to reduce recovery loss.
[0058] Such a SiC semiconductor device is manufactured by, after forming the trench 25, performing ion implantation of n-type impurities into the bottom surface of the trench 25 before arranging the gate insulating film 26.
[0059] According to the present embodiment described above, the impurity concentration of the second current spreading layer 17 is set higher than the impurity concentration of the first current spreading layer 14, and therefore, the same effects as those of the first embodiment can be obtained.
[0060] (1) In this embodiment, the high-concentration layer 31 is formed so as to contact the bottom of the trench 25. This prevents the depletion layer from extending too far toward the trench 25 in the on-state, thereby improving the current capability. The current capability can also be improved by making the impurity concentration of the second current spreading layer 17 the same as that of the high-concentration layer 31. However, if the overall impurity concentration of the second current spreading layer 17 is made the same as that of the high-concentration layer 31, the gate-drain capacitance Cgd increases, resulting in increased switching loss. Therefore, in this embodiment, the high-concentration layer 31 is disposed within the second current spreading layer 17.
[0061] (Third embodiment) A third embodiment will be described. This embodiment is different from the second embodiment in that the location of the high concentration layer 31 is changed. As the rest is the same as the second embodiment, a description thereof will be omitted here.
[0062] 7, in the SiC semiconductor device of this embodiment, the second current spreading layer 17 has a high-concentration layer 31 arranged along the surface direction of the semiconductor substrate 10. That is, the second current spreading layer 17 has the high-concentration layer 31 arranged along a direction intersecting the stacking direction of the substrate 11 and the low-concentration layer 13. In this embodiment, the high-concentration layer 31 is arranged in the second current spreading layer 17 so as to be in contact with the side surface of the trench 25 and the second deep layer 18. Note that such a high-concentration layer 31 is formed by ion-implanting n-type impurities into the second current spreading layer 17 at a predetermined acceleration voltage using an appropriate mask.
[0063] According to the present embodiment described above, the impurity concentration of the second current spreading layer 17 is set higher than the impurity concentration of the first current spreading layer 14, and therefore, the same effects as those of the first embodiment can be obtained.
[0064] (1) Even if the high concentration layer 31 is arranged along the surface direction of the semiconductor substrate 10 as in this embodiment, the same effects as those of the second embodiment can be obtained.
[0065] (Fourth embodiment) A fourth embodiment will be described. This embodiment is different from the second embodiment in that the location of the high concentration layer 31 is changed. As the rest is the same as the second embodiment, a description thereof will be omitted here.
[0066] 8, in the SiC semiconductor device of this embodiment, a high-concentration layer 31 is formed in the second current spreading layer 17 along the thickness direction. In this embodiment, the high-concentration layer 31 is disposed at the interface between the second current spreading layer 17 and the second deep layer 18. Note that such a high-concentration layer 31 is formed by ion-implanting n-type impurities into the second current spreading layer 17 at a predetermined acceleration voltage using an appropriate mask.
[0067] According to the present embodiment described above, the impurity concentration of the second current spreading layer 17 is set higher than the impurity concentration of the first current spreading layer 14, and therefore, the same effects as those of the first embodiment can be obtained.
[0068] (1) As in this embodiment, even if the high-concentration layer 31 is arranged along the normal direction to the surface direction of the substrate 11, the same effect as in the second embodiment can be obtained. Furthermore, by arranging the high-concentration layer 31 at the interface between the second current spreading layer 17 and the second deep layer 18 as in this embodiment, when the parasitic diode operates, it becomes more difficult for holes to be injected into the second current spreading layer 17 from the base layer 21 side. This makes it possible to further reduce recovery loss.
[0069] (Other embodiments) Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.
[0070] For example, in the above-described embodiments, an n-channel type trench gate structure MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. However, the SiC semiconductor device may be configured by forming a p-channel type trench gate structure MOSFET in which the conductivity type of each component is inverted from that of the n-channel type. Furthermore, the SiC semiconductor device may be configured by forming an IGBT with a similar structure in addition to the MOSFET. In the case of an IGBT (abbreviation for Insulated Gate Bipolar Transistor), the n-channel type MOSFET in the above-described embodiments may be formed by forming a p-channel type trench gate structure MOSFET in which the conductivity type of each component is inverted from that of the n-channel type. + The substrate 11 is + Except for the change to the substrate 11 of the same type, the MOSFET is the same as that described in the first embodiment.
[0071] In addition, in each of the above embodiments, an example has been described in which the linear portions of the first current spreading layer 14 and the first deep layer 15 are formed along a direction intersecting the longitudinal direction of the trench 25, and the second current spreading layer 17 and the second deep layer 18 are formed along the longitudinal direction of the trench 25. However, the linear portions of the first current spreading layer 14 and the first deep layer 15 may be formed along the longitudinal direction of the trench 25. Alternatively, the linear portions of the first current spreading layer 14 and the first deep layer 15 may be formed in a direction intersecting the longitudinal direction of the trench 25, and the second current spreading layer 17 and the second deep layer 18 may be formed along a direction intersecting the longitudinal direction of the trench 25.
[0072] Furthermore, in each of the above embodiments, an example has been described in which the semiconductor substrate 10 is made of SiC, but the semiconductor substrate 10 may be made of silicon, other compound semiconductors, etc.
[0073] Furthermore, in the second embodiment, the high-concentration layer 31 may be formed narrower than the width of the trench 25, but is preferably long enough to prevent the depletion layer D from penetrating below the trench 25. In the third embodiment, the high-concentration layer 31 may be formed so as to contact the side surface of the trench 25 and one of the second deep layers 18. Furthermore, in the third embodiment, the high-concentration layer 31 may be formed closer to the first current spreading layer 14 than the bottom surface of the trench 25. In the fourth embodiment, the high-concentration layer 31 may be formed on the trench 25 side, rather than at the interface with the second deep layer 18. In other words, the location of the high-concentration layer 31 can be changed as appropriate, taking the impurity concentration into consideration, as long as the depletion layer D is prevented from penetrating below the trench 25.
[0074] The above embodiments can also be combined as appropriate. For example, the second embodiment can be combined with the third or fourth embodiment, and the high-concentration layer 31 can be formed so as to contact the bottom surface of the trench 25. The third embodiment can be combined with the fourth embodiment, and the high-concentration layer 31 can be formed along the surface direction of the substrate 11. Furthermore, combinations of the above embodiments can also be combined with each other. [Explanation of symbols]
[0075] 11 Substrate (first impurity region) 13 Low concentration layer 14 1st current distribution layer 15 First Deep Layer 17 Second current distribution layer 18 Second Deep Layer 22 Source region (second impurity region) 25 Trench 26 Gate insulating film 27 Gate electrode 29 Upper electrode (1st electrode) 30 Lower electrode (second electrode)
Claims
1. A semiconductor device having a trench gate structure, a first impurity region (11) of a first conductivity type or a second conductivity type; a low-concentration layer (13) of a first conductivity type disposed on the first impurity region and having a lower impurity concentration than the first impurity region; a first deep layer (15) of a second conductivity type disposed on the low concentration layer and having a plurality of linear portions whose longitudinal direction is in one direction intersecting with the stacking direction of the first impurity region and the low concentration layer; a first current spreading layer (14) of a first conductivity type disposed on the low concentration layer and having a linear portion sandwiched between the first deep layers; a second current spreading layer (17) of the first conductivity type disposed on the first current spreading layer; a second deep layer (18) of a second conductivity type disposed on the first deep layer; a base layer (21) of a second conductivity type disposed on the second current spreading layer and the second deep layer; a second impurity region (22) of the first conductivity type formed in a surface layer portion of the base layer; the trench gate structure having a gate insulating film (26) formed on a wall surface of a trench (25) that penetrates the second impurity region and the base layer to reach the second current spreading layer, and a gate electrode (27) formed on the gate insulating film; a first electrode (29) electrically connected to the second impurity region and the base layer; a second electrode (30) electrically connected to the first impurity region; the second current spreading layer has a higher impurity concentration than the first current spreading layer, A high concentration layer (31) having a higher impurity concentration than the second current spreading layer is disposed in the second current spreading layer, The high concentration layer is disposed away from the base layer and has a portion in contact with a side surface of the trench.
2. The semiconductor device according to claim 1 , wherein the high-concentration layer is disposed in a direction intersecting the stacking direction and is sandwiched between the second current spreading layers in the stacking direction.
Citation Information
Patent Citations
Semiconductor device and method of manufacturing the same
JP2019016775A