Semiconductor equipment

Abstract

The objective is to provide a semiconductor device that can increase the gate threshold voltage. [Solution] The semiconductor device of the embodiment comprises a semiconductor member, a drain electrode, a gate electrode, a source electrode, and an insulating film. The semiconductor member is provided with a first groove and a second groove. The gate electrode is located inside the first groove. The source electrode is located inside the second groove. The insulating film is provided on the inner surface of the second groove. The insulating film contains negative fixed charges. The first semiconductor region of the semiconductor member has a first conductivity type impurity. The second semiconductor region of the semiconductor member has a high concentration of the first conductivity type impurity. The second semiconductor region is located above the first semiconductor region. The source electrode is Schottky junctionable with the first semiconductor region. The source electrode is ohmic junctionable with the second semiconductor region. At least a portion of the first semiconductor region is located between the gate electrode and the source electrode. The insulating film is sandwiched between a portion of the first semiconductor region and the source electrode.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] There are semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) that can promote depletion of the semiconductor region by forming a Schottky junction to achieve an off state. In this structure, there is a problem that it is difficult to increase the gate threshold voltage.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor device capable of increasing the gate threshold voltage.

Means for Solving the Problems

[0005] The semiconductor device of the embodiment includes a semiconductor member, a drain electrode, a gate electrode, a source electrode, and an insulating film. The semiconductor member is provided with a first groove and a second groove. The first groove and the second groove extend in a first direction. The first groove and the second groove are aligned in a second direction intersecting the first direction. The first groove and the second groove are recessed on one side of a third direction intersecting both the first and second directions. The drain electrode is located on one side of the semiconductor member in the third direction. The gate electrode is located inside the first groove. The source electrode is located inside the second groove. The insulating film is provided on at least a portion of the inner surface of the second groove. The insulating film contains negative fixed charges. The semiconductor member is provided with a first semiconductor region and a second semiconductor region. The first semiconductor region has a first conductivity type impurity. The second semiconductor region has a higher concentration of the first conductivity type impurity than the first semiconductor region. The second semiconductor region is located on the other side of the third direction than the first semiconductor region. The source electrode is Schottky junctionable with a first semiconductor region. The source electrode is ohmic junctionable with a second semiconductor region. At least a portion of the first semiconductor region is located between the gate electrode and the source electrode in a second direction. An insulating film is sandwiched between the portion of the first semiconductor region and the source electrode in a second direction. [Brief explanation of the drawing]

[0006] [Figure 1] A schematic cross-sectional view of a semiconductor device according to one embodiment. [Figure 2] A schematic diagram of a semiconductor device of the first comparative form. [Figure 3] Partial schematic diagram of the semiconductor device of the second comparative form. [Figure 4] A graph showing the simulation results of the transfer characteristics of the semiconductor device in the embodiment and the first and second comparative embodiments. [Modes for carrying out the invention]

[0007] The semiconductor device of the embodiment will be described below with reference to the drawings.

[0008] Figure 1 is a schematic cross-sectional view of a semiconductor device 1 according to one embodiment. The X, Y, and Z axes are shown in the drawings as appropriate. The X, Y, and Z axes are orthogonal to each other.

[0009] In this specification, “direction” is defined as a vector that includes the concepts of positive and negative, parallel to a particular axis. Therefore, “direction” is a concept that encompasses two directions (one side and the other side) that point to opposite sides of each other. In the following embodiments, the direction parallel to the Y-axis corresponds to the “first direction,” the direction parallel to the X-axis corresponds to the “second direction intersecting the first direction,” and the direction parallel to the Z-axis corresponds to the “third direction intersecting both the first and second directions.” Furthermore, in the following embodiments, the side of the third direction Z opposite to the direction of the Z-axis arrow (-Z) is called the down side, or one side of the third direction, and the side of the third direction Z in which the Z-axis arrow points (+Z) is called the up side, or the other side of the third direction. Note that in this specification, the concepts of “up” and “down” do not necessarily indicate a relationship with the direction of gravity.

[0010] As shown in Figure 1, the semiconductor device 1 according to this embodiment includes a semiconductor member 10, a drain electrode (first electrode) 51, a source electrode (second electrode) 52, a gate electrode (third electrode) 53, a field plate (conductive member) 61, an insulating member 41, and an insulating film 45. In this specification, the thickness direction of the semiconductor device 1 (i.e., the direction from the drain electrode 51 to the source electrode 52) is the third direction Z.

[0011] The semiconductor device 1 in this embodiment is a trench-type metal-oxide-semiconductor field-effect transistor (MOSFET). Furthermore, the semiconductor device 1 in this embodiment is a Schottky contact type transistor. The semiconductor device 1 can control the depletion of the semiconductor region of the semiconductor material 10 by controlling the potential of the gate electrode 53. That is, the semiconductor device 1 can control the current flowing between the drain electrode 51 and the source electrode 52 by controlling the potential of the gate electrode 53.

[0012] The semiconductor component 10 includes, for example, at least one selected from the group consisting of silicon (Si), nitride semiconductors (e.g., GaN), silicon carbide (SiC), and oxide semiconductors (e.g., GaO).

[0013] The semiconductor member 10 is provided with a plurality of gate electrode grooves (first grooves) 21 and a plurality of source electrode grooves (second grooves) 22. The gate electrode grooves 21 and source electrode grooves 22 are recessed downward from the upper surface 10f of the semiconductor member 10 (on one side in the third direction Z). The gate electrode grooves 21 and source electrode grooves 22 extend in the first direction Y and are arranged alternately in the second direction X. Therefore, gate electrode grooves 21 are provided on both sides of the source electrode groove 22 in the second direction X.

[0014] The inner surface of the gate electrode groove 21 is provided with an upward-facing bottom portion 21a and a pair of side wall portions 21b that face each other in the second direction X. Similarly, the inner surface of the source electrode groove 22 is provided with an upward-facing bottom portion 22a and a pair of side wall portions 22b that face each other in the second direction X. The gate electrode groove 21 is formed deeper than the source electrode groove 22. That is, the bottom portion 21a of the gate electrode groove 21 is located below the bottom portion 22a of the source electrode groove 22. Also, the width dimension of the gate electrode groove 21 is greater than the width dimension of the source electrode groove 22. In the following description, the width dimension refers to the dimension in the second direction X.

[0015] The semiconductor member 10 includes a first semiconductor region 11 and a second semiconductor region 12. Both the first semiconductor region 11 and the second semiconductor region 12 are n-type semiconductors. When the semiconductor member 10 contains silicon, examples of impurities of the first conductivity type include pentavalent elements such as phosphorus and arsenic. That is, the impurities of the first conductivity type are n-type impurities. In the silicon-containing semiconductor member 10, the first semiconductor region 11 and the second semiconductor region 12 are formed by adding and diffusing pentavalent elements as impurities. Furthermore, impurities diffuse at a higher concentration in the second semiconductor region 12 than in the first semiconductor region 11. The first semiconductor region 11 is, for example, an n- layer. The second semiconductor region 12 is an n-layer or an n+ layer. In this embodiment, no p-type semiconductor is formed in the semiconductor member 10. Therefore, the manufacturing process of the semiconductor device 1 can be simplified.

[0016] The first semiconductor region 11 has a drift region 11a and a cell region 11c. The drift region 11a is the region in the first semiconductor region 11 below the lower end of the source electrode 52 (i.e., the lower end of the contact portion 52b, which will be described later). The lower end of the drift region 11a is in contact with the upper surface 51f of the drain electrode 51. The cell region 11c is located above the drift region 11a. The cell region 11c is the region sandwiched between the gate electrode groove 21 and the source electrode groove 22.

[0017] The cell region 11c is the region between the gate electrode groove 21 and the source electrode groove 22 in the first semiconductor region 11. That is, in the second direction X, the cell region 11c is located between the source electrode 52 and the gate electrode 53. The cell region 11c is located at the upper end of the first semiconductor region 11. The width dimension W of the cell region 11c is, for example, 25 nm or more and 100 nm or less.

[0018] The second semiconductor region 12 is formed to a certain depth from the upper surface 10f of the semiconductor member 10. The second semiconductor region 12 is provided above the first semiconductor region 11. The second semiconductor region 12 is in contact with the cell region 11c of the first semiconductor region 11. The second semiconductor region 12 is located above the bottom 21a of the gate electrode trench 21 and the bottom 22a of the source electrode trench 22. For this reason, the second semiconductor region 12 is divided by the gate electrode trench 21 and the source electrode trench 22 in the second direction X. The width dimension of the second semiconductor region 12 is substantially equal to the width dimension W of the cell region 11c.

[0019] The drain electrode 51, the source electrode 52, the gate electrode 53, and the field plate 61 each extend along the first direction Y. The gate electrode 53 and the source electrode 52 are arranged side by side in the second direction X. The gate electrode 53 and the field plate 61 are arranged side by side in the third direction Z. [[ID=@5]]

[0020] The drain electrode 51 is provided on the lower surface 10e of the semiconductor member 10. The drain electrode 51 contains, for example, Al, Cu, Mo, W, Ta, Co, Ru, Ti, Pt, etc.

[0021] At least a part of the source electrode 52 is disposed inside the source electrode trench 22. The source electrode 52 has an electrode portion 52a, a contact portion (metal portion) 52b, and a metal film 70. The electrode portion 52a is located above the upper surface 10f of the semiconductor member 10. The electrode portion 52a is provided above the contact portion 52b and the insulating member 41. The contact portion 52b is disposed inside the source electrode trench 22. The electrode portion 52a and the contact portion 52b contain, for example, Al, Cu, Mo, W, Ta, Co, Ru, Ti, Pt, etc.

[0022] The metal film 70 is composed of a different metallic material than, for example, the electrode portion 52a and the contact portion 52b. The metallic material constituting the metal film 70 has a higher work function than the first semiconductor region 11. For this reason, the metal film 70 can be Schottky bonded to the first semiconductor region 11. In this specification, the portion where the metal film 70 and the first semiconductor region 11 are Schottky bonded is referred to as the Schottky junction 32. In this embodiment, the Schottky junction 32 is provided at the bottom 22a of the source electrode groove 22. In this specification, when comparing the work functions of multiple portions, the energy levels of each portion are compared.

[0023] The metallic material constituting the metal film 70 has a lower work function than the second semiconductor region 12. Therefore, the metal film 70 can be ohmic bonded to the second semiconductor region 12. In this specification, the portion where the metal film 70 and the second semiconductor region 12 are ohmic bonded is referred to as the ohmic junction 31. In this embodiment, the ohmic junction 31 is provided at the upper end (the other end in the third direction Z) of the side wall portion 22b of the source electrode groove 22.

[0024] In one example, when the semiconductor component 10 contains silicon, the metal film 70 that enables Schottky junctions and ohmic junctions includes, for example, at least one selected from the group consisting of Ti, W, Mo, Ta, Zr, Al, Sn, V, Re, Os, Ir, Pt, Pd, Rh, Ru, Nb, Sr, and Hf.

[0025] In this embodiment, the source electrode 52 has a metal film 70 formed on the surface of the contact portion 52b, with a work function higher than that of the first semiconductor region 11. However, the source electrode 52 may be entirely composed of a metal material with a work function higher than that of the first semiconductor region 11. In this case, the metal film 70 may be omitted.

[0026] The gate electrode 53 is positioned inside the gate electrode groove 21. The lower end of the gate electrode 53 is located below the lower end of the contact portion 52b. The upper end of the gate electrode 53 and the second semiconductor region 12 overlap in the second direction X. The upper end of the gate electrode 53 is located below the upper end of the contact portion 52b. An insulating member 41 is interposed between the first semiconductor region 11 and the gate electrode 53 within the gate electrode groove 21. That is, the insulating member 41 insulates the semiconductor member 10 and the gate electrode 53 within the gate electrode groove 21. The gate electrode 53 faces the surface of the cell region 11c of the first semiconductor region 11 in the second direction X via the insulating member 41. The gate electrode 53 includes, for example, polysilicon.

[0027] The field plate 61 is positioned inside the gate electrode groove 21. The field plate 61 is located below the gate electrode 53. The width dimension of the field plate 61 (dimension in the second direction X) is smaller than the width dimension of the gate electrode 53. Inside the gate electrode groove 21, an insulating member 41 is interposed between the field plate 61 and the gate electrode 53. Therefore, the field plate 61 and the gate electrode 53 are insulated from each other. In addition, an insulating member 41 is interposed between the first semiconductor region 11 and the field plate 61 within the gate electrode groove 21. That is, the insulating member 41 insulates the semiconductor member 10 and the field plate 61 within the gate electrode groove 21.

[0028] The insulating member 41 is positioned inside the gate electrode groove 21. The insulating member 41 includes a gate insulating film 41a and a field plate insulating film 41b. The gate insulating film 41a is located between the first semiconductor region 11 and the gate electrode 53. On the other hand, the field plate insulating film 41b is located between the first semiconductor region 11 and the field plate 61.

[0029] The field plate 61 is electrically connected to the source electrode 52. The field plate 61 and the source electrode 52 are electrically connected, for example, by wiring 52L. This ensures that the field plate 61 and the source electrode 52 are at the same potential. The field plate 61 may also be extended to the top surface of the semiconductor device 1 (not shown) and electrically connected to the source electrode 52.

[0030] By providing a field plate 61 in the gate electrode groove 21, the electric field strength in the drift region 11a can be mitigated. This improves the withstand voltage characteristics between the drain electrode 51 and source electrode 52 of the semiconductor component 10. Furthermore, as the withstand voltage improves, the impurity concentration in the drift region 11a can be set higher, thereby reducing the on-resistance of the semiconductor device 1.

[0031] The insulating film 45 is formed on the inner surface of the source electrode groove 22. The thickness of the insulating film 45 is, for example, 1 nm to 30 nm. The insulating film 45 is, for example, silicon oxide (SiO2), aluminum oxide (Al2O3), or gallium oxide (Ga2O3). The insulating film 45 may also be made of other materials as long as they are insulating.

[0032] The insulating film 45 of this embodiment contains negative fixed charges. When the insulating film 45 contains a metal oxide, the negative fixed charges are defects, for example, caused by composite vacancies between metal atoms, oxygen atoms, and bonding portions. The amount of negative fixed charges added to the insulating film 45 is 10 12 cm -2 The above 10 14 cm -2 The following is preferable:

[0033] In this embodiment, the insulating film 45 is formed on the inner surface of the source electrode groove 22, excluding the upper end of the side wall portion 22b and the bottom portion 22a. In other words, the insulating film 45 is not formed on the upper end of the side wall portion 22b and the bottom portion 22a.

[0034] A second semiconductor region 12 is provided at the upper end of the semiconductor member 10. Therefore, the upper end of the side wall portion 22b of the inner surface of the source electrode groove 22 exposes the second semiconductor region 12. In the semiconductor member 10, the second semiconductor region 12 is located above the bottom portion 22a of the source electrode groove 22, and a first semiconductor region 11 is provided below the second semiconductor region 12. Therefore, the bottom portion 22a of the inner surface of the source electrode groove 22 exposes the first semiconductor region 11. Furthermore, the metal film 70 of the source electrode 52 is formed along the entire inner surface of the source electrode groove 22, including the bottom portion 22a. Thus, the metal film 70 is in direct contact with the semiconductor member 10 at the upper end and bottom portion 22a of the side wall portion 22b of the inner surface of the source electrode groove 22, and in contact with the insulating film 45 in other portions (i.e., regions other than the upper end of the side wall portion 22b). The metal film 70 contacts the second semiconductor region 12 at the upper end of the side wall portion 22b, forming an ohmic junction 31. The metal film 70 also contacts the first semiconductor region 11 at the bottom portion 22a, forming a Schottky junction 32.

[0035] The insulating film 45 covers the entire portion of the source electrode 52 that faces the gate electrode 53 in the second direction X. That is, the upper end of the insulating film 45 is positioned in the same location in the third direction Z as the upper or lower end of the contact portion 52b and the upper end of the gate electrode 53, which is either above or below the lower end (the upper end of the gate electrode 53 in this embodiment). Similarly, the lower end of the insulating film 45 is positioned in the same location in the third direction Z as the lower or upper end of the source electrode 52 (the lower end of the contact portion 52b in this embodiment) and the lower end of the gate electrode 53, which is either above or below the lower end (the lower end of the source electrode 52 in this embodiment).

[0036] In this embodiment, the insulating film 45 is placed between the metal film 70, which has a high work function, and the semiconductor member 10. Therefore, the metal film 70, the insulating film 45, and the first semiconductor region 11 of the semiconductor member 10 constitute a Metal-Insulator-Semiconductor (MIS) type junction. In this specification, the portion where the metal film 70, the insulating film 45, and the first semiconductor region 11 are MIS-joined is referred to as the MIS junction 33. In this embodiment, the MIS junction 33 is provided on the side wall portion 22b of the source electrode groove 22.

[0037] Next, a description will be given of the manufacturing method of the semiconductor device 1 according to this embodiment. In the manufacturing method of the semiconductor device 1 of this embodiment, first, a semiconductor member 10 containing n-type impurities throughout (i.e., a semiconductor member 10 in which a first semiconductor region 11 is formed throughout) is prepared. Next, a gate electrode groove 21 and a source electrode groove 22 are formed in the semiconductor member 10. For example, reactive ion etching (RIE) can be used for the process of forming the gate electrode groove 21 and the source electrode groove 22.

[0038] In the manufacturing method of the semiconductor device 1 of this embodiment, a field plate 61 embedded in an insulating member 41 and a gate electrode 53 are then formed inside the gate electrode groove 21. The process of forming the insulating member 41, the field plate 61, and the gate electrode 53 is carried out by repeatedly forming the insulating member 41, forming a groove in the insulating member 41, and forming a conductive member inside the groove.

[0039] In the manufacturing method of the semiconductor device 1 of this embodiment, an insulating film 45, a metal film 70, and a contact portion 52b are formed inside the source electrode groove 22. In this step, first, the insulating film 45 is formed on the entire inner surface of the source electrode groove 22, including the bottom portion 22a. The insulating film 45 is formed, for example, by chemical vapor deposition (CVD). Next, the insulating film 45 is partially masked to remove the insulating film 45 provided on the upper end of the side wall portion 22b and the bottom portion 22a. The removal of the insulating film 45 is performed, for example, by means of reactive ion etching. Furthermore, a negative fixed charge is introduced into the insulating film 45. If the insulating film 45 contains aluminum oxide, the fixed charge can be easily retained in the insulating film 45 by controlling the atmosphere during film formation so as not to introduce nitrogen elements into the insulating film 45. Also, if the insulating film 45 contains gallium oxide, the content of fixed charge in the insulating film 45 can be adjusted by performing a hydrogen annealing treatment after film formation. Next, a metal film 70 is formed along the entire inner surface of the source electrode groove 22, including the bottom 22a. The metal film 70 is formed, for example, by chemical vapor deposition (CVD) or atomic layer deposition (ALD). Then, a contact portion 52b is formed within the groove.

[0040] Next, impurities are diffused into the upper part of the semiconductor member 10 to form a second semiconductor region 12 on the upper part of the semiconductor member 10. Furthermore, an electrode portion 52a is formed on the upper side of the semiconductor member 10. Also, a drain electrode 51 is formed on the lower side of the semiconductor member 10. In this way, the semiconductor device 1 is obtained.

[0041] Next, the operating principle of the semiconductor device 1 of this embodiment will be described. In this embodiment, a depletion layer is formed in the cell region 11c because the work function of the metal film 70 is higher than the work function of the first semiconductor region 11. When no voltage is applied to the gate electrode 53, an off state is obtained in which no current flows in the cell region 11c due to the depletion layer. By controlling the potential of the gate electrode 53, an electron storage layer is formed as a channel in the cell region 11c, and an on state is obtained in which a drain current flows in the cell region 11c. Therefore, in the semiconductor device 1, the current between the drain electrode 51 and the source electrode 52 is controlled by the potential of the gate electrode 53. The potential of the gate electrode 53 is a potential relative to the potential of the source electrode 52.

[0042] In this embodiment, the metal film 70 is ohmic-bonded with the second semiconductor region 12 at the upper end of the source electrode groove 22, forming an ohmic junction 31. When the device is ON, the current passing through the channel formed in the cell region 11c flows through the ohmic junction 31 to the source electrode 52.

[0043] In this embodiment, the metal film 70 forms a Schottky junction 32 with the first semiconductor region 11 at the bottom 22a of the source electrode groove 22. As a result, the boundary between the metal film 70 and the first semiconductor region 11 functions as a diode (body diode), allowing current to flow in the forward direction.

[0044] In this embodiment, the insulating film 45 contains negative fixed charges. This raises the band of the first semiconductor region 11, making the Schottky barrier higher. As a result, depletion of the cell region 11c becomes significant, and a large voltage must be applied to the cell region 11c from the gate electrode 53 to allow current to flow to the cell region 11c (i.e., to turn it on). In other words, according to this embodiment, by including negative fixed charges in the insulating film 45, it is possible to raise the gate threshold voltage.

[0045] In particular, in this embodiment, the insulating film 45 covers the entire cell region 11c sandwiched between the gate electrode groove 21 and the source electrode groove 22 from the second direction X. As a result, the negative fixed charge contained in the insulating film 45 raises the overall band of the cell region 11c, promoting overall depletion of the cell region 11c. Consequently, it becomes more difficult for current to flow through the cell region 11c in the off state, making it possible to further increase the gate threshold voltage.

[0046] This document compares the effects and benefits of semiconductor device 1 of this embodiment with semiconductor devices C1 and C2 of a comparative form. Figures 2 and 3 show enlarged views of the vicinity of the cell region 11c of the comparative semiconductor devices C1 and C2. In Figures 2 and 3, components similar to those in the semiconductor device 1 of the embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0047] Figure 4 is a graph showing the simulation results of the transfer characteristics of semiconductor device 1 of the embodiment, semiconductor device C1 of the first comparative form, and semiconductor device C2 of the second comparative form. Specifically, Figure 4 shows the change in drain current when the voltage between the drain electrode 51 and the source electrode 52 is kept constant and the voltage between the gate electrode 53 and the source electrode 52 is varied. The horizontal axis of Figure 4 shows the potential difference between the gate electrode 53 and the source electrode 52, and the horizontal axis shows the current flowing through the drain electrode 51. Figure 4 is also a semi-logarithmic graph with the vertical axis being logarithmic.

[0048] The semiconductor device C1 of the first comparative embodiment shown in Figure 2 does not have an insulating film 45 compared to the semiconductor device 1 of the embodiment. In the semiconductor device C1 of the first comparative embodiment, a metal film 70 with a high work function is in direct contact with the cell region 11c of the first semiconductor region 11 to form a Schottky junction. As a result, in the semiconductor device C1 of the first comparative embodiment, depletion is promoted in the portion along the side wall portion 22b of the source electrode groove 22 of the cell region 11c, promoting current and making it difficult for current to flow. However, in the semiconductor device C1 of the first comparative embodiment, the degree of depletion of the cell region 11c depends on the work function of the metal film 70. For this reason, in the semiconductor device C1 of the first comparative embodiment, there is a limit to the depletion of the cell region 11c, and it is difficult to sufficiently increase the gate threshold voltage.

[0049] The semiconductor device C2 of the second comparative embodiment shown in Figure 3 has an insulating film 45C that does not contain fixed charges, compared to the semiconductor device C1 of the first comparative embodiment. Compared to the semiconductor device 1 of the embodiment, the insulating film 45C of the semiconductor device C2 of the second comparative embodiment does not contain fixed charges. In the semiconductor device C2 of the second comparative embodiment, the cell region 11c and the metal film 70 are separated by the thickness of the insulating film 45C and are insulated, so no charge movement occurs, and thus depletion of the cell region 11c is less likely to progress. Therefore, in the semiconductor device C2 of the second comparative embodiment, current flows more easily into the cell region 11c than in the semiconductor device C1 of the first comparative embodiment, and the gate threshold voltage is lower.

[0050] Thus, it is difficult to raise the gate threshold voltage in the semiconductor device C1 of the first comparison form, and it is even more difficult to raise the gate threshold voltage in the semiconductor device C2 of the second comparison form. Furthermore, in the semiconductor device C1 of the first comparison form, an insulating film may be formed on the inner surface of the source electrode groove 22 during the manufacturing process, resulting in a structure in which an insulating material is interposed between the metal film 70 and the cell region 11c, similar to the semiconductor device C2 of the second comparison form. In this case, in the semiconductor device C1 of the first comparison form, depletion of the cell region 11c becomes difficult to progress, similar to the semiconductor device C2 of the second comparison form, and the gate threshold voltage becomes low.

[0051] In contrast to these comparative configurations, in the semiconductor device 1 of this embodiment, the depletion of the cell region 11c progresses due to the action of negative fixed charges on the insulating film 45. Therefore, the gate threshold voltage can be higher with the semiconductor device 1 of this embodiment than with the semiconductor devices C1 and C2 of the comparative configurations.

[0052] As shown in Figure 4, in the semiconductor device 1 of this embodiment, it can be confirmed that current does not flow easily through the semiconductor member 10 even when the potential of the gate electrode 53 is increased, compared to the semiconductor devices C1 and C2 of the first and second comparative embodiments. In other words, the gate threshold voltage can be increased in the semiconductor device 1 of this embodiment.

[0053] Next, the effects and advantages of this embodiment will be described. The semiconductor device 1 of this embodiment includes a semiconductor member 10, a drain electrode 51, a gate electrode 53, a source electrode 52, and an insulating film 45. The semiconductor member 10 is provided with a gate electrode groove 21 and a source electrode groove 22. The gate electrode groove 21 and the source electrode groove 22 are aligned in a second direction X that intersects a first direction Y. The gate electrode groove 21 and the source electrode groove 22 are recessed on one side (downward) of a third direction Z that intersects both the first direction Y and the second direction X. The gate electrode 53 is located inside the gate electrode groove 21. The drain electrode 51 is located on one side (downward) of the semiconductor member 10 in the third direction Z. The gate electrode 53 is located inside the gate electrode groove 21. The source electrode 52 is located inside the source electrode groove 22. The insulating film 45 is provided on at least a portion of the inner surface of the source electrode groove 22. The insulating film 45 contains a negative fixed charge. The semiconductor member 10 is provided with a first semiconductor region 11 and a second semiconductor region 12. The first semiconductor region 11 has a first conductivity type impurity. The second semiconductor region 12 has a first conductivity type impurity at a higher concentration than the first conductivity type impurity in the first semiconductor region 11. The second semiconductor region 12 is located on the other side (above) of the first semiconductor region 11 in the third direction. The source electrode 52 can be Schottky bonded to the first semiconductor region 11. The source electrode 52 can be ohmic bonded to the second semiconductor region 12. At least a portion of the first semiconductor region 11 (cell region 11c) is located between the gate electrode 53 and the source electrode 52 in the second direction X. The insulating film 45 is sandwiched between a portion of the first semiconductor region 11 (cell region 11c) and the source electrode 52 in the second direction X.

[0054] With this configuration, the inclusion of negative fixed charges in the insulating film 45 causes the band in the first semiconductor region 11 to rise, making depletion more pronounced in the portion of the first semiconductor region 11 extending in the third direction Z along the contact portion 52b. As a result, the gate electrode 53 cannot be turned on unless a large voltage is applied, making it possible to raise the gate threshold voltage.

[0055] In the semiconductor device 1 of this embodiment, the insulating film 45 covers the entire portion of the contact portion 52b that faces the gate electrode 53 in the second direction X.

[0056] With this configuration, the negative fixed charge contained in the insulating film 45 raises the overall band of the portion of the first semiconductor region 11 sandwiched between the source electrode 52 and the gate electrode 53 (cell region 11c), thereby promoting overall depletion of the cell region 11c. As a result, it becomes more difficult to pass current across the entire cell region 11c in the off state, making it possible to further increase the gate threshold voltage. In this embodiment, the portion of the source electrode 52 facing the gate electrode 53 in the second direction X is the contact portion 52b located within the source electrode groove 22. The insulating film 45 covers the entire portion of the contact portion 52b facing the gate electrode 53.

[0057] In the semiconductor device 1 of this embodiment, the metal film 70, which is part of the source electrode 52, and the second semiconductor region 12 are in direct contact (ohmic contact) at the other end (upper end) of the source electrode groove 22 in the third direction Z. With this configuration, the current passing through the channel formed in the cell region 11c in the ON state can be passed to the source electrode 52 through the boundary where the second semiconductor region 12 and the source electrode 52 are ohmic joined.

[0058] In the semiconductor device 1 of this embodiment, the source electrode 52 and the first semiconductor region 11 are in direct contact at the bottom 22a of the source electrode groove 22. With this configuration, the bottom 22a of the source electrode groove 22, where the source electrode 52 and the first semiconductor region 11 are connected by a Schottky junction, can function as a diode.

[0059] In the semiconductor device 1 of this embodiment, the source electrode 52 has a metal film 70 formed along the inner surface of the source electrode groove 22, and a contact portion (metal portion) 52b disposed inside the metal film 70. The metal film 70 can be Schottky bonded to the first semiconductor region 11. The metal film 70 can also be ohmic bonded to the second semiconductor region 12. The work function of the contact portion 52b is lower than the work function of the metal film 70. With this configuration, only the metal film 70 of the source electrode 52 can be made from a material with a high work function, and the contact portion 52b can be made from a material with a low work function. This makes it possible to reduce the amount of metal with a high work function used, and to manufacture an inexpensive semiconductor device 1.

[0060] The semiconductor device 1 of this embodiment includes a field plate 61. The field plate 61 is located inside the gate electrode groove 21, below the gate electrode 53, and between the gate electrode 53 and the first semiconductor region 11. The field plate 61 is insulated from the gate electrode 53 and is electrically connected to the source electrode 52. This configuration makes it possible to mitigate the electric field strength in the drift region 11a of the first semiconductor region 11, thereby improving the dielectric strength of the semiconductor device 1. In this embodiment, the case in which the semiconductor device 1 has a field plate 61 has been described, but the semiconductor device 1 does not necessarily have to have a field plate 61.

[0061] According to at least one embodiment described above, by having an insulating film between the first semiconductor region 11 and the Schottky-junctionable source electrode 52 and the first semiconductor region, depletion of the first semiconductor region 11 can be promoted and the gate threshold voltage can be increased.

[0062] The present invention includes the following appended embodiments. (Note 1) A semiconductor member having a first groove and a second groove extending in a first direction, aligned in a second direction intersecting the first direction, and recessed on one side of a third direction intersecting both the first and second directions, A drain electrode located on one side of the semiconductor member in the third direction, A gate electrode disposed inside the first groove, A source electrode is disposed inside the second groove, The second groove comprises an insulating film containing a negative fixed charge, provided on at least a portion of the inner surface of the groove, The aforementioned semiconductor member includes: A first semiconductor region having a first conductivity type impurity, A second semiconductor region is provided, which has a higher concentration of the first conductivity type impurity than the first conductivity type impurity in the first semiconductor region and is located on the other side of the third direction from the first semiconductor region. The source electrode is The first semiconductor region is capable of Schottky bonding, The second semiconductor region is capable of ohmic bonding, At least a portion of the first semiconductor region is located between the gate electrode and the source electrode in the second direction, The insulating film is sandwiched between the part of the first semiconductor region and the source electrode in the second direction. Semiconductor equipment. (Note 2) The insulating film covers the entire portion of the source electrode that faces the gate electrode in the second direction. The semiconductor device described in Appendix 1. (Note 3) At the other end of the second groove in the third direction, the source electrode and the second semiconductor region are in direct contact. The semiconductor device described in Appendix 1 or 2. (Note 4) At the bottom of the second groove, the source electrode and the first semiconductor region are in direct contact. A semiconductor device as described in any one of the appendices 1 to 3. (Note 5) The source electrode is A metal film formed along the inner surface of the second groove, It has a metal part disposed on the inside of the metal film, The aforementioned metal film is The first semiconductor region is capable of Schottky bonding, The second semiconductor region is capable of ohmic bonding, The work function of the metal part is lower than the work function of the metal film. A semiconductor device as described in any one of the appendices 1 to 4. (Note 6) The device comprises a conductive member located inside the first groove, on one side of the gate electrode in the third direction, and between the gate electrode and the first semiconductor region, The conductive member is insulated from the gate electrode and is electrically connected to the source electrode. A semiconductor device as described in any one of the appendices 1 to 5.

[0063] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0064] 1...Semiconductor device, 10...Semiconductor component, 11...First semiconductor region, 12...Second semiconductor region, 21...Gate electrode groove (first groove), 21a, 22a...Bottom, 22...Source electrode groove (second groove), 45, 45C...Insulating film, 51...Drain electrode, 52...Source electrode, 52b...Contact portion (metal part), 53...Gate electrode, 61...Field plate (conductive component), 70...Metal film, X...Second direction, Y...First direction

Claims

1. A semiconductor member having a first groove and a second groove extending in a first direction, aligned in a second direction intersecting the first direction, and recessed on one side of a third direction intersecting both the first and second directions, A drain electrode located on one side of the semiconductor member in the third direction, A gate electrode disposed inside the first groove, A source electrode is disposed inside the second groove, The second groove comprises an insulating film containing a negative fixed charge, provided on at least a portion of the inner surface of the groove, The aforementioned semiconductor member includes: A first semiconductor region having a first conductivity type impurity, A second semiconductor region is provided, which has a higher concentration of the first conductivity type impurity than the first conductivity type impurity in the first semiconductor region and is located on the other side of the third direction from the first semiconductor region. The source electrode is The first semiconductor region is capable of Schottky bonding, The second semiconductor region is ohmic junctionable, At least a portion of the first semiconductor region is located between the gate electrode and the source electrode in the second direction, The insulating film is sandwiched between the part of the first semiconductor region and the source electrode in the second direction. Semiconductor equipment.

2. The insulating film covers the entire portion of the source electrode that faces the gate electrode in the second direction. The semiconductor device according to claim 1.

3. At the other end of the second groove in the third direction, the source electrode and the second semiconductor region are in direct contact. The semiconductor device according to claim 1.

4. At the bottom of the second groove, the source electrode and the first semiconductor region are in direct contact. The semiconductor device according to claim 1.

5. The source electrode is A metal film formed along the inner surface of the second groove, It has a metal part disposed on the inside of the metal film, The aforementioned metal film is The first semiconductor region is capable of Schottky bonding, The second semiconductor region is ohmic junctionable, The work function of the metal part is lower than the work function of the metal film. The semiconductor device according to claim 1.

6. The conductive member is located inside the first groove, on one side of the gate electrode in the third direction, and between the gate electrode and the first semiconductor region. The conductive member is insulated from the gate electrode and is electrically connected to the source electrode. A semiconductor device according to any one of claims 1 to 5.

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