Image sensor

Abstract

This invention provides an image sensor that increases the conversion gain by omitting the metal wiring connecting the floating diffusion region (FD) and the amplification transistor. [Solution] The device has a first layer on which multiple pixels are formed and a second layer stacked in a first direction with the first layer, on which peripheral circuits that drive the multiple pixels are arranged and connected to the multiple pixels through multiple matrix lines. The multiple pixels include a photodiode, a floppy disk (FD) on which charge is stored, a transmission transistor connected between the two, and an amplification transistor connected to the FD. The first layer includes a first substrate, a first interlayer insulating layer formed on one surface of the first substrate, a semiconductor layer formed in a part of the surface of the first substrate, and a first insulating layer formed between the first substrate and the semiconductor layer. The source region, drain region, and channel region of the amplification transistor are formed in the semiconductor layer, and the channel region of the amplification transistor is formed in a part of the semiconductor layer superimposed on the FD in a first direction.

Description

Technical Field

[0001] The present invention relates to an image sensor, and more particularly to an image sensor capable of increasing a conversion gain.

Background Art

[0002] An image sensor is a sensor that receives light and generates an electrical signal, and includes a pixel array having a plurality of pixels, a peripheral circuit for driving the pixel array to generate an image, and the like. Each pixel includes a photodiode and a pixel circuit that converts the charge generated by the photodiode into an electrical signal. The ratio at which the charge generated by the photodiode is converted into a voltage is defined as a conversion gain.

[0003] In a low-light environment, the amount of light reaching the image sensor is small, and a small amount of charge may be generated by the photodiode. At this time, it is important to increase the conversion gain to convert a small amount of charge into a high voltage. Various methods for increasing the conversion gain have constantly been an issue.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the problems in the above-described conventional image sensor, and an object of the present invention is to provide an image sensor capable of increasing a conversion gain by omitting a metal wiring connecting between a floating diffusion region and an amplification transistor.

Means for Solving the Problems

[0005] To achieve the above objective, the present invention provides an image sensor comprising: a first layer on which a plurality of pixels are formed; a second layer stacked in a first direction with the first layer, on which peripheral circuits for driving the plurality of pixels are arranged and connected to the plurality of pixels through a plurality of row lines and a plurality of column lines; each of the plurality of pixels includes a photodiode, a floating diffusion region where the charge generated by the photodiode is stored, a transmission transistor connected between the photodiode and the floating diffusion region, and an amplification transistor connected to the floating diffusion region; the first layer comprises a first substrate, a first interlayer insulating layer formed on one surface of the first substrate, a semiconductor layer formed in a portion of the surface of the first substrate, and a first insulating layer formed between the first substrate and the semiconductor layer; the source region, drain region, and channel region of the amplification transistor are formed in the semiconductor layer, and the channel region of the amplification transistor is formed in a portion of the semiconductor layer superimposed on the floating diffusion region in a first direction.

[0006] Furthermore, an image sensor according to the present invention made to achieve the above objective comprises a first layer on which a plurality of pixels are formed, and a second layer stacked in a first direction with the first layer, on which peripheral circuits for driving the plurality of pixels and acquiring pixel signals are arranged, wherein each of the plurality of pixels includes a photodiode, a floating diffusion region where the charge generated by the photodiode is stored, a transmission transistor connected between the photodiode and the floating diffusion region, an amplification transistor connected to the floating diffusion region, and a selection transistor connected between the amplification transistor and a column line, wherein the first layer includes a first substrate, a first interlayer insulating layer formed on one surface of the first substrate, a semiconductor layer formed in a part of the surface of the first substrate, and a first insulating layer formed between the first substrate and the semiconductor layer, wherein the second direction on which the gate of the transmission transistor and the floating diffusion region are arranged intersects with a third direction on which the semiconductor layer extends, and the second and third directions are parallel to the upper surface of the first substrate and perpendicular to the first direction.

[0007] Furthermore, the image sensor according to the present invention, made to achieve the above objective, comprises a first layer on which a plurality of pixels are formed, and a second layer stacked in a first direction with the first layer, on which peripheral circuits for driving the plurality of pixels and acquiring pixel signals are arranged, and each of the plurality of pixels includes a photodiode, a floating diffusion region where the charge generated by the photodiode is stored, a transmission transistor connected between the photodiode and the floating diffusion region, a reset transistor connected between the floating diffusion region and a first power node, an amplification transistor connected to the floating diffusion region, and a selection transistor connected between the amplification transistor and a column line, and the first ray The YA comprises a first substrate, a first interlayer insulating layer formed on one surface of the first substrate, a semiconductor layer formed in a portion of the surface of the first substrate, and a first insulating layer formed between the first substrate and the semiconductor layer, wherein the photodiode, the floating diffusion region, the active region of the transmission transistor, and the active region of the reset transistor are formed on the first substrate, the channel region of the amplification transistor is formed in a portion of the semiconductor layer disposed above the floating diffusion region, the gate of the amplification transistor is formed in the floating diffusion region, the gate of the transmission transistor is a vertical transmission gate, and the photodiode is disposed below the floating diffusion region in the first direction. [Effects of the Invention]

[0008] According to the image sensor of the present invention, the layer on which multiple pixels are formed includes a semiconductor layer, and the active region of the amplification transistor is formed in the semiconductor layer. This eliminates the need for metal wiring connecting the floating diffusion region and the amplifying transistor, thereby increasing the conversion gain. [Brief explanation of the drawing]

[0009] [Figure 1] This is a block diagram showing a schematic configuration of an image sensor according to one embodiment of the present invention. [Figure 2] This diagram briefly illustrates the pixel array structure of an image sensor according to one embodiment of the present invention. [Figure 3] This diagram briefly illustrates the structure of pixels included in an image sensor according to one embodiment of the present invention. [Figure 4] This is a circuit diagram of a pixel included in an image sensor according to one embodiment of the present invention. [Figure 5] This diagram illustrates the operation of an image sensor according to one embodiment of the present invention. [Figure 6] This is a layout diagram showing an outline of a pixel region according to one embodiment of the present invention. [Figure 7] This is a partial cross-sectional view taken along the line A-A' in the pixel region shown in Figure 6 according to one embodiment of the present invention. [Figure 8] This is a partial cross-sectional view obtained by cutting along the line B-B' in the pixel region shown in Figure 6 according to one embodiment of the present invention. [Figure 9] This is a partial cross-sectional view obtained by cutting along the line B-B' in the pixel region shown in Figure 6 according to one embodiment of the present invention. [Figure 10] This is a layout diagram showing an outline of a pixel region according to one embodiment of the present invention. [Figure 11] This is a partial cross-sectional view obtained by cutting along the line A-A' in the pixel region shown in Figure 10 according to one embodiment of the present invention. [Figure 12] This is a partial cross-sectional view obtained by cutting along the line B-B' in the pixel region shown in Figure 10 according to one embodiment of the present invention. [Figure 13] This is a layout diagram showing an outline of a pixel region according to one embodiment of the present invention. [Figure 14] This is a partial cross-sectional view taken along the line A-A' in the pixel region shown in Figure 13 according to one embodiment of the present invention. [Figure 15]A partial cross-sectional view taken along the line B-B' of the pixel region shown in FIG. 13 according to an embodiment of the present invention. [Figure 16] A layout diagram showing an overview of a pixel region according to an embodiment of the present invention. [Figure 17] A partial cross-sectional view taken along the line A-A' of the pixel region shown in FIG. 16 according to an embodiment of the present invention. [Figure 18] A partial cross-sectional view taken along the line B-B' of the pixel region shown in FIG. 16 according to an embodiment of the present invention. [Figure 19] A circuit diagram of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 20] A layout diagram showing an overview of a pixel region according to an embodiment of the present invention. [Figure 21] A partial cross-sectional view taken along the line A-A' of the pixel region shown in FIG. 6 according to an embodiment of the present invention. [Figure 22] A partial cross-sectional view taken along the line B-B' of the pixel region shown in FIG. 6 according to an embodiment of the present invention. [Figure 23] A circuit diagram of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 24] A layout diagram showing an overview of a pixel region according to an embodiment of the present invention. [Figure 25] A partial cross-sectional view taken along the line A-A' of the pixel region shown in FIG. 24 according to an embodiment of the present invention. [Figure 26] A partial cross-sectional view taken along the line B-B' of the pixel region shown in FIG. 24 according to an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0010] Next, a specific example of an embodiment for implementing an image sensor according to the present invention will be described while referring to the drawings.

[0011] Figure 1 is a block diagram showing a schematic configuration of an image sensor according to one embodiment of the present invention. Referring to Figure 1, the image sensor 10 includes a pixel array 20 and peripheral circuits 30, etc.

[0012] The pixel array 20 includes multiple pixel regions arranged in an array configuration along multiple rows and multiple columns. Each of the multiple pixel regions is equipped with a photoelectric converter that generates an electric charge in response to light, and the photoelectric converter is connected to a pixel circuit that generates and outputs a signal corresponding to the charge generated by the photoelectric converter. A pixel is realized through a photoelectric conversion element and a pixel circuit. Photoelectric conversion elements may include photodiodes formed from semiconductor materials, and / or organic photodiodes formed from organic materials.

[0013] For example, a pixel circuit includes multiple transistors. A capacitor stores the excess charge generated by the photodiode and is connected to the photodiode through at least one transistor. Another example is a pixel circuit, which further includes a capacitor. The capacitor may be a MIM (Metal-Insulator-Metal) capacitor, a MOS (Metal-Oxide-Semiconductor) capacitor, or a LOFIC (Lateral Over-Flow Integration Capacitor) capacitor.

[0014] The peripheral circuit 30 includes a circuit for controlling the pixel array 20. For example, the peripheral circuit 30 includes a row driver 31, a readout circuit 32, a data output circuit 33, and control logic 34. The row driver 31 drives the pixel array 20 in row (ROW) units. For example, the row driver 31 inputs control signals to the pixel array 20 on a row-line basis, controlling the on / off state of each transistor included in the pixel circuit. Pixels that are located at the same position along the row direction (horizontal direction in Figure 1) within a pixel share the same column line. For example, pixels located at the same position in the column direction (vertical direction in Figure 1) are simultaneously selected by the row driver 31 and output pixel signals through the column line. In one embodiment, the readout circuit 32 simultaneously receives signals from pixels selected by the row driver 31 through the column lines. For example, the readout circuit 32 sequentially receives a reset voltage and a signal voltage from each pixel, and the signal voltage is the voltage in which the charge generated by each photodiode of the pixel is reflected in the reset voltage.

[0015] The readout circuit 32 includes multiple correlated duplexers and multiple counters, the correlated duplexers being connected through pixels and column lines. As an example, one column line is connected to one correlated dual sampler and one counter. The correlated dual sampler reads voltage signals through the column lines from pixels connected to row lines selected by the row line selection signal of the row driver 31. One of the input terminals of the correlated dual sampler is connected to a column line, and the other input terminal receives a ramp voltage input. Each output terminal of the correlated dual sampler is connected to a counter, which counts the time each output of the correlated dual sampler is maintained at a specific voltage to generate a digital pixel signal. For example, a counter counts the time when the ramp voltage input to a correlated duplex sampler is greater than the voltage of the column line, and converts the output of the correlated duplex sampler into a digital pixel signal. The data output circuit 33 may include memory such as a latch and buffer circuit for temporarily storing the digital pixel signal.

[0016] The control logic 34 includes a timing controller for controlling the operating timing of the row driver 31, the readout circuit 32, and the data output circuit 33. In this embodiment, the control logic 34 can also determine the data format to be output by the data output circuit 33, or it can perform preprocessing on the data to be output by the data output circuit 33.

[0017] In a typical image sensor, the amplification transistor has a gate connected to a floating diffusion region, and the floating diffusion region and the gate of the amplification transistor are connected by metal wiring. In this case, parasitic capacitance may occur between adjacent metal wires, potentially causing capacitive coupling of the metal wires. This means there may be a limit to how much the conversion gain can be increased. For example, a typical conversion gain is in the range of 150 to 200 μV / e.

[0018] One embodiment of the present invention, an image sensor 10, omits the metal wiring connecting the floating diffusion region and the amplification transistor. The active region of an amplifying transistor is formed in a portion of the semiconductor layer located above the floating diffusion region. In other words, the gate of an amplifying transistor is formed in the floating diffusion region. This eliminates the capacitive coupling of the metal wiring, thereby increasing the conversion gain. An image sensor 10 according to one embodiment of the present invention may have a conversion gain of 200 μV / e or more, and as an example, may have a conversion gain of 500 μV / e. Because it can convert a small amount of charge into a high voltage even under high conversion gain conditions in low-light environments, the sensitivity of the image sensor can be improved.

[0019] Figure 2 is a simplified diagram showing the pixel array structure of an image sensor according to one embodiment of the present invention. Referring to Figure 2, the pixel array 50 of the image sensor according to one embodiment of the present invention includes a plurality of pixels (51-53) arranged along a second direction (X-axis direction) and a third direction (Y-axis direction). For example, the pixel array 50 includes red pixels 51, green pixels 52, and blue pixels 53. Each of the red pixels 51 contains a red color filter, each of the green pixels 52 contains a green color filter, and each of the blue pixels 53 contains a blue color filter.

[0020] In one embodiment shown in Figure 2, each of the green pixels 52 is adjacent to a portion of the red pixels 51 and a portion of the blue pixels 53 in the second and third directions. Each of the multiple pixels (51-53) contains one photodiode. In one embodiment of the present invention, the conversion gain in low-light environments can be increased in each of the multiple pixels (51-53) through the design of the pixel circuit connected to the photodiode. This makes it possible to improve the sensitivity of the image sensor.

[0021] Figure 3 is a simplified diagram showing the structure of pixels included in an image sensor according to one embodiment of the present invention. Referring to Figure 3, an image sensor 100 according to one embodiment of the present invention includes a first layer L1 and a second layer L2. The first layer L1 and the second layer L2 are stacked in the first direction (Z-axis direction). The first layer L1 includes a first substrate 101, on which a photodiode PD and a plurality of transistors 110 are formed. Multiple transistors 110 are connected to each other by metal wiring 111, providing a pixel circuit connected to a photodiode PD.

[0022] The incident light strikes one surface of the first layer L1. For example, incident light enters the image sensor 100 from outside in a first direction. One side of the first substrate 101 is used to arrange multiple transistors 110 for processing electrical signals generated from the photodiode PD. The metal wiring 111 is placed within the first interlayer insulating layer 120 formed on one surface of the first substrate 101. The uppermost wiring 115, located at the top of the first interlayer insulation layer 120, is connected to the uppermost wiring 155 of the second layer L2. On the other hand, a color filter 103 and a microlens 105 may be arranged on the other side of the first substrate 101.

[0023] In the embodiment shown in Figure 3, the capacitor 130 is connected to a plurality of transistors 110 and included in the pixel circuit. Capacitor 130 is an MIM capacitor, but the type of capacitor 130 is not limited to this. Furthermore, unlike in Figure 3, the pixel circuit does not need to include capacitor 130.

[0024] The second layer L2 includes a second substrate 102, on which multiple transistors 140 are formed. Multiple transistors 140 are connected to each other by metal wiring 151 located within the second interlayer insulating layer 150, providing peripheral circuits that drive the pixel array, such as row drivers and readout circuits. The uppermost wiring 155, located at the topmost end within the second interlayer insulating layer 150, is connected to the uppermost wiring 115 of the first layer L1.

[0025] In one embodiment of the present invention, the first layer L1 further includes a semiconductor layer (not shown) formed on a portion of one surface of the first substrate 101, and a first insulating layer (not shown) formed between the first substrate 101 and the semiconductor layer. The semiconductor layer may consist of amorphous oxide semiconductor, 2D nanomaterial, amorphous silicon, or polycrystalline silicon. The semiconductor layer is formed by depositing the above-mentioned material onto the first substrate 101 as a thin film.

[0026] The first insulating layer is a Gox (Gate Oxide) insulating layer placed between the gate and channel regions of multiple transistors 110. For example, the first insulating layer may be composed of silicon oxide (SiO2) or high-k materials. In one embodiment of the present invention, a portion of the active region of a plurality of transistors 110 is formed in a semiconductor layer (not shown). Some of the multiple transistors 110 include amplifying transistors. By forming the active region of the amplification transistor in a semiconductor layer and the gate of the amplification transistor in a floating diffusion region, the capacitor coupling of the metal wiring can be eliminated, thereby increasing the conversion gain of the image sensor 100.

[0027] Figure 4 is a circuit diagram of a pixel included in an image sensor according to one embodiment of the present invention. Referring to Figure 4, a pixel PX according to one embodiment of the present invention includes a photodiode PD and a pixel circuit. The pixel circuit includes a floating diffusion node FDN, a transmission transistor TX, a gain control transistor DCX, a capacitor CAP, a reset transistor RX, an amplification transistor SF, and a selection transistor SX, among others. Each of the multiple transistors included in the pixel circuit contains a gate (TG, RG, DCG, SEL). The control signals that control the multiple transistors included in the pixel circuit are output by the row driver.

[0028] The floating diffusion node (FDN) is connected to the photodiode (PD) via the transmission transistor (TX). When the transmission transistor TX is turned on by the transmission control signal, the charge of the photodiode PD is stored in the floating diffusion node FDN. The gain control transistor DCX is connected between the floating diffusion node FDN and the first node N1. Capacitor CAP is connected to the first node N1.

[0029] When the gain control transistor DCX is turned on by the gain control signal, capacitor CAP is connected to the floating diffusion node FDN. This increases the capacitance of the floating diffusion node (FDN), reducing the conversion gain of the pixel PX. Conversely, when the gain control transistor DCX is turned off by the gain control signal, the conversion gain of pixel PX increases.

[0030] A reset transistor RX is connected between the first power supply node and the first node N1. The first power supply node is the node that supplies the first power supply voltage VDD1 and is connected to the drain of the reset transistor RX. The amplification transistor SF is connected to the floating diffusion node FDN, and the amplification transistor SF is connected between the second power supply node and the selection transistor SX. The second power node is the node that supplies the second power supply voltage VDD2. Depending on the embodiment, the first power supply voltage VDD1 may be the same as or different from the second power supply voltage VDD2. The amplifying transistor SF acts as a source-follower amplifier, amplifying the voltage across the floating diffusion node FDN to generate a signal. The signal generated by the amplification transistor SF is output to the column line COL by the turn-on operation of the selection transistor SX. Column line COL is connected to one of the input terminals of the correlated duplex sampler, which transmits the output signal to column line COL and the output signal determined by the ramp voltage to the counter.

[0031] In one embodiment of the present invention, the source region, drain region, and channel region of the amplification transistor SF are formed in a semiconductor layer. The channel region of the amplification transistor SF is formed in a portion of the semiconductor layer located on the region where the floating diffusion node FDN is formed. In other words, the metal wiring between the floating diffusion node FDN and the gate of the amplification transistor SF can be omitted, and the conversion gain when the gain control transistor DCX is turned off can be further increased.

[0032] Figure 5 is a diagram illustrating the operation of an image sensor according to one embodiment of the present invention. Figure 5 is a diagram that simply illustrates the operation of pixels included in an image sensor according to one embodiment of the present invention. In one embodiment, the pixels included in the pixel array are arranged along the row and column directions, connected to row drivers in the row direction and to readout circuits in the column direction. The row driver drives pixels arranged in the row direction simultaneously; therefore, the operation shown in Figure 5 is performed simultaneously on two or more pixels arranged along the row direction.

[0033] The pixel operation includes shutter operation SH, exposure time EIT, first readout operation RD1, and second readout operation RD2. During shutter operation SH, a reset operation is performed to remove the charge from the photodiode and floating diffusion node. For example, in shutter operation SH, the transmission transistor, conversion gain transistor, and reset transistor are turned on. In shutter operation SH, the photodiode, floating diffusion node, and capacitor are electrically connected to the first power supply node. The first power supply voltage removes the charge from the photodiode, floating diffusion node, and capacitor.

[0034] During the exposure time (EIT), the photodiode is exposed to light and generates an electric charge. For example, during exposure time (EIT), all transistors are turned off. The photodiode and the floating diffusion node are electrically isolated from each other. Therefore, the charge generated by the photodiode does not move to the floating diffusion node. A photodiode generates an electric charge in response to light, and this generated charge remains within the photodiode. The first readout operation RD1 is a readout operation performed under conditions where the pixels are set to have a high conversion gain. However, depending on the embodiment, an operation to reset the floating diffusion node may be performed after the exposure time EIT has ended, prior to executing the first readout operation RD1.

[0035] When the exposure time (EIT) ends, the row driver turns on the selection transistor, and a reset voltage is output through the column line connected to the readout circuit. When the reset voltage is output, the transmission transistor turns on, and the charge generated by the photodiode during exposure time is transferred to the floating diffusion node. The amplifying transistor outputs a signal voltage to the column line that is an amplified version of the voltage at the floating diffusion node. The readout circuit connected to the column line calculates the first pixel signal from the difference between the reset voltage and the signal voltage. The first pixel signal is a signal that covers a relatively low range of illumination. The gain control transistor connected to the floating diffusion node remains in the turned-off state so that the pixels have a high conversion gain while the first readout operation is performed. Therefore, the capacitance of the floating diffusion node can be kept sufficiently small, and the pixels can have a high conversion gain.

[0036] The second readout operation RD2 is a readout operation performed under conditions where the pixels are configured to have a low conversion gain. While the second readout operation RD2 is performed, the gain control transistor DCX is turned on, and the capacitor is electrically connected to the floating diffusion node. With the gain control transistor turned on and the capacitance of the floating diffusion node increased, the transmission transistor is turned on, and the residual charge remaining in the photodiode moves to the floating diffusion node. In the second readout operation RD, a signal voltage is output to the column line under the condition that the pixel has a low conversion gain.

[0037] In the first readout operation RD1, at least some of the photodiode's charge has already moved to the floating diffusion node, so in the second readout operation RD2, no reset voltage is output prior to the signal voltage. The transmission transistor, reset transistor, and gain control transistor are turned on, and the pixels output a reset voltage through the column line. The readout circuit calculates the second pixel signal under low conversion gain conditions by utilizing the difference between the signal voltage acquired in the second readout operation RD2 and the reset voltage mentioned above. The second pixel signal is a signal that covers a relatively high range of illumination. Unlike the embodiment shown in Figure 5, a third readout operation may be performed. The third readout operation involves reading the signal voltage corresponding to the charge generated by the photodiode and stored in the capacitor during the exposure operation using very strong light.

[0038] In environments where the intensity of light flowing into a photodiode is very strong, charge is generated that exceeds the photodiode's FWC (Full Well Capacity). In this case, the excess charge generated by the photodiode causes a decrease in the voltage at the node where the photodiode and the transmission transistor are connected, resulting in leakage through the transmission transistor. The charge generated above the photodiode's FWC (Free Flow Capacity) is then transferred to the capacitor and stored due to overflow. In the third readout operation, the gain control transistor is turned on and the charge stored in the capacitor is moved to the floating diffusion node, and the signal voltage is output to the column line.

[0039] Figure 6 is a layout diagram showing an outline of a pixel region according to one embodiment of the present invention, Figure 7 is a partial cross-sectional view taken along the line A-A' of the pixel region shown in Figure 6 according to one embodiment of the present invention, and Figure 8 is a partial cross-sectional view taken along the line B-B' of the pixel region shown in Figure 6 according to one embodiment of the present invention. The image sensor includes a first layer on which multiple pixels are formed and a second layer on which peripheral circuits are arranged. The peripheral circuitry is connected to multiple pixels through multiple row lines and multiple column lines, and drives multiple pixels. The first and second layers are stacked in the first direction (Z-axis direction). The specific embodiment of the image sensor is the same as described in Figures 1 to 5 above.

[0040] Multiple pixels are separated from each other through Deep Trench Isolation (DTI). In the embodiment shown in Figure 4, one pixel is formed in the pixel region. Figures 6 to 8 show the pixel PX of the embodiment shown in Figure 4. Deep trench isolation (DTI) is a shape that surrounds a pixel region, and the pixel region is rectangular. However, unlike in Figure 4, multiple pixels may be formed in a pixel region.

[0041] Deep trench isolation (DTI) is formed from multiple materials. For example, deep trench isolation (DTI) can be formed by combining silicon oxide (SiO) and polycrystalline silicon, or by combining silicon oxide and a metal. As another example, deep trench isolation (DTI) can be formed using a combination of aluminum oxide and silicon oxide.

[0042] Figures 7 and 8 show cross-sections of a portion of the first layer of the pixel region in the embodiment shown in Figure 6. The first layer includes a first substrate SUB, a first interlayer insulating layer IIL, a semiconductor layer SL, and a first insulating layer IL. The first substrate SUB may be bulk silicon or SOI (silicon-on-insulator). Alternatively, the first substrate SUB may be a silicon substrate, or may contain silicon germanium, indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate SUB may be a base substrate on which an epitaxial layer is formed.

[0043] The first interlayer insulating layer IIL is formed on one surface of the first substrate SUB, and this surface of the first substrate SUB is utilized to arrange multiple transistors for processing the electrical signals generated from the photodiode PD. For example, transmission transistors, amplification transistors, selection transistors, and reset transistors are formed on one side of the first substrate SUB. As another example, a gain control transistor may also be formed on the first substrate SUB. The first interlayer insulating layer IIL is formed on one surface of the first substrate SUB. The first interlayer insulating layer IIL may contain at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-dielectric-constant (low-k) material having a lower dielectric constant than silicon oxide.

[0044] The semiconductor layer SL is formed on one surface of the first substrate SUB; specifically, the semiconductor layer SL is formed on the first substrate SUB. In an embodiment of the present invention, the active region of the amplification transistor is formed in the semiconductor layer SL. The semiconductor layer SL may be composed of amorphous oxide semiconductor, 2D nanomaterial, amorphous silicon, or polycrystalline silicon. The semiconductor layer SL is formed by depositing the above material as a film onto the first substrate SUB. The first insulating layer IL is formed between the gate and channel regions of multiple transistors. The first insulating layer IL is a Gox insulating layer. For example, the first insulating layer may be composed of silicon oxide or a high dielectric constant material.

[0045] Referring to Figures 6 to 8, the pixel region includes a photodiode PD, a floating diffusion region FD, a transmission transistor, an amplification transistor, a selection transistor, and a reset transistor. According to one embodiment of the present invention, the photodiode PD, the floating diffusion region FD, the active region of the transmission transistor, and the active region of the reset transistor are formed on the first substrate SUB. Furthermore, the channel region of the amplification transistor is formed in a portion of the semiconductor layer SL located on top of the floating diffusion region FD.

[0046] Referring to Figures 6 and 7, the gate TG and floating diffusion region FD of the transmission transistor are arranged in a second direction (X-axis direction) that is parallel to the upper surface of the first substrate SUB and perpendicular to the first direction. Referring to Figures 6 and 8, the semiconductor layer SL extends in a third direction (Y-axis direction) that is parallel to the upper surface of the first substrate SUB and perpendicular to the second direction. The second direction in which the gate TG and floating diffusion region FD of the transmission transistor are located intersects with the third direction in which the semiconductor layer SL is extended.

[0047] Referring to Figures 7 and 8, the Shallow Trench Isolation (STI) defines the active region within the pixel area. The element isolation film STI is formed within the first substrate SUB adjacent to one surface of the first substrate SUB. The element isolation film STI is formed by embedding an insulating material in trenches created by patterning the first substrate SUB. As a result, the device isolation film STI defines the region where the device isolation film STI is not formed as the active region.

[0048] Referring to Figure 7, the gate TG of the transmission transistor according to the embodiment of the present invention is a vertical transfer gate. A first insulating layer IL is placed between the gate TG of the transmission transistor and the first substrate SUB. In this configuration, the photodiode PD is positioned below the floating diffusion region FD in the first direction (Z-axis direction). Unlike the diagrams in Figures 7 and 8, the gate TG of the transmission transistor and the photodiode PD may be arranged on one surface of the first substrate SUB in the second direction (X-axis direction).

[0049] An isolation region (IS) is formed around the photodiode (PD). The isolation region IS is formed in contact with the deep trench isolation film DTI and / or the device isolation film STI. The isolation region (IS) and the photodiode (PD) have different doping types. For example, the isolation region (IS) is doped with P-type, and the photodiode (PD) is doped with N-type. This prevents the isolation region IS from dispersing to other regions, so that the charge generated by the photodiode PD is stored in the floating diffusion region FD.

[0050] Referring to Figures 6 and 7, the first node region NR1 is the region where the first node N1 in Figure 4 is formed. Referring to Figure 6, the first node region NR1 extends along the second and third directions. In a portion of the first node region NR1 that extends along the second direction, the gate TG and floating diffusion region FD of the transmission transistor are positioned in the second direction. A portion of the first node region NR1 that extends along the third direction is located in the active region of the reset transistor and in the third direction.

[0051] In an embodiment of the present invention, the source region AC1, the drain region AC2, and the channel region CH of the amplification transistor are formed in the semiconductor layer SL. The source region AC1 of the amplification transistor and the second power supply node are connected via a metal wiring CT. The second power supply node is the node that supplies the second power supply voltage. In an embodiment of the present invention, the gate of the amplification transistor is formed in a floating diffusion region (FD). The channel region CH of the amplification transistor is formed between the source region AC1 and the drain region AC2 of the amplification transistor. Specifically, the channel region CH of the amplification transistor is formed in a portion of the semiconductor layer SL that superimposes with the floating diffusion region FD in the first direction (Z-axis direction).

[0052] In the embodiments shown in Figures 6 to 8, the active region of the selected transistor is also formed in the semiconductor layer SL. The source region AC2 and drain region AC3 of the selected transistor are formed in the semiconductor layer SL. The gate SEL of the selection transistor is formed on the semiconductor layer SL, and a first insulating layer IL is placed between the gate SEL of the selection transistor and the semiconductor layer SL. The selection transistor is connected between the amplification transistor and the column line. The drain region AC3 and column line of the select transistor are connected via metal wiring CT. At this time, the selection transistor outputs a reset voltage and / or a signal voltage to the column line.

[0053] The source and drain regions of the reset transistor are formed on the first substrate SUB, and the gate of the selection transistor is formed on the first insulating layer IL. The structure of a reset transistor is similar to that of a gain control transistor. The reset transistor is connected between the floating diffusion region (FD) and the first power supply node. Specifically, the reset transistor is connected between the first node region NR1 and the first power supply node. The source region of the reset transistor and the first power supply node are connected via a metal wiring transformer (CT). The first power supply node is the node that supplies the first power supply voltage.

[0054] In the embodiments shown in Figures 6 to 8, the pixel includes a gain control transistor and a capacitor. The gain control transistor is connected between the floating diffusion region FD and the first node region NR1. The active region of the gain control transistor is formed on the first substrate SUB between the floating diffusion region FD and the first node region NR1. The gate DCG of the gain control transistor is located on the first substrate SUB, and a first insulating layer IL is placed between the gate DCG of the gain control transistor and the first substrate SUB. In other words, the gate DCG of the gain control transistor is formed on the first insulating layer IL. For example, the gate DCG of a gain control transistor is located adjacent to the semiconductor layer SL.

[0055] The capacitor is formed on the first insulating layer IL. The specific embodiment is the same as that shown in Figure 4. The first node region NR1 and the capacitor are connected via metal wiring CT.

[0056] Referring to Figure 6, each pixel includes the ground area GRD. The grounding region (GRD) provides a reference potential to the pixel and is connected to various elements formed on the pixel. The photodiode PD and capacitor are connected to the ground region GRD through metal wiring, allowing for stable charge transfer at the reference potential. Furthermore, the isolation region IS is connected to the ground region GRD through metal wiring, which stably prevents the charge generated by the photodiode PD from dispersing due to the reference potential.

[0057] In the embodiments shown in Figures 6 to 8, the active regions of the amplification transistor and the selection transistor are formed in the semiconductor layer. The channel region CH of the amplification transistor is superimposed on the floating diffusion region FD in the first direction. This allows for an increase in conversion gain by eliminating the need for metal wiring connecting the floating diffusion region (FD) and the amplification transistor.

[0058] Figure 9 is a partial cross-sectional view obtained by cutting along the line B-B' of the pixel region shown in Figure 6 according to one embodiment of the present invention. The layout diagram of the pixel region shown in Figure 9 is identical to that of Figure 6, and the partial cross-sectional view of the pixel region cut along the line A-A' shown in Figure 9 is identical to that of Figure 7. The specific embodiment for the pixel region according to the embodiment shown in Figure 9 may be the same as that described in Figures 6 to 8 above, except for the form of the semiconductor layer SL.

[0059] Comparing Figure 9 with Figure 8, the morphology of the semiconductor layer SL is different. The entire lower surface of the semiconductor layer SL in Figure 8 is in contact with the first insulating layer IL. In contrast, the underside of a portion of the semiconductor layer SL in Figure 9 can be in contact with the first insulating layer IL, while the underside of the remaining portion of the semiconductor layer can be in contact with the first interlayer insulating layer IIL. A portion of the semiconductor layer SL in contact with the first insulating layer IL overlaps with the floating diffusion region FD in the first direction (Z-axis direction). In other words, a channel region CH of the amplification transistor is formed in a portion of the semiconductor layer SL that is in contact with the first insulating layer IL. The gate of an amplifying transistor is formed in a floating diffusion region (FD).

[0060] The source and / or drain regions (AC1 to AC3) formed in the semiconductor layer SL are formed in a portion of the upper part of the semiconductor layer SL, as shown in the embodiment in Figure 9. However, the formation location and / or form of the source and / or drain regions (AC1 to AC3) formed in the semiconductor layer SL are not limited to the embodiment shown in Figure 9. In the active region of the selected transistor shown in Figure 8, a device isolation film (STI) is formed in a portion of the first substrate (SUB) that overlaps with the first direction. In contrast, an isolation region IS can be formed in a portion of the first substrate SUB that superimposes the active region of the selected transistor in Figure 9 in the first direction. The lower surface of the remaining region of the semiconductor layer in contact with the first interlayer insulating layer IIL in Figure 9 has a predetermined distance from the upper surface of the first substrate SUB in the first direction. As a result, the active region of the selected transistor in Figure 9 is not affected by the potential formed in the isolation region IS, and therefore the element isolation film STI can be omitted.

[0061] Figure 10 is a layout diagram showing a schematic of a pixel region according to one embodiment of the present invention, Figure 11 is a partial cross-sectional view taken along the line A-A' of the pixel region shown in Figure 10 according to one embodiment of the present invention, and Figure 12 is a partial cross-sectional view taken along the line B-B' of the pixel region shown in Figure 10 according to one embodiment of the present invention. Comparing Figures 10-12 with Figures 6-8, the pixel area layout according to the embodiment shown in Figures 10-12 further includes a back gate (BG). The specific embodiments for the pixel region shown in Figures 10 to 12 may be the same as those described in Figures 6 to 8 above, except for the back gate (BG).

[0062] Referring to Figures 10 to 12, the pixel region further includes the back gate (BG). The back gate overlaps with the floating diffusion region (FD) and a portion of the semiconductor layer (SL) in the first direction (Z-axis direction). Specifically, a portion of the semiconductor layer SL mentioned above includes the channel region CH of the amplification transistor. A negative voltage is applied to the back gate (BG). As a result, the channel region CH of the amplification transistor can be formed only in the semiconductor layer SL that is close to the floating diffusion region FD in the first direction. Comparing Figures 11 and 12 with Figures 8 and 9, the thickness of the channel region CH of the amplification transistors in Figures 11 and 12 is thinner than the thickness of the channel region CH of the amplification transistors in Figures 8 and 9.

[0063] As the thickness of the channel region CH of the amplification transistor in the embodiments shown in Figures 11 and 12 decreases, it becomes even more susceptible to the influence of the voltage in the floating diffusion region FD. In other words, the responsiveness of the channel region (CH) of the amplification transistor is improved. This allows for a further increase in the conversion gain.

[0064] Figure 13 is a layout diagram showing a schematic of a pixel region according to one embodiment of the present invention, Figure 14 is a partial cross-sectional view taken along the line A-A' of the pixel region shown in Figure 13 according to one embodiment of the present invention, and Figure 15 is a partial cross-sectional view taken along the line B-B' of the pixel region shown in Figure 13 according to one embodiment of the present invention. The specific embodiments for the pixel region shown in Figures 13 to 15 may be the same as those described in Figures 6 to 8 above, except for the region where the selection transistor is formed. The partial cross-section obtained by cutting along the line A-A' in the pixel region of one embodiment of the present invention shown in Figure 14 is identical to that of the embodiment of the present invention shown in Figure 7 described above.

[0065] Referring to Figures 13 to 15, the source and drain regions of the selection transistor are formed on the first substrate SUB, and the gate SEL of the selection transistor is formed on the first insulating layer IL. On the other hand, the source region and drain region of the selected transistor in the embodiments shown in Figures 6 to 8 are formed in the semiconductor layer SL. Referring to Figure 15, a channel region of the selection transistor is formed in a portion of the first substrate SUB that superimposes the gate SEL of the selection transistor in the first direction (Z-axis direction). An isolation region IS is placed beneath a portion of the first substrate SUB. In embodiments of the present invention, the utilization of the first substrate SUB is increased by forming the selected transistor on the first substrate SUB instead of the semiconductor layer SL.

[0066] Figure 16 is a layout diagram showing a schematic of a pixel region according to one embodiment of the present invention, Figure 17 is a partial cross-sectional view taken along the line A-A' of the pixel region shown in Figure 16 according to one embodiment of the present invention, and Figure 18 is a partial cross-sectional view taken along the line B-B' of the pixel region shown in Figure 16 according to one embodiment of the present invention. The specific embodiments for the pixel region shown in Figures 16 to 18 may be the same as those described in Figures 6 to 8 above, except for the structure of the semiconductor layer.

[0067] Referring to Figures 16 to 18, some regions of the semiconductor layer SL have a fin structure, and some regions of the semiconductor layer SL are adjacent to the floating diffusion region FD. In the first direction (Z-axis direction), a portion of the semiconductor layer SL overlaps with the first substrate SUB, and another portion overlaps with the first interlayer insulating layer IIL. The floating diffusion region FD surrounds a portion of the semiconductor layer SL, and a first insulating layer IL is positioned between the semiconductor layer SL and the floating diffusion region FD.

[0068] In the embodiment shown in Figure 18, the source and / or drain regions (AC1 to AC3) formed in the semiconductor layer SL are formed in a portion of the upper part of the semiconductor layer SL. However, the formation location and / or form of the source and / or drain regions (AC1 to AC3) formed in the semiconductor layer SL are not limited to the embodiment shown in Figure 9. Comparing Figures 16-18 with Figures 6-8, the semiconductor layer SL in Figures 16-18 has an increased contact area with the floating diffusion region FD. In other words, the area in contact between the gate of the amplification transistor and the channel region CH of the amplification transistor increases. This makes it easier to control charge transfer in the channel region CH of the amplification transistor.

[0069] The pixel region structures of the embodiments of the present invention shown in Figures 6 to 18 can be merged and applied to one another. As an example, the embodiments of Figures 10 to 12 are combined with the embodiments of Figures 13 to 15, so that the back gate BG is formed to overlap with the channel region CH formed in the semiconductor layer SL in the first direction. At this time, the gate SEL of the selection transistor is formed on the first insulating layer IL placed on the first substrate SUB.

[0070] As another example, by combining the embodiments of Figures 16 to 18 with the embodiment of Figure 9, a portion of the semiconductor layer SL on which the channel region CH of the amplification transistor is formed may have a fin structure. At this time, the lower surface of the remaining region of the semiconductor layer SL is in contact with the first interlayer insulating layer IIL. However, the types of combinations of embodiments of the present invention shown in Figures 6 to 18 are not limited thereto.

[0071] Figure 19 is a circuit diagram of a pixel included in an image sensor according to one embodiment of the present invention. Referring to Figure 19, a pixel PX according to one embodiment of the present invention includes a photodiode PD and a pixel circuit. The pixel circuit includes a floating diffusion node FDN, a transmission transistor TX, a gain control transistor DCX, a capacitor CAP, a reset transistor RX, an amplification transistor SF, and a selection transistor SX, among others. It includes multiple transistors (TG, RG, DRG, RG, SEL) within the pixel circuit. The control signals that control the multiple transistors included in the pixel circuit are output by the row driver.

[0072] The floating diffusion node (FDN) is connected to the photodiode (PD) via the transmission transistor (TX). When the transmission transistor TX is turned on by the transmission control signal, the charge of the photodiode PD is stored in the floating diffusion node FDN. In the embodiment shown in Figure 19, the gain control transistor DCX is connected between the floating diffusion node FDN and the first node N1. Capacitor CAP is connected to the first node N1. A reset transistor RX is connected between the first power node and the floating diffusion node FDN. The first power supply node is the node that supplies the first power supply voltage VDD1 and is connected to the drain of the reset transistor RX.

[0073] Comparing Figure 19 with Figure 4, the connection structure of the gain control transistor DCX and capacitor CAP is different. Specifically, in the embodiment of the present invention shown in Figure 19, the gain control transistor DCX and capacitor CAP are not connected between the reset transistor RX and the floating diffusion node FDN.

[0074] When the gain control transistor DCX is turned on by the gain control signal, capacitor CAP is connected to the floating diffusion node FDN. This increases the capacitance of the floating diffusion node (FDN), reducing the conversion gain of the pixel PX. Conversely, when the gain control transistor DCX is turned off by the gain control signal, the conversion gain of pixel PX increases.

[0075] The amplification transistor SF is connected to the floating diffusion node FDN, and the amplification transistor SF is connected between the second power supply node and the selection transistor SX. The second power node is the node that supplies the second power supply voltage VDD2. In this embodiment, the first power supply voltage VDD1 may be the same as or different from the second power supply voltage VDD2. The amplifying transistor SF acts as a source-follower amplifier, amplifying the voltage across the floating diffusion node FDN to generate a signal. The signal generated by the amplification transistor SF is output to the column line COL by the turn-on operation of the selection transistor SX. Column line COL is connected to one of the input terminals of the correlated duplex sampler, which transmits the output signal to column line COL and the output signal determined by the ramp voltage to the counter.

[0076] In the embodiment of the present invention, the source region, drain region, and channel region of the amplification transistor SF are formed in a semiconductor layer. The channel region of the amplification transistor SF is formed in a portion of the semiconductor layer located above the region where the floating diffusion node FDN is formed. In other words, by omitting the metal wiring between the floating diffusion node FDN and the gate of the amplification transistor SF, the conversion gain when the gain control transistor DCX is turned off can be further increased. The operation of the image sensor including pixel PX in the embodiment of the present invention shown in Figure 19 may be the same as that described in Figure 5 above.

[0077] Figure 20 is a layout diagram showing an outline of a pixel region according to one embodiment of the present invention, Figure 21 is a partial cross-sectional view taken along the line A-A' of the pixel region shown in Figure 6 according to one embodiment of the present invention, and Figure 22 is a partial cross-sectional view taken along the line B-B' of the pixel region shown in Figure 6 according to one embodiment of the present invention.

[0078] The image sensor includes a first layer on which multiple pixels are formed and a second layer on which peripheral circuits are arranged. The peripheral circuitry is connected to multiple pixels through multiple row lines and multiple column lines, and drives multiple pixels. The first and second layers are stacked in the first direction (Z-axis direction). The specific embodiment of the image sensor may be the same as that described in Figures 1 to 3 above. Multiple pixels are separated from each other through deep trench isolation (DTI). In the embodiment shown in Figure 20, one pixel is formed in the pixel region. Figures 20 to 22 show the pixel PX of the embodiment shown in Figure 19.

[0079] Figures 21 and 22 show cross-sections of a portion of the first layer of the pixel region in the embodiment shown in Figure 20. The first layer includes a first substrate SUB, a first interlayer insulating layer IIL, a semiconductor layer SL, and a first insulating layer IL. The pixel region includes a photodiode PD, a floating diffusion region FD, a transmission transistor, an amplification transistor, a selection transistor, a reset transistor, a gain control transistor, and a capacitor. Specific embodiments of the pixel region may be similar to those described in Figures 6 to 8 above.

[0080] Comparing Figures 20-22 with Figures 6-8, the positions where the gain control transistor and reset transistor are formed are different. Referring to Figures 20 and 21, the gate TG of the transmission transistor, the floating diffusion region FD, the gate RG of the reset transistor, and the second node region NR2 are arranged in a second direction (X-axis direction) that is parallel to the upper surface of the first substrate SUB and perpendicular to the first direction. The second node region NR2 is the region where the first power supply voltage node in Figure 19 is formed.

[0081] Referring to Figures 20 and 22, the semiconductor layer SL is parallel to the upper surface of the first substrate SUB, perpendicular to the first direction, and extends in a third direction (Y-axis direction) that is orthogonal to the second direction. The second direction in which the gate TG of the transmission transistor and the second node region NR2 are located intersects with the third direction in which the semiconductor layer SL is extended. Furthermore, the first node region NR1, the gate DCG of the gain control transistor, the floating diffusion region FD, and the gate SEL of the selection transistor are arranged in the third direction. The first node region NR1 is the region where the first node N1 in Figure 19 is formed. The structure of the pixel region in the embodiments shown in Figures 20 to 22 may be adapted to at least one of the embodiments shown in Figures 10 to 18 described above.

[0082] Figure 23 is a circuit diagram of a pixel included in an image sensor according to one embodiment of the present invention. Referring to Figure 23, a pixel PX according to one embodiment of the present invention includes a photodiode PD and a pixel circuit. The pixel circuit includes a floating diffusion node FDN, a transmission transistor TX, a reset transistor RX, an amplification transistor SF, and a selection transistor SX, among others. Comparing Figure 23 with Figures 4 and 19, the pixel PX in the embodiment shown in Figure 23 does not include the gain control transistor DCX and the capacitor CAP.

[0083] Each of the multiple transistors included in the pixel circuit contains a gate (TG, RG, SEL). The control signals that control the multiple transistors included in the pixel circuit are output by the row driver. The floating diffusion node (FDN) is connected to the photodiode (PD) via the transmission transistor (TX). When the transmission transistor TX is turned on by the transmission control signal, the charge of the photodiode PD is stored in the floating diffusion node FDN.

[0084] In the embodiment shown in Figure 23, a reset transistor RX is connected between the first power supply node and the floating diffusion node FDN. The first power supply node is the node that supplies the first power supply voltage VDD1 and is connected to the drain of the reset transistor RX. The amplification transistor SF is connected to the floating diffusion node FDN, and the amplification transistor SF is connected between the second power supply node and the selection transistor SX. The second power node is the node that supplies the second power supply voltage VDD2. Depending on the embodiment, the first power supply voltage VDD1 may be the same as or different from the second power supply voltage VDD2.

[0085] The amplifying transistor SF acts as a source-follower amplifier, amplifying the voltage across the floating diffusion node FDN to generate a signal. The signal generated by the amplification transistor SF is output to the column line COL by the turn-on operation of the selection transistor SX. Column line COL is connected to one of the input terminals of the correlated duplex sampler, which transmits the output signal to column line COL and the output signal determined by the ramp voltage to the counter.

[0086] In the embodiment of the present invention, the source region, drain region, and channel region of the amplification transistor SF are formed in a semiconductor layer. The channel region of the amplification transistor SF is formed in a portion of the semiconductor layer located on the region where the floating diffusion node FDN is formed. In other words, by omitting the metal wiring between the floating diffusion node FDN and the gate of the amplification transistor SF, the conversion gain when the gain control transistor DCX is turned off can be further increased.

[0087] Figure 24 is a layout diagram showing an outline of a pixel region according to one embodiment of the present invention, Figure 25 is a partial cross-sectional view taken along the line A-A' of the pixel region shown in Figure 24 according to one embodiment of the present invention, and Figure 26 is a partial cross-sectional view taken along the line B-B' of the pixel region shown in Figure 24 according to one embodiment of the present invention.

[0088] The image sensor includes a first layer on which multiple pixels are formed and a second layer on which peripheral circuits are arranged. The peripheral circuitry is connected to multiple pixels through multiple row lines and multiple column lines, and drives multiple pixels. The first and second layers are stacked in the first direction (Z-axis direction). The specific embodiment of the image sensor may be the same as that described in Figures 1 to 3 above.

[0089] Multiple pixels are separated from each other through deep trench isolation (DTI). In the embodiment shown in Figure 24, one pixel is formed in the pixel region. Figures 24 to 26 show the pixel PX of the embodiment shown in Figure 23. Figures 25 and 26 show cross-sections of a portion of the first layer of the pixel region in the embodiment shown in Figure 24. The first layer includes a first substrate SUB, a first interlayer insulating layer IIL, a semiconductor layer SL, and a first insulating layer IL. The pixel region includes a photodiode PD, a floating diffusion region FD, a transmission transistor, an amplification transistor, a selection transistor, and a reset transistor. A specific embodiment of the pixel region may be the same as that described in Figure 23 above.

[0090] Referring to Figures 24 and 25, the gate TG of the transmission transistor, the floating diffusion region FD, the gate RG of the reset transistor, and the second node region NR2 are arranged in a second direction (X-axis direction) that is parallel to the upper surface of the first substrate SUB and perpendicular to the first direction. The second node region NR2 is the region where the first power supply voltage node in Figure 23 is formed. Referring to Figures 24 and 26, the semiconductor layer SL extends in a third direction (Y-axis direction) that is parallel to the upper surface of the first substrate SUB, perpendicular to the first direction, and orthogonal to the second direction. The second direction in which the gate TG of the transmission transistor and the second node region NR2 are located intersects with the third direction in which the semiconductor layer SL is extended. Furthermore, the floating diffusion region FD and the gate SEL of the selection transistor can be located in the third direction. The structure of the pixel region in the embodiments shown in Figures 24 to 26 may be adapted to at least one of the embodiments shown in Figures 10 to 18 described above.

[0091] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of Symbols]

[0092] 10 Image Sensors 20, 50 pixel array 30 Peripheral Circuits 31-line driver 32. Lead-out circuit 33. Data output circuit 34 Control Logic 51, 52, 53 (red, green, blue) pixels 100 Image Sensors 101 First board 102 Second board 103 Color Filters 105 Microlens 110, 140 Multiple transistors 111 Metal wiring 115 Top end wiring 120 First interlayer insulating layer 130 Capacitors 150 Second interlayer insulating layer 155 Topmost wiring of the second layer AC1 Amplifier transistor source region Drain region of AC2 amplification transistor AC3 Select Transistor Drain Region CAP Capacitor CH channel region of amplifier transistor COL column line CT metal wiring DCG (Gate of a Gain-Controlled Transistor) DCX Gain Control Transistor DTI Deep Trench Isolation FD Floating Diffusion Region FDN Floating Diffusion Node GRD ground area IIL (First Interlayer Insulation) IL (First Insulating Layer) IS Isolation Area L1, L2 (1st, 2nd) layers NR1 1st node area N1 First Node PD photodiode PX pixels RG Reset transistor gate RX Reset Transistor SF Amplifying Transistor SL semiconductor layer SEL Select Transistor Gate STI device isolation membrane SUB 1st board SX Select Transistor TG (Gate of a transmission transistor) TX transmission transistor VDD1, VDD2 (1st, 2nd) power supply voltages

Claims

1. A first layer in which multiple pixels are formed, A peripheral circuit is arranged to connect to the plurality of pixels through a plurality of row lines and a plurality of column lines, and to drive the plurality of pixels, and the first layer and a second layer stacked in a first direction are provided. Each of the plurality of pixels includes a photodiode, a floating diffusion region where the charge generated by the photodiode is stored, a transmission transistor connected between the photodiode and the floating diffusion region, and an amplification transistor connected to the floating diffusion region. The first layer includes a first substrate, a first interlayer insulating layer formed on one surface of the first substrate, a semiconductor layer formed in a portion of one surface of the first substrate, and a first insulating layer formed between the first substrate and the semiconductor layer. The source region, drain region, and channel region of the amplification transistor are formed in the semiconductor layer. The image sensor is characterized in that the channel region of the amplification transistor is formed in a part of the semiconductor layer that superimposes the floating diffusion region in the first direction.

2. The image sensor according to claim 1, characterized in that the gate of the transmission transistor is a vertical transmission gate.

3. The image sensor according to claim 2, characterized in that the photodiode is positioned below the floating diffusion region in the first direction.

4. The image sensor according to claim 1, characterized in that the semiconductor layer is composed of an amorphous oxide semiconductor.

5. The image sensor according to claim 1, characterized in that the semiconductor layer is composed of a 2D nanomaterial.

6. The image sensor according to claim 1, characterized in that the semiconductor layer is composed of amorphous silicon or polycrystalline silicon.

7. The image sensor according to claim 1, characterized in that each of the plurality of pixels further includes a selection transistor connected between the amplification transistor and the column line.

8. The source region and drain region of the selected transistor are formed in the semiconductor layer. The image sensor according to claim 7, characterized in that the gate of the selection transistor is formed on the semiconductor layer.

9. The lower surface of a portion of the semiconductor layer is in contact with the first insulating layer, and the lower surface of the remaining portion of the semiconductor layer is in contact with the first interlayer insulating layer. The image sensor according to claim 8, characterized in that a portion of the semiconductor layer overlaps with the floating diffusion region in the first direction.

10. The source region and drain region of the selected transistor are formed on the first substrate. The image sensor according to claim 7, characterized in that the gate of the selection transistor is formed on the first insulating layer.

11. Each of the plurality of pixels further includes a reset transistor connected between the floating diffusion region and the first power node, The amplification transistor is connected between the floating diffusion region and the second power supply node. The source region and drain region of the reset transistor are formed on the first substrate. The image sensor according to claim 7, characterized in that the gate of the selection transistor is formed on the first insulating layer.

12. Each of the plurality of pixels further includes a gain control transistor connected between the floating diffusion region and the first node and a capacitor connected to the first node, The gate of the gain control transistor and the capacitor are formed on the first insulating layer. The image sensor according to claim 11, characterized in that the gate of the gain control transistor is arranged adjacent to the semiconductor layer.

13. The image sensor according to claim 12, characterized in that the reset transistor is connected between the first power supply node and the first node.

14. Each of the plurality of pixels further includes a back gate to which a negative voltage is applied. The back gate overlaps with the floating diffusion region and a portion of the semiconductor layer in the first direction. The image sensor according to claim 1, characterized in that a portion of the semiconductor layer includes the channel region of the amplification transistor.

15. The image sensor according to claim 1, characterized in that a portion of the semiconductor layer adjacent to the floating diffusion region has a fin structure.

16. A first layer in which multiple pixels are formed, A peripheral circuit is arranged to drive the plurality of pixels and acquire a pixel signal, and the device has a first layer and a second layer stacked in a first direction, Each of the plurality of pixels includes a photodiode, a floating diffusion region where the charge generated by the photodiode is stored, a transmission transistor connected between the photodiode and the floating diffusion region, an amplification transistor connected to the floating diffusion region, and a selection transistor connected between the amplification transistor and a column line. The first layer includes a first substrate, a first interlayer insulating layer formed on one surface of the first substrate, a semiconductor layer formed in a portion of one surface of the first substrate, and a first insulating layer formed between the first substrate and the semiconductor layer. The second direction in which the gate of the transmission transistor and the floating diffusion region are located intersects with the third direction in which the semiconductor layer is extended. The image sensor is characterized in that the second and third directions are parallel to the upper surface of the first substrate and perpendicular to the first direction.

17. Each of the plurality of pixels further includes a gain control transistor connected between the floating diffusion region and the first node and a capacitor connected to the first node, The active region of the gain control transistor is formed on the first substrate. The image sensor according to claim 16, characterized in that the capacitor is formed on the first insulating layer.

18. The image sensor according to claim 17, wherein each of the plurality of pixels further includes a reset transistor connected between a first power supply node and the first node.

19. The image sensor according to claim 16, characterized in that the semiconductor layer is composed of an amorphous oxide semiconductor, a 2D nanomaterial, amorphous silicon, or polycrystalline silicon.

20. A first layer in which multiple pixels are formed, A peripheral circuit is arranged to drive the plurality of pixels and acquire a pixel signal, and the device has a first layer and a second layer stacked in a first direction, Each of the plurality of pixels includes a photodiode, a floating diffusion region where the charge generated by the photodiode is stored, a transmission transistor connected between the photodiode and the floating diffusion region, a reset transistor connected between the floating diffusion region and a first power node, an amplification transistor connected to the floating diffusion region, and a selection transistor connected between the amplification transistor and a column line. The first layer includes a first substrate, a first interlayer insulating layer formed on one surface of the first substrate, a semiconductor layer formed in a portion of one surface of the first substrate, and a first insulating layer formed between the first substrate and the semiconductor layer. The photodiode, the floating diffusion region, the active region of the transmission transistor, and the active region of the reset transistor are formed on the first substrate. The channel region of the amplification transistor is formed in a portion of the semiconductor layer located on the floating diffusion region. The gate of the amplification transistor is formed in the floating diffusion region. The gate of the aforementioned transmission transistor is a vertical transmission gate. The image sensor is characterized in that the photodiode is positioned below the floating diffusion region in the first direction.

Images