Semiconductor equipment

Abstract

To increase the speed of switching. [Solution] The semiconductor device according to this embodiment comprises a semiconductor layer, a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third electrode, a third semiconductor region of a first conductivity type, a fourth semiconductor region of a second conductivity type, and a fifth semiconductor region of a second conductivity type. The first electrode and the second electrode are provided on the first and second main surfaces of the semiconductor layer, respectively. The first semiconductor region is provided within the semiconductor layer. The second semiconductor region is located above the first semiconductor region. The third electrode faces the second semiconductor region via an insulating region. The third semiconductor region is located above the second semiconductor region. The fourth semiconductor region is located between the first electrode and the first semiconductor region. The fifth semiconductor region is provided so as to be surrounded by the fourth semiconductor region and has a lower impurity concentration than the fourth semiconductor region.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] In semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), it is preferable that the switching speed is increased. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-101242 [Patent Document 2] Japanese Patent Publication No. 2015-72950 [Overview of the project] [Problems that the invention aims to solve]

[0004] Embodiments of the present invention provide a semiconductor device capable of high-speed switching. [Means for solving the problem]

[0005] The semiconductor device according to this embodiment includes a semiconductor layer, a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third electrode, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type, and a fifth semiconductor region of the second conductivity type. The semiconductor layer includes a first main surface and a second main surface. The first electrode is provided on the first main surface. The second electrode is provided on the second main surface. The first semiconductor region is provided within the semiconductor layer. The second semiconductor region is provided within the semiconductor layer and is located above the first semiconductor region. The third electrode faces the second semiconductor region via an insulating region. The third semiconductor region is provided within the semiconductor layer, is located above the second semiconductor region, and is electrically connected to the second electrode. The fourth semiconductor region is provided within the semiconductor layer, is located between the first electrode and the first semiconductor region, and is electrically connected to the first electrode. The fifth semiconductor region is provided within the semiconductor layer so as to be surrounded by the fourth semiconductor region and is electrically connected to the first electrode. The fifth semiconductor region has a lower impurity concentration than the fourth semiconductor region.

Brief Description of the Drawings

[0006] [Figure 1] It is a plan view of the semiconductor device according to the first embodiment. [Figure 2] It is a bottom view of the semiconductor device according to the first embodiment. [Figure 3] It is a cross-sectional view of the semiconductor device according to the first embodiment and is a cross-sectional view taken along line A-A in FIGS. 1 and 2. [Figure 4] It is a bottom view of the semiconductor device according to a modified example of the first embodiment. [Figure 5] It is a graph showing the evaluation results of the short-circuit withstand of the semiconductor devices according to the first embodiment and the comparative example. [Figure 6A] It is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device according to the first embodiment. [Figure 6B] It is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device according to the first embodiment following FIG. 6A. [Figure 6C] It is a cross-sectional view for explaining an example of a manufacturing process of a semiconductor device according to the first embodiment, following FIG. 6B. <000098><000099>It is a cross-sectional view for explaining an example of a manufacturing process of a semiconductor device according to the first embodiment, following FIG. 6C. [Figure 6E] It is a cross-sectional view for explaining an example of a manufacturing process of a semiconductor device according to the first embodiment, following FIG. 6D. [Figure 6F] It is a cross-sectional view for explaining an example of a manufacturing process of a semiconductor device according to the first embodiment, following FIG. 6E. [Figure 7] It is a bottom view of a semiconductor device according to the second embodiment. [Figure 8] It is a bottom view of a semiconductor device according to a modified example of the second embodiment.

MODE FOR CARRYING OUT THE INVENTION

[0007] Hereinafter, embodiments according to the present invention will be described with reference to the drawings. The embodiments do not limit the present invention. The drawings are schematic or conceptual, and the ratios of each part are not necessarily the same as those in reality. In the specification and drawings, the same reference numerals are given to the same elements as those described above with respect to the previous drawings, and detailed descriptions are omitted as appropriate.

[0008] Also, for convenience of explanation, as shown in FIGS. 1 to 3, an XYZ orthogonal coordinate system is adopted. The Z-axis direction is the stacking direction (thickness direction) of the semiconductor device. Also, among the Z-axis directions, the emitter electrode side is also referred to as "up", and the collector electrode side is also referred to as "down". However, this expression is for convenience and has nothing to do with the direction of gravity.

[0009] Also, in the following description, in order to represent the relative levels of impurity concentrations in each conductivity type, n , , - , - ,

[0009] , + , , + , + , n, n - , and, p + , p, p - notation may be used. That is, n + has a relatively higher n-type impurity concentration than n, and n- indicates that the n-type impurity concentration is relatively lower than n. Also, p + indicates that the p-type impurity concentration is relatively higher than p, and p - indicates that the p-type impurity concentration is relatively lower than p. These notations represent the relative high or low levels of the net impurity concentration after the impurities have compensated for each other when both p-type and n-type impurities are included in their respective regions. n-type, n + -type and n - -type are examples of the first conductivity type in the claims. p-type, p + ?-type and p - -type are examples of the second conductivity type in the claims. In the following description, the n-type and p-type may be reversed. That is, the first conductivity type may be p-type.

[0010] Also, the impurity concentration in the semiconductor region can be measured, for example, by Secondary Ion Mass Spectrometry (SIMS). Also, the relative high or low level of the impurity concentration can be determined, for example, from the high or low carrier concentration obtained by Scanning Capacitance Microscopy (SCM).

[0011] [[ID=二十]] [[ID=二十一]] [[ID=二十二]]

[0012] [[ID=二十三]] (First Embodiment) It should be noted that there seems to be an unclear "p + ?-type" in the original text. I've translated it as best as possible while keeping the unclear part as it is. If there is an error in the original text, it may affect the accuracy of the translation.The semiconductor device 1 according to the first embodiment will be described with reference to Figures 1 to 3. Figure 1 is a plan view of the semiconductor device 1 according to the first embodiment. Figure 2 is a bottom view of the semiconductor device 1 according to the first embodiment. Figure 3 is a cross-sectional view of the semiconductor device 1 according to the first embodiment, and is a cross-sectional view along line AA in Figures 1 and 2. Note that the emitter electrode 12 is omitted in Figure 1, and the collector electrode 11 is omitted in Figure 2.

[0013] The semiconductor device 1 is, for example, an IGBT. In this embodiment, the case in which the semiconductor device 1 is a vertical IGBT having a trench gate structure will be described as an example. However, the semiconductor device 1 may also be a vertical IGBT having a planar gate structure or the like.

[0014] As shown in Figure 3, the semiconductor device 1 according to this embodiment comprises a semiconductor layer 2, a collector electrode 11, an emitter electrode 12, a gate electrode 13, and an insulating region 30.

[0015] The semiconductor layer 2 has a lower surface 2a, an upper surface 2b opposite to the lower surface 2a, and a side portion 2c. The lower surface 2a and the upper surface 2b are examples of the first and second main surfaces in the claims, respectively.

[0016] Furthermore, the semiconductor layer 2 has an outer peripheral region OA that extends inward from the side portion 2c of the semiconductor layer 2, and an inner region IA that is inside the outer peripheral region OA. The inner region IA is the main path for current when the semiconductor device 1 is operating, and is also called the cell region. In Figures 1 to 3, the symbol B1 represents the boundary between the outer peripheral region OA and the inner region IA. As shown in Figures 1 and 2, the outer peripheral region OA, located outside the boundary B1, surrounds the inner region IA, located inside the boundary B1.

[0017] As shown in Figure 3, the semiconductor layer 2 includes, for example, an n-base region 21, a buffer region 22, a p-base region 23, an emitter region 24, a collector region 25, a low-concentration region 26, a low-concentration region 27, and a guard ring region 28. Details of these regions will be described later.

[0018] The semiconductor layer 2 may be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate with an epitaxial layer disposed thereon. In this embodiment, the semiconductor layer 2 is silicon (Si). In this case, for example, arsenic (As), phosphorus (P), or antimony (Sb) can be used as the n-type impurity, and for example, boron (B) can be used as the p-type impurity.

[0019] The collector electrode 11 functions as the collector electrode of the IGBT. The collector electrode 11 is provided on the lower surface 2a of the semiconductor layer 2 and is in contact with the collector region 25, the low-concentration region 26, and the low-concentration region 27. The collector electrode 11 is an example of the first electrode in the claims. The collector electrode 11 is made of a material that includes at least one of the following: aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), etc.

[0020] The emitter electrode 12 functions as the emitter electrode of the IGBT. The emitter electrode 12 is provided on the upper surface 2b of the semiconductor layer 2 and is in contact with the p-base region 23, the emitter region 24, and the guard region. The emitter electrode 12 is an example of the second electrode in the claims. The emitter electrode 12 is made of a material that includes at least one of the following: aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), etc.

[0021] The gate electrode 13 functions as the gate electrode of the IGBT. The gate electrode 13 faces the p-base region 23 via an insulating region 30. In this embodiment, the gate electrode 13 is located within the p-base region 23 via the insulating region 30 and is electrically insulated from the emitter electrode 12 and the semiconductor layer 2 by the insulating region 30. The gate electrode 13 is an example of the third electrode in the claims. The gate electrode 13 is made of, for example, polysilicon containing p-type or n-type impurities. When a voltage is applied to the gate electrode 13, a channel is formed in the p-base region 23, and carriers flow between the n-base region 21 and the emitter region 24. This turns the IGBT ON.

[0022] The insulating region 30 is provided so as to cover the upper surface of the gate electrode 13 and the side walls of the multiple trenches provided on the upper surface 2b of the semiconductor layer 2. The insulating region 30 is an insulating film containing, for example, silicon oxide or silicon nitride.

[0023] Next, we will describe the details of each region provided within semiconductor layer 2.

[0024] As shown in Figure 3, the n-base region 21 functions as the n-base region (drift region) of the IGBT. As shown in Figure 3, the n-base region 21 is located above the buffer region 22 (above the collector electrode 11). The n-base region 21 is, for example, n - This is a semiconductor region of a certain type. The n-type impurity concentration in the n-base region 21 is, for example, 1 × 10⁻⁶. 12 cm -3 The above 1 x 10 15 cm -3 The following applies:

[0025] The buffer region 22 functions as a buffer region of the IGBT. The buffer region 22 is located between the n-base region 21 and the collector region 25. The buffer region 22 is, for example, an n-type semiconductor region. That is, the n-type impurity concentration in the buffer region 22 is higher than the n-type impurity concentration in the n-base region 21. The n-type impurity concentration in the buffer region 22 is, for example, 1 × 10⁻⁶ 15 cm -3 The above 1 x 10 17 cm -3 The following applies:

[0026] An example of the first semiconductor region in the claims is formed by the n-base region 21 and the buffer region 22. Note that the buffer region 22 is not required. In this case, for example, the n-base region 21 may also be provided in the position of the buffer region 22. Alternatively, the n-base region 21 is not required. In this case, for example, the buffer region 22 may also be provided in the position of the n-base region 21.

[0027] The p-base region 23 functions as the p-base region of the IGBT. The p-base region 23 is located above the n-base region 21. The p-base region 23 is an example of the second semiconductor region in the claims. The p-base region 23 is, for example, a p-type semiconductor region. The p-type impurity concentration of the p-base region 23 is, for example, 1 × 10⁻⁶ 17 cm -3 The above 1 x 10 19 cm -3 The following applies. As shown in Figure 1, the p-base region 23 extends in the Y-axis direction. In the example shown in Figure 3, the p-base region 23 has a first portion located below the emitter region 24 and a second portion extending from the first portion toward the upper surface 2b of the semiconductor layer 2 and penetrating the emitter region 24. The second portion is in contact with the emitter electrode 12 and is electrically connected to the emitter electrode 12. The p-type impurity concentration in the second portion may be higher than that in the first portion.

[0028] The emitter region 24 functions as the emitter region of the IGBT. The emitter region 24 is located above the p-base region 23. The emitter region 24 is in contact with the emitter electrode 12 and is electrically connected to the emitter electrode 12. The emitter region 24 is an example of the third semiconductor region in the claims. As shown in Figure 1, the emitter region 24 extends in the Y-axis direction. The emitter region 24 is, for example, n + This is a semiconductor region of a certain type. The n-type impurity concentration in the emitter region 24 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0029] The collector region 25 functions as the collector region of the IGBT. As shown in Figure 3, the collector region 25 is located between the collector electrode 11 and the n-base region 21, more specifically between the collector electrode 11 and the buffer region 22. The collector region 25 is in contact with the collector electrode 11 and is electrically connected to the collector electrode 11. The collector region 25 is an example of the fourth semiconductor region in the claims. The collector region 25 is, for example, a p-type semiconductor region. The p-type impurity concentration in the collector region 25 is, for example, 5 × 10⁻¹⁶. 17 cm -3 It is to that extent.

[0030] The low-concentration region 26 is provided within the semiconductor layer 2 so as to be surrounded by the collector region 25. That is, the collector region 25 is provided on both sides of the low-concentration region 26 along the X-axis direction, and the collector region 25 is provided on both sides of the low-concentration region 26 along the Y-axis direction. Furthermore, the low-concentration region 26 is separated from the low-concentration region 27 by the collector region 25. The low-concentration region 26 is in contact with the collector electrode 11 and is electrically connected to the collector electrode 11. The low-concentration region 26 is an example of the fifth semiconductor region in the claims. The low-concentration region 26 is, for example, p - This is a semiconductor region of a certain shape. That is, the p-type impurity concentration in the low-concentration region 26 is lower than the p-type impurity concentration in the collector region 25. The p-type impurity concentration in the low-concentration region 26 is, for example, 1 × 10⁻⁶ 16 cm -3 The above 5 x 10 17 cm -3 It is less than.

[0031] As shown in Figures 1 and 2, in this embodiment, the low-concentration region 26 is located at the center of the inner region IA, i.e., at the center of the collector region 25.

[0032] The low-density region 26 may be located at a location other than the center of the inner region IA. Figure 4 is a bottom view of a semiconductor device 1A according to a modified example of the first embodiment. In Figure 4, the reference numeral B2 indicates a position that is one-quarter of the width d of the inner region IA from the boundary B1 between the outer region OA and the inner region IA. In the example in Figure 4, the low-density region 26 is not located at the center of the inner region IA. However, the low-density region 26 is located in the region inside the boundary B2 (hereinafter also referred to as the "cell center") and is not provided in the region between the boundary B1 and the boundary B2 (hereinafter also referred to as the "cell edge"). In other words, the low-density region 26 is located at a distance of one-quarter or more of the width d of the inner region IA from the boundary B1. More specifically, the low-density region 26 is located at a distance of one-quarter or more of the length in the X-axis direction of the inner region IA from the boundary B1, and at a distance of one-quarter or more of the length in the Y-axis direction of the inner region IA from the boundary B1.

[0033] Furthermore, in the example shown in Figure 4, the planar shape of the inner region IA was square. However, it is not limited to this, and the planar shape of the inner region IA may also be rectangular. In this case as well, the low-density region 26 is provided so as to be at least one-quarter of the length of the inner region IA in the X-axis direction from the boundary B1, and at least one-quarter of the length of the inner region IA in the Y-axis direction from the boundary B1.

[0034] In the examples in Figures 2 and 4, the width of the low-density region 26 is at least 1 / 60th of the width of the semiconductor layer 2. More specifically, the length of the low-density region 26 in the X-axis and Y-axis directions is at least 1 / 60th of the larger of the X-axis and Y-axis lengths of the semiconductor layer 2.

[0035] Furthermore, in the examples in Figures 2 and 4, the planar shape of the low-concentration region 26 is circular. However, the planar shape of the low-concentration region 26 is arbitrary and may be rectangular, polygonal, or other shapes.

[0036] The low-concentration region 27 is provided within the outer peripheral region OA of the semiconductor layer 2. As shown in Figure 2, the low-concentration region 27 is provided so as to surround the collector region 25. As shown in Figure 3, the low-concentration region 27 is in contact with the collector electrode 11 and is electrically connected to the collector electrode 11. The low-concentration region 27 is an example of the sixth semiconductor region in the claims. The low-concentration region 27 is, for example, p - This is a semiconductor region of a certain shape. That is, the p-type impurity concentration in the low-concentration region 27 is lower than the p-type impurity concentration in the collector region 25. The p-type impurity concentration in the low-concentration region 27 is, for example, 1 × 10⁻⁶. 17 cm -3 It is to that extent.

[0037] Because a collector region 25, a low-concentration region 26, and a low-concentration region 27 are provided, the p-type impurity concentration along the X-axis and Y-axis increases from the low-concentration region 26 to the collector region 25, and then decreases from the collector region 25 to the low-concentration region 27.

[0038] In this embodiment, the p-type impurity concentration in the low-concentration region 27 is equal to the p-type impurity concentration in the low-concentration region 26. However, the p-type impurity concentration in the low-concentration region 27 may be lower than the p-type impurity concentration in the low-concentration region 26.

[0039] Note that the p-type impurity concentrations in the collector region 25, low-concentration region 26, and low-concentration region 27 described above are just examples, and may vary by about one to two orders of magnitude in other embodiments.

[0040] In this embodiment, as shown in Figures 1 and 3, a guard ring region 28 is provided. The guard ring region 28 is provided within the outer peripheral region OA of the semiconductor layer 2. The guard ring region 28 is in contact with the emitter electrode 12 and is electrically connected to the emitter electrode 12. Also, as shown in Figure 1, the guard ring region 28 is in contact with the end of the p-base region 23 in the Y-axis direction. The guard ring region 28 is, for example, a p-type semiconductor region. The p-type impurity concentration in the guard ring region 28 is, for example, 1 × 10⁻⁶. 17 cm -3 The above 1 x 1019 cm -3 The following is true: By providing a guard ring region 28, it is possible to improve the withstand voltage of the semiconductor device 1.

[0041] In the example shown in Figure 3, both the low-concentration region 27 and the guard ring region 28 are located within the outer region OA. On the other hand, neither the low-concentration region 27 nor the guard ring region 28 are located within the inner region IA. In other words, the inner ends of the low-concentration region 27 and the guard ring region 28 coincide and are both located on boundary B1. However, the inner ends of the low-concentration region 27 and the guard ring region 28 do not necessarily have to coincide. That is, the inner end of the low-concentration region 27 may be located inside or outside the inner end of the guard ring region 28.

[0042] Although not shown in the figures, the semiconductor device 1 may further include a field plate electrode (FP electrode) provided within the semiconductor layer 2 via an insulating region. The FP electrode is electrically insulated from the semiconductor layer 2 by the insulating region and is electrically connected to the emitter electrode 12. By providing such an FP electrode, when the IGBT is in the off state, a depletion layer extends from the FP electrode to the surrounding n-base region 21 due to the voltage applied between the collector electrode 11 and the emitter electrode 12. This depletion layer connects with the depletion layer of the adjacent FP electrode, making it possible to improve the breakdown voltage of the semiconductor device 1.

[0043] Furthermore, the configuration of the semiconductor device 1 shown in Figures 1 to 3 is just one example, and this embodiment is not limited thereto. For example, in the examples in Figures 1 and 3, the low-density region 26 is provided below the gate electrode 13. However, it is not limited to this, and the low-density region 26 may be provided in a location other than below the gate electrode 13. In other words, the positional relationship between the low-density region 26 and the gate electrode 13 is arbitrary. Also, the number of gate electrode 13s extending in the Y-axis direction, i.e., the number of insulating regions 30, may be more or less than in the example in Figure 1. In addition, a gate pad may be provided on the upper surface 2b of the semiconductor layer 2.

[0044] As described above, the semiconductor device 1 according to the first embodiment comprises a semiconductor layer 2, a collector electrode 11, an emitter electrode 12, an n-base region 21 and a buffer region 22 of a first conductivity type, a p-base region 23 of a second conductivity type, a gate electrode 13, an emitter region 24 of a first conductivity type, a collector region 25 of a second conductivity type, and a low-concentration region 26 of a second conductivity type. The semiconductor layer 2 comprises a lower surface 2a and an upper surface 2b. The collector electrode 11 is provided on the lower surface 2a of the semiconductor layer 2. The emitter electrode 12 is provided on the upper surface 2b of the semiconductor layer 2. The n-base region 21 and the buffer region 22 are provided within the semiconductor layer 2. The p-base region 23 is provided within the semiconductor layer 2 and is located above the n-base region 21. The gate electrode 13 faces the p-base region 23 via an insulating region 30. The emitter region 24 is provided within the semiconductor layer 2 and is located above the p-base region 23 and is electrically connected to the emitter electrode 12. The collector region 25 is provided within the semiconductor layer 2, located between the collector electrode 11 and the buffer region 22, and is electrically connected to the collector electrode 11. The low-concentration region 26 is provided within the semiconductor layer 2 so as to be surrounded by the collector region 25, and is electrically connected to the collector electrode 11. The low-concentration region 26 has a lower p-type impurity concentration than the collector region 25.

[0045] In this embodiment, the low-density region 26 is arranged so as to be surrounded by the collector region 25. This suppresses the amount of holes injected from the collector region 25 to the n-base region 21, thereby reducing the switching loss of the semiconductor device 1. Here, switching loss refers to the power loss that occurs when the semiconductor device 1 is turned on or off. According to this embodiment, because the low-density region 26 is surrounded by the collector region 25, the amount of holes injected is suppressed more effectively than when it is arranged around the collector region 25. Therefore, according to this embodiment, the switching of the semiconductor device 1 can be increased in speed.

[0046] Furthermore, the semiconductor device 1 according to this embodiment further includes a low-concentration region 27 of a second conductivity type, which is provided within the outer peripheral region OA of the semiconductor layer 2, is electrically connected to the collector electrode 11, and has a lower p-type impurity concentration than the collector region 25. This makes it possible to improve the avalanche withstand capability of the semiconductor device 1.

[0047] Furthermore, in this embodiment, the p-type impurity concentration in the low-concentration region 27 is equal to the p-type impurity concentration in the low-concentration region 26. This allows the low-concentration region 26 and the low-concentration region 27 to be formed simultaneously, as will be described later. Note that the p-type impurity concentration in the low-concentration region 27 may be lower than the p-type impurity concentration in the low-concentration region 26. This further improves the avalanche tolerance of the semiconductor device 1.

[0048] Furthermore, in this embodiment, the low-concentration region 26 is located at the center of the inner region IA on the lower surface 2a of the semiconductor layer 2. This reduces switching losses at the center of the inner region IA where the current density is high, and enables efficient and high-speed switching of the semiconductor device 1.

[0049] Furthermore, the low-concentration region 26 is located at a distance of at least one-quarter of the width d of the inner region IA from the boundary B1 between the outer region OA and the inner region IA. This improves the short-circuit withstand capability of the semiconductor device 1. This effect will be explained in detail below with reference to Figure 5. Figure 5 is a graph showing the evaluation results of the short-circuit withstand capability of the semiconductor device according to the first embodiment and comparative example.

[0050] The horizontal axis in Figure 5 represents the diameter and location of the low-density region 26 in each semiconductor device used for evaluating short-circuit withstand capability. "None" indicates that no low-density region 26 is provided. "Small," "Medium," and "Large" indicate that the diameter of the low-density region 26 is 1 / 300, 1 / 100, and 1 / 60 of the width of the semiconductor layer 2, respectively. "Cell Center" indicates that the low-density region 26 is located in the area inside boundary B2 in Figure 4 (cell center), that is, the low-density region 26 is at least one-quarter of the width d of the inner region IA from boundary B1 between the outer region OA and the inner region IA. "Cell Edge" indicates that the low-density region 26 is located in the area between boundary B1 and boundary B2 (cell edge), that is, the low-density region 26 is not at least one-quarter of the width d of the inner region IA from boundary B1. The semiconductor device 1 according to the first embodiment and the semiconductor device 1A according to a modified example of the first embodiment both correspond to the "Cell Center" and "Large" cases in Figure 5. The vertical axis in Figure 5 represents the gate-emitter voltage applied to each semiconductor device. The cross marks (×) in the graph represent the gate-emitter voltage at which the semiconductor device failed, and the circles (○) represent the gate-emitter voltage at which the semiconductor device did not fail.

[0051] As shown in Figure 5, when the low-concentration region 26 is located in the "center of the cell," the short-circuit withstand capability of the semiconductor device is higher than when it is located at the "end of the cell," regardless of the size of the low-concentration region 26. More specifically, when the low-concentration region is in the "center of the cell" and "small," the short-circuit withstand capability is higher than when it is at the "end of the cell" and "small." When the low-concentration region is in the "center of the cell" and "medium," the short-circuit withstand capability is higher than when it is at the "end of the cell" and "medium." When the low-concentration region is in the "center of the cell" and "large," the short-circuit withstand capability is higher than when it is at the "end of the cell" and "large." Therefore, by having the low-concentration region 26 located at least one-quarter of the width d of the inner region IA from the boundary B1 between the outer region OA and the inner region IA, the short-circuit withstand capability of the semiconductor device 1 can be improved.

[0052] As shown in Figure 5, when the low-concentration region 26 is located in the center of the cell and is large, the short-circuit withstand capability of the semiconductor device appears to be lower compared to when it is located in the center of the cell and is small, or in the center of the cell and is medium. However, although not shown in the figure, the failure mode of the semiconductor device changes when the low-concentration region 26 is located in the center of the cell and is large. More specifically, when the low-concentration region 26 is located in the center of the cell and is small, or in the center of the cell and is medium, the failure mode of the semiconductor device was failure at shutdown. On the other hand, when the low-concentration region 26 is located in the center of the cell and is large, the failure mode of the semiconductor device was BT (Bias Temperature) failure, which is thermal failure after being turned off. Therefore, when the low-concentration region 26 is located in the center of the cell, the short-circuit withstand capability of the semiconductor device 1 can be further improved by ensuring that the width of the low-concentration region 26 is 1 / 60th or more of the width of the semiconductor layer 2.

[0053] <Method for manufacturing semiconductor device 1> Next, an example of a method for manufacturing the semiconductor device 1 according to this embodiment will be described with reference to Figures 6A to 6F. Figures 6A to 6F are cross-sectional views illustrating an example of the manufacturing process for the semiconductor device 1 according to the first embodiment. Note that in Figures 6A to 6F, the portion of the p-base region 23 that penetrates the emitter region 24 (second portion) is omitted.

[0054] First, as shown in Figure 6A, a semiconductor layer 2 is prepared, which has a lower surface 2a and an upper surface 2b opposite to the lower surface 2a. The semiconductor layer 2 includes a gate electrode 13, an n-base region 21, a p-base region 23, an emitter region 24, a guard ring region 28, and an insulating region 30.

[0055] Next, as shown in Figure 6B, a buffer region 22 is formed below the n-base region 21 by ion implanting n-type impurities into the lower surface 2a of the semiconductor layer 2. The n-type impurities used at this time are, for example, at least one of phosphorus (P) and arsenic (As). The concentration of n-type impurities in the buffer region 22 is higher than the concentration of n-type impurities in the n-base region 21.

[0056] Next, as shown in Figure 6C, a p-type impurity is ion-implanted into the lower surface 2a of the semiconductor layer 2 to form a p-region 250. The p-type impurity used at this time is, for example, boron (B). The p-region 250 is, for example, p - This is a semiconductor region in shape.

[0057] Next, as shown in Figure 6D, resists 41 and 42 are formed on a portion of the lower surface 2a of the semiconductor layer 2. More specifically, resist 41 is formed on a portion of the lower surface 2a of the semiconductor layer 2 in the inner region IA, and resist 42 is formed on the lower surface 2a of the semiconductor layer 2 in the outer region OA.

[0058] Next, as shown in Figure 6E, a collector region 25 is formed by ion implanting p-type impurities into the lower surface 2a of the semiconductor layer 2. The p-type impurities used at this time are, for example, boron (B). The concentration of p-type impurities in the collector region 25 is higher than the concentration of p-type impurities in the p-region 250. Furthermore, as a result of this process, the portion of the p-region 250 covered with resist 41 becomes a low-concentration region 26, and the portion covered with resist 42 becomes a low-concentration region 27.

[0059] Next, as shown in Figure 6F, resists 41 and 42 are removed.

[0060] Subsequently, although not shown in the diagram, a collector electrode 11 and an emitter electrode 12 are formed on the lower surface 2a and upper surface 2b of the semiconductor layer 2, respectively.

[0061] The semiconductor device 1 is manufactured through the above process.

[0062] According to the manufacturing method of the semiconductor device 1 of this embodiment, the low-concentration region 26 and the low-concentration region 27 can be formed at the same time. In this case, the p-type impurity concentration in the low-concentration region 27 is equal to the p-type impurity concentration in the low-concentration region 26.

[0063] Alternatively, for example, the p-region 250 may be formed with a lower p-type impurity concentration, and after forming the collector region 25, the resist 41 may be removed while the resist 42 remains, and then p-type impurities may be ion-implanted again into the lower surface 2a of the semiconductor layer 2. This allows the p-type impurity concentration in the low-concentration region 27 to be lower while maintaining the p-type impurity concentration in the low-concentration region 26. In this case, the p-type impurity concentration in the low-concentration region 27 will be lower than the p-type impurity concentration in the low-concentration region 26.

[0064] (Second Embodiment) Referring to Figure 7, the semiconductor device 1B according to the first embodiment will be described. Figure 7 is a bottom view of the semiconductor device 1B according to the second embodiment. One of the differences between this embodiment and the first embodiment is the number of low-density regions 26. Hereinafter, this embodiment will be described focusing on the differences from the first embodiment.

[0065] As shown in Figure 7, the semiconductor device 1B according to this embodiment includes a plurality of low-density regions 26. Specifically, in the example in Figure 7, the semiconductor device 1B includes five low-density regions 26. The number of low-density regions 26 may be four or fewer, or six or more.

[0066] Each low-concentration region 26 is provided within the semiconductor layer 2 so as to be surrounded by the collector region 25 and is spaced apart from each other. Each low-concentration region 26 is in contact with the collector electrode 11 and is electrically connected to the collector electrode 11.

[0067] The p-type impurity concentration in each low-concentration region 26 is lower than the p-type impurity concentration in the collector region 25. Note that the p-type impurity concentrations in each low-concentration region 26 may all be equal, or the p-type impurity concentration in at least one low-concentration region 26 may differ from the p-type impurity concentrations in the other low-concentration regions 26.

[0068] In the example shown in Figure 7, each low-concentration region 26 is located inside the boundary B2 (in the center of the cell). Additionally, one of the multiple low-concentration regions 26 is located at the center of the lower surface 2a of the semiconductor layer 2.

[0069] Furthermore, in the example shown in Figure 7, the multiple low-density regions 26 are arranged symmetrically on the lower surface 2a of the semiconductor layer 2. More specifically, the multiple low-density regions 26 are arranged symmetrically with respect to a line passing through the center of the lower surface 2a of the semiconductor layer 2 and parallel to the X-axis, and also symmetrically with respect to a line passing through the same center and parallel to the Y-axis. This allows for efficient and high-speed switching of the semiconductor device 1B. Alternatively, the multiple low-density regions 26 may be arranged symmetrically with respect to at least one line passing through the center of the lower surface 2a of the semiconductor layer 2 and parallel to the XY plane. Or, the multiple low-density regions 26 may be arranged point-symmetrically with respect to the center of the lower surface 2a of the semiconductor layer 2.

[0070] According to this embodiment, the provision of multiple low-concentration regions 26 makes it possible to speed up the switching of the semiconductor device 1B.

[0071] Furthermore, the multiple low-density regions 26 may be arranged such that their density increases as they approach the center of the lower surface 2a of the semiconductor layer 2. Figure 8 is a bottom view of a semiconductor device 1C according to a modified example of the second embodiment.

[0072] In the example shown in Figure 8, among the multiple low-density regions 26, those located near the center of the lower surface 2a of the semiconductor layer 2 are closer to other low-density regions 26 than those located near the boundary B2. Therefore, in the semiconductor device 1C, the density of low-density regions 26 is higher near the center of the lower surface 2a of the semiconductor layer 2 than near the boundary B2. In other words, in the example shown in Figure 8, the multiple low-density regions 26 are arranged such that their density increases as they approach the center of the lower surface 2a of the semiconductor layer 2. This allows for efficient and high-speed switching of the semiconductor device 1C.

[0073] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0074] 1 Semiconductor device 2 Semiconductor layers 11 Collector electrode 12 Emitter electrode 13 gates 21 n base region 22 Buffer area 23 p base region 24. Emitter region 25 Collector area 26,27 Low concentration area 28 Guard Ring Area 30 Insulation Area B1,B2 boundary IA inner area OA outer area

Claims

1. A semiconductor layer comprising a first main surface and a second main surface, The first electrode provided on the first main surface, The second electrode provided on the second main surface, A first semiconductor region of a first conductivity type provided within the semiconductor layer, A second semiconductor region of a second conductivity type is provided within the semiconductor layer and located above the first semiconductor region, A third electrode facing the second semiconductor region through an insulating region, A third semiconductor region of a first conductivity type is provided within the semiconductor layer, located on the second semiconductor region, and electrically connected to the second electrode, A fourth semiconductor region of a second conductivity type is provided within the semiconductor layer, located between the first electrode and the first semiconductor region, and electrically connected to the first electrode. Within the semiconductor layer, a fifth semiconductor region is provided so as to be surrounded by the fourth semiconductor region, is electrically connected to the first electrode, and has a second conductivity type with a lower impurity concentration than the fourth semiconductor region, A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, further comprising a sixth semiconductor region having a second conductivity type having a lower impurity concentration than the fourth semiconductor region, provided in an outer peripheral region extending from the side of the semiconductor layer to the inside of the semiconductor layer, electrically connected to the first electrode.

3. The semiconductor device according to claim 2, wherein the impurity concentration of the sixth semiconductor region is equal to the impurity concentration of the fifth semiconductor region.

4. The semiconductor device according to claim 2, wherein the impurity concentration in the sixth semiconductor region is lower than the impurity concentration in the fifth semiconductor region.

5. The semiconductor device according to claim 1, wherein the semiconductor device comprises a plurality of fifth semiconductor regions.

6. The semiconductor device according to claim 5, wherein the plurality of fifth semiconductor regions are arranged symmetrically on the first main surface of the semiconductor layer.

7. The semiconductor device according to claim 5, wherein the plurality of fifth semiconductor regions are arranged such that their density increases as they approach the center of the first main surface of the semiconductor layer.

8. The semiconductor layer comprises an outer peripheral region extending from the side of the semiconductor layer to the inside of the semiconductor layer, and an inner region located inside the outer peripheral region. The semiconductor device according to any one of claims 1 to 7, wherein the fifth semiconductor region is located at a distance of one-quarter or more of the width of the inner region from the boundary between the outer peripheral region and the inner region.

9. The semiconductor device according to claim 8, wherein the fifth semiconductor region is located at the center of the inner region on the first main surface of the semiconductor layer.

10. The semiconductor device according to claim 8, wherein the width of the fifth semiconductor region is 1 / 60th or more of the width of the semiconductor layer.

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