Semiconductor equipment

Abstract

To provide a semiconductor device with low on-resistance and highly efficient power control. [Solution] The semiconductor device 100 includes a first electrode 10, a second electrode 20, a first semiconductor region 31 of a first conductivity type provided between the first electrode and the second electrode, a third electrode 22 extending along a first direction Z toward the second electrode and provided on the upper part of the first semiconductor region, a fourth electrode 40 provided facing the third electrode in a second direction X perpendicular to the first direction, a second semiconductor region 32 of a second conductivity type provided between the third electrode and the fourth electrode and in contact with the third electrode in at least a second direction, an insulating layer 50 including a first insulating region in contact with the fourth electrode and facing the third electrode in a second direction, and a third semiconductor region 33 of a first conductivity type provided between the second electrode and the second semiconductor region and having a higher impurity concentration than the first semiconductor region.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] Metal-oxide-semiconductor field-effect transistor MOSFET (Field Effect Transistor) and isolation Insulated Gate Bipolar Transistor Semiconductor devices such as IGBTs control high voltages and large currents. They are known as semiconductor devices. These power semiconductor devices increase on-resistance. Highly efficient power control is required. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-93891 [Patent Document 2] Japanese Patent Publication No. 2022-47934 [Patent Document 3] Patent No. 7010095 specification [Overview of the project] [Problems that the invention aims to solve]

[0004] The semiconductor device of this embodiment provides a semiconductor device with low on-resistance and capable of highly efficient power control. do. [Means for solving the problem]

[0005] The semiconductor device of the embodiment comprises a first electrode, a second electrode, and a first electrode A first semiconductor region of a first conductivity type provided between the pole and the second electrode, and from the first electrode to the second It has a third electrode provided above the first semiconductor region and extending along a first direction toward the electrode. Further, it has a fourth electrode provided opposite to the third electrode in a second direction orthogonal to the first direction. The semiconductor device has a second semiconductor region of a second conductivity type provided between the third electrode and the fourth electrode and contacting at least the third electrode in the second direction. Furthermore, it has an insulating layer including a first insulating region that contacts the fourth electrode and is provided opposite to the third electrode in the second direction. A semiconductor device in which a third semiconductor region of a first conductivity type having a higher impurity concentration than the first semiconductor region is provided between the second electrode and the second semiconductor region. 。 。

Brief Description of Drawings

[0006] [Figure 1] It is a schematic cross-sectional view showing a semiconductor device 100 according to a first embodiment. [Figure 2] It is a cross-sectional view showing a broken line A portion in FIG. 1. [Figure 3] It is a schematic cross-sectional view showing a semiconductor device 900 according to a comparative example. [Figure 4] It is a partial cross-sectional view of a semiconductor device 200 according to a first modification. [Figure 5] It is a partial cross-sectional view of a semiconductor device 300 according to a second modification. [Figure 6] It is a partial cross-sectional view of a semiconductor device 400 according to a third modification. [Figure 7] It is a partial cross-sectional view of a semiconductor device 500 according to a fourth modification. [Figure 8] It is a partial cross-sectional view of a semiconductor device 600 according to a fifth modification. [Figure 9] It is a partial cross-sectional view of a semiconductor device 700 according to a sixth modification. [Figure 10] It is a partial cross-sectional view of a semiconductor device 800 according to a seventh modification. [Figure 11] This is a schematic cross-sectional view of the first manufacturing process, which represents a part of the manufacturing process for the third electrode 22. [Figure 12] This is a schematic cross-sectional view of the second manufacturing process, which represents a part of the manufacturing process for the third electrode 22. [Figure 13] This is a schematic cross-sectional view of the third manufacturing process, which represents a part of the manufacturing process for the third electrode 22. [Figure 14] This is a schematic cross-sectional view of the fourth manufacturing process, which represents part of the manufacturing process for the third electrode 22. [Modes for carrying out the invention]

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Common parts are denoted by common reference numerals in the figures. Note that this embodiment does not limit the present invention. The dimensional ratios in the drawings are not limited to those shown. See below for further explanation. Now, we will explain by defining the first conductivity type as n-type and the second conductivity type as p-type, but this is not the only way to explain it. No. The first conductivity type can be p-type, and the second conductivity type can be n-type.

[0008] [First Embodiment] (Configuration of semiconductor device 100) The configuration of the semiconductor device 100 according to the first embodiment will be explained with reference to Figures 1 and 2. Here, Figure 2 shows the dashed line A enclosed by the dashed line in Figure 1. The semiconductor device 100 shown in Figure 1 For example, MOSFET (Metal Oxide Silicon Field Efficiency) (ect Transistor). As shown in Figure 1, the semiconductor device 100 is a first Electrode 10, second electrode 20, semiconductor part 30, third electrode 22, fourth electrode 40, insulating layer It comprises 50 and an interlayer insulating layer 46. In this embodiment, it further comprises a fifth electrode 41. This explanation will be based on this configuration, but it is not limited to this.

[0009] The direction from the first electrode 10 to the second electrode 20 is defined as the first direction, and is called the Z direction. The direction perpendicular to the X direction is designated as the second direction. The direction perpendicular to the Z direction and the X direction is The third direction will be the Y direction. Also, for the sake of explanation, the first direction will be referred to as upward (+Z direction), and the first direction The direction opposite to the direction of travel is defined as downwards (-Z direction).

[0010] The direction from the first electrode 10 to the semiconductor part 30 is along the Z direction. The semiconductor part 30 is the first semiconductor Body region 31, second semiconductor region 32, third semiconductor region 33, fourth semiconductor region 34, This includes the semiconductor region 30, which comprises a first semiconductor region 31, a third semiconductor region 33, and a fourth semiconductor region. Region 34 is the first conductivity type (e.g., n-type). The second semiconductor region 32 is the second conductivity type (e.g., It is in the p form.

[0011] The first semiconductor region 31 is provided between the first electrode 10 and the second electrode 20. The direction from region 31 to the second electrode 20 is along the Z direction. The third electrode 22 is in the first semiconductor region 3 It is located at the top of 1 and extends in the Z direction. The second semiconductor region 32 is located in the first semiconductor region 31 It is located on the upper part and is in contact with the third electrode 22 in the X direction. The third semiconductor region 33 is the second It is provided between electrode 20 and the first semiconductor region 31, and is in contact with the third electrode 22 in the X direction. The fourth semiconductor region 34 is provided between the first electrode 10 and the first semiconductor region 31, and the XY plane It is in contact with the first semiconductor region 31 on the surface.

[0012] Furthermore, the third semiconductor region 33 contains more n-type impurities than the first semiconductor region 31. Furthermore, the fourth semiconductor region 34 contains more n-type impurities than the first semiconductor region 31. The impurity concentration of the first conductivity type in the semiconductor region 31 is, for example, 1 × 10⁻⁶ 15 ate / c m 3 The above 2 x 10 17 atoms / cm 3 In the following cases, the third semiconductor region 33 and the fourth semiconductor region The impurity concentration of the first conductive type in body region 34 is, for example, 1 × 10⁻⁶. 17 atoms / cm 3 That's all. 1 x 10 21 atoms / cm 3 The following applies. Note that the fourth semiconductor region 34 is connected to the first electrode 10. This configuration is provided to reduce the electrical resistance between the second electrodes 20, but it is not necessarily essential.

[0013] Furthermore, a trench U is provided extending in the -Z direction from the upper surface 30a of the semiconductor portion 30. The trench U extends continuously, for example, in the Y direction. The trench U is spaced apart in the X direction. A number of these may be provided.

[0014] The insulating layer 50 is provided in the trench U. The fourth electrode 40 and the fifth electrode 41 are located in the trench Within the U, it is surrounded by an insulating layer 50. The insulating layer 50 is surrounded by the fourth electrode 40 and the fifth electrode 4 1, and the first semiconductor region 31 are in contact. The insulating layer 50 is in contact with the fourth electrode 40 and the first semiconductor region 3 Between 1, between the fifth electrode 41 and the first semiconductor region 31, between the fourth electrode 40 and the fifth electrode 41 The interlayer insulating layer 46 provides electrical insulation between the fourth electrode 40 and the second electrode 20. , to electrically insulate.

[0015] Between the multiple arbitrary trenches U provided in the X direction, from the upper surface 30a of the semiconductor part 30 to -Z A trench T is provided in the direction.

[0016] The third electrode 22 is provided in the trench T. The third electrode 22 is electrically connected to the second electrode 20. It is a trench contact connected to the third electrode. Also, according to Figure 2, the third electrode 22 is the third electrode The wall surface 90 surrounding 22 and along the Z direction, and the first semiconductor region 31 facing and in contact with it in the X direction. It has a bottom surface 91 that follows the X direction and an upper surface 92 that is in contact with and opposite the second electrode 20. The three electrodes 22 have a corner portion 80 where the wall surface 90 and the bottom surface 91 intersect, and the corner portion 80 is The corners are acute, obtuse, or right angles, or they are chamfered. The corner section 80 is designed and manufactured. The shape is determined by the process. Furthermore, the bottom surface 91 is curved and continuously connects to the wall surface 90. If so, for example, the part where the curvature of the bottom surface 91 changes will be designated as the corner section 80. These walls Surface 90, bottom surface 91, and top surface 92 are included in the third electrode 22.

[0017] Furthermore, as shown in Figure 2, the insulating layer 50 is connected to the first semiconductor region 31 and the fourth electrode in the X direction. It includes a first insulating region 51 provided between 40 and the second semiconductor region 32. It is provided between the first semiconductor region 31 and the fourth electrode 40, and in the X direction, the first semiconductor region 31 and the third electrode 22 It is in contact with the opposite side. At this time, the second semiconductor region 32 is in the Z direction relative to the third semiconductor region 33 It is acceptable whether or not it is in contact with it. Between the second semiconductor region 32 and the first insulating region 51 Then, the first channel region r1 is formed. Regarding the first channel region r1, semiconductor device 1 This will be explained later when describing its operation.

[0018] The fourth electrode 40 and fifth electrode 41 shown in Figure 1 are, for example, made of polysilicon and metal at a minimum. It may include either of the following. The second electrode 20 may be, for example, Al, Cu, Mo, W, Ta, C It includes at least one selected from the group consisting of o, Ru, Ti, and Pt. First electrode 10 For example, the group consisting of Al, Cu, Mo, W, Ta, Co, Ru, Ti, Ni, and Pt. It includes at least one selected from. If the first conductivity type is n-type as in this embodiment, then The work function of the metal of the three electrodes 22 is such that it forms a Schottky junction with the first semiconductor region 31. It is best to select a genus. For example, a metal with a work function of 4.3 eV or higher, such as Ir , Pd, Au, Ti, Cr, Fe, Cu, Zr, Mo, Ru, Ag, Pt, Nd, Bi, It includes at least one selected from Ni, Co, etc. Furthermore, the third electrode 22 and the second half It is best to select a metal such that it forms an ohmic junction with the conductor region 32.

[0019] The fifth electrode 41 shown in Figure 1 is electrically connected to the second electrode 20 by an electrode (wiring, etc.) not shown. It may be connected to the target. The fifth electrode 41 functions, for example, as a field plate, and in this field In addition, when the MOSFET is in the off-operation state, the depletion layer expands in the first semiconductor region 31, maintaining the breakdown voltage. It can be made to happen.

[0020] (Operation of semiconductor device 100) The operation of the semiconductor device 100 will be described. The semiconductor device 100 is, for example, a MOSFET. In this case, by controlling the potential of the fourth electrode 40, between the first electrode 10 and the second electrode 20 The current flow can be controlled. The first electrode 10 functions, for example, as a drain electrode. The second electrode 20 functions, for example, as a source electrode. The third electrode 22 is the second electrode. It is at the same potential as 20 and is the source electrode. The third semiconductor region 33 is, for example, the source region. In Figure 2, the first channel region r1, shown by the dashed line, is connected to the second semiconductor region 32. It includes a depletion layer formed by a pn junction between the first semiconductor region 31, and for example, as a channel region The fourth electrode 40 functions, for example, as a gate electrode. The first insulating region 51 is, for example It functions as a gate insulating film. Also, the interface where the third electrode 22 and the first semiconductor region 31 meet. Therefore, a depletion layer is formed by Schottky junctions.

[0021] The first channel region r1 is, for example, in the X direction, the second semiconductor region 32 and the first insulating region It is in contact with 51. Also, the first channel region r1 is provided on the surface of the first semiconductor region 31. The third semiconductor region 33 is also in contact with the first channel region r1 in the Z direction. This is the region where the carrier density changes depending on the potential of the fourth electrode 40, and is indicated by the dashed line. Not limited to this.

[0022] A pn junction formed at the interface between the first channel region r1 and the second semiconductor region 32, as shown in Figure 2. The thickness of the depletion layer (distance in the X direction) is controlled by the potential of the fourth electrode 40. In other words, when the carrier density in the first channel region r1 is low due to the potential of the fourth electrode 40 Therefore, virtually no current flows between the third electrode 22 and the second electrode 20 and the first electrode 10. In other words, an off state is obtained. The potential of the fourth electrode 40 controls the capacitance of the first channel region r1. When the rear density is high, current flows between the third electrode 22 and the second electrode 20 and the first electrode 10. It can be activated. In other words, the ON state is obtained.

[0023] As described above, the semiconductor device 100 according to this embodiment is based on the first channel region r1 This is a semiconductor device in which a depletion layer is formed. The carrier density of the depletion layer is determined by the fourth electrode 40. It controls the process.

[0024] Here, Figure 3 shows a comparative example semiconductor device 900. The semiconductor device 900 has a second electrode 20 The second semiconductor region 32 of the second conductivity type, which is provided between the first electrode 10 and the first electrode 10, in the X direction It is in contact with both the third electrode 22 and the first insulating region 51. The second semiconductor region 32 is thick in the Z direction. So.

[0025] The semiconductor device 900 has a second semiconductor region 32 and a first semiconductor region 31 that are in contact in the Z direction. A depletion layer is formed across the interface. Electrical connection between the first electrode 10 and the second electrode 20 This is blocked by a second semiconductor region 32 that includes a depletion layer formed across the XY plane. When a voltage is applied to the fourth electrode 40, the second semiconductor region 32 and the insulating layer 50 come into contact in the X direction. Carriers gather at the interface, forming a channel and resulting in an ON state.

[0026] On the other hand, in the semiconductor device 100 according to this embodiment, the second semiconductor region 32 and the first semiconductor region A depletion layer is formed at the interface where region 31 is in contact in the X direction. In other words, semiconductor device 90 A second semiconductor region that is in contact with both the third electrode 22 and the first insulating region 51 in the X direction such as 0. Region 32 is not provided in the semiconductor device 100. As a result, the semiconductor device 100 is ON We can provide semiconductor devices that can reduce resistance.

[0027] (First variation) Figure 4 is a schematic diagram of a semiconductor device 200 according to a first modified example of the first embodiment. .

[0028] The semiconductor device 200 is such that the lowest point 32c of the second semiconductor region 32 of the semiconductor device 100 is the third electric This is an example where the lowest point 22c of pole 22 is located on the second electrode 20 side in the Z direction. The lowest point 22c is included in the base surface 91. An example of such a semiconductor device 200 is a semiconductor device. The on-resistance and reverse recovery charge amount Qrr can be lower than 100. The reduction in Qrr is due to... The recovery time during turn-off can be shortened. Note that in Figure 4, the lowest point 32c is Although described in planar form, it is not limited to this. Concentration considering the diffusion width of the second semiconductor region 32 From the degree distribution, the lowest point on the Z-axis can be determined.

[0029] (Second variation) Figure 5 is a schematic diagram of a semiconductor device 300 according to a second modified example of the first embodiment. .

[0030] The semiconductor device 300 has a third electrical component where the lowest point 32c of the second semiconductor region 32 of the semiconductor device 100 is the third electrical component. This is an example where the lowest point 22c of pole 22 is located on the first electrode 10 side in the Z direction. This increases the Z-direction length of the depletion layer formed in the first channel region r1. The Z-direction distance of the first channel region r1 increases, and the overall pressure resistance of the device increases. In other words, This can reduce leakage current between the source and drain.

[0031] (Third variation) Figure 6 is a schematic diagram of a semiconductor device 400 according to a third modified example of the first embodiment. .

[0032] The semiconductor device 400 has a second semiconductor region across the entire interface between the third electrode 22 and the first semiconductor region 31. A region 32 is formed. The second semiconductor region 32 is provided so as to surround the outer surface of the third electrode 22. The outer surface here is a continuous surface where the third electrode 22 is in contact with the second semiconductor region 32. This results in the formation of a depletion layer by the pn junction that covers the outer surface of the third electrode 22. Therefore, a depletion layer is formed on the bottom surface 91 of the third electrode 22, and the source and drain The Z-direction distance of the depletion layer blocking the gap becomes longer, which reduces leakage current.

[0033] (Fourth variation) Figure 7 is a schematic diagram of a semiconductor device 500 according to a fourth modified example of the first embodiment. .

[0034] The semiconductor device 500 has the shape of the semiconductor device 300, and further the bottom surface 9 of the third electrode 22 An insulating layer 53 is provided on 1. Similar to the semiconductor device 400, from the bottom surface 91 of the third electrode 22 This has the advantage of reducing leakage current.

[0035] (Fifth variation) Figure 8 is a schematic diagram of a semiconductor device 600 according to a fifth modified example of the first embodiment. .

[0036] The semiconductor device 600 has a second semiconductor region provided between the first insulating region 51 and the third electrode 22. 32 is in contact with both the first insulating region 51 and the third electrode 22 in the X direction. The semiconductor region 32 has a concentration gradient of the second conductivity type in the X direction, and the third electrode 22 The concentration of the second conductivity type decreases from the first insulating region 51 toward the first insulating region 51. For example, concentration distribution It follows the diffusion equation and has a slope similar to a Gaussian distribution.

[0037] In areas of the second semiconductor region 32 where the concentration of the second conductivity type is low, accumulation occurs when a gate voltage is applied. Layer formation becomes easier, and channel resistance can be reduced, while the gate voltage can be applied to 0V or less. In this case, the channel portion is blocked and can remain in the off state. Such a semiconductor device 60 0 is achieved when the second semiconductor region 32 covers up to the first channel region r1, across the XY plane. A second semiconductor region 32 is provided. This allows the semiconductor device 100 according to the first embodiment to Compared to this, the leakage current between the source and drain can be reduced. The concentration of the second conductivity type of 2 may be 0 in the portion in contact with the first insulating region 51.

[0038] (Sixth variation) Figure 9 is a schematic diagram of a semiconductor device 700 according to a sixth modified example of the first embodiment.

[0039] The semiconductor device 700 is configured such that the second semiconductor region 32 surrounds the corner portion 80 of the third electrode 22. It is provided in that. In other words, as shown in Figure 9, the third electrode 22 is at least a part of the second The semiconductor region 32 is in contact with the semiconductor region 32 in the X direction. Furthermore, the third electrode 22 is in contact with the first half It is in contact with both the conductor region 31 and the second semiconductor region 32 in the Z direction. The wall surface 90 of the third electrode 22 may be in contact with the first semiconductor region 31 in the X direction.

[0040] Such a semiconductor device 700 has a first channel between the third electrode 22 and the first insulating region 51. A region r1 is formed. The semiconductor device 700 surrounds the second semiconductor region 32 with the first semi Because a depletion layer spreads from the interface with the conductive region 31, the first insulating region 51 and the second semiconductor region 32 The first channel region r1 between the third electrode 22 and the first channel is blocked. As a result, the first channel is blocked from the third electrode 22. It can block the leakage current that escapes into region r1. Furthermore, it can block the leakage current that escapes from the third electrode 22 to the bottom surface 91. It can also interrupt leakage current. Furthermore, semiconductor device 700 is a semiconductor device 300-600 By not completely covering the wall surface 90 of the third electrode 22, it becomes possible to reduce the channel resistance. .

[0041] The semiconductor device 700 does not completely cover the bottom surface 91 of the third electrode 22 with the second semiconductor region 32. Therefore, a portion of the bottom surface 91 of the third electrode 22 has a region that is in contact with the first semiconductor region 31. As a result, a body diode is formed at the interface between the third electrode 22 and the first semiconductor region 31. The semiconductor device 400 and semiconductor device 900 in the comparative example are formed by a pn junction on the body die. While an diode is formed, semiconductor device 700 is a Schottky diode, Compared to a pn junction, it has a lower forward voltage and a shorter reverse recovery time.

[0042] (Seventh variation) Figure 10 is a schematic diagram of a semiconductor device 800 according to the seventh modification of the first embodiment. .

[0043] In the semiconductor device 800, the width in the X direction gradually narrows as the third electrode 22 moves toward the -Z direction. It has a certain shape. In other words, the bottom surface 91 of the third electrode 22 is greater than the top surface 92 of the third electrode 22. The width in the X direction is small. This semiconductor device 800, like semiconductor device 700, has a second semiconductor region Region 32 is provided so as to surround the corner portion 80 of the third electrode 22. As shown in Figure 10. Furthermore, at least a portion of the third electrode 22 is in contact with the second semiconductor region 32 in the X direction. Furthermore, the third electrode 22 is connected to both the first semiconductor region 31 and the second semiconductor region 32. They are in contact with each other in the Z direction. Furthermore, the wall surface 90 of the third electrode 22 is the first semiconductor region 3 It may be in contact with 1 in the X direction.

[0044] Such a semiconductor device 800 has a first channel between the third electrode 22 and the first insulating region 51. A region is formed. Also, the semiconductor device 800 has a width in the X direction of the bottom surface 91 of the third electrode 22. Because it is narrow, the area of ​​the base 91 is reduced, which reduces the leakage current from the base 91. Moreover, in a part of the bottom surface 91 of the third electrode 22, a depletion layer formed by the interface between the first semiconductor region 31 and the second semiconductor region 32 is formed, and the leakage current can be reduced.

[0045] Furthermore, by not covering the entire bottom surface 91 of the third electrode 22 with the second semiconductor region 32, a body diode between the third electrode 22 and the first semiconductor region 31 is formed. In the semiconductor device 800, the forward voltage is lower than that of a pn junction, and the reverse recovery time can be shortened. Note that, in the semiconductor device 800, the bottom surface 91 of the third electrode 22 may not be in contact with the second semiconductor region 32 in the Z direction.

[0046] The semiconductor devices according to the above-described first embodiment and the first to seventh modification examples are all designed such that the MOSFET is in an off state based on the depletion layer width determined by the concentrations of the first conductivity type and the second conductivity type.

[0047] Here, the width of the depletion layer in a general pn junction is expressed by the following equation (1).

[0048]

Equation

[0049] [[ID=^{37}]] W is the width of the depletion layer (μm), ε₀ is the permittivity of vacuum, for example, 8.85×10 -14 F / cm ε r is the relative permittivity of the semiconductor, for example, 11.9, q is the elementary charge, for example, 1.60×10 - 19 C / V, the permittivity of the conductor, V bi is the bulk potential between unbiased junctions, Na is the p-type impurity concentration, and Nd is the n-type impurity concentration.

[0050] ​​​​​​X direction of the first channel region r1 formed between the second semiconductor region 32 and the first insulating region 51 If the distance at a given point is defined as the first length L, then the first length L can be determined according to the width of the depletion layer. The first length L is determined by the impurity concentration of the first semiconductor region and the impurity concentration of the second semiconductor region 32. The calculation can be performed based on equation (1).

[0051] Here, for example, if the second semiconductor region 32 is not provided on the wall surface 90 of the third electrode 2, The Schottky barrier between 2 and the first semiconductor region 31 is used to turn it off when no power is applied. For this to work, the length of L must be approximately 0.05 μm or less. In that case, microfabrication is required. Therefore, it is difficult to manufacture. On the other hand, in the semiconductor device 100 according to this embodiment, n-type impurities Concentration is 1 × 10 15 atoms / cm 3 The above 1 x 10 17 atoms / cm 3 Below, p type The impurity concentration is 1 × 10 17 atoms / cm 3 The above 1 x 10 19 atoms / cm 3 below In this case, the length of L required to turn off the circuit when not energized can be calculated from equation (1) to be approximately 0.1 to 1 μm. This can be maintained. In other words, in this embodiment, a second semiconductor region 32 is provided on the wall surface 90 of the third electrode 22. It is easier to manufacture than semiconductor devices using Schottky barriers, from a processability standpoint. Furthermore, from equation (1), the concentration of n-type impurities is 1 × 10⁻⁶. 15 atoms / cm 3 , p-type impurity concentration The degree is 1 x 10 17 atoms / cm 3 The above 1 x 10 19 atoms / cm 3 In the following cases, The depletion layer is approximately 0.9 to 1 μm thick. The n-type impurity concentration is 1 × 10⁻⁶. 16atom / cm 3 , p-type impurity concentration is 1 × 10 17 atoms / cm 3 The above 1 x 10 19 atoms / cm 3 In the following case, the depletion layer will be approximately 0.3 μm thick. 17 atoms / cm 3 , p-type impurity concentration is 1 × 10 17 atoms / cm 3 The above 1 x 1 0 19 atoms / cm 3 In the following cases, the depletion layer will be approximately 0.07 to 0.1 μm thick. By using these values ​​to control the depletion layer width, the processing process can be reduced and other configurations can be improved. This improves the trade-off relationship with the elements and reduces on-resistance.

[0052] (First manufacturing process) Figures 11(a) to (e) show schematic representations of the first manufacturing process, which is part of the manufacturing process for the third electrode 22. This is a cross-section.

[0053] As shown in Figure 11(a), first of the interlayer insulating layer 46, insulating layer 50 and semiconductor portion 30 For example, a trench T is formed in the part. Here, the manufacturing of the semiconductor device 800 according to the seventh modified example. The method involves adjusting the taper angle using the Bosch process at RIE, in the Z direction. This allows for the formation of a trench T with a narrow width in the X direction. As shown in Figure 11(a) and then in Figure 11(b)... Sea urchin, fill the trench T with CVD (Chemical Vapor Deposits) An oxide film 70 is formed by the (I) method. Subsequently, as shown in Figure 11(c), the reaction By ion etching such as RIE (Reactive Ion Etching) The upper surface of the oxide film 70 is recessed in the -Z direction, and the oxide film 70 is used as a mask material 71 at the bottom of the trench T. It remains in the part. Or, the photoresist used in the lithography process is placed in trench T. Fill the trench, adjust the exposure amount, and use the resist formed at the bottom of the trench T as the mask material 71. It is also possible to do this. Furthermore, if a positive-type photoresist is filled into the trench T, exposure The film may be developed and the mask material 71 may be formed by ashing with oxygen plasma. Then, as shown in Figure 11(d), the ion implantation angle is set from the upper surface of the first semiconductor region 31. By adjusting, a second type of impurity is injected. This results in the second type of impurity. A first diffusion region r2 is formed by this. At this time, the first diffusion region r2 is located on the inner wall of the trench T. These are formed in the first semiconductor region 31 and the third semiconductor region 33 where silicon is exposed.

[0054] After the formation of the first diffusion region r2, the mask material 71 is peeled off, and the impurities in the first diffusion region r2 are removed. To cure it, an annealing process is carried out at a high temperature of 700°C or higher. Two diffusion regions grow, and a second semiconductor region 32 is formed. The mask material 71 is subjected to CVD. If an oxide film is formed, the mask material 71 may be peeled off after the annealing process. The first diffusion region r2 does not diffuse into the third semiconductor region 33, where the impurity concentration is high.

[0055] Furthermore, the peeling process of the mask material 71 may use, for example, chemical peeling, but a different method may be used. It's okay to be there.

[0056] This results in the second semiconductor contacting the third electrode 22 of the semiconductor device 100 according to the first embodiment. Region 32 can be formed.

[0057] Inside the trench T, CVD, plating, and PVD (Physical Vapor Deposition) are used. By embedding Schottky metal using methods such as (eposition), the third electrode 22 This allows for the formation of trench contacts.

[0058] Furthermore, by increasing the thickness of the mask material 71 in Figure 11(c), Figure 9(d) This allows the Z-direction length of the first diffusion region r2 formed on the exposed inner wall of the trench T to be shortened. This makes it possible to form the second semiconductor region 32 of the semiconductor device 200 according to the first modified example.

[0059] Furthermore, during the annealing process of the first diffusion region r2 in Figure 11(d), the concentration gradient is It is also possible to allow the first diffusion region r2 to reach the first insulating region 51. In this case, the fifth The second semiconductor region 32 of the semiconductor device 600 according to the modified example can be formed. For example, in annealing Concentration gradients can also be formed by utilizing diffusion.

[0060] These methods allow the semiconductor device 600 to move from the third electrode 22 toward the first insulating region 51 A second semiconductor region 32 is formed that has a concentration gradient such that the concentration of the second conductive type decreases. .

[0061] (Second manufacturing process) Figures 12(a) to (d) show schematic diagrams of the second manufacturing process, representing a part of the manufacturing process for the third electrode 22. This is a cross-sectional view. It is an example of a different manufacturing process for the semiconductor device 100 according to the first embodiment.

[0062] As shown in Figure 12(a), a trench T is formed. Then, as shown in Figure 12(b) Next, a second type of conductive impurity is injected so as to cover the entire exposed inner wall of trench T. This creates a second diffusion region r3 that covers the entire inner wall of trench T. This is the impurity layer of the second conductivity type. And, of the second diffusion region r3, the bottom wall and the part in contact with the bottom wall A portion of the sidewall is removed by RIE. Subsequently, the second diffusion region r3 is created by the annealing process. As it grows, the second semiconductor region 32 is formed.

[0063] Examples of the first and second manufacturing processes also relate to the temperature and time conditions of the annealing process. Thus, the thickness of the second semiconductor region 32 formed in the X direction can be controlled.

[0064] Furthermore, the step of partially removing the second diffusion region r3 is not limited to RIE and may use a different method. .

[0065] Furthermore, in Figures 12(c) and 12(d), the bottom wall of trench T in the second diffusion region r3. By removing only the part in contact with the other using RIE and adjusting the annealing time, a second modified form can be obtained. The second semiconductor region 32 of the semiconductor device 300 can be formed. The second diffusion region r3 is It does not diffuse into the third semiconductor region 33 where the concentration of pure substances is high.

[0066] (Third manufacturing process) Figures 13(a) to (c) show schematic representations of the third manufacturing process, which is part of the manufacturing process for the third electrode 22. This is a cross-sectional view. The third manufacturing process is an example of a semiconductor device 400 according to the third modified example.

[0067] As shown in Figure 13, a trench T is formed in the same manner as described above. Then, as shown in Figure 13(b) As shown, a second type of conductive impurity is injected so as to cover the entire exposed inner wall of trench T. This creates a third diffusion region r4 that covers the entire inner wall of the trench T. In the manufacturing process, the third diffusion region r4 is grown by the annealing process without processing by RIE. A second semiconductor region 32 is formed that covers the entire inner wall of the trench T. The third diffusion region r4 is not It does not diffuse into the third semiconductor region 33 where the concentration of pure substances is high.

[0068] (Fourth manufacturing process) Figures 14(a) to (e) show schematic representations of the fourth manufacturing process, which is part of the manufacturing process for the third electrode 22. This is a cross-sectional view. The fourth manufacturing process is an example of a semiconductor device 500 according to the fourth modified example.

[0069] As shown in Figure 14, a trench T is formed in the same manner as described above. Then, the trench T is filled. An oxide film 70 is formed to fill the gap. Subsequently, as shown in Figure 14(c), acid is applied using RIE or the like. The upper surface of the oxide film 70 is recessed in the -Z direction, and the mask material 71 is trenched as part of the oxide film 70. It remains at the bottom of T. Then, as shown in Figure 14(d), the second lead from the upper surface of the first semiconductor region 31 An electrolytic impurity is injected. The fourth diffusion region r5 is formed on the exposed inner wall of the trench T. At this time, the fourth diffusion region r5 is the first semiconductor region where silicon is exposed on the inner wall of the trench T. Formed in 31 and the third semiconductor region 33.

[0070] The mask material 71 is left at the bottom of trench T and, without removal, the fourth expansion due to impurities of the second conductive type... The diffusion region r5 is grown by the annealing process. Note that the fourth diffusion region r5 has a high impurity concentration. 3. It does not diffuse within the semiconductor region 33.

[0071] Although embodiments of the present invention have been described, these embodiments are presented as examples only, and the invention It is not intended to limit the scope of brightness. For example, insulated gate bipolar transistors IGBT (Insulated Gate Bipolar Transistor) ), vertical diodes, or other semiconductor chips may also be used.

[0072] These novel embodiments can be implemented in various other forms, and the invention Various omissions, substitutions, and modifications may be made as long as they do not deviate from the main point. The form and its variations are included in the scope and essence of the invention, as well as described in the claims. It is included within the scope of the invention and its equivalents. [Explanation of Symbols]

[0073] 10 1st electrode 20 2nd electrode 22 3rd electrode 30 Semiconductor Division 30a top surface 31. Semiconductor Area 1 32. Second Semiconductor Area 33 Third Semiconductor Area 34. Fourth Semiconductor Area r1 First channel region r2 First diffusion region r3 Second diffusion region r4 3rd diffusion region r5 4th diffusion region T, U Trench 40 4th electrode 41 5th electrode 46 interlayer insulating layer 50, 53 Insulating layer 51 First Insulation Region 70 Oxide film 71 Masking material 90 Wall surface 91 Bottom 92 Top

Claims

1. First electrode and The second electrode and A first semiconductor region of a first conductivity type is provided between the first electrode and the second electrode, The first semiconductor region extends along a first direction from the first electrode toward the second electrode. A third electrode is provided at the top of the, In a second direction perpendicular to the first direction, a fourth electrode is provided opposite to the third electrode. The poles, Provided between the third electrode and the fourth electrode, and at least in the second direction of the third electrode and the second electrode. A second semiconductor region of the second conductivity type that is in contact with the second semiconductor region, The first electrode is in contact with the fourth electrode and is provided facing the third electrode in the second direction. An insulating layer including the edge region, It is provided between the second electrode and the second semiconductor region, and is more impure than the first semiconductor region. The third semiconductor region of the first conductivity type with a high concentration of material, Semiconductor device.

2. The second semiconductor region is in the second direction with respect to both the third electrode and the first semiconductor region. A semiconductor device according to claim 1, wherein two surfaces are in contact with each other.

3. The first lowest point located in the second semiconductor region in the direction opposite to the first direction is the third electric Located on the second electrode side of the second lowest point, which is located in the direction opposite to the first direction of the pole. The semiconductor device according to claim 1.

4. The first lowest point located in the second semiconductor region in the direction opposite to the first direction is the third electric A second lowest point located in the opposite direction to the first direction of the pole is located closer to the first electrode. The semiconductor device according to claim 1.

5. The second semiconductor region is located between the third electrode and the first semiconductor region, and the third electrode The semiconductor device according to claim 1, provided so as to surround the outer surface of the electrode.

6. It is provided between the third electrode and the first electrode, and is in contact with the third electrode in the first direction. The semiconductor device according to claim 1, further comprising an insulating layer.

7. The impurity concentration of the first conductivity type in the first semiconductor region is 1 × 10 １５ atoms / cm ３ That's all. 1 x 10 １７ atoms / cm ３ The semiconductor device according to claim 1, as described below.

8. The first semiconductor region provided between the second semiconductor region and the first insulating region The semiconductor device according to claim 1, wherein the first length in the second direction is 0.1 to 1 μm.

9. The third electrode has an upper surface that is in contact with the second electrode in the first direction, The first semiconductor region and a bottom surface that are in contact with each other in the first direction are further comprising The width of the bottom surface in the second direction is smaller than the width of the top surface in the second direction, according to claim 1. Semiconductor device.

10. The third electrode is connected to both the first semiconductor region and the second semiconductor region in the first direction. A semiconductor device according to claim 1 or 9, wherein two surfaces are in contact with each other.

11. First electrode and The second electrode and A first semiconductor region of a first conductivity type is provided between the first electrode and the second electrode, The first semiconductor region extends along a first direction from the first electrode toward the second electrode. A third electrode is provided at the top of the, In a second direction perpendicular to the first direction, a fourth electrode is provided opposite to the second electrode. The poles, The first electrode is in contact with the fourth electrode and is provided facing the third electrode in the second direction. An insulating layer including the edge region, The third electrode and the first insulating material have a concentration gradient of a second conductive type impurity along the second direction, and the third electrode and the first insulating material Provided between the edge region, and in the second direction, both the third electrode and the first insulating region A second semiconductor region of the second conductivity type that is in contact with, Semiconductor device.

12. The concentration gradient is such that the concentration decreases from the second electrode toward the first insulating region. The semiconductor device described in item 11.

13. The semiconductor device according to claim 11, wherein the concentration gradient has a Gaussian distribution.

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