Solar cells and methods for manufacturing the same

Abstract

This reduces the risk of burn-through in solar cells and improves photoelectric conversion performance. [Solution] The solar cell of the present invention includes a semiconductor substrate having a first surface having a plurality of first texture structures, the first texture structures having a side surface and a top surface connected to one end of the side surface in a direction away from the first surface, a tunnel layer located on the first surface of the semiconductor substrate, a doped semiconductor layer located on the surface of the tunnel layer away from the semiconductor substrate, an electrode located on the surface of the doped semiconductor layer away from the semiconductor substrate and in contact with the doped semiconductor layer, and metal crystals distributed at positions in contact with the electrode in the doped semiconductor layer, the distribution density in the doped semiconductor layer located on the top surface being greater than the distribution density in the doped semiconductor layer located on the side surface.

Description

Technical Field

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[0001] This application relates to the technical field of photovoltaic cells, and specifically, this application relates to solar cells and their manufacturing methods.

Background Art

[0002] In solar cells, in order to improve efficiency, various passivation contact schemes are increasingly being applied. The back surface of a TOPCon (Tunnel Oxide Passivated Contact) cell usually has a polished structure. In order to enhance the light confinement ability of the back surface of a TOPCon cell, the polished structure of the back surface of the cell usually has a concavo-convex fine structure.

[0003] In the case where a tunnel layer and a doped polycrystalline silicon layer are deposited on the conventional fine structure, the tunnel layer and the doped polycrystalline silicon layer on the side walls of the concavo-convex structure are generally thin and unevenly distributed. During subsequent sintering, the side walls of the concavo-convex structure may burn through.

Summary of the Invention

[0004] In view of this, this application provides a solar cell and a manufacturing method to at least partially solve at least one of the technical problems mentioned above.

[0005] To achieve the above object, the technical solution of this application is as follows.

[0006] According to one aspect of the present invention, a solar cell is provided, comprising: a semiconductor substrate including a first surface having a plurality of first texture structures, wherein the first texture structures in a direction away from the first surface include a side surface and a top surface connected to one end of the side surface; a tunnel layer located on the first surface of the semiconductor substrate; a doped semiconductor layer located on the surface of the tunnel layer away from the semiconductor substrate; an electrode located on the surface of the doped semiconductor layer away from the semiconductor substrate and in contact with the doped semiconductor layer; and metal crystals distributed at positions in contact with the electrode within the doped semiconductor layer, the distribution density in the doped semiconductor located on the top surface being greater than the distribution density in the doped semiconductor located on the side surface.

[0007] According to another aspect of the present invention, a method for manufacturing a solar cell is provided, comprising: texturing and polishing the first surface of an initial substrate to form a plurality of first texture structures on the first surface to obtain a semiconductor substrate; fabricating a tunnel layer, a doped semiconductor layer, a first passivation / anti-reflective layer, and an electrode material on the first surface of the semiconductor substrate in this order; and sintering the electrode material to form electrodes, such that the electrodes pass through the first passivation / anti-reflective layer and come into contact with the doped semiconductor layer, and forming metal crystals at the positions in the doped semiconductor layer where the electrodes come into contact.

[0008] The first textured structure of the solar cell provided in this application helps to increase the scattering and absorption of sunlight and enhance the light confinement effect. Because the top surface is formed in the first textured structure, the proportion of the side surface is small, which reduces the probability of contact between the side surface and the metal paste, thereby reducing the possibility of metal crystal formation on the side surface and helping to reduce the risk of burn-through. As for the electrode paste, since it is easily sintered to form a porous morphology, the probability of contact between the side surface and the metal paste is further reduced, reducing burn-through of the side walls and suppressing the formation of metal crystals. This creates a special distribution morphology in which the distribution density of metal crystals on the top surface is greater than that on the side surfaces, which contributes to the optimization of the current collection path, is advantageous for carrier extraction in the direction perpendicular to the top surface, and improves the photoelectric conversion performance of the solar cell.

[0009] In this invention, texturing the first surface of the initial substrate creates a fine texture or roughness on the first surface of the initial substrate, which contributes to increasing light scattering and absorption. Polishing the first surface creates a first textured structure with a top surface, reducing the proportion of side surfaces. Furthermore, a tunnel layer, a doped semiconductor layer, a first passivation / anti-reflective layer, and electrode material are fabricated on the first surface in this order. It has been found that the microstructure with a small proportion of side surfaces reduces the possibility of the doped semiconductor layer located on the side surfaces contacting the electrodes, reduces the possibility of metal crystal formation on the side surfaces, reduces the burn-through risk, and also creates a distribution pattern in which the distribution density of metal crystals located on the top surface is greater than the distribution density of metal crystals located on the side surfaces. [Brief explanation of the drawing]

[0010] The embodiments of this application will become clearer when described below with reference to the drawings. The above and other purposes, features, and advantages of this application will become clearer. The drawings are described below.

[0011] [Figure 1] This is a schematic diagram of the structure of the solar cell according to an embodiment of the present invention. [Figure 2] This is a schematic diagram of the side surface of the first texture structure of an embodiment of the present application, where a is a schematic diagram of the side surface when the first texture structure is a protruding structure, and b is a schematic diagram of the side surface when the first texture structure is a grooved structure. [Figure 3] This is a scanning electron microscope image of a cross-section of a solar cell according to an embodiment of the present invention. [Figure 4] This is a scanning electron microscope image of a cross-section of the first texture structure of an embodiment of the present invention. [Figure 5] This is a schematic diagram of the side surface of the protruding structure of the first texture structure of the embodiment of the present application. [Figure 6A-6C] These are magnified sections showing the distribution of metal crystals at different locations in the cross-section of a solar cell. [Figure 7] This is a schematic flowchart of a method for manufacturing a solar cell according to another embodiment of the present invention. [Figure 8]This is a schematic flowchart of a manufacturing method for a TOPCon battery in another embodiment of the present invention. [Figure 9] This is a schematic diagram of the manufacturing process of a TOPCon battery according to another embodiment of the present invention. [Figure 10] This is a schematic diagram of the structure of a back-contact solar cell of yet another embodiment of the present invention. [Modes for carrying out the invention]

[0012] To make the purpose, technical solution, and advantages of this application clearer and easier to understand, the present application will be described in more detail below with reference to the drawings and specific embodiments.

[0013] The terms used herein are for illustrative purposes only and are not intended to limit the application. The terms “including,” “consisting of,” etc., used herein describe the presence of features, steps, operations, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components. All terms used herein (including technical and scientific terms) have the meanings that a person skilled in the art would ordinarily understand unless otherwise defined. It should be noted that the terms used herein should be interpreted to have meanings consistent with the context herein and should not be interpreted in an idealistic or overly rigid manner.

[0014] The relative position between two members (e.g., film layers or regions) referred to in this application, for example, "above," "upper," or "above," may mean that the two described members are in direct contact, or that they are indirectly in contact. Similarly, the relative position between two members referred to in this application, for example, "below," "down," or "below," may mean that the two described members are in direct contact, or that they are indirectly in contact. For example, if one member (e.g., film layer or region) is described as "located in another member," it may be directly located in another member, or there may be another member between them. On the other hand, if a member is described as "located in another member," there is no member between them. Also, if one member is described as "located in another member," they have an upper-lower relationship in plan view, and this member can be located above or below the other member; this upper-lower relationship is determined by the orientation of the device.

[0015] In solar cells with tunnel passivation contact structures, a textured surface is typically created on the semiconductor substrate to improve the surface's light confinement capability. However, when a tunnel layer and a doped polycrystalline silicon layer are subsequently deposited in such a textured surface, the tunnel layer and doped polycrystalline silicon layer often become thinner at the sidewalls of the textured surface, resulting in a non-uniform layered structure. For example, when a metallization process such as electrode sintering is performed afterward, the sidewalls of the textured surface have a relatively high risk of burn-through. In particular, when a laser-induced sintering process is employed, the current density can increase instantaneously during this process, further increasing the risk of burn-through due to the non-uniformity of the tunnel layer and doped polycrystalline silicon layer at the sidewalls.

[0016] In the process of realizing the concept of this invention, it was discovered that by texturing and polishing the first surface of the initial substrate, a first textured structure with a top surface is formed on the first surface of the semiconductor substrate, which helps to reduce the proportion of side surfaces, reduces the probability of contact between the side surfaces and the metal paste, reduces the possibility of metal crystal formation on the side surfaces, and mitigates the burn-through risk of the side surfaces. Furthermore, when manufacturing electrodes using electrode paste, a porous morphology is formed, further reducing the probability of contact between the side surfaces and the electrode paste, which is advantageous in reducing the burn-through risk of the side surfaces, and suppresses the formation of metal crystals on the side surfaces. As a result, more metal crystals are distributed on the top surface, which helps to optimize the current collection path.

[0017] Specifically, according to an embodiment of one aspect of the present application, a solar cell is provided. Figure 1 is a schematic diagram of the structure of the solar cell of the embodiment of the present application. Figure 2 is a schematic diagram of the side surface of the first texture structure of the embodiment of the present application, where (a) is a schematic diagram of the side surface when the first texture structure is a protruding structure, and (b) is a schematic diagram of the side surface when the first texture structure is a grooved structure. As shown in Figures (a) to (b) in Figures 1 and 2, the solar cell provided in the embodiment of the present application includes a semiconductor substrate 101, a tunnel layer 102, a doped semiconductor layer 103, an electrode 104, and a metal crystal 105. The semiconductor substrate 101 includes a first surface 101a having a plurality of first texture structures 1011, and in a direction away from the first surface 101a, the first texture structure 1011 includes a side surface 1011b and a top surface 1011a connected to one end of the side surface 1011b. The tunnel layer 102 is located on the first surface 101a of the semiconductor substrate 101. The doped semiconductor layer 103 is located on the surface of the tunnel layer 102 away from the semiconductor substrate 101. The electrode 104 is located on the surface of the doped semiconductor layer 103 away from the semiconductor substrate 101 and is in contact with the doped semiconductor layer 103. The metal crystal 105 is distributed in the doped semiconductor layer 103 at a position in contact with the electrode 104, and at least some of the elements of the metal crystal 105 originate from the elements in the electrode 104. The distribution density of the metal crystal 105 in the doped semiconductor layer located on the top surface 1011a is greater than the distribution density in the doped semiconductor layer located on the side surface 1011b. The above relationship of distribution density may be understood as follows: the distribution density within the doped semiconductor layer on the top surface 1011a is greater than the distribution density within the doped semiconductor layer on the side surface 1011b adjacent to the top surface 1011a; or, within the range of the first texture structure covered by the entire doped semiconductor layer 103, the overall distribution density within the doped semiconductor layer on the top surface 1011a is greater than the overall distribution density within the doped semiconductor layer on the side surface 1011b adjacent to the top surface 1011a; or, within the range of the first texture structure in a local region covered by the entire doped semiconductor layer 103, the overall distribution density within the doped semiconductor layer on the top surface 1011a is greater than the overall distribution density within the doped semiconductor layer on the side surface 1011b adjacent to the top surface 1011a.

[0018] According to the embodiments of the present application, continuing to refer to (a) to (b) in FIG. 2, in the direction S away from the first surface, the first texture structure may be a protrusion structure or a concave groove structure, and the top surface 1011a of the first texture structure is a plane protruding in the direction away from the semiconductor substrate 101.

[0019] Furthermore, optionally, the "first texture structure" in the semiconductor substrate 101 may be a fine structure fabricated by polishing after performing texturing on the first surface of the initial substrate. It can be understood that the top surface 1011a is a polished surface formed through polishing. ...

[0020] According to the embodiments of the present application, the "distribution density" of the metal crystals 105 refers to the number of metal crystals 105 within an equivalent unit volume or unit planar area or unit cross-sectional area in the doped semiconductor layer on the top surface 1011a and the side surface 1011b.

[0021] According to the embodiments of the present application, the semiconductor substrate 101 can be an N-type or P-type silicon substrate. For example, it may be one of the semiconductor materials such as single-crystalline silicon, polycrystalline silicon, and microcrystalline silicon, and it is preferably an N-type or P-type single-crystalline silicon substrate. The photoelectric conversion efficiency of a battery using a single-crystalline silicon substrate is higher than that of other types such as polycrystalline silicon batteries. By introducing donor impurities such as elemental phosphorus (P), arsenic (As), or antimony (Sb) into these semiconductor materials, an N-type silicon substrate can be obtained, or by introducing acceptor impurities such as elemental boron (B), aluminum (Al), or gallium (Ga) into these semiconductor materials, a P-type silicon substrate can be obtained.

[0022] More preferably, the semiconductor substrate 101 may be an N-type single-crystalline silicon substrate with a (100) crystal orientation. The top surface 1011a is a (100) crystal plane, and its electron mobility is higher than when the side surface 1011b is other crystal planes. By setting the distribution density of metal crystals on the top surface 1011a and the side surface 1011b in this way, it is more advantageous for efficient transmission of electrons, light-generated carriers can be easily extracted, and it helps to form better performance of the device.

[0023] According to the embodiments of the present application, the tunnel layer 102 and the doped semiconductor layer 103 are combined to form a tunnel passivation contact structure. Among them, the tunnel layer 102 is used to transmit majority carriers and achieve a passivation effect, and may be made of materials such as silicon oxide, gallium oxide, aluminum oxide, titanium oxide, etc., but is not limited thereto. The thickness of the tunnel layer 102 is preferably 1 to 2 nm, and for example, it may be 1 nm, 1.2 nm, 1.5 nm, 1.8 nm, 2 nm, etc.

[0024] The doped semiconductor layer 103 may be at least one semiconductor material such as a polycrystalline silicon layer or a microcrystalline silicon layer. Its doping type may be the same as or different from the doping type of the semiconductor substrate 101. Specifically, it can be determined by the type of the battery and the semiconductor substrate 101. For example, taking the TOPcon battery as an example, when the semiconductor substrate 101 is an N-type silicon substrate, the doped semiconductor layer 103 may be N-type doped or P-type doped. Or when the semiconductor substrate 101 is a P-type silicon substrate, the doped semiconductor layer 103 may be N-type doped or P-type doped. The thickness of the doped semiconductor layer 103 may be, for example, 80 to 200 nm, and for example, it may be 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, etc.

[0025] According to the embodiment of the present invention, the formation of the first texture structure 1011 gives the surface of the semiconductor substrate 101 an uneven texture structure, which increases the light confinement effect and helps to improve the photoelectric conversion efficiency of the solar cell. The first texture structure 1011 having a top surface 1011a has a small proportion of side surfaces, which reduces the probability of contact between the doped semiconductor and the metal paste on the side surfaces. This reduces the possibility of metal crystal formation on the side surfaces 1011b when subsequent sintering is performed, and also reduces the burn-through probability of the side surfaces 1011b.

[0026] Furthermore, with respect to the electrode paste, by selecting appropriate paste components, a porous morphology is formed after sintering, and a porous structure is more easily formed on the side surface 1011b of the first texture structure 1011. The presence of the porous structure further reduces the probability of contact between the side surface and the metal paste, further reduces the burn-through probability of the side surface 1011b, and suppresses the formation of metal crystals on the side surface 1011b. As a result, the distribution density of metal crystals on the top surface 1011a is greater than the distribution density of metal crystals on the side surface 1011b, which is advantageous for the extraction of photogenerated carriers in the direction perpendicular to the top surface 1011a, improving the photoelectric conversion efficiency and current collection efficiency of the solar cell and helping to obtain better device performance.

[0027] Figure 3 is a scanning electron microscope image of a cross-section of a part of the solar cell of an embodiment of the present invention. Figure 4 is a scanning electron microscope image of a cross-section of the first texture structure of an embodiment of the present invention. The first texture structure 1011 is a protruding structure, which may be, for example, a truncated pyramidal shape as shown in Figure 3 or Figure 4, but is not limited thereto, and may be a conical shape, etc. Here, "truncated pyramidal shape" generally refers to a shape that exhibits the shape of a truncated pyramid, and the same applies to "conical shape". The truncated pyramidal shape may further be a pyramidal base structure in which alternating layers are stacked. An appropriate protruding structure is advantageous for the uniform deposition of the subsequent tunnel oxide layer and doped polycrystalline silicon layer, and also reduces the proportion of the side surface 1011b when the inclination angle of the side surface is the same. Here, "inclination angle" refers to the angle made between the plane on which both ends of the side surface 1011b are located and the top surface.

[0028] According to an embodiment of the present application, Figure 5 is a schematic diagram of the side surface of the protrusion structure of the first texture structure according to an embodiment of the present application. As shown in Figure 5, in a direction S away from the first surface, the first texture structure 1011 includes a side surface 1011b and a top surface 1011a. The lateral dimension W2 of the projection of the side surface 1011b in the direction where the top surface 1011a is located means the lateral dimension W2 of the orthographic projection of the side surface 1011b in the plane where the top surface 1011a is located. The ratio of the lateral dimension W2 of the orthographic projection of the side surface 1011b in the plane where the top surface 1011a is located to the lateral dimension W1 of the top surface 1011a is 0.1 to 0.3, and may be, for example, 0.1, 0.13, 0.15, 0.18, 0.2, 0.23, 0.25, 0.27, or 0.3. As the ratio of the two increases, an irregular morphology consisting of multiple tower base structures becomes apparent. However, if the ratio becomes too high, the proportion of the side surface 1011b increases, which is unfavorable for the uniform deposition of subsequent functional layers such as tunnel oxide layers and doped polycrystalline silicon layers fabricated on the first surface 101a. More importantly, the risk of burn-through of the side surface 1011b increases. If the ratio becomes too low, it becomes difficult for subsequent functional layers to maintain a micromorphology limited by multiple protrusion structures, making it difficult to effectively improve light incidence and light utilization. It is understandable that the "lateral dimension" of the top surface 1011a can be a dimension along the plane in which the top surface 1011a is located. For example, if the top surface 1011a is rectangular, its lateral dimension may be the length of the side or the length of the diagonal, and if the top surface 1011a is circular, its lateral dimension may be the length of the diameter.

[0029] Furthermore, the transverse dimension W2 of the orthographic projection of the side surface 1011b in the plane where the top surface 1011a is located is 0.3 to 3 μm, and may be, for example, 0.3 μm, 0.5 μm, 0.8 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, or 3 μm. The transverse dimension W1 of the top surface 1011a is 5 to 25 μm, and may be, for example, 5 μm, 7 μm, 9 μm, 11 μm, 13 μm, 15 μm, 17 μm, 19 μm, 21 μm, or 23 μm. Appropriate dimensions of the protrusion structure help to ensure that the first texture structure 1011 has a high light confinement effect while reducing the probability of contact between the side surface 1011b and the metal paste.

[0030] According to an embodiment of the present invention, referring to Figure 2, the first texture structure 1011 further includes a bottom surface 1011c, which is connected to the other end of the side surface 1011b away from the top surface 1011a and is located between two adjacent side surfaces 1011b of the first texture structure 1011. The distribution density of the metal crystals 105 in the doped semiconductor layer located on the bottom surface 1011c is greater than the distribution density in the doped semiconductor layer located on the side surface. The formation of the top surface 1011a and bottom surface 1011c in the first texture structure 1011 further reduces the proportion of side surfaces 1011b, further reduces the probability of contact between the side surfaces 1011b and the metal paste, and reduces the possibility of metal crystal formation on the side surfaces 1011b, thereby reducing the risk of burn-through of the side surfaces 1011b. In addition, since many metal crystals can be formed in the doped semiconductor layer on the bottom surface 1011c, it helps to further optimize the current collection path and reduce contact resistance.

[0031] If the semiconductor substrate is an N-type single-crystal silicon substrate with a (100) crystal orientation, the bottom surface 1011c is also a (100) crystal plane, similar to the top surface 1011a. Setting the distribution of metal crystals 105 on the bottom surface 1011c in this way is advantageous for efficient electron transmission, allows for easy extraction of photogenerated carriers, and enables superior device performance.

[0032] According to the embodiment of the present application, the distance between two adjacent first texture structures 1011 is 9 μm or less, and may be, for example, 0 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, or 9 μm. If both adjacent first texture structures are protruding structures, the distance between the two adjacent first texture structures 1011 is the shortest distance between the two adjacent side surfaces 1011b of the two adjacent protruding structures. If both adjacent first texture structures are grooved structures, the distance between the two adjacent first texture structures 1011 is the shortest distance between the two adjacent side surfaces 1011b of the two adjacent grooved structures. If the distance between two adjacent first texture structures 1011 is 0, they are deposited alternately between the two adjacent first texture structures 1011. As the spacing increases, the number of first texture structures 1011 in a unit area decreases. Maintaining the distance between the two within the appropriate range described above helps to maintain the micromorphology limited by the multiple first texture structures 1011, improve the scattering and reflectivity to incident light, and increase light utilization, as well as reducing the proportion of side surfaces 1011b and reducing the probability of contact between side surfaces 1011b and the metal paste.

[0033] According to embodiments of the present application, the height from the bottom surface 1011c to the top surface 1011a is 0.1 to 0.8 μm, and may be, for example, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, or 0.8 μm. An appropriate height helps subsequent functional layers, such as tunnel oxide layers and doped polycrystalline silicon layers, to be uniformly deposited on the first surface 101a. In this specification, “height from the bottom surface 1011c to the top surface 1011a” is the dimension in the direction S away from the first surface between the plane in which the bottom surface 1011c is located and the plane in which the top surface 1011a is located.

[0034] According to the embodiment of the present application, referring to Figures 3 and 4, the side surface 1011b of the first texture structure 1011 has a curved arc that is recessed toward the interior of the semiconductor substrate 101. Thus, the recessed bottom of the first texture structure 1011 exhibits a concave curved surface. The concave curved surface morphology helps to reduce the probability of contact between the side surface 1011b and the metal paste and to prevent the doped semiconductor layer 103 located on the side surface 1011b from burning through.

[0035] According to embodiments of the present application, Figures 6A to 6C are partial enlarged views of the distribution of metal crystals at different locations in the cross-section of the solar cell. As shown in Figures 6A to 6C, the metal crystals are mainly dispersed within the doped semiconductor layer 103. Furthermore, the metal crystals 105 are dendritic, toothed, or floral nanoparticles, and aggregates of metal particles. The average particle size of the metal crystals 105 is 20 to 200 nm, and may be, for example, 20 nm, 40 nm, 60 nm, 100 nm, 140 nm, 180 nm, or 200 nm. The formation of the metal crystals 105 is advantageous for the collection and transmission of photogenerated carriers produced by photoexcitation, and their dimensions and morphology can be controlled by a sintering process of the electrode 104, such as a heating sintering and / or laser-enhanced contact optimization process, and the appropriate particle size and morphology of the metal crystals 105 helps control the transmission of photogenerated carriers.

[0036] According to embodiments of the present application, the metal crystal 105 may be an alloy containing the metal element of the electrode 104 and the silicon element. The alloy can establish good ohmic contact between the electrode and the silicon substrate, which helps to improve the transmission efficiency of photogenerated carriers and reduce contact resistance.

[0037] According to embodiments of the present invention, as shown in Figure 1, the semiconductor substrate 101 further includes a second surface 101b having a plurality of second texture structures 1012, where the second texture structures are grooved structures or protruding structures. The formed second texture structures help to enhance the light confinement effect, increase light absorption, and improve photoelectric conversion efficiency. The solar cell further includes an emitter 107 formed within the second surface of the semiconductor substrate 101.

[0038] According to embodiments of the present application, the emitter 107 typically has a high doping concentration in order to more selectively form good ohmic contact, reduce contact resistance, and improve current injection efficiency. The emitter 107 may be N-type doped or P-type doped, and its doping type may be the same as or different from that of the semiconductor substrate. More selectively, N-type doping can be achieved by highly doping the second surface 101b of the semiconductor substrate 101 with a donor element such as phosphorus (P), arsenic (As), or antimony (Sb), or by introducing an acceptor element such as boron (B), aluminum (Al), or gallium (Ga) into the second surface 101b of the semiconductor substrate 101.

[0039] Selectively, as shown in Figure 1, the solar cell further includes a first passivation and anti-reflective layer 106 located on the surface of the doped semiconductor layer 103 away from the semiconductor substrate 101, and the electrode 104 is in contact with the doped semiconductor layer 103 through the first passivation and anti-reflective layer 106.

[0040] According to embodiments of the present invention, as shown in Figure 1, the solar cell further includes a second passivation and anti-reflective layer 108 located on the surface of the emitter 107. The second passivation and anti-reflective layer 108 provides a good passivation and anti-reflective effect and helps to increase the dark saturation current density and implicit open-circuit voltage of the solar cell. The second passivation and anti-reflective layer 108 may be, for example, a laminated film of silicon dioxide, silicon nitride, or a combination of both.

[0041] For example, the first passivation and anti-reflective layer 106 and the second passivation and anti-reflective layer 108 may each include an aluminum oxide layer and a silicon nitride layer, respectively, arranged in a direction away from the semiconductor substrate 101. More selectively, the thickness of the aluminum oxide layer may be 3 to 5 nm, for example, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, etc., and the thickness of the silicon nitride layer may be 80 to 120 nm, for example, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, etc.

[0042] Another embodiment of the present application further provides a method for manufacturing a solar cell. Figure 7 is a schematic flowchart of a method for manufacturing a solar cell according to another embodiment of the present application. Referring to Figure 7 and Figure 1, the method for manufacturing a solar cell according to an embodiment of the present application includes operations S801 to S803.

[0043] In operation S801, the first surface of the initial substrate is texturized and polished to form multiple first texture structures 1011 on the first surface 101a, thereby obtaining a semiconductor substrate 101.

[0044] In operation S802, the tunnel layer 102, the doped semiconductor layer 103, the first passivation / anti-reflective layer 106, and the electrode material are fabricated on the first surface 101a of the semiconductor substrate 101 in this order.

[0045] In operation S803, the electrode material is sintered to form an electrode 104, and the electrode 104 passes through the first passivation / anti-reflective layer 106 to contact the doped semiconductor layer 103, where a metal crystal 105 is formed in the doped semiconductor layer 103 at the position where the electrode 104 is in contact.

[0046] According to the embodiment of the present invention, a plurality of first texture structures 1011 having a top surface 1011a are formed by texturing and polishing the first surface of an initial substrate. The presence of the top surface 1011a reduces the proportion of the side surface, thereby decreasing the probability of contact between the doped semiconductor layer 103 located on the side surface 1011b and the metal paste or metal component during subsequent sintering. This reduces the possibility of metal crystal formation within the doped semiconductor layer 103 on the side surface 1011b, and reduces the probability of burn-through of the doped semiconductor layer 103 on the side surface 1011b. As a result, the distribution density of the formed metal crystals 105 is greater on the top surface 1011a of the first texture structure 1011 than on the side surface 1011b, which is advantageous for the extraction of photogenerated carriers in the direction perpendicular to the top surface 1011a. When manufactured into a solar cell, this can improve photoelectric conversion efficiency and current collection efficiency.

[0047] According to the embodiment of the present application, operation S801 specifically includes wet texturing the first surface of an initial substrate to form a plurality of second texture structures on the first surface, and polishing the wet-textured first surface using a polishing reagent containing nitric acid and hydrofluoric acid to form a plurality of first texture structures on the first surface and obtain a semiconductor substrate 101.

[0048] According to embodiments of the present application, the wet texturing may, for example, involve etching the surface of an initial substrate, such as an original silicon wafer, at 70-80°C using an alkaline solution (e.g., a 2 wt% to 6 wt% potassium hydroxide or sodium hydroxide solution with 0.1 wt% to 1.0 wt% of a texturing additive). This wet texturing process is suitable for texturing single-crystal silicon wafers to form pyramidal structures. Furthermore, for example, the wet texturing may also involve etching the surface of an initial substrate at 5-45°C using an acidic solution (e.g., an HF / HNO3 solution in a volume ratio of 5:1 to 1:6). This wet texturing process is suitable for texturing polycrystalline silicon wafers to form recessed structures. Of course, the wet texturing process is not limited to wet texturing, and a combination of dry texturing processes, such as laser etching, may be used to form a uniformly arranged array of microholes on the surface of the initial substrate. Dry texturing processes are suitable for texturing single-crystal silicon wafers or polycrystalline silicon wafers.

[0049] In the embodiments of this application, the polishing reagent is further selectively configured to have a concentration of 68 wt% HNO3 and a concentration of 0.2 wt% HF. By selecting the appropriate chemical polishing reagent as described above, in the first texture structure 1011, the concentration of HF is low at the other end of the side surface 1011b away from the top surface 1011a, making it difficult for etching products to diffuse from that other end, and the etching rate near the other end of the side surface 1011b tends to decrease in a gradient. Therefore, the side surface tends to become more circular near the other end, potentially forming an arc surface or even a concave curved surface, reducing contact between the side surface 1011b and the metal paste, and mitigating the risk of burn-through of the side surface 1011b.

[0050] According to the embodiments of the present invention, in operation S802, the tunnel layer 102 may be deposited on the surface of the semiconductor substrate 101 by chemical vapor deposition or atomic layer deposition, if necessary. For example, taking the semiconductor substrate as a silicon substrate, the silicon substrate can be thermally oxidized using low-pressure chemical vapor deposition to obtain a tunnel layer 102 with a thickness of 1 to 2 nm.

[0051] Furthermore, an undoped semiconductor layer may be selectively deposited on the surface of the tunnel layer 102 by chemical vapor deposition, and a doped semiconductor layer 103 may be formed by diffusion or ion implantation as needed. For example, if the doped semiconductor layer 103 is a doped polycrystalline silicon layer, a polycrystalline silicon or amorphous silicon layer can be deposited on the surface of the tunnel layer 102 by low-pressure chemical vapor deposition, and the polycrystalline silicon or amorphous silicon layer can be converted into a doped polycrystalline silicon layer by a diffusion process.

[0052] Furthermore, a first passivation and anti-reflective layer 106 may be selectively deposited on the doped semiconductor layer 103, and the first passivation and anti-reflective layer 106 may be, for example, at least one of silicon nitride and silicon dioxide.

[0053] Furthermore, the electrode material is selectively printed onto the first passivation / anti-reflective layer 106. The printing method may be, for example, screen printing or inkjet printing, and is used as needed. The electrode paste used for printing, such as silver paste, contains organic components, which easily volatilize in the subsequent sintering process, forming the porous structure shown in Figure 3.

[0054] In embodiments of the present application, operation S803 may be performed by thermal sintering or laser-assisted sintering, preferably laser-assisted sintering, and specifically includes undersintering the electrode material by a heat treatment method and irradiating the edge region where the undersintered electrode material and the doped semiconductor layer 103 are in contact with a laser. In the present application, "undersintering" can be understood as incompletely sintering the electrode during sintering, for example by lowering the sintering temperature and / or shortening the sintering time, thereby avoiding excessive diffusion of each other due to excessive sintering. After undersintering, irradiating the edge region where the electrode material and the doped semiconductor layer 103 are in contact with a laser induces diffusion of the metallic component of the electrode 104 and the silicon component of the doped semiconductor layer 103, which helps in the formation of the metallic crystal 105. Laser induction helps in the formation of good ohmic contact between the electrode 104 and the doped semiconductor layer 103, which improves carrier transmission.

[0055] Specifically, using the TOPCon battery as an example, Figure 8 is a schematic flowchart of the manufacturing method of the TOPCon battery according to another embodiment of the present application, and Figure 9 is a schematic diagram of the manufacturing process of the TOPCon battery according to yet another embodiment of the present application. As shown in Figures 8 and 9, the manufacturing method of the TOPCon battery according to the embodiment of the present application includes operations S901 to S905.

[0056] In operation S901, a double-sided texturing is performed on an N-type single-crystal silicon wafer to obtain a silicon substrate 901 having a second texture structure 9012. For example, texturing can be performed using an alkaline method with, for instance, a 3% sodium hydroxide solution to create a pyramidal structure for the second texture structure 9012, which can then be distributed on the opposing first surface 901a and second surface 901b of the silicon substrate 901.

[0057] In operation S902, as shown in Figure 9(b), the second surface 901b of the silicon substrate 901 having the second texture structure 9012 is doped by a diffusion process to form an emitter 907. Exemplarily, the emitter 907 may be formed within the second surface 901b of the silicon substrate by a boron diffusion process.

[0058] In operation S903, as shown in Figure 9(c), one-sided polishing is performed on the first surface 901a of the silicon substrate 901 that is facing the second surface 901b to obtain a first surface 901a having a plurality of first texture structures 9011. In a direction away from the first surface 901a, the first texture structure 9011 includes a bottom surface 9011c, a side surface 9011b, and a top surface 9011a, where the top surface 9011a is connected to one end of the side surface 9011b and the bottom surface 9011c is connected to the other end of the side surface 9011b.

[0059] In operation S904, the tunnel layer 902, the doped semiconductor layer 903, the first passivation / anti-reflective layer 906, and the electrode material are fabricated in this order on the first surface 901a of the silicon substrate 901, and the second passivation / anti-reflective layer 908 and the electrode material are fabricated in this order on the surface of the emitter 907. Exemplarily, the doped semiconductor layer 903 is an N-type doped polycrystalline silicon layer formed by a phosphorus diffusion process.

[0060] In operation S905, as shown in Figure 9(d), the electrode material is sintered to form an electrode 904, so that the electrode 904 located on the first surface 901a passes through the first passivation / anti-reflective layer 906 and comes into contact with the doped semiconductor layer 903, and a metal crystal 905 is formed at the position in the doped semiconductor layer 903 where the electrode 904 is in contact, so that the electrode 904 located on the second surface 901b passes through the second passivation / anti-reflective layer 908 and comes into contact with the emitter. Specifically, the sintering operation of the electrode 904 located on the first surface 901a includes under-sintering the electrode material by heat treatment, and then irradiating the edge region where the under-sintered electrode material and the doped semiconductor layer 903 come into contact with a laser.

[0061] In the exemplary embodiment described above, in the single-sided polishing of operation S903, a chain-type apparatus is used to perform single-sided polishing using a polishing reagent containing 68 wt% HNO3 and 0.2 wt% HF, and the cross-section of the finally manufactured TOPCon battery exhibits the form shown in Figures 3 and 6A to 6C, where the distribution density of metal crystals in the doped polycrystalline silicon layer located at the top and bottom surfaces is greater than the distribution density in the doped polycrystalline silicon layer located at the side surfaces.

[0062] Another embodiment of the present application provides a back-contact solar cell including the above-described metal crystal distribution structure. Figure 10 is a schematic diagram of the structure of yet another embodiment of the present application, and the main differences from the structure of the solar cell shown in Figure 1 are as follows. The first surface is the non-light-receiving surface of the back-contact solar cell, and the first surface 101a includes a first region A and a second region B that are spaced apart and alternately distributed, and the tunnel passivation contact structure formed by the tunnel layer 102 and the doped semiconductor layer 103 is located in the first region A, or in the first region A and the second region B, respectively. In this case, the distribution structure of the metal crystal within the doped semiconductor layer 103 is the same as described above, and a detailed explanation is omitted here.

[0063] Exemplary, as shown in Figure 10, in one embodiment, the tunnel passivation contact structure may be located in a first region A and a second region B, respectively. In this case, the tunnel layer 102 and the doped semiconductor layer 103 may be understood as a patterned layer structure, and the corresponding back-contact solar cell is a TBC (TopCon-Back Contact, tunnel oxidative passivation contact-back contact) cell. Furthermore, the doped semiconductor layer 103 located in the first region A and the doped semiconductor layer 103 located in the second region B have different doping types. For example, the doped semiconductor layer 103 located in the first region A is N-type doped and the doped semiconductor layer 103 located in the second region B is P-type doped, or the doped semiconductor layer 103 located in the first region A is P-type doped and the doped semiconductor layer 103 located in the second region B is N-type doped.

[0064] Exemplary, in another embodiment, other passivation contact structures may be used instead of the tunnel passivation contact structure located in the second region B. For example, the tunnel layer 102 and doped semiconductor layer 103 located in the second region B may be replaced as a whole with an aluminum backfield, thereby forming an aluminum backfield passivation structure in the second region B, and the corresponding back contact solar cell may be an HPBC (Hybrid Passivated Back Contact) cell. Alternatively, for example, the tunnel layer 102 and doped semiconductor layer 103 located in the second region B may be replaced as a whole with intrinsic amorphous silicon and doped amorphous silicon arranged sequentially in a direction away from the second region, thereby forming a heterojunction passivation contact structure in the second region B, and the corresponding back contact solar cell may be a hybrid BC (Back Contact) cell.

[0065] According to the embodiments of the present invention, the distributed metal crystal structure of the present invention can be widely applied to various battery types, including tunnel passivation contact structures, thereby reducing the risk of burn-through on the side surface of the first textured structure, optimizing the current collection path, and improving battery efficiency.

[0066] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of the present application. These are merely specific embodiments of the present application and are not intended to limit it. Any modifications, equivalent replacements, improvements, etc., made within the spirit and principles of the present application are understood to be included within the scope of protection.

Claims

1. A semiconductor substrate comprising a first surface having a plurality of first texture structures, wherein the first texture structures are located in a direction away from the first surface, and the first texture structures are located on side surfaces and on top surfaces connected to one end of the side surfaces, A tunnel layer located on the first surface of the semiconductor substrate, A doped semiconductor layer located on the surface of the tunnel layer away from the semiconductor substrate, A porous electrode located on the surface of the doped semiconductor layer away from the semiconductor substrate and in contact with the doped semiconductor layer, A metal crystal having a dispersed distribution such that the distribution density in the doped semiconductor layer located on the top surface is greater than the distribution density in the doped semiconductor layer located on the side surface, The ratio of the lateral dimension of the orthographic projection of the side surface in the plane where the top surface is located to the lateral dimension of the top surface is 0.1 to 0.

3. A solar cell characterized by containing [something].

2. The solar cell according to claim 1, characterized in that the lateral dimension of the orthographic projection of the side surface in the plane where the top surface is located is 0.3 to 3 μm, and the lateral dimension of the top surface is 5 to 25 μm.

3. The first texture structure further includes a bottom surface connected to the other end of the side surface away from the top surface and located between two adjacent side surfaces of the first texture structure. The solar cell according to claim 1 or 2, characterized in that the distribution density of the metal crystal in the doped semiconductor layer located on the bottom surface is greater than the distribution density in the doped semiconductor layer located on the side surface.

4. The solar cell according to claim 2, characterized in that the distance between two adjacent first texture structures is 9 μm or less, and the height from the bottom surface to the top surface is 0.1 to 0.8 μm.

5. The solar cell according to any one of claims 1 to 2, 4, characterized in that the side surface has an arc that is recessed toward the interior of the semiconductor substrate.

6. The aforementioned metal crystals are dendritic, tooth-shaped, or flower-shaped nanoparticles. The solar cell according to claim 1, characterized in that the particle size of the metal crystal is 20 to 200 nm.

7. The solar cell according to claim 1 or 6, characterized in that the metal crystal is an alloy containing the metal element of the electrode and the silicon element.

8. The semiconductor substrate further includes a second surface having a plurality of second texture structures, wherein the second texture structure is a grooved structure or a protruding structure. The solar cell according to claim 1, further comprising an emitter formed in the second surface of the semiconductor substrate.

9. To obtain a semiconductor substrate, a first surface of an initial substrate is texturized and polished to form a plurality of first texture structures on the first surface. The tunnel layer, doped semiconductor layer, first passivation / anti-reflective layer, and electrode material are fabricated on the first surface of the semiconductor substrate in this order. The electrode material is sintered to form an electrode, the electrode passes through the first passivation / anti-reflective layer and contacts the doped semiconductor layer, and a metal crystal is formed in the doped semiconductor layer at the position where the electrode is in contact. A method for manufacturing a solar cell according to any one of claims 1 to 8, characterized by including the following:

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