Image sensor and imaging device

Abstract

The present invention provides an image sensor equipped with an A / D conversion unit, which allows for a smaller circuit size. [Solution] The image sensor comprises a first conversion unit having a plurality of pixels, a first comparison unit electrically connected to a first pixel, and a plurality of storage units each containing a first transistor having a gate unit electrically connected to the first comparison unit and a drain unit that holds the digital signal of a first signal read from the first pixel; a first read unit that reads the digital signal of a first signal held in the drain unit of the first transistor included in the first storage unit and the second storage unit, respectively; and a second read unit that is electrically connected to a third storage unit and a fourth storage unit among the plurality of storage units of the first conversion unit, and reads the digital signal of a first signal held in the drain unit of the first transistor included in the third storage unit and the fourth storage unit, respectively.

Description

Technical Field

[0001] The present invention relates to an imaging device and an imaging apparatus.

Background Art

[0002] An imaging device including an A / D conversion unit is known (for example, Patent Document 1). Conventionally, there has been a problem that the circuit scale of the imaging device becomes large.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] According to a first aspect, the imaging device includes a plurality of pixels each having a photoelectric conversion unit that converts light into charge, and a conversion unit that converts an analog signal into a digital signal, a first comparison unit electrically connected to a first pixel among the plurality of pixels, a first transistor including a gate unit electrically connected to the first comparison unit and a drain unit that holds a digital signal of a first signal read from the first pixel, and a first conversion unit including a plurality of storage units each including the first transistor, a first reading unit electrically connected to a first storage unit and a second storage unit among the plurality of storage units of the first conversion unit, the first reading unit reading a digital signal of the first signal held in the drain unit of the first transistor included in the first storage unit and a digital signal of the first signal held in the drain unit of the first transistor included in the second storage unit, and a second reading unit electrically connected to a third storage unit and a fourth storage unit among the plurality of storage units of the first conversion unit, the second reading unit reading a digital signal of the first signal held in the drain unit of the first transistor included in the third storage unit and a digital signal of the first signal held in the drain unit of the first transistor included in the fourth storage unit. According to the second embodiment, the imaging device comprises an image sensor according to the first embodiment. [Brief explanation of the drawing]

[0005] [Figure 1] This figure shows an example of the configuration of an imaging device according to an embodiment. [Figure 2] This is a block diagram showing an example of the configuration of an image sensor according to an embodiment. [Figure 3] This figure shows an example of the pixel configuration of an image sensor according to the embodiment. [Figure 4] This figure shows some examples of the configuration of an image sensor according to an embodiment. [Figure 5] This figure shows another example of a part of the image sensor according to the embodiment. [Figure 6] This figure shows another example of a part of the image sensor according to the embodiment. [Figure 7] This is a timing chart showing an example of the operation of the image sensor according to the embodiment. [Figure 8] This figure shows an example of a partial configuration of the image sensor according to Modification 1. [Figure 9] This figure shows an example of a partial configuration of the image sensor according to Modification 2. [Figure 10] This figure shows an example of a partial configuration of the image sensor according to Modification 3. [Figure 11] This figure shows an example of a partial configuration of the image sensor related to Modification 4. [Modes for carrying out the invention]

[0006] (Embodiment) Figure 1 shows an example of the configuration of a camera 1, which is an example of an imaging device according to an embodiment. The camera 1 comprises an imaging optical system (imaging optical system) 2, an image sensor 3, a control unit 4, a memory 5, a display unit 6, and an operation unit 7. The imaging optical system 2 has a plurality of lenses, including a focus lens (focus adjustment lens), and an aperture (aperture diaphragm), and forms an image of the subject on the image sensor 3. The imaging optical system 2 may be detachable from the camera 1.

[0007] The image sensor 3 is an image sensor such as a CMOS image sensor or a CCD image sensor. The image sensor 3 receives the light beam that has passed through the imaging optical system 2 and captures the subject image formed by the imaging optical system 2. The image sensor 3 has a plurality of pixels, each having a photoelectric conversion unit, arranged in a two-dimensional manner (row and column directions). The photoelectric conversion unit is composed of photodiodes (PDs) and converts incident light into electric charge. The image sensor 3 generates a signal by photoelectric conversion of the received light and outputs the generated signal to the control unit 4.

[0008] Memory 5 is composed of a non-volatile storage medium or the like. Memory 5 stores image data, programs and data used to control each part of Camera 1, etc. The control unit 4 writes data to Memory 5 and reads data from Memory 5.

[0009] The display unit 6 is a liquid crystal display, an organic EL display, etc. The display unit 6 displays a live view image of the subject, an image based on image data stored in memory 5, an image indicating the focus detection area (AF area) such as an AF frame, shooting-related information such as shutter speed and aperture value, and a menu screen, etc. The display unit 6 may include a touch panel and may also function as an input / output unit. The display unit (input / output unit) 6 may generate signals based on user operations and output them to the control unit 4.

[0010] The control unit 7 includes components such as a release button, a power button (switch), operation buttons, and switches for switching between various modes, and receives operations on the camera 1. The control unit 7 detects operations by the user and outputs signals based on those operations to the control unit 4. The control unit 7 may include the touch panel of the display unit 6.

[0011] The control unit 4 has a processor and memory, and controls each part of the camera 1. The control unit 4 has devices such as a CPU, GPU, FPGA, and ASIC, and memory such as ROM and RAM. The control unit 4 reads and executes programs stored in memory. The control unit 4 can also be described as a processing unit (information processing unit) that performs information processing based on the program.

[0012] The control unit 4 supplies control signals to the image sensor 3 and controls the operation of the image sensor 3. When taking still images, taking video, or displaying a through-image of the subject on the display unit 6, the control unit 4 causes the image sensor 3 to capture an image of the subject and output pixel signals. The control unit 4 performs various image processing on the signal of each pixel output from the image sensor 3 to generate image data that includes the signal of each pixel. The control unit 4 is also an image data generation unit 4, and generates still image data and video image data based on the signal output from the image sensor 3. The control unit 4 performs image processing such as color interpolation and gradation conversion.

[0013] Figure 2 is a block diagram showing an example of the configuration of an image sensor according to an embodiment. The image sensor 3 is constructed by stacking a first substrate 111 on which a plurality of pixels 10 are formed and a second substrate 112 on which a plurality of analog / digital conversion units (AD conversion units) 40 are formed. The first substrate 111 and the second substrate 112 are each made of semiconductor substrates. The circuits provided on the first substrate 111 and the circuits provided on the second substrate 112 are electrically connected by connection parts such as electrodes and bumps.

[0014] The first substrate 111 has a plurality of pixels 10 arranged in two dimensions. The pixels 10 output photoelectric conversion signals and dark signals, which will be described later, to the second substrate 112. The signal lines 20 are signal lines connecting the pixels 10 and the AD conversion unit 40, and signals are output from the pixels 10. The signal lines 20 are signal lines using connection parts such as electrodes and bumps. An AD conversion unit 40 is provided for each of the plurality of signal lines 20.

[0015] The second substrate 112 includes a plurality of AD conversion units 40, a count unit 70, a signal generation unit 80, a read control unit 90, and a signal processing unit 100. The read control unit 90 is composed of a plurality of circuits such as a timing generator, logic circuits (AND circuit, OR circuit, etc.), a latch circuit, and a buffer. The read control unit 90 is controlled by the control unit 4 of the camera 1, supplies signals such as a signal TX and a signal FDRST, which will be described later, to each pixel, and controls the operation of each pixel. The read control unit 90 supplies a signal to the gate of each transistor of the pixel to turn the transistor on (connected state, conductive state, short-circuit state) or off (disconnected state, non-conductive state, open state, cut-off state). The signal of each pixel is output to the signal line 20 connected to that pixel.

[0016] Based on the pulse signal from the timing generator of the read control unit 90, the signal generation unit 80 generates a ramp signal, which is a reference signal that changes with time. The signal generation unit 80 is a circuit (signal generation circuit) that generates a reference signal, is commonly connected to each AD conversion unit 40 provided for each pixel 10, and outputs the reference signal to each AD conversion unit 40.

[0017] The count unit 70 is a counter circuit and generates a digital signal based on the count result based on the pulse signal from the timing generator of the read control unit 90. The count unit (counter) 70 is commonly connected to each AD conversion unit 40 provided for each pixel 10 and outputs a digital signal based on the count result to each AD conversion unit 40. It can also be said that the count unit 70 generates and outputs a signal indicating the count value. [[ID=(9]]

[0018] The AD conversion unit 40 is provided for each pixel 10. The AD conversion unit 40 includes a comparison unit and a storage unit, which will be described later. The AD conversion unit 40 converts the signal of the pixel (photoelectric conversion signal, dark signal), which is an analog signal input from each pixel 10 via the signal line 20, into a digital signal with a predetermined number of bits. The signal of the pixel converted into a digital signal is output to the signal processing unit 100.

[0019] In the imaging device 3 according to this embodiment, using the signal lines 20 provided for each pixel 10, the pixel signals from a plurality of pixels 10 are read out in parallel. The readout control unit 90 causes the pixel signals to be output simultaneously (in parallel) to the AD conversion units 40 provided for each pixel 10, and each AD conversion unit 40 can simultaneously perform signal processing on the pixel signals.

[0020] The signal processing unit 100 is composed of a plurality of circuits such as a logic circuit, a memory circuit, and an output circuit corresponding to a high-speed interface. The signal processing unit 100 performs signal processing such as correlated double sampling (CDS) and processing for correcting the signal amount on the input pixel signals. The signal processing unit 100 outputs the processed signals to the control unit 4 of the camera 1.

[0021] FIG. 3 is a diagram showing a configuration example of a pixel of the imaging device according to the embodiment. The pixel 10 includes a photoelectric conversion unit 11, a transfer unit 12, a floating diffusion (FD) 14, a reset unit 15, an amplification unit 16, and a current source 17. The photoelectric conversion unit 11 is a photodiode PD, which converts incident light into charges and accumulates the photoelectrically converted charges .

[0022] The transfer unit 12 is composed of a transistor M1 controlled by a signal TX, and electrically connects or disconnects the photoelectric conversion unit 11 and the FD 14. The transfer unit 12 transfers the charges photoelectrically converted by the photoelectric conversion unit 11 to the FD 14. The transistor M1 is a transfer transistor . The capacitance C of the FD 14 is a capacitance for accumulating (holding) the charges transferred to the FD 14. The FD 14 accumulates the charges generated by the photoelectric conversion unit 11. The current source 17 generates a current for reading out a signal from the pixel 10 and supplies the generated current to the signal line 20 and the amplification unit 16.

[0023] The amplification unit 16 consists of a transistor M3 whose gate (terminal) is connected to FD14. The amplification unit 16 amplifies and outputs the signal based on the charge stored in the capacitance C of FD14. The drain (terminal) of transistor M3 is connected to the power line (power supply voltage VDD1). The source (terminal) of transistor M3 is connected to the current source 17 and the signal line 20. Transistor M3 is an amplifying transistor. The amplification unit 16 can also be described as an output unit that generates and outputs a signal based on the charge generated by the photoelectric conversion unit 11.

[0024] The reset unit 15 consists of a transistor M2 controlled by the signal FDRST. The reset unit (discharge unit) 15 discharges the charge accumulated in FD14 and resets the voltage of FD14 to the reset voltage (voltage corresponding to voltage VDD1). The reset unit (discharge unit) 15 can also discharge the charge accumulated in the photoelectric conversion unit 11 via the transfer unit 12 and reset the voltage of the photoelectric conversion unit 11. Transistor M2 is a reset transistor.

[0025] Pixel 10 sequentially outputs to the signal line 20 a signal (dark signal) when the voltage of FD14 is reset, and a signal (photoelectric conversion signal) corresponding to the charge transferred from the photoelectric conversion unit 11 to FD14 by the transfer unit 12. The photoelectric conversion signal is an analog signal generated based on the charge photoelectrically converted by the photoelectric conversion unit 11. The dark signal is an analog signal that indicates a reference level for the photoelectric conversion signal and is used to correct the photoelectric conversion signal. The dark signal can also be said to be a signal used to remove noise contained in the photoelectric conversion signal.

[0026] The readout control unit 90 (see Figure 2) controls signals TX, FDRST, etc., input to each pixel 10 to read out the dark signal and the photoelectric conversion signal. The dark signal and photoelectric conversion signal output sequentially from the pixel 10 are input to the AD conversion unit 40 via the signal line 20 and converted into digital signals.

[0027] Figure 4 shows an example of a partial configuration of an image sensor according to an embodiment. The image sensor 3 has an AD conversion unit 40 and a readout unit 50 provided for each pixel 10. The AD conversion unit 40 has a comparison unit 41 and a storage unit 42, and converts the signal from the pixel input via the signal line 20 into a digital signal. The storage unit 42 has a first switch unit 43 and a capacitor C1, and stores the pixel signal (digital signal based on the dark signal, digital signal based on the photoelectric conversion signal) that has been converted into a digital signal. Multiple storage units 42 and multiple readout units 50 are provided corresponding to the number of bits of the digital signal to be stored.

[0028] The comparison unit 41 is configured to include a comparator circuit. One input terminal of the comparison unit 41 receives the signal (photoelectric conversion signal, dark signal) output from the pixel 10 to the signal line 20. The other input terminal of the comparison unit 41 receives a ramp signal, which is a reference signal whose signal level changes over time, from the signal generation unit 80 (see Figure 2). The comparison unit 41 compares the signal input from the pixel 10 with the reference signal Ramp and outputs the output signal CMP, which is the comparison result, from its output terminal. The output terminal of the comparison unit 41 is electrically connected to the first switch unit 43 of each storage unit 42.

[0029] The first switch unit 43 is composed of a transistor M5 controlled by the output signal CMP of the comparison unit 41, and electrically connects or disconnects the count unit 70 and the capacitor C1. The first switch unit 43 can also be called a switching unit (connection unit) that switches between connection and disconnection. The first switch unit 43 receives the output signal CMP indicating the comparison result from the comparison unit 41 and a digital signal based on the count result from the count unit 70. In the example shown in Figure 4, multiple first switch units 43 receive a counter signal cnt indicating the count value. <0> ~cnt <n>The input is received. When the first switch unit 43 is in the ON state, it outputs the counter signal cnt to the capacitor C1.

[0030] Capacitance C1 is a diffusion capacitance, MOS capacitance, MIM capacitance, or a capacitance obtained by stacking these. Capacitance C1 can hold a counter signal cnt, which is a digital signal output from the first switch unit 43. In this embodiment, capacitance C1 is composed of capacitance (diffusion capacitance) added by the drain (or source) of the MOS transistor of the second switch unit 51 of the read unit 50 and the first switch unit 43. Capacitance C1 can also be said to be composed of capacitance caused by the depletion layer of the PN junction at the drain (or source) of the MOS transistor, that is, parasitic capacitance formed on the electrodes of the MOS transistor. Note that the storage unit 42 may also be configured to include the second switch unit 51.

[0031] The first switch unit 43 and capacitor C1 hold a digital signal as the converted pixel signal, which represents a count value corresponding to the elapsed time from the start of the comparison by the comparison unit 41 until the comparison result is reversed, based on the output signal CMP from the comparison unit 41. In the example shown in Figure 4, the first switch unit 43 and capacitor C1 hold a count value of the counter signal cnt corresponding to the time until the relative magnitude relationship between the level of the signal output from the pixel 10 and the level of the reference signal Ramp changes (reverses), based on the signal CMP output from the comparison unit 41.

[0032] When the dark signal of pixel 10 is input to the comparison unit 41, the comparison unit 41 compares the dark signal with the reference signal and outputs the comparison result to the first switch unit 43. While the first switch unit 43 is ON according to the comparison result between the dark signal and the reference signal, the counter signal cnt is input to the capacitor C1 from the count unit 70. When the first switch unit 43 is turned OFF according to the comparison result between the dark signal and the reference signal, the capacitor C1 holds a digital signal of the value of the counter signal cnt corresponding to the elapsed time from the start of the comparison by the comparison unit 41 until the inversion of the comparison result, as a digital signal based on the dark signal.

[0033] When the photoelectric conversion signal from pixel 10 is input to the comparison unit 41, the comparison unit 41 compares the photoelectric conversion signal with a reference signal and outputs the comparison result to the first switch unit 43. While the first switch unit 43 is ON according to the comparison result between the photoelectric conversion signal and the reference signal, a counter signal cnt is input to the capacitor C1 from the count unit 70. When the first switch unit 43 is turned OFF according to the comparison result between the photoelectric conversion signal and the reference signal, the capacitor C1 stores a digital signal of the value of the counter signal cnt corresponding to the elapsed time from the start of the comparison by the comparison unit 41 until the reversal of the comparison result, as a digital signal based on the photoelectric conversion signal.

[0034] As described above, the AD conversion unit 40 has a plurality of first switch units 43 and capacitors C1 corresponding to the number of bits in the digital signal. Each of the plurality of capacitors C1 is input to a counter signal indicating a count value via the first switch unit 43. In the example shown in Figure 4, each of the plurality of capacitors C1 is input to the counter signal cnt <0> ~counter signal cnt <n>The following is input. The AD conversion unit 40 can convert the dark signal, which is an analog signal, into a digital signal of a predetermined number of bits, and convert the photoelectric conversion signal, which is an analog signal, into a digital signal of a predetermined number of bits, using a plurality of first switch units 43 and capacitor C1.

[0035] The reading unit 50 has a plurality of second switch units 51 corresponding to the number of bits of the digital signal obtained by AD conversion. A second switch unit 51 is provided for each capacitor C1. The reading unit 50 also has a holding unit 52, a reset unit 53 (referred to as a signal reset unit 53), and an output unit 55. The reading unit 50 reads a signal based on the digital signal held in the capacitor C1 to a signal line 60 (referred to as a read signal line 60). A read signal line 60 is provided for each of the plurality of reading units 50. A read signal line 60 may be provided for each reading unit 50.

[0036] The second switch unit 51 is composed of a transistor M6 controlled by the signal BSEL, and electrically connects or disconnects the capacitor C1 and the holding unit 52. By electrically connecting the capacitor C1 and the holding unit 52, the second switch unit 51 outputs the digital signal held in the capacitor C1 to the holding unit 52. The second switch unit 51 can also be described as a switching unit (connecting unit) that switches between connecting and disconnecting the capacitor C1 and the holding unit 52. When the second switch unit 51 is in the ON state, it outputs the digital signal held in the capacitor C1 to the holding unit 52.

[0037] The holding section 52 is composed of a capacitance C2 and holds (stores) the digital signal input from the second switch section 51. The capacitance C2 is composed of, for example, a capacitance (stray capacitance) added to the holding section 52. The capacitance C2 includes the diffusion capacitance of the second switch section 51 and the gate capacitance of the amplification section 56 (referred to as the signal amplification section 56) of the output section 55. The capacitance C2 may be a diffusion capacitance, a MOS capacitance, a MIM capacitance, or a capacitance with these stacked together.

[0038] The output unit 55 has a signal amplification unit 56 and a selection unit 57, and outputs a signal based on the digital signal held in the holding unit 52 to the read signal line 60. The signal amplification unit 56 consists of a transistor M8 whose gate is connected to the holding unit 52. The signal amplification unit 56 amplifies the digital signal held in the capacitance C2 of the holding unit 52 and outputs it. The drain and source of transistor M8 are connected to the power line (power supply voltage VDD2) and the selection unit 57, respectively. The source of the signal amplification unit 56 is connected to the read signal line 60 via the selection unit 57.

[0039] The selection unit 57 consists of a transistor M9 controlled by the signal GSEL, and electrically connects or disconnects the signal amplification unit 56 and the read signal line 60. When the transistor M9 of the selection unit 57 is ON, it outputs the signal from the signal amplification unit 56 to the read signal line 60.

[0040] The signal reset unit 53 consists of a transistor M7 controlled by the signal RST, and resets the digital signal held in the holding unit 52. The signal reset unit (ejection unit) 53 ejects the digital signal held in the holding unit 52 and resets the voltage of the holding unit 52 to the reset voltage (voltage corresponding to voltage Vrst). The value of voltage Vrst is set so that the signal amplification unit 56 does not operate in the weak inversion region, enabling the source follower circuit to operate normally.

[0041] The readout control unit 90 (see Figure 2) supplies signals such as the BSEL, GSEL, and RST signals mentioned above to each readout unit 50 to control the operation of each readout unit 50. The readout unit 50 reads out the signal based on the digital signal held in the capacitor C1 as a digital signal of the pixel (photoelectric conversion signal, dark signal) to the readout signal line 60. The readout control unit 90 sequentially selects one of the multiple readout units 50 and reads out the digital signal of the pixel from the selected readout unit 50. In the example shown in Figure 4, the multi-bit pixel signals converted to digital signals are sequentially output to the readout signal line 60 by multiple second switch units 51 and output units 55.

[0042] As shown in Figure 4, the image sensor 3 is provided with a current source 61 and a sense amplifier 62 connected to the readout signal line 60. The current source 61 is connected to each readout unit 50 via the readout signal line 60. The current source 61 generates a current for reading out the photoelectric conversion signal and dark signal converted to digital signals from the readout unit 50, and supplies the generated current to the readout signal line 60 and the output unit 55 of each readout unit 50.

[0043] The read signal line 60 transfers (transmits) the signals input from each read unit 50 to the sense amplifier 62. The sense amplifier 62 amplifies and reads the signals input to the read signal line 60. In this way, the pixel signals converted into digital signals by the AD conversion unit 40 are sequentially output to the signal processing unit 100 via the read unit 50, the read signal line 60, and the sense amplifier 62. The signal processing unit 100 performs signal processing such as correlated double sampling on the pixel signals input from the sense amplifier 62. The signal processing unit 100 outputs the processed signal to the control unit 4. The signal processing unit 100 may also be configured to include the sense amplifier 62.

[0044] As described above, in the image sensor 3 according to this embodiment, the memory unit 42 is configured using a first switch unit 43 and a capacitor C1. Therefore, compared to the case where a memory unit using a large number of transistors, such as SRAM, is provided, the AD conversion unit can be miniaturized. It becomes possible to reduce the circuit area for each pixel 10. This makes it possible to suppress an increase in the chip area of ​​the image sensor 3 and an increase in manufacturing costs. In addition, it becomes possible to realize a multi-bit AD conversion unit 40 with a small circuit area.

[0045] Furthermore, the memory unit 42 can be constructed using only NMOS transistors without using PMOS transistors, preventing the formation of parasitic thyristors in the memory unit 42 and thus preventing latch-up. Moreover, a general semiconductor process can be used to form the memory unit 42 according to this embodiment, thus preventing an increase in manufacturing costs.

[0046] The signal processing unit 100 may also have a storage unit 101 for the photoelectric conversion signal and a storage unit 102 for the dark signal, as shown in the example in Figure 5. The signal processing unit 100 controls the switch SW1 to turn on and off, causing the photoelectric conversion signal converted to a digital signal to be stored in the storage unit 101, and the dark signal converted to a digital signal to be stored in the storage unit 102. The signal processing unit 100 performs CDS processing, which is the difference processing between the photoelectric conversion signal stored in the storage unit 101 and the dark signal stored in the storage unit 102. After performing signal processing such as CDS processing, the signal processing unit 100 outputs the processed signal to the control unit 4.

[0047] As described above, the image sensor 3 may have multiple storage units 42 and multiple reading units 50 for each AD conversion unit 40. In the example shown in Figure 6, each AD conversion unit 40 is provided with six storage units 42 (storage units 42a1 to 42a6) and two reading units 50 (reading units 50a1 and 50a2).

[0048] Figure 7 is a timing chart showing an example of the operation of the image sensor according to the embodiment. The operation example of the image sensor 3 shown in Figure 6 will be explained with reference to this flowchart. In Figure 7, the vertical axis represents the voltage level of the signal, and the horizontal axis represents time. Also in Figure 7, transistors that receive high-level control signals (e.g., power supply voltage) (signals FDRST, TX, RST, BSEL, GSEL) are turned ON, and transistors that receive low-level control signals (e.g., ground voltage) are turned OFF.

[0049] At time t1 shown in Figure 7, the signal FDRST becomes high level. When the signal FDRST becomes high level, the transistor M2 of the reset unit 15 turns on at pixel 10. Also at time t1, when the signal TX becomes high level, the transistor M1 of the transfer unit 12 turns on, and the photoelectric conversion unit 11 and FD14 are electrically connected. With both the transistor M2 of the reset unit 15 and the transistor M1 of the transfer unit 12 turned on, the charge in FD14 and the photoelectric conversion unit 11 is discharged, and the voltages of FD14 and the photoelectric conversion unit 11 are reset. At time t2, the signal TX becomes low level, and the transistor M1 of the transfer unit 12 turns off. Also, when the signal FDRST becomes low level, the transistor M2 of the reset unit 15 turns off.

[0050] At time t3, the signal FDRST becomes high level. When the signal FDRST becomes high level, transistor M2 of the reset unit 15 turns on, resetting the charge of FD14, and the voltage of FD14 becomes the reset voltage. The signal based on the reset voltage of pixel 10, that is, the signal after resetting the charge of FD14 of pixel 10, is output to the signal line 20 by the amplification unit 16. The signal based on the reset voltage is input to the AD conversion unit 40 via the signal line 20 as a dark signal (reset signal). Also at time t3, the comparison unit 41 of the AD conversion unit 40 receives a signal Ramp with a voltage lower than the dark signal voltage from the signal generation unit 80 and outputs a high-level signal CMP.

[0051] At time t4, the signal FDRST becomes low, and the reset unit 15 turns off. Also at time t4, the signal RST becomes high. When the signal RST becomes high, the transistor M7 of the signal reset unit 53 in the read unit 50 turns on, the charge in the holding unit 52 is reset, and the holding unit 52 becomes reset.

[0052] During the period ΔT1 from time t4 to time t5, the potential (level) of the signal Ramp increases with time. The comparison unit 41 compares the potential of the dark signal with the potential of the signal Ramp. When the relative magnitudes of the potentials of the dark signal and the signal Ramp change, the comparison unit 41 inverts the signal level of the signal CMP. In this case, in the memory units 42a1 to 42a6, the transistor M5 of the first switch unit 43 changes from the ON state to the OFF state, and the capacitance C1 of each memory unit 42a1 to 42a6 changes to the counter signal cnt <0> ~cnt <5> Each of these stores a count value. In this way, the memory units 42a1 to 42a6 store digital signals based on the pixel dark signals.

[0053] At time t5, signal RST becomes low level and signal BSEL1 becomes high level. When signal BSEL1 becomes high level, transistor M6a of the second switch unit 51a is turned ON in each of the read units 50a1 and 50a2. Capacitor C1 of the memory unit 42a1 and the holding unit 52 of the read unit 50a1 are electrically connected. The voltage of capacitor C2 of the read unit 50a1 becomes a voltage corresponding to the voltage of the digital signal of the dark signal input from capacitor C1 of the memory unit 42a1. Also, capacitor C1 of the memory unit 42a4 and the holding unit 52 of the read unit 50a2 are electrically connected. The voltage of capacitor C2 of the read unit 50a2 becomes a voltage corresponding to the voltage of the digital signal of the dark signal input from capacitor C1 of the memory unit 42a4.

[0054] Furthermore, at time t5, signal GSEL1 becomes high level. When signal GSEL1 becomes high level, transistor M9 of the selection unit 57 of the output unit 55 is turned on in the read unit 50a1. As a result, the signal based on the digital signal held in the holding unit 52 of the read unit 50a1, that is, the signal based on the digital signal of the dark signal from the memory unit 42a1, is output to the read signal line 60 by the output unit 55.

[0055] Next, the signal GSEL2 goes high, and in the read unit 50a2, the transistor M9 of the selection unit 57 of the output unit 55 is turned on. As a result, the signal based on the digital signal held in the holding unit 52 of the read unit 50a2, that is, the signal based on the digital signal of the dark signal from the memory unit 42a4, is output to the read signal line 60 by the output unit 55. Subsequently, when the signal RST goes high, the signal reset unit 53 in the read units 50a1 and 50a2 is turned on, and the voltage of the holding unit 52 is reset.

[0056] At time t6, signal BSEL2 becomes high. When signal BSEL2 becomes high, the second switch unit 51b in the read units 50a1 and 50a2 is turned ON. Also at time t6, signal GSEL1 becomes high, and the selection unit 57 of the read unit 50a1 is turned ON. As a result, the signal based on the digital signal of the dark signal held by the memory unit 42a2 is output to the read signal line 60 by the output unit 55. Next, signal GSEL2 becomes high, and the selection unit 57 of the read unit 50a2 is turned ON. As a result, the signal based on the digital signal of the dark signal held by the memory unit 42a5 is output to the read signal line 60 by the output unit 55. After that, signal RST becomes high, and the voltage of the holding unit 52 is reset.

[0057] At time t7, signal BSEL3 becomes high. When signal BSEL3 becomes high, the second switch unit 51c in the read units 50a1 and 50a2 is turned ON. Also at time t7, signal GSEL1 becomes high, and the selection unit 57 of read unit 50a1 is turned ON. As a result, the signal based on the digital signal of the dark signal held by the storage unit 42a3 is output to the read signal line 60 by the output unit 55. Next, signal GSEL2 becomes high, and the selection unit 57 of read unit 50a2 is turned ON. As a result, the signal based on the digital signal of the dark signal held by the storage unit 42a6 is output to the read signal line 60 by the output unit 55. After that, signal RST becomes high, and the voltage of the storage unit 52 is reset. In this way, during the period from time t5 to time t8 shown in Figure 7, the dark signal converted into a multi-bit digital signal is read out.

[0058] At time t9, signal TX becomes high level. When signal TX becomes high level, the transfer unit 12 in pixel 10 turns on, and the charge photoelectrically converted by the photoelectric conversion unit 11 is transferred to FD 14. The signal based on the charge generated by the photoelectric conversion unit 11 of pixel 10 (photoelectric conversion signal) is output to the signal line 20 by the amplification unit 16. The photoelectric conversion signal is input to the AD conversion unit 40 via the signal line 20. At time t10, signal TX becomes low level, and the transfer unit 12 turns off. Also at time t10, signal RST becomes high level, and the holding unit 52 of the readout unit 50 is reset.

[0059] During the period ΔT2 from time t10 to time t11, the potential of signal Ramp increases with time. The comparison unit 41 compares the potential of the photoelectric conversion signal with the potential of signal Ramp. When the relative magnitudes of the potentials of the photoelectric conversion signal and signal Ramp change, the comparison unit 41 inverts the signal level of signal CMP. In this case, the first switch unit 43 in the storage units 42a1 to 42a6 changes from the ON state to the OFF state, and the respective capacitances C1 of the storage units 42a1 to 42a6 are controlled by the counter signal cnt <0> ~cnt <5> Each of these stores a count value. In this way, the memory units 42a1 to 42a6 store digital signals based on the photoelectric conversion signals of the pixels.

[0060] At time t11, signal RST becomes low level and signal BSEL1 becomes high level. When signal BSEL1 becomes high level, the second switch unit 51a in read units 50a1 and 50a2 is turned ON. In this case, the voltage of the capacitor C2 of read unit 50a1 corresponds to the voltage of the digital signal of the photoelectric conversion signal input from capacitor C1 of storage unit 42a1. The voltage of the capacitor C2 of read unit 50a2 corresponds to the voltage of the digital signal of the photoelectric conversion signal input from capacitor C1 of storage unit 42a4.

[0061] Furthermore, at time t11, signal GSEL1 becomes high level, and the selection unit 57 of the read unit 50a1 turns on. As a result, the signal based on the digital signal held in the holding unit 52 of the read unit 50a1, i.e., the signal based on the digital signal of the photoelectric conversion signal from the storage unit 42a1, is output to the read signal line 60 by the output unit 55. Next, signal GSEL2 becomes high level, and the selection unit 57 of the read unit 50a2 turns on. As a result, the signal based on the digital signal held in the holding unit 52 of the read unit 50a2, i.e., the signal based on the digital signal of the photoelectric conversion signal from the storage unit 42a4, is output to the read signal line 60 by the output unit 55. Subsequently, when signal RST becomes high level, the signal reset unit 53 in the read units 50a1 and 50a2 turns on, and the voltage of the holding unit 52 is reset.

[0062] At time t12, signal BSEL2 becomes high. When signal BSEL2 becomes high, the second switch unit 51b in the readout units 50a1 and 50a2 is turned ON. Also at time t12, signal GSEL1 becomes high, and the selection unit 57 of the readout unit 50a1 is turned ON. As a result, the signal based on the digital signal of the photoelectric conversion signal held by the storage unit 42a2 is output to the readout signal line 60 by the output unit 55. Next, signal GSEL2 becomes high, and the selection unit 57 of the readout unit 50a2 is turned ON. As a result, the signal based on the digital signal of the photoelectric conversion signal held by the storage unit 42a5 is output to the readout signal line 60 by the output unit 55. After that, signal RST becomes high, and the voltage of the storage unit 52 is reset.

[0063] At time t13, signal BSEL3 becomes high. When signal BSEL3 becomes high, the second switch unit 51c in the readout units 50a1 and 50a2 is turned ON. Also at time t13, signal GSEL1 becomes high, and the selection unit 57 of readout unit 50a1 is turned ON. As a result, the signal based on the digital signal of the photoelectric conversion signal held by the storage unit 42a3 is output to the readout signal line 60 by the output unit 55. Next, signal GSEL2 becomes high, and the selection unit 57 of readout unit 50a2 is turned ON. As a result, the signal based on the digital signal of the photoelectric conversion signal held by the storage unit 42a6 is output to the readout signal line 60 by the output unit 55. After that, signal RST becomes high, and the voltage of the storage unit 52 is reset. In this way, during the period from time t11 to time t14 as shown in Figure 7, the photoelectric conversion signal converted into a multi-bit digital signal is read out.

[0064] The dark signal and photoelectric conversion signal, converted to digital signals, are sequentially output to the signal processing unit 100 via the readout signal line 60 and sense amplifier 62. The signal processing unit 100 performs signal processing such as CDS processing on the input pixel signals and then outputs the processed signals to the control unit 4.

[0065] According to the embodiment described above, the following effects can be obtained: (1) The image sensor 3 includes a photoelectric conversion unit 11 that converts light into electric charge, a comparison unit 41 that compares a signal based on the electric charge converted by the photoelectric conversion unit 11 with a reference signal, a counting unit 70 that outputs a digital signal based on the counting result, a first switch unit 43 that outputs a digital signal input from the counting unit 70 based on the comparison result by the comparison unit 41, a capacitor C1 that holds the digital signal output from the first switch unit 43, and a readout unit (readout unit 50) that reads out a signal based on the digital signal held in the capacitor C1. In this way, the image sensor 3 according to this embodiment can hold the signal of a pixel converted into a digital signal in the capacitor C1 by controlling the first switch unit 43. Furthermore, the image sensor 3 can output the signal of a pixel converted into a digital signal by controlling the readout unit 50.

[0066] (2) In this embodiment, the capacitor C1 holds the pixel signal that has been converted to a digital signal. Therefore, the AD conversion unit can be miniaturized compared to the case where a memory unit using a large number of transistors, such as SRAM, is provided. This can suppress an increase in the chip area of ​​the image sensor 3.

[0067] The following modifications are also within the scope of the present invention, and it is possible to combine one or more of these modifications with the embodiments described above.

[0068] (Variation 1) The image sensor 3 may have a storage unit 42 and a readout unit 50 for photoelectric conversion signals, and a storage unit 42 and a readout unit 50 for dark signals. Figure 8 shows an example of a part of the configuration of an image sensor according to Modification 1. In the example shown in Figure 8, each AD conversion unit 40 is provided with three storage units 42a (42a1 to 42a3) and a readout unit 50a for photoelectric conversion signals, and three storage units 42b (42b1 to 42b3) and a readout unit 50b for dark signals.

[0069] In Figure 8, the third switch section 45a (45a1 to 45a3) is composed of transistor M10a controlled by the signal SW_SIG. The third switch section 45a electrically connects or disconnects the counting section 70 and the first switch section 43 of the memory section 42a for the photoelectric conversion signal. The third switch section 45b (45b1 to 45b3) is composed of transistor M10b controlled by the signal SW_DARK. The third switch section 45b electrically connects or disconnects the counting section 70 and the first switch section 43 of the memory section 42b for the dark signal.

[0070] The readout control unit 90 controls the on / off state of the third switch units 45a and 45b using the signals SW_SIG and SW_DARK. By turning on the third switch units 45a1 to 45a3, the readout control unit 90 can output the counter signal cnt to the photoelectric conversion signal storage units 42a1 to 42a3, thereby performing AD conversion of the photoelectric conversion signal. Furthermore, by turning on the third switch units 45b1 to 45b3, the readout control unit 90 can output the counter signal cnt to the dark signal storage units 42b1 to 42b3, thereby performing AD conversion of the dark signal.

[0071] (Modification 2) In the embodiments and modifications described above, an example was described in which the signal amplification unit 56 is composed of a transistor M8 that functions as part of a source follower circuit. However, the signal amplification unit 56 may also be a buffer circuit. For example, the signal amplification unit 56 may be a NOT(INV) circuit composed of a PMOS transistor M8a and an NMOS transistor M8b, as shown in Figure 9.

[0072] (Variation 3) The pixel signals, converted into multi-bit digital signals, may be read out by dividing them into multiple read signal lines 60. For example, as shown in Figure 10, two read signal lines 60a and 60b may be provided to the read unit 50. The current source 61a and sense amplifier 62a shown in Figure 10 are provided for the read signal line 60a. The current source 61b and sense amplifier 62b are provided for the read signal line 60b. Signal reading from read unit 50a1 to read signal line 60a and signal reading from read unit 50a2 to read signal line 60b can be performed simultaneously (in parallel). The image sensor 3 according to this modified example is capable of reading out the signals of each pixel, which have been converted into digital signals, at high speed.

[0073] (Modification 4) Figure 11 shows an example of a partial configuration of an image sensor according to Modification 4. In the image sensor 3, in addition to the readout signal line 60a from which the pixel signal is output from the readout unit 50, an output unit 65 and a readout signal line 60b are provided. The current source 61 and sense amplifier 62 are provided for the readout signal line 60b. The output unit 65 has an amplification unit 66 and a selection unit 67. The amplification unit 66 is composed of a transistor M10 whose gate is connected to the readout signal line 60a, and it amplifies the pixel signal input to the readout signal line 60a and outputs it.

[0074] The selection unit 67 consists of a transistor M11 controlled by the signal G2SEL, which electrically connects or disconnects the amplification unit 66 and the readout signal line 60b. When the transistor M11 of the selection unit 67 is ON, it outputs the signal from the amplification unit 66 to the readout signal line 60b. In this modified example, the pixel signals output from the readout unit 50 are transmitted to the sense amplifier 62 via the output unit 65, thereby suppressing signal delay and signal level degradation of the pixel signals. As a result, the image sensor 3 can read out the signals of each pixel at high speed.

[0075] (Variation 5) In the embodiment described above, an example was described in which the image sensor 3 is constructed by stacking a first substrate 111 and a second substrate 112. However, the first substrate 111 and the second substrate 112 do not necessarily have to be stacked. Furthermore, the image sensor 3 may be constructed from three or more substrates, or from a single substrate.

[0076] (Experimental variation 6) In the embodiments and modifications described above, examples were given in which a photodiode was used as the photoelectric conversion unit. However, a photoelectric conversion film (organic photoelectric film) may also be used as the photoelectric conversion unit.

[0077] (Example 7) The image sensor and imaging device described in the above embodiments and modifications may be applied to cameras, smartphones, tablets, cameras built into PCs, in-vehicle cameras, cameras mounted on unmanned aerial vehicles (drones, radio-controlled aircraft, etc.).

[0078] Although various embodiments and modifications have been described above, the present invention is not limited to these. Other embodiments conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention. [Explanation of symbols]

[0079] 1...Imaging device, 3...Image sensor, 10...Pixel, 11...Photoelectric conversion unit, 40...AD conversion unit, 41...Comparison unit, 42...Storage unit, 43...First switch unit, 50...Reading unit, 51...Second switch unit, 52...Holding unit, 53...Reset unit, 55...Output unit, 70...Counting unit, 80...Signal generation unit, 90...Reading control unit, 100...Signal processing unit< / n> < / n>

Claims

1. Multiple pixels, each having a photoelectric conversion unit that converts light into electric charge, A conversion unit for converting an analog signal to a digital signal, comprising a plurality of storage units, each including a first comparison unit electrically connected to a first pixel among a plurality of pixels, and a first transistor having a gate unit electrically connected to the first comparison unit and a drain unit that holds the digital signal of the first signal read from the first pixel, A read unit electrically connected to a first storage unit and a second storage unit among the plurality of storage units of the first conversion unit, the first read unit reads out the digital signal of the first signal held in the drain portion of the first transistor included in the first storage unit and the digital signal of the first signal held in the drain portion of the first transistor included in the second storage unit, A reading unit electrically connected to the third and fourth storage units among the plurality of storage units of the first conversion unit, the reading unit reads the digital signal of the first signal held in the drain portion of the first transistor included in the third storage unit and the digital signal of the first signal held in the drain portion of the first transistor included in the fourth storage unit. An image sensor equipped with the following features.

2. In the image sensor according to claim 1, The first read unit includes an output unit having a transistor having a gate portion electrically connected to the drain portion of the first transistor included in the first storage unit and the drain portion of the first transistor included in the second storage unit, and includes a first output unit that outputs the digital signal of the first signal held in the drain portion of the first transistor included in the first storage unit and the digital signal of the first signal held in the drain portion of the first transistor included in the second storage unit. The second read unit includes an output unit having a transistor having a gate portion electrically connected to the drain portion of the first transistor included in the third storage unit and the drain portion of the first transistor included in the fourth storage unit, and includes a second output unit that outputs the digital signal of the first signal held in the drain portion of the first transistor included in the third storage unit and the digital signal of the first signal held in the drain portion of the first transistor included in the fourth storage unit. Image sensor.

3. In the image sensor according to claim 2, The first read unit includes a first connection unit for electrically connecting the drain portion of the first transistor included in the first storage unit and the transistor of the first output unit, and a second connection unit for electrically connecting the drain portion of the first transistor included in the second storage unit and the transistor of the first output unit. The second read unit includes a third connection unit for electrically connecting the drain portion of the first transistor included in the third storage unit and the transistor of the second output unit, and a fourth connection unit for electrically connecting the drain portion of the first transistor included in the fourth storage unit and the transistor of the second output unit. Image sensor.

4. In the image sensor according to claim 3, The first connection unit includes a transistor having a source unit that holds the digital signal of the first signal, together with the drain unit of the first transistor included in the first storage unit. The second connection unit includes a transistor having a source unit that holds the digital signal of the first signal, together with the drain unit of the first transistor included in the second storage unit. The third connection unit includes a transistor having a source unit that holds the digital signal of the first signal, together with the drain unit of the first transistor included in the third storage unit. The fourth connection section includes a transistor having a source section that holds the digital signal of the first signal, together with the drain section of the first transistor included in the second storage section. Image sensor.

5. In the image sensor according to claim 4, The drain portion of the transistor included in the first connection portion and the drain portion of the transistor included in the second connection portion transfer the digital signal of the first signal held in the drain portion of the first transistor included in the first storage portion and the digital signal of the first signal held in the drain portion of the first transistor included in the second storage portion. The drain portion of the transistor included in the third connection portion and the drain portion of the transistor included in the fourth connection portion are used to transfer the digital signal of the first signal held in the drain portion of the first transistor included in the third storage portion and the digital signal of the first signal held in the drain portion of the first transistor included in the fourth storage portion. Image sensor.

6. In the image sensor according to claim 4 or claim 5, The first read unit is a reset unit including a transistor for electrically connecting the drains of both the drains of the transistor included in the first connection unit and the drains of the transistor included in the second connection unit, and a supply unit to which a predetermined voltage is supplied, and includes a first reset unit that resets the potential of the drains of the transistor included in the first connection unit and the potential of the drains of the transistor included in the second connection unit. The second read unit is a reset unit including a transistor for electrically connecting the drains of both the transistor included in the third connection unit and the transistor included in the fourth connection unit to the supply unit, and includes a second reset unit for resetting the potential of the drains of the transistor included in the third connection unit and the potential of the drains of the transistor included in the fourth connection unit. Image sensor.

7. In the image sensor according to any one of claims 2 to 6, An image sensor comprising a first signal line electrically connected to the transistor of the first output unit and the transistor of the second output unit, the first signal line outputting the digital signal of the first signal held in the drain portion of the first transistor included in the first storage unit, the digital signal of the first signal held in the drain portion of the first transistor included in the second storage unit, the digital signal of the first signal held in the drain portion of the first transistor included in the third storage unit, and the digital signal of the first signal held in the drain portion of the first transistor included in the fourth storage unit.

8. In the image sensor according to claim 7, A read unit including a transistor having a gate portion electrically connected to the first signal line, the read unit reads the digital signal of the first signal held in the drain portion of the first transistor included in the first storage unit, the digital signal of the first signal held in the drain portion of the first transistor included in the second storage unit, the digital signal of the first signal held in the drain portion of the first transistor included in the third storage unit, and the digital signal of the first signal held in the drain portion of the first transistor included in the fourth storage unit. A signal line electrically connected to the transistor of the third read unit, the second signal line on which the digital signal of the first signal held in the drain portion of the first transistor included in the first storage unit is output, the digital signal of the first signal held in the drain portion of the first transistor included in the second storage unit, the digital signal of the first signal held in the drain portion of the first transistor included in the third storage unit, and the digital signal of the first signal held in the drain portion of the first transistor included in the fourth storage unit are output. An image sensor equipped with the following features.

9. In the image sensor according to any one of claims 2 to 6, A signal line electrically connected to the transistor of the first output unit, the first signal line on which the digital signal of the first signal held in the drain portion of the first transistor included in the first storage unit and the digital signal of the first signal held in the drain portion of the first transistor included in the second storage unit are output, A signal line electrically connected to the transistor of the second output unit, the second signal line on which the digital signal of the first signal held in the drain portion of the first transistor included in the third storage unit and the digital signal of the first signal held in the drain portion of the first transistor included in the fourth storage unit are output. An image sensor equipped with the following features.

10. In the image sensor according to any one of claims 1 to 9, The first signal includes a signal based on the charge converted by the photoelectric conversion unit of the first pixel, Image sensor.

11. In the image sensor according to claim 10, The first signal includes a signal for correcting the signal based on the charge converted by the photoelectric conversion unit of the first pixel. Image sensor.

12. In the image sensor according to any one of claims 1 to 11, A conversion unit for converting an analog signal to a digital signal, comprising a plurality of storage units, each containing a second transistor having a second comparison unit electrically connected to a second pixel located next to a first pixel in a first direction among the plurality of pixels, a gate unit electrically connected to the second comparison unit, and a drain unit that holds the digital signal of the second signal read from the second pixel, A conversion unit for converting an analog signal to a digital signal, comprising a plurality of storage units, each containing a third transistor having a third comparison unit electrically connected to a third pixel located next to a first pixel in a second direction intersecting the first direction among the plurality of pixels, a gate unit electrically connected to the third comparison unit, and a drain unit that holds the digital signal of the third signal read from the third pixel; An image sensor equipped with the following features.

13. In the image sensor according to any one of claims 1 to 12, The plurality of pixels are arranged on the first semiconductor substrate. The first conversion unit is arranged on a second semiconductor substrate which is stacked together with the first semiconductor substrate. Image sensor.

14. In the image sensor according to claim 13, The first reading unit and the second reading unit are arranged on the second semiconductor substrate. Image sensor.

15. An imaging device comprising an image sensor according to any one of claims 1 to 14.

16. In the imaging apparatus according to claim 15, An imaging device comprising a generation unit that is electrically connected to the image sensor and generates image data.

17. In the imaging apparatus according to claim 15 or claim 16, An imaging device comprising a mounting section to which an optical system for emitting light is detachably attached to the aforementioned image sensor.

18. In the imaging apparatus according to claim 15 or claim 16, An imaging device comprising an optical system for emitting light to the aforementioned image sensor.

Images