Semiconductor equipment

Abstract

The present invention provides a semiconductor device that relaxes design rules related to electrodes. [Solution] The semiconductor device 1 includes a semiconductor layer 10 having main surfaces 11 and 12, a switching element formed on the semiconductor layer, a first electrode 50 disposed on the main surface 11 and electrically connected to the switching element, a second electrode 55 disposed on the main surface at a distance from the first electrode and electrically connected to the switching element, a first terminal electrode 70 having a portion that overlaps with the first electrode and a portion that overlaps with the second electrode in a plan view and electrically connected to the first electrode, and a second terminal electrode 75 having a portion that overlaps with the second electrode in a plan view and electrically connected to the second electrode.

Description

[Technical Field]

[0001] This application corresponds to Japanese Patent Application No. 2020-156343, filed with the Japan Patent Office on 17 September 2020, and the full disclosure of this application is incorporated herein by reference. The present invention relates to a semiconductor device. [Background technology]

[0002] Patent document 1 discloses technology relating to a semiconductor device including a SiC substrate. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2015 / 295079 [Overview of the project] [Problems that the invention aims to solve]

[0004] One embodiment provides a semiconductor device that can relax design rules related to electrodes. [Means for solving the problem]

[0005] One embodiment provides a semiconductor device comprising: a semiconductor layer having a main surface; a switching element formed on the semiconductor layer; a first electrode disposed on the main surface and electrically connected to the switching element; a second electrode disposed on the main surface at a distance from the first electrode and electrically connected to the switching element; a first terminal electrode having a portion overlapping the first electrode and a portion overlapping the second electrode in a plan view and electrically connected to the first electrode; and a second terminal electrode having a portion overlapping the second electrode in a plan view and electrically connected to the second electrode.

[0006] One embodiment provides a semiconductor device comprising: a semiconductor layer having a main surface; a main element formed in the semiconductor layer and generating a main current; a sense element formed in the semiconductor layer in a region different from the main element and generating a monitor current for monitoring the main current; a first electrode disposed on the main surface and electrically connected to the main element; a second electrode disposed on the main surface at a distance from the first electrode and electrically connected to the main element; a third electrode disposed on the main surface at a distance from the first and second electrodes and electrically connected to the sense element; a first terminal electrode on the first electrode and electrically connected to the first electrode; a second terminal electrode on the second electrode and electrically connected to the second electrode; and a third terminal electrode having a portion that overlaps with the third electrode and a portion that overlaps with the second electrode in a plan view and is electrically connected to the third electrode.

[0007] One embodiment provides a semiconductor device comprising: a semiconductor layer having a main surface; a switching element formed in the semiconductor layer; a diode formed in a region of the semiconductor layer different from the switching element; a first electrode disposed on the main surface and electrically connected to the switching element; a second electrode disposed on the main surface at a distance from the first electrode and electrically connected to the switching element; a first terminal electrode on the first electrode and electrically connected to the first electrode; a second terminal electrode on the second electrode and electrically connected to the second electrode; and a polarity terminal electrode having a portion that overlaps with the diode and a portion that overlaps with the second electrode in a plan view, and electrically connected to the diode.

[0008] One embodiment provides a semiconductor device including a semiconductor layer containing SiC and having a first main surface on one side and a second main surface on the other side, a vertical transistor formed in the semiconductor layer, a first electrode disposed on the first main surface, a second electrode disposed on the first main surface with a space from the first electrode, a first electrode pad disposed on the side opposite to the semiconductor layer with respect to the first electrode so as to overlap at least a part of the first electrode in a plan view and electrically connected to the first electrode, and an electrode disposed on the second main surface, wherein the first electrode pad overlaps a part of the second electrode in a plan view.

[0009] One embodiment provides a method of manufacturing a semiconductor device, including the steps of preparing a semiconductor layer containing SiC and having a first main surface on one side and a second main surface on the other side and including a vertical transistor, forming a first electrode and a second electrode with a space on the first main surface, and forming a first electrode pad at a position on the side opposite to the semiconductor layer with respect to the first electrode so as to overlap at least a part of the first electrode and be electrically connected to the first electrode, wherein in the step of forming the first electrode pad, the first electrode pad overlapping a part of the second electrode is formed.

[0010] The above or still other objects, features, and effects will be clarified by the description of the embodiments described with reference to the accompanying drawings.

Brief Description of the Drawings

[0011] [Figure 1] FIG. 1 is a cross-sectional view showing a main part of a semiconductor device according to Embodiment 1. [Figure 2] FIG. 2 is a cross-sectional view showing another main part of the semiconductor device shown in FIG. 1. [Figure 3] FIG. 3 is a plan view of the semiconductor device shown in FIG. 1. [Figure 4] FIG. 4 is a plan view seen from the position of line IV-IV shown in FIG. 2. [Figure 5] FIG. 5 is a plan view seen from the position of line V-V shown in FIG. 2. [Figure 6] FIG. 6 is a plan view seen from the position of the VI-VI line shown in FIG. 2. [Figure 7] FIG. 7 is a plan view obtained by removing the protective insulating layer from the plan view of FIG. 3. [Figure 8] FIG. 8 is a plan view showing an example of the layout of through holes with respect to the gate pad. [Figure 9] FIG. 9 is a plan view showing another example of the layout of through holes with respect to the gate pad. [Figure 10] FIG. 10 is a plan view showing another example of the layout of the main surface gate electrode and the main surface source electrode. [Figure 11] FIG. 11 is a plan view showing yet another example of the layout of the main surface gate electrode and the main surface source electrode. [Figure 12] FIG. 12 is an enlarged cross-sectional view showing the outer peripheral portion of the semiconductor device shown in FIG. 2. [Figure 13A] FIG. 13A is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in FIG. 2. [Figure 13B] FIG. 13B is a cross-sectional view showing the process after FIG. 13A. [Figure 13C] FIG. 13C is a cross-sectional view showing the process after FIG. 13B. [Figure 13D] FIG. 13D is a cross-sectional view showing the process after FIG. 13C. [Figure 13E] FIG. 13E is a cross-sectional view showing the process after FIG. 13D. [Figure 14] FIG. 14 is an enlarged cross-sectional view showing a modified example of the outer peripheral portion of the semiconductor device shown in FIG. 2. [Figure 15] FIG. 15 is a cross-sectional view of the semiconductor device according to Embodiment 2. [Figure 16] FIG. 16 is a plan view of the semiconductor device shown in FIG. 15. [Figure 17] FIG. 17 is a plan view obtained by removing the protective insulating layer from the plan view of FIG. 16. [Figure 18] FIG. 18 is a plan view seen from the position of the XVIII-XVIII line shown in FIG. 15. [Figure 19]Figure 19 is a plan view showing a modified example of the semiconductor device shown in Figure 15. [Figure 20] Figure 20 is a plan view of the top surface of the electrodes of the semiconductor device shown in Figure 19. [Figure 21] Figure 21 is a cross-sectional view of a semiconductor device according to Embodiment 3. [Figure 22] Figure 22 is a plan view of the semiconductor device shown in Figure 21. [Figure 23] Figure 23 is a plan view of Figure 22 with the protective insulating layer removed. [Figure 24] Figure 24 is a plan view taken from the position of line XXIV-XXIV shown in Figure 21. [Figure 25] Figure 25 is a plan view showing a modified example of the semiconductor device shown in Figure 21. [Figure 26] Figure 26 is a plan view of the top surface of the electrodes of the semiconductor device shown in Figure 25. [Figure 27] Figure 27 is a plan view showing another modified example of the semiconductor device shown in Figure 21. [Figure 28] Figure 28 is a plan view of the top surface of the electrodes of the semiconductor device shown in Figure 27. [Figure 29] Figure 29 is a front view of an example of a semiconductor package according to Embodiment 4. [Figure 30] Figure 30 is a rear view showing an example of the semiconductor package shown in Figure 29. [Figure 31] Figure 31 is a front view of another example of the semiconductor package shown in Figure 29. [Figure 32] Figure 32 is a cross-sectional view of a semiconductor device having a configuration in which plating layers are formed to cover the gate pad and source pad, respectively. [Modes for carrying out the invention]

[0012] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit the present invention. Furthermore, components in the following embodiments that are not described in an independent claim are described as optional components.

[0013] The attached drawings are schematic diagrams and not necessarily strictly accurate. For example, the scale and other aspects do not necessarily match between the attached drawings. In the attached drawings, substantially identical components are denoted by the same reference numerals, and redundant explanations are omitted or simplified.

[0014] In this specification, terms indicating relationships between elements such as vertical and horizontal, terms indicating the shape of elements such as rectangles, and numerical ranges are not expressions that represent only strict meanings, but rather expressions that include substantially equivalent ranges. For example, in the shape of a polygon or polygonal prism, the vertices may be rounded.

[0015] In this specification, the terms "upper" and "lower" do not refer to the absolute spatial directions of upward (vertically upward) and downward (vertically downward), but are defined by the relative positional relationship based on the stacking order in the stacked configuration. For example, the first main surface side of a semiconductor layer is described as the upper side (upper), and the second main surface side as the lower side (lower). In actual use of a semiconductor device (vertical transistor), the first main surface side may be the lower side (lower), and the second main surface side may be the upper side (upper). Of course, the semiconductor device (vertical transistor) may be used in an orientation where the first and second main surfaces are inclined or perpendicular to the horizontal plane.

[0016] The terms “above” and “below” apply not only when two components are spaced apart vertically with another component in between, but also when two components are positioned vertically so that they are in close contact with each other.

[0017] In this specification and in the drawings, the x, y, and z axes represent the three axes of a three-dimensional Cartesian coordinate system. In this specification, “stack direction” means the direction perpendicular to the principal surface of the semiconductor layer. In this specification, “plan view” means the view from a direction perpendicular to the first principal surface of the semiconductor layer.

[0018] Figure 1 is a cross-sectional view of a vertical transistor included in a semiconductor device according to Embodiment 1. In Figure 1, for the sake of readability, the shading representing the cross-section of the semiconductor layer 10 is not applied. Referring to Figure 1, the semiconductor device 1 is an example of a switching device and includes a vertical transistor 2 (switching element). The vertical transistor 2 is, for example, a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor).

[0019] The semiconductor device 1 includes a semiconductor layer 10, a gate electrode 20, a source electrode 30, and a drain electrode 40. The semiconductor layer 10 is formed in the shape of a rectangular parallelepiped chip. The semiconductor layer 10 has a first main surface 11 on one side and a second main surface 12 on the other side. The semiconductor layer 10 mainly contains SiC (silicon carbide). Specifically, the semiconductor layer 10 is an n-type (first conductivity type) SiC semiconductor layer containing a SiC single crystal.

[0020] The SiC single crystal may be a 4H-SiC single crystal. The first main surface 11 may be the silicon surface ((0001) surface) where the silicon of the SiC crystal is exposed. The second main surface 12 may be the carbon surface ((000-1) surface) where the carbon of the SiC crystal is exposed. The semiconductor layer 10 may have an off-angle that is tilted at an angle of 10° or less with respect to the [11-20] direction from the (0001) surface of the 4H-SiC single crystal. The off-angle may be 0° or more and 4° or less.

[0021] The off-angle may exceed 0° and be less than 4°. The off-angle may be 2° or 4°. The off-angle may be set within the range of 2° ± 0.2° or 4° ± 0.4°. The x-axis direction may be the [11 - 20] direction, and the y-axis direction may be the [1 - 100] direction. Of course, the x-axis direction may be the [1 - 100] direction, and the y-axis direction may be the [11 - 20] direction.

[0022] The semiconductor layer 10 has a stacked structure including an n-type semiconductor substrate 13 and an n-type epitaxial layer 14. The semiconductor substrate 13 contains a SiC single crystal. The lower surface of the semiconductor substrate 13 is the second main surface 12. The epitaxial layer 14 is stacked on the upper surface of the semiconductor substrate 13. The epitaxial layer 14 is an n-type SiC semiconductor layer containing a SiC single crystal. The upper surface of the epitaxial layer 14 is the first main surface 11.

[0023] The n-type impurity concentration of the semiconductor substrate 13 is 1.0×10 cm -3 or more and 1.0×10 21 cm -3 or less. In this specification, "impurity concentration" means the peak value of the impurity concentration. The n-type impurity concentration of the epitaxial layer 14 is preferably less than the n-type impurity concentration of the semiconductor substrate 13. The n-type impurity concentration of the epitaxial layer 14 is 1.0×10 15 cm -3 or more and 1.0×10 17 cm -3 or less. The semiconductor substrate 13 is provided as an n + -type drain region. The epitaxial layer 14 is provided as an n - -type drain drift region.

[0024] The thickness of the semiconductor substrate 13 may be 1 μm or more and less than 1000 μm. The thickness of the semiconductor substrate 13 may be 5 μm or more, 25 μm or more, 50 μm or more, or 100 μm or more. The thickness of the semiconductor substrate 13 may be 700 μm or less, 500 μm or less, 400 μm or less, 300 μm or less, 250 μm or less, 200 μm or less, 150 μm or less, or 100 μm or less. In the vertical transistor 2, current flows in the stacking direction of the semiconductor layer 10 (i.e., the thickness direction). Therefore, by reducing the thickness of the semiconductor substrate 13, the resistance can be reduced by shortening the current path.

[0025] The thickness of the epitaxial layer 14 may be 1 μm or more and 100 μm or less. The thickness of the epitaxial layer 14 may be 5 μm or more, 10 μm or more, or 50 μm or less. The thickness of the epitaxial layer 14 may be 40 μm or less, 30 μm or less, 20 μm or less, 15 μm or less, or 10 μm or less. Preferably, the thickness of the epitaxial layer 14 is less than the thickness of the semiconductor substrate 13.

[0026] Referring to Figure 1, the semiconductor device 1 includes a p-type (second conductivity type) body region 16, a plurality of trench gate structures 21, a plurality of trench source structures 31, an n-type source region 17, and a p-type contact region 18. The body region 16 is provided on the surface portion of the first main surface 11 of the semiconductor layer 10. - This is a type of semiconductor region. The body region 16 is formed on the surface of the epitaxial layer 14. The p-type impurity concentration in the body region 16 is 1.0 × 10⁻⁶ 16 cm -3 The above 1.0 × 10 19 cm -3 The following is also acceptable.

[0027] The multiple trench gate structures 21 are arranged on the first main surface 11 with spacing in the x-axis direction in a plan view, and each is formed in a strip shape extending in the y-axis direction. The multiple trench gate structures 21 are formed to penetrate from the first main surface 11 through the body region 16. The multiple trench gate structures 21 are formed within the epitaxial layer 14 with spacing from the semiconductor substrate 13 toward the first main surface 11.

[0028] Each trench gate structure 21 includes a gate trench 22, a gate insulating layer 23, and a gate electrode 20. The gate trench 22 is formed by excavating the first main surface 11 toward the second main surface 12. The gate trench 22 has a rectangular cross-sectional shape in the xz section and is formed as a recess (groove) that extends in a band shape in the y-axis direction.

[0029] The gate trench 22 may have a length on the order of millimeters in the longitudinal direction (y-axis direction). The length of the gate trench 22 may be 1 mm or more and 10 mm or less. The length of the gate trench 22 may be 2 mm or more and 5 mm or less. The total length of one or more gate trenches 22 per unit area is 0.5 μm / μm 2 More than 0.75μm / μm 2 The following is also acceptable.

[0030] The gate insulating layer 23 is formed in a film-like manner along the side walls 22a and bottom wall 22b of the gate trench 22. The gate insulating layer 23 partitions a concave space inside the gate trench 22. The gate insulating layer 23 may contain at least one of silicon oxide, silicon without impurities, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0031] The thickness of the gate insulating layer 23 may be between 0.01 μm and 0.5 μm. The thickness of the gate insulating layer 23 may be uniform or may vary depending on the location. The gate insulating layer 23 includes a side wall portion 23a that covers the side wall 22a of the gate trench 22, and a bottom wall portion 23b that covers the bottom wall 22b of the gate trench 22. The thickness of the bottom wall portion 23b may exceed the thickness of the side wall portion 23a.

[0032] The thickness of the bottom wall portion 23b may be between 0.01 μm and 0.2 μm. The thickness of the side wall portion 23a may be between 0.05 μm and 0.5 μm. The gate insulating layer 23 may include a covering portion that covers the first main surface 11 outside the gate trench 22. The thickness of the covering portion may exceed the thickness of the side wall portion 23a.

[0033] The gate electrode 20 is embedded in the gate trench 22, with the gate insulating layer 23 in between. In other words, the gate electrode 20 is embedded in a concave space partitioned by the gate insulating layer 23. The gate electrode 20 may contain at least one of a nonmetallic conductor and a metal. The gate electrode 20 may contain at least one of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, tungsten, and titanium nitride (conductive metal nitride).

[0034] The aspect ratio of the trench gate structure 21 may be between 0.25 and 15.0. The aspect ratio of the trench gate structure 21 is defined by the ratio of the depth (length in the z-axis direction) of the trench gate structure 21 to the width (length in the x-axis direction) of the trench gate structure 21. The aspect ratio of the gate trench 22 is the same as the aspect ratio of the trench gate structure 21.

[0035] The width of the trench gate structure 21 may be between 0.2 μm and 2.0 μm. For example, the width of the trench gate structure 21 may be about 0.4 μm. The depth of the trench gate structure 21 may be between 0.5 μm and 3.0 μm. For example, the depth of the trench gate structure 21 may be about 1.0 μm.

[0036] Multiple trench source structures 31 are formed in the region between adjacent trench gate structures 21 on the first main surface 11. Each of the multiple trench source structures 31 is formed in a strip shape extending in the y-axis direction. As a result, the multiple trench source structures 31 are arranged alternately with the multiple trench gate structures 21 one at a time in the x-axis direction. Figure 1 shows only the region where one trench gate structure 21 is sandwiched between two trench source structures 31. In a plan view, the multiple trench source structures 31 form a stripe structure with the multiple trench gate structures 21 (see Figure 5 below).

[0037] Each trench source structure 31 may be formed with a spacing of 0.3 μm to 1.0 μm from adjacent trench gate structures 21. Multiple trench source structures 31 are formed to penetrate the body region 16 from the first main surface 11 and demarcate the body region 16 extending along the y-axis direction between them and the multiple trench gate structures 21. Multiple trench source structures 31 are formed within the epitaxial layer 14 with a spacing from the semiconductor substrate 13 toward the first main surface 11. Multiple trench source structures 31 are formed deeper than multiple trench gate structures 21.

[0038] The trench source structure 31 includes a source trench 32, a barrier forming layer 33, a source electrode 30, and a deep well region 15. The source trench 32 is formed by excavating the first main surface 11 toward the second main surface 12. The source trench 32 has a rectangular cross-sectional shape in the xz section and is formed as a recess (groove) extending in a band shape in the y-axis direction. The source trench 32 is formed deeper than the gate trench 22. That is, the bottom wall 32b of the source trench 32 is located toward the second main surface 12 than the bottom wall 22b of the gate trench 22.

[0039] The source electrode 30 is embedded in the source trench 32. The source electrode 30 may contain at least one of a non-metallic conductor and a metal. The source electrode 30 may contain at least one of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, tungsten, and titanium nitride (conductive metal nitride). The source electrode 30 may contain n-type polysilicon with n-type impurities, or p-type polysilicon with p-type impurities. The source electrode 30 may be formed from the same material as the gate electrode 20. In this case, the source electrode 30 can be formed in the same process as the gate electrode 20.

[0040] The barrier-forming layer 33 is interposed between the wall surface of the source trench 32 and the source electrode 30. In this configuration, the barrier-forming layer 33 coats the side walls 32a and bottom wall 32b of the source trench 32 in a film-like manner, defining a concave space within the source trench 32. In other words, the source electrode 30 is embedded in the concave space defined by the barrier-forming layer 33.

[0041] The barrier-forming layer 33 is formed from a different material than the source electrode 30. The barrier-forming layer 33 has a potential barrier higher than the potential barrier between the source electrode 30 and the semiconductor layer 10 (specifically the deep well region 15 described later). The barrier-forming layer 33 may be a conductive barrier-forming layer. In this case, the barrier-forming layer 33 may contain at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum.

[0042] The barrier-forming layer 33 is preferably an insulating barrier-forming layer. In this case, the barrier-forming layer 33 may contain at least one of silicon oxide, impurity-free silicon, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride. The barrier-forming layer 33 may be formed from the same material as the gate insulating layer 23. In this case, the barrier-forming layer 33 may have the same film thickness as the gate insulating layer 23. For example, if the gate insulating layer 23 and the barrier-forming layer 33 are formed from silicon oxide, the gate insulating layer 23 and the barrier-forming layer 33 can be formed simultaneously by a thermal oxidation treatment method.

[0043] The deep well region 15 is formed in the semiconductor layer 10 in a region along the trench source structure 31. The deep well region 15 is referred to as the breakdown voltage holding region. - This is a semiconductor region of type 1.0. The deep well region 15 is 1.0 × 10⁻⁶. 17 cm -3 The above 1.0 × 10 19 cm -3 The following p-type impurity concentrations may be present. Preferably, the p-type impurity concentration in the deep well region 15 exceeds the n-type impurity concentration in the epitaxial layer 14. The p-type impurity region in the deep well region 15 may be equal to the p-type impurity concentration in the body region 16. The p-type impurity concentration in the deep well region 15 may be less than the p-type impurity concentration in the body region 16.

[0044] The deep well region 15 includes a sidewall portion 15a that covers the sidewall 32a of the source trench 32, and a bottom wall portion 15b that covers the bottom wall 32b of the source trench 32. The sidewall portion 15a is electrically connected to the body region 16. The bottom wall portion 15b is formed in the epitaxial layer 14 at a distance from the semiconductor substrate 13. The thickness of the bottom wall portion 15b (length in the z-axis direction) is preferably greater than or equal to the thickness of the sidewall portion 15a (length in the x-axis direction). At least a portion of the bottom wall portion 15b may be located within the semiconductor substrate 13.

[0045] The aspect ratio of the trench source structure 31 is greater than the aspect ratio of the trench gate structure 21. The aspect ratio of the trench source structure 31 may be between 0.5 and 18.0. Preferably, the aspect ratio of the trench source structure 31 is between 1.5 and 4.0. The aspect ratio of the trench source structure 31 is defined by the ratio of the depth (length in the z-axis direction) of the trench source structure 31 to the width (length in the x-axis direction) of the trench source structure 31.

[0046] The width of the trench source structure 31 is the sum of the width of the source trench 32 and the width of the side wall portions 15a of the deep well regions 15 located on both sides of the source trench 32. The depth of the trench source structure 31 is the sum of the depth of the source trench 32 and the thickness of the bottom wall portion 15b of the deep well region 15.

[0047] The width of the trench source structure 31 may be between 0.6 μm and 2.4 μm. For example, the width of the trench source structure 31 may be about 0.8 μm. The depth of the trench source structure 31 may be between 1.5 μm and 11 μm. For example, the depth of the trench source structure 31 may be about 2.5 μm. By increasing the depth of the trench source structure 31, the pressure resistance effect of the SJ (Super Junction) structure can be enhanced.

[0048] The source region 17 is formed on the surface portion of the first main surface 11 of the semiconductor layer 10. +This is a semiconductor region of type 17. The source region 17 is formed on the body region 16 (on the surface of the body region 16) and is connected to the body region 16. The source region 17 is formed in the region along the gate trench 22. The source region 17 covers the gate insulating layer 23 and faces the gate electrode 20 across the gate insulating layer 23.

[0049] The source region 17 is formed in a band shape extending in the y-axis direction in a plan view. The width (length in the x-axis direction) of the source region 17 may be 0.2 μm or more and 0.6 μm or less. For example, the width of the source region 17 may be about 0.4 μm. The n-type impurity concentration in the source region 17 is 1.0 × 10⁻⁶ 18 cm -3 The above 1.0 × 10 21 cm -3 The following is also acceptable.

[0050] The contact region 18 is formed on the surface portion of the first main surface 11 of the semiconductor layer 10. + This is a semiconductor region of type 16. The contact region 18 is formed on the body region 16 (on the surface of the body region 16) and is connected to the body region 16. The contact region 18 is also connected to the source region 17. The contact region 18 is formed in the region along the source trench 32. The contact region 18 covers the barrier forming layer 33 and faces the source electrode 30 across the barrier forming layer 33.

[0051] The contact region 18 is formed in a band shape extending along the y-axis in a plan view. The width (length in the x-axis direction) of the contact region 18 may be 0.1 μm or more and 0.4 μm or less. For example, the width of the contact region 18 may be about 0.2 μm. The p-type impurity concentration in the contact region 18 is 1.0 × 10⁻⁶. 18 cm -3 The above 1.0 × 10 21 cm -3 The following is also acceptable.

[0052] The semiconductor device 1 includes a drain electrode 40 that covers the second main surface 12 of the semiconductor layer 10. The drain electrode 40 is electrically connected to the semiconductor substrate 13 at the second main surface 12. The drain electrode 40 may contain at least one of titanium, nickel, copper, aluminum, gold, and silver. The drain electrode 40 may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer stacked in this order from the second main surface 12.

[0053] The drain electrode 40 may have a four-layer structure including a Ti layer, an AlCu layer, a Ni layer, and an Au layer stacked in this order from the second main surface 12. The AlCu layer is an alloy layer of aluminum and copper. The drain electrode 40 may have a four-layer structure including a Ti layer, an AlSiCu layer, a Ni layer, and an Au layer stacked in this order from the second main surface 12. The AlSiCu layer is an alloy layer of aluminum, silicon, and copper. The drain electrode 40 may have a single-layer structure consisting of a TiN layer instead of a Ti layer, or a stacked structure including a Ti layer and a TiN layer.

[0054] The vertical transistor 2 switches between an ON state, where drain current flows, and an OFF state, where no drain current flows, depending on the gate voltage applied to the gate electrode 20. The gate voltage may be between 10V and 50V. For example, the gate voltage may be 30V. The source voltage applied to the source electrode 30 may be a reference voltage that serves as the basis for circuit operation, such as the ground voltage (0V). The drain voltage applied to the drain electrode 40 is a voltage greater than or equal to the source voltage. The drain voltage may be, for example, between 0V and 10000V. The drain voltage may be 1000V or more.

[0055] When a gate voltage is applied to the gate electrode 20, p - A channel is formed in the portion of the body region 16 of the mold that is in contact with the gate insulating layer 23. This creates a current path from the source electrode 30 to the drain electrode 40, via the contact region 18, source region 17, body region 16 (channel), epitaxial layer 14, and semiconductor substrate 13.

[0056] The drain electrode 40 is at a higher potential than the source electrode 30. Therefore, the drain current flows from the drain electrode 40 to the source electrode 30 through the semiconductor substrate 13, epitaxial layer 14, body region 16 (channel), source region 17, and contact region 18. In this way, the drain current flows along the thickness direction of the semiconductor device 1.

[0057] The deep well region 15 forms a pn junction with the epitaxial layer 14. When the vertical transistor 2 is ON, the source voltage is applied to the deep well region 15 via the source electrode 30, and a drain voltage higher than the source voltage is applied to the epitaxial layer 14 via the drain electrode 40. In other words, when the vertical transistor 2 is ON, a reverse bias voltage is applied to the pn junction, and the depletion layer spreads from the pn junction toward the drain electrode 40.

[0058] This increases the breakdown voltage of the vertical transistor 2. The deep well region 15, which has a p-type impurity concentration higher than the n-type impurity concentration of the epitaxial layer 14, allows the depletion layer to be appropriately extended from the interface between the deep well region 15 and the epitaxial layer 14.

[0059] In this embodiment, a trench gate structure is employed, but a planar gate structure may also be employed. Furthermore, in this embodiment, a trench source structure is formed, but a configuration without a trench source structure may also be adopted. Also, in this embodiment, a so-called stripe cell structure is employed, but a mesh cell structure may also be employed.

[0060] In the embodiments of this specification, an FET structure (transistor structure) is defined as a structure having three regions: a source region, a drain region, and a gate region, and controlling the current between the source region and the drain region by an electric field generated in the channel region when a voltage is applied to the gate region. In this sense, the FET structure is a concept that includes junction FETs in addition to MOSFETs and MISFETs.

[0061] In other words, the FET structure is a concept that also includes IGBTs (Insulated Gate Bipolar Transistors) which have an "emitter region" and a "collector region" corresponding to the "source region" and "drain region," respectively. In the embodiment, the FET structure is composed of a body region 16, a source region 17, a gate electrode 20, an epitaxial layer 14, etc.

[0062] In embodiments relating to this specification, the active region is a region (partitioned region) in a semiconductor device where an FET structure is formed. In a single semiconductor device, the active region may be a single region or multiple regions divided from each other. Furthermore, if a diode structure such as a Schottky barrier diode is formed within a region containing an FET structure, the region containing both the FET structure and the diode structure is defined as the active region. Furthermore, if the region containing the diode structure is adjacent to the region containing the FET structure, the region containing both the diode structure and the region containing the FET structure is defined as the active region.

[0063] In the embodiments of this specification, the inactive region is the region other than the active region. Examples of the inactive region include the region directly below the gate wiring section, the outer peripheral voltage-bearing structure section, and the region directly below the PN diode structure for the temperature sensor. In the embodiments of this specification, the FET structure for current sensing is defined as the inactive region.

[0064] Next, the overall structure of the semiconductor device 1 (in particular, the pad structure for supplying a predetermined voltage to the gate electrode 20 and source electrode 30) will be described. Figure 2 is a cross-sectional view showing other essential parts of the semiconductor device 1 shown in Figure 1. In Figure 2, the specific configuration of the semiconductor layer 10 shown in Figure 1 is omitted. In Figure 2, the shading representing the cross-section of the semiconductor layer 10 is omitted. Figure 2 shows a cross-section along the line II-II in Figure 3. Figure 3 is a plan view of the semiconductor device 1 shown in Figure 1. In Figure 3, the outer edge 70b of the gate pad 70 (wide portion 72), the outer edge 75a of the source pad 75, and the inner edge 75b of the source pad 75 are shown by dashed lines.

[0065] Figure 4 is a plan view of the semiconductor device 1 in a plane parallel to the substrate surface, as seen from the position of line IV-IV in Figure 2. Figure 4 shows the planar shape of the main surface gate electrode 50 and the main surface source electrode 55. Specifically, Figure 4 is a plan view of the semiconductor device 1 as seen from the positive z-axis side, with the gate pad 70 and source pad 75 shown in Figure 3 visible through it.

[0066] Figure 5 is a plan view of the semiconductor device 1 in a plane parallel to the substrate surface as seen from the position of the VV line in Figure 2. Figure 5 shows the arrangement of the gate electrode 20 and source electrode 30 in a plan view. Specifically, Figure 5 is a plan view of the semiconductor device 1 as seen from the positive side of the z axis, with the main surface gate electrode 50, main surface source electrode 55, insulating layer 60, gate pad 70 and source pad 75 visible through it (see also Figures 3 and 4).

[0067] Figure 6 is a plan view of a plane parallel to the substrate surface as seen from the position of line VI-VI in Figure 2. In Figure 6, the upper insulating layer 63 and the end insulating layer 65 are shown by white areas. In Figure 6, the columnar portion 71 and source pad 75 of the main surface gate electrode 50, exposed through the gap between the upper insulating layer 63 and the end insulating layer 65, are shown by shaded areas.

[0068] In Figure 6, the outer edge 75a and inner edge 75b of the upper part of the gate pad 70 (wide section 72) and source pad 75 are shown by dashed lines. Figure 7 is a plan view of Figure 3 with the protective insulating layer 66 removed. Figure 7 shows the planar shapes of the gate pad 70 and source pad 75. In other words, Figure 7 is a plan view of Figure 3 with the protective insulating layer 66 removed.

[0069] Referring to Figures 2 and 3, the semiconductor device 1 is a semiconductor chip with a rectangular planar shape. The length of one side of the semiconductor device 1 may be between 1 mm and 10 mm. The length of one side of the semiconductor device 1 may be between 2 mm and 5 mm. The semiconductor device 1 includes a main surface gate electrode 50, a main surface source electrode 55, an insulating layer 60, a gate pad 70, a source pad 75, and a protective insulating layer 66.

[0070] Referring to Figures 1 and 5, the semiconductor device 1 includes a plurality of gate electrodes 20 and a plurality of source electrodes 30 embedded in the first main surface 11. Each of the plurality of gate electrodes 20 and the plurality of source electrodes 30 is formed in an elongated shape extending along the y-axis. In a plan view, the plurality of gate electrodes 20 and the plurality of source electrodes 30 are arranged alternately along the x-axis, forming a stripe structure. In Figure 5, the number of gate electrodes 20 and the number of source electrodes 30 are schematically illustrated to the extent that they can be counted. However, the actual number of gate electrodes 20 and source electrodes 30 is far greater than the number illustrated.

[0071] The semiconductor device 1 includes a plurality of gate finger portions 20b electrically connected to a plurality of gate electrodes 20. The plurality of gate finger portions 20b are arranged at both ends in the y-axis direction on the semiconductor layer 10 and are formed in an elongated shape extending along the x-axis direction. The plurality of gate finger portions 20b are connected to both ends in the y-axis direction of the plurality of gate electrodes 20.

[0072] The number of gate finger portions 20b is arbitrary. Therefore, a single gate finger portion 20b may be connected to only one end of a plurality of gate electrodes 20 in the y-axis direction. The plurality of gate electrodes 20 may be separated in the central part in the y-axis direction. In this case, the semiconductor device 1 may include gate finger portions 20b located in the inner part of the semiconductor layer 10 in a plan view. The inner gate finger portions 20b may extend along the x-axis direction through the region between a plurality of adjacent gate electrodes 20 in the y-axis direction. Furthermore, the inner gate finger portions 20b may be electrically connected to a plurality of adjacent gate electrodes 20 in the y-axis direction.

[0073] The semiconductor device 1 includes a main surface gate electrode 50 as an example of a first electrode electrically connected to a plurality of gate electrodes 20. The main surface gate electrode 50 is located above the plurality of gate electrodes 20 (on the positive side in the z-axis direction) and is electrically connected to the plurality of gate electrodes 20. The main surface gate electrode 50 may have an area of ​​20% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. Preferably, the main surface gate electrode 50 has an area of ​​10% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view.

[0074] Referring to Figure 4, the main surface gate electrode 50 may be formed in an H-shape in plan view. Specifically, the main surface gate electrode 50 includes a power receiving portion 50a, a power supply portion 50b, and a connection portion 50c. The power receiving portion 50a is located directly below the gate pad 70, which will be described later, and is the portion connected to the columnar portion 71 of the gate pad 70. In plan view, the portion of the main surface gate electrode 50 that overlaps with the columnar portion 71 of the gate pad 70 corresponds to the power receiving portion 50a.

[0075] The power supply sections 50b are positioned at both ends in the y-axis direction and are formed in an elongated shape extending along the x-axis direction. The power supply sections 50b are connected to the gate finger section 20b via via conductors (not shown) that penetrate the lower insulating layer 61, which will be described later.

[0076] The connection section 50c connects the power receiving section 50a and the power supply section 50b. The connection section 50c is formed in an elongated shape that extends along the y-axis direction. In the example shown in Figure 4, the connection section 50c is drawn out from the power receiving section 50a to the positive and negative sides in the y-axis direction, respectively, and extends to the power supply section 50b.

[0077] The main gate electrode 50 may contain a non-metallic conductor or a metal. Preferably, the main gate electrode 50 is formed of an aluminum-based metal material. Examples of aluminum-based metal materials for the main gate electrode 50 include aluminum, aluminum-silicon (Al-Si) alloys, aluminum-copper (Al-Cu) alloys, etc. Of course, the main gate electrode 50 may also be formed of conductive polysilicon, tungsten, titanium, nickel, copper, silver, gold, titanium nitride (metal nitride), etc. The main gate electrode 50 may be formed of the same material as the gate electrode 20.

[0078] The main gate electrode 50 may have a laminated structure including multiple metal layers. For example, the main gate electrode 50 may include a base layer and metal layers laminated in this order from the semiconductor layer 10 side. The base layer may be formed of a barrier metal such as titanium. The metal layer may be formed of an aluminum-based metal material formed on the base layer. The semiconductor device 1 may include a plating layer that covers the surface of the main gate electrode 50.

[0079] The semiconductor device 1 includes a main surface source electrode 55 as an example of a second electrode electrically connected to a plurality of source electrodes 30. The main surface source electrode 55 is located above the plurality of source electrodes 30 (on the positive side in the z-axis direction) and is electrically connected to the plurality of source electrodes 30. Referring to Figure 1, the main surface source electrode 55 is directly connected to the upper surface of the plurality of source electrodes 30.

[0080] The main surface source electrode 55 is positioned at a distance from the main surface gate electrode 50 in a plan view. The main surface source electrode 55 may be formed over almost the entire area of ​​the first main surface 11 in a plan view, excluding the area where the main surface gate electrode 50 is located and the surrounding area of ​​the area where the main surface gate electrode 50 is located.

[0081] The main surface source electrode 55 is formed with a larger area than the main surface gate electrode 50 in a plan view. The main surface source electrode 55 may have an area of ​​50% or more of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. Preferably, the main surface source electrode 55 has an area of ​​70% or more of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view.

[0082] The main surface source electrode 55 may contain a non-metallic conductor or a metal. The main surface gate electrode 50 is preferably formed of an aluminum-based metallic material. Examples of aluminum-based metallic materials for the main surface gate electrode 50 include aluminum, aluminum-silicon (Al-Si) alloys, aluminum-copper (Al-Cu) alloys, etc.

[0083] Of course, the main surface gate electrode 50 may be formed from conductive polysilicon, tungsten, titanium, nickel, copper, silver, gold, titanium nitride (metal nitride), etc. The main surface source electrode 55 may be formed from the same material as the main surface gate electrode 50. In this case, the main surface source electrode 55 can be formed in the same process as the main surface gate electrode 50.

[0084] The main surface source electrode 55 may have a laminated structure including multiple metal layers. The main surface source electrode 55 may include a base layer and metal layers laminated in this order from the semiconductor layer 10 side. The base layer may be formed of a barrier metal such as titanium. The metal layer may be formed of an aluminum-based metal material formed on the base layer. The semiconductor device 1 may include a plating layer that covers the surface of the main surface source electrode 55.

[0085] In this configuration, the main surface gate electrode 50 contains tungsten, and the main surface source electrode 55 contains tungsten. In other words, the active region 3 is covered by the main surface source electrode 55, which contains tungsten, a material with relatively high hardness. This allows the active region 3 to be protected by the main surface source electrode 55. Furthermore, damage to the FET structure caused by stress such as wire bonding can be suppressed in the active region 3. Such a structure is particularly effective when wire bonding with relatively hard copper wire is performed on the source pad 75, which will be described later.

[0086] As another example of a configuration, the portion of the main surface gate electrode 50 embedded in the through-hole (gate contact hole) may be formed of tungsten, while the portion of the main surface gate electrode 50 outside the through-hole (gate contact hole) may be formed of an aluminum-based metal material. The portion of the main surface gate electrode 50 outside the through-hole (gate contact hole) is the portion formed on the lower insulating layer 61 described later. The tungsten may be a pure metal or a tungsten alloy. Furthermore, the tungsten may be formed via a barrier film made of titanium / titanium nitride or the like.

[0087] Furthermore, the portion of the main surface source electrode 55 embedded in the source contact hole 61b may be formed of tungsten, while the portion of the main surface source electrode 55 outside the source contact hole 61b may be formed of an aluminum-based metal material. The portion of the main surface source electrode 55 outside the through hole (gate contact hole) is formed on the lower insulating layer 61, which will be described later. The tungsten may be a pure metal or a tungsten alloy. Also, the tungsten may be formed via a barrier film made of titanium / titanium nitride or the like.

[0088] In semiconductor device 1, the main surface source electrode 55 is positioned in a region including the center of the semiconductor layer 10 in a plan view, and the main surface gate electrode 50 is positioned in a region avoiding the main surface source electrode 55. However, the arrangement of the main surface gate electrode 50 and the main surface source electrode 55 is arbitrary and not limited to the above arrangement. For example, the main surface gate electrode 50 may be positioned in a region including the center of the semiconductor layer 10 in a plan view, and the main surface source electrode 55 may be positioned to surround the main surface gate electrode 50 in a plan view.

[0089] Referring to Figure 2, the insulating layer 60 includes a lower insulating layer 61, an upper insulating layer 63 as an example of a first insulating layer (first insulator), and an end insulating layer 65. The lower insulating layer 61 is an interlayer insulating film and is provided on the first main surface 11. Specifically, the lower insulating layer 61 covers multiple trench gate structures 21 collectively. Referring to Figure 1, the lower insulating layer 61 is provided to prevent the main surface source electrode 55 from contacting the gate electrode 20.

[0090] The lower insulating layer 61 has a plurality of source contact holes 61b. A portion of the main surface source electrode 55 is embedded in the plurality of source contact holes 61b and is electrically connected to the plurality of source electrodes 30 within the plurality of source contact holes 61b. The main surface source electrode 55 is also electrically connected to the source region 17 and the contact region 18 within the plurality of source contact holes 61b.

[0091] Although not shown in the diagram, the lower insulating layer 61 includes at least one (or more in this configuration) through-holes (gate contact holes) that expose the power supply portion 50b. A portion of the power supply portion 50b of the main surface gate electrode 50 (see Figure 4) is embedded in the multiple through-holes (gate contact holes) and is electrically connected to the gate finger portion 20b (see Figure 5) within the multiple through-holes (gate contact holes). This electrically connects the main surface gate electrode 50 to the gate electrode 20.

[0092] It is preferable that the multiple through holes (gate contact holes) are formed simultaneously with the multiple source contact holes 61b. In this case, the material and structure of the main surface gate electrode 50 (power supply section 50b) embedded in the multiple through holes (gate contact holes) are the same as the material and structure of the main surface source electrode 55 embedded in the multiple source contact holes 61b.

[0093] The upper insulating layer 63 covers a portion of the main surface gate electrode 50 and a portion of the main surface source electrode 55. The upper insulating layer 63 is interposed between the gate pad 70 (described later) and the main surface source electrode 55 so that the gate pad 70 does not come into contact with the main surface source electrode 55. The upper insulating layer 63 is also interposed between the source pad 75 (described later) and the main surface gate electrode 50 so that the source pad 75 does not come into contact with the main surface gate electrode 50.

[0094] The upper insulating layer 63 has through holes 64 that cover the connection portion 50c of the main surface gate electrode 50 and selectively expose the power receiving portion 50a. Specifically, the upper insulating layer 63 exposes a portion of the upper surface 52 of the power receiving portion 50a through the through holes 64. In this configuration, one through hole 64 is formed in the upper insulating layer 63 in a portion facing approximately the center of the gate pad 70.

[0095] The gate pad 70 is connected only to the upper surface 52 of the power receiving section 50a via the through hole 64. The planar shape of the through hole 64 (the planar shape of the columnar section 71 described later) may be a square or a rectangle. The length of one side of the through hole 64 in plan view may be 5 μm or more and 50 μm or less. As an example, the planar shape of the through hole 64 is a square of about 20 μm × 20 μm.

[0096] The through-hole 64 can have various layouts. Another example of the layout of the through-hole 64 is described below. Figure 8 is a plan view showing an example of the layout of the through-hole 64 relative to the gate pad 70. In Figure 8, the protective insulating layer 66 is omitted from the illustration. Referring to Figure 8, the through-hole 64 may be located near the edge of the gate pad 70. In this case, it is preferable that the bonding wire 303g (shown by a dashed line) is connected to the gate pad 70 so as not to overlap the through-hole 64 (columnar portion 71) in a plan view. This structure makes it possible to suppress the stress applied to the through-hole 64 (columnar portion 71) during wire bonding.

[0097] Figure 9 is a plan view showing another example of the layout of through holes 64 for the gate pad 70. Referring to Figure 9, the upper insulating layer 63 may have multiple through holes 64 for a single gate pad 70. In this case, the multiple through holes 64 (columnar portions 71) are formed in the region where the gate pad 70 and the main surface gate electrode 50 overlap in a plan view. This ensures that the gate pad 70 and the main surface gate electrode 50 are electrically connected. It is preferable that the bonding wire 303g (shown by dashed lines) is connected so as not to overlap at least some of the through holes 64 (columnar portions 71).

[0098] Referring again to Figure 2, the upper insulating layer 63 is interposed between the gate pad 70 and the main surface source electrode 55 with respect to the z-axis direction. This allows the upper insulating layer 63 to insulate the gate pad 70 from the main surface source electrode 55. The upper insulating layer 63 is formed (patterned) by etching, so that the side surface 63a of the upper insulating layer 63 is formed as a plane extending perpendicularly (in the z-axis direction) to the first main surface 11. Here, "perpendicular" means substantially perpendicular, not strictly perpendicular.

[0099] The end insulating layer 65 covers the outer periphery (peripheral portion) of the semiconductor device 1 (semiconductor layer 10). The end insulating layer 65 covers the entire outer periphery (peripheral portion) of the semiconductor device 1 (semiconductor layer 10). The end insulating layer 65 covers the power supply portion 50b of the main surface gate electrode 50. A portion of the end insulating layer 65 overlaps the lower insulating layer 61 and the main surface source electrode 55.

[0100] The lower insulating layer 61, the upper insulating layer 63, and the end insulating layer 65 may contain an inorganic insulating material. The inorganic insulating material may include silicon oxide or silicon nitride, etc. Silicon oxide includes PSG (Phosphor Silicate Glass), BPSG (Boron Phosphor Silicate Glass), etc. The lower insulating layer 61, the upper insulating layer 63, and the end insulating layer 65 may contain an organic insulating material. The organic insulating material may include polyimide or PBO (Polybenzaloxazole), etc.

[0101] The lower insulating layer 61, the upper insulating layer 63, and the end insulating layer 65 may be formed from the same insulating material, or from different insulating materials. For example, the lower insulating layer 61, the upper insulating layer 63, and the end insulating layer 65 may all be formed from silicon oxide. Of course, the lower insulating layer 61 may be formed from silicon oxide, while the upper insulating layer 63 and the end insulating layer 65 are formed from silicon nitride.

[0102] The thickness of the upper insulating layer 63 and the end insulating layer 65 may both be 3 μm or more and 20 μm or less. Preferably, the thickness of the upper insulating layer 63 and the end insulating layer 65 is 5 μm or more and 15 μm or less. Particularly preferable is that the thickness of the upper insulating layer 63 and the end insulating layer 65 is 5 μm or more and 10 μm or less.

[0103] The semiconductor device 1 includes a gate pad 70 as an example of a first electrode pad (first terminal electrode) electrically connected to the main surface gate electrode 50. The gate pad 70 overlaps the main surface gate electrode 50 in a plan view and is electrically connected to the main surface gate electrode 50. Specifically, the gate pad 70 is positioned such that the current-receiving portion 50a of the main surface gate electrode 50 is located inside the gate pad 70 in a plan view. That is, the gate pad 70 completely covers the current-receiving portion 50a of the main surface gate electrode 50.

[0104] Referring to Figure 2, the gate pad 70 includes a columnar portion 71 as an example of a lower conductive layer and a wide portion 72 as an example of an upper conductive layer. The columnar portion 71 is provided on the main surface gate electrode 50. Specifically, the columnar portion 71 is connected to the upper surface 52 of the power receiving portion 50a and is formed in a columnar shape extending in the direction normal to the upper surface 52 (z-axis direction). The height of the columnar portion 71 is equal to the thickness of the portion of the upper insulating layer 63 located on the power receiving portion 50a. In a plan view, the columnar portion 71 is formed with a gap inward from the periphery of the power receiving portion 50a. That is, the side surface 74 of the columnar portion 71 facing in the y-axis direction is located inside the main surface gate electrode 50 relative to the side surface 53 of the main surface gate electrode 50 facing in the y-axis direction.

[0105] The wide section 72 is provided at the upper end of the columnar section 71 and connects the power receiving section 50a and the columnar section 71. The wide section 72 is an extended portion of the upper end of the columnar section 71. In other words, the wide section 72 has a larger area than the columnar section 71 in a plan view. The wide section 72 is formed so that, in a plan view, the columnar section 71 is located inside the wide section 72. In a plan view, the size and shape of the wide section 72 match the size and shape of the gate pad 70.

[0106] The wide portion 72 is formed to extend outward from the power receiving portion 50a in a plan view. In this configuration, the wide portion 72 is formed in an umbrella shape that extends outward from the main surface gate electrode 50 in a direction perpendicular to the direction in which the main surface gate electrode 50 extends from the power receiving portion 50a (y-axis direction) (x-axis direction). In this configuration, the wide portion 72 extends in an umbrella shape on both the negative and positive sides in the x-axis direction.

[0107] As a result, the width of the wide portion 72 in the x-axis direction is greater than the width of the main surface gate electrode 50 in the x-axis direction. In other words, the gate pad 70 has an intersection that intersects with at least one side (two sides in this embodiment) of the main surface gate electrode 50 in a plan view. In a plan view, the portion of the upper surface 73 of the wide portion 72 that overlaps with the columnar portion 71 is recessed toward the main surface gate electrode 50.

[0108] The upper surface 73 of the wide portion 72 is used for electrical connections between the semiconductor device 1 and other circuits. For example, the upper surface 73 of the wide portion 72 is electrically connected to a power supply circuit that supplies the gate voltage. Metal wires may be connected to the upper surface 73 of the wide portion 72 by wire bonding. The metal wires may include at least one of aluminum, copper, and gold. In this embodiment, an aluminum wire is wedge-bonded to the gate pad 70 (upper surface 73 of the wide portion 72). Instead of wire bonding, a metal plate may be connected to the upper surface 73 of the wide portion 72 by solder.

[0109] The gate pad 70 has an area of ​​20% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. Preferably, the gate pad 70 has an area of ​​10% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. The wide portion 72 (area of ​​the gate pad 70) has a larger area than the area of ​​the power receiving portion 50a (i.e., columnar portion 71) in a plan view. The area of ​​the wide portion 72 may be 200 times or more and 40,000 times or less of the area of ​​the power receiving portion 50a. Preferably, the area of ​​the wide portion 72 is 400 times or more of the area of ​​the power receiving portion 50a. As an example, the area of ​​the wide portion 72 may be about 2,500 times the area of ​​the power receiving portion 50a.

[0110] For proper wire bonding, the wide portion 72 (gate pad 70) must have a certain minimum size. Preferably, the wide portion 72 has an area of ​​800 μm × 800 μm or more and 1 mm × 1 mm or less in plan view. In this case, the wide portion 72 may be formed in a square shape in plan view. In this case, the orientation of the metal wire connection can be set in any direction. Of course, the wide portion 72 may be formed in a square shape larger than 1 mm × 1 mm in plan view. Also, the wide portion 72 may be formed in a rectangular shape of 400 μm × 800 μm or more.

[0111] The columnar portion 71 and the wide portion 72 may be formed from the same conductive material. The columnar portion 71 and the wide portion 72 may be formed from an aluminum-based metal material. Of course, the columnar portion 71 and the wide portion 72 may be formed from titanium, nickel, copper, silver, gold, tungsten, etc. The columnar portion 71 and the wide portion 72 may be formed from different conductive materials.

[0112] The height of the gate pad 70 may be between several tens of micrometers and several hundred micrometers (i.e., between 20 micrometers and less than 1,000 micrometers). The height of the gate pad 70 (length in the z-axis direction) is calculated by the sum of the height of the columnar portion 71 (length in the z-axis direction) and the thickness of the wide portion 72 (length in the z-axis direction). Figure 2 shows an example where the height of the columnar portion 71 is equal to the thickness of the wide portion 72, but the height of the columnar portion 71 may be greater than or less than the thickness of the wide portion 72.

[0113] The semiconductor device 1 includes a source pad 75 as an example of a second electrode pad (second terminal electrode) electrically connected to the main surface source electrode 55. In a plan view, the source pad 75 overlaps the main surface source electrode 55 and is electrically connected to the main surface source electrode 55. The source pad 75 is provided on the main surface source electrode 55. In other words, the source pad 75 covers the upper surface 56 of the main surface source electrode 55. The source pad 75 is formed in a plate shape with its thickness direction being the normal direction (z-axis direction) of the upper surface 56 of the main surface source electrode 55, and extends along the upper surface 56.

[0114] The source pad 75 is positioned in a region that includes the center of the semiconductor layer 10 (first main surface 11) in a plan view. The source pad 75 is positioned in a region that avoids the gate pad 70. In this embodiment, the gate pad 70 is positioned in a region that includes the center of the semiconductor layer 10 (first main surface 11), and the source pad 75 is positioned to surround the gate pad 70.

[0115] The negative end 79 of the source pad 75 in the x-axis direction overlaps the upper insulating layer 63 from above the main surface source electrode 55. The side surface 77 of the source pad 75 is located on the upper insulating layer 63. The source pad 75 has an area smaller than the area of ​​the main surface source electrode 55 in a plan view. The source pad 75 has an area larger than the area of ​​the gate pad 70 in a plan view. The source pad 75 has an area of ​​50% or more of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. Preferably, the source pad 75 has an area of ​​70% or more of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view.

[0116] In a plan view, the source pad 75 is positioned at a distance from the gate pad 70 and forms a gap between it and the gate pad 70 above the main surface source electrode 55, exposing the upper insulating layer 63. The gap is defined by the portion of the side surface of the gate pad 70 located above the main surface source electrode 55, and the portion of the side surface 77 of the source pad 75 located above the main surface source electrode 55.

[0117] This prevents short circuits caused by contact between the gate pad 70 and the source pad 75 above the main surface source electrode 55, and allows for stable formation of the source pad 75. In this embodiment, the side surface 77 of the source pad 75 is formed as a plane extending perpendicular or substantially perpendicular to the first main surface 11. However, the side surface 77 does not necessarily have to be flat, and may be a curved or uneven surface.

[0118] The top surface 76 of the source pad 75 is used for electrical connections between the semiconductor device 1 and other circuits. For example, the top surface 76 of the source pad 75 is connected to a power supply circuit that supplies the source voltage. Metal wires may be connected to the top surface 76 of the source pad 75 by wire bonding. The metal wires may include at least one of aluminum, copper, and gold. For example, in this embodiment, an aluminum wire is wedge-bonded to the source pad 75. Instead of wire bonding, a metal plate may be connected to the source pad 75 by solder.

[0119] The source pad 75 is formed of a conductive material. The source pad 75 may be formed of an aluminum-based metal material. Of course, the source pad 75 may be formed of titanium, nickel, copper, silver, gold, tungsten, etc. The source pad 75 may be formed of the same material as the gate pad 70. In this case, the source pad 75 can be formed in the same process as the gate pad 70. Of course, the source pad 75 may be formed of a different material than the gate pad 70.

[0120] Preferably, the gate pad 70 is formed in the same process as the source pad 75. In this case, the structure and material of the gate pad 70 will be the same as that of the source pad 75. If the source pad 75 is wire-bonded with aluminum wire, it is preferable that the source pad 75 be made of an aluminum-based material. In this case, the gate pad 70 will be made of an aluminum-based material, similar to the source pad 75.

[0121] When the source pad 75 is connected to a metal plate by solder, a plating layer may be formed on the surface of the source pad 75. In this case, the source pad 75 may be made of an aluminum-based metal material. The plating layer may also include at least one of nickel plating and gold plating. The plating layer may have a single-layer structure consisting of nickel plating, or it may have a layered structure including nickel plating and gold plating, which are stacked in this order from the source pad 75 side.

[0122] In this case, the gate pad 70 may have the same configuration as the source pad 75. That is, a plating layer may be formed on the surface of the gate pad 70. In this case, the gate pad 70 may be made of an aluminum-based metal material. The plating layer may also include at least one of nickel plating and gold plating. The plating layer may have a single-layer structure consisting of nickel plating, or it may have a layered structure including nickel plating and gold plating stacked in this order from the gate pad 70 side.

[0123] When the source pad 75 is connected to a metal plate by a sintered material such as Ag, a plating layer may be formed on the surface of the source pad 75. In this case, the source pad 75 may be made of an aluminum-based metal material. The plating layer may also include at least one of nickel plating, palladium plating, and gold plating. For example, the plating layer may have a laminated structure including nickel plating, palladium plating, and gold plating, stacked in this order from the source pad 75 side.

[0124] In this case, the gate pad 70 may have the same configuration as the source pad 75. That is, a plating layer may be formed on the surface of the gate pad 70. In this case, the gate pad 70 may be made of an aluminum-based metal material. The plating layer may also include at least one of nickel plating, palladium plating, and gold plating. For example, the plating layer may have a laminated structure including nickel plating, palladium plating, and gold plating, stacked in this order from the gate pad 70 side.

[0125] Here, an example is shown in which the gate pad 70 and source pad 75 include an aluminum-based material, but the gate pad 70 and source pad 75 may be formed from a metallic material such as copper or nickel instead of an aluminum-based material. In other words, the gate pad 70 may include a columnar portion 71 and a wide portion 72 formed from a metallic material such as copper or nickel.

[0126] The main surface gate electrode 50, main surface source electrode 55, gate pad 70, and source pad 75 can be formed in various layouts, not limited to those described above. Figure 10 is a plan view showing another layout example of the gate pad 70 and the power receiving portion 50a. In other words, Figure 10 shows another layout example of the main surface gate electrode 50 and the main surface source electrode 55. Referring to Figure 10, the power receiving portion 50a of the main surface gate electrode 50 may be located at the outermost periphery (periphery) of the semiconductor device 1 (chip, semiconductor layer 10).

[0127] The wide portion 72 may be formed in an umbrella shape that extends only on the positive side in the x-axis direction. In other words, the gate pad 70 has an intersection that intersects at least one side (one side in this embodiment) of the main surface gate electrode 50 in a plan view. In the layout example of Figure 10, the main surface source electrode 55 is formed in a rectangular shape in a plan view, and the main surface gate electrode 50 is formed in a rectangular ring shape that surrounds the main surface source electrode 55 in a plan view.

[0128] Figure 11 is a plan view showing yet another layout example of the main surface gate electrode 50 and the main surface source electrode 55. Figure 11 is an example in which, in addition to the layout example of Figure 10, the main surface gate electrode 50 has a portion that extends in the x-axis direction from the power receiving portion 50a. Thus, the arrangement of the main surface gate electrode 50 and the main surface source electrode 55, and the arrangement of the gate pad 70 relative to the main surface gate electrode 50 and the main surface source electrode 55, can take various forms.

[0129] Referring again to Figures 2 to 5, the semiconductor device 1 includes an active region 3 and an inactive region 4. In Figures 3 and 5, the active region 3 is indicated by the area enclosed by the dashed line. The active region 3 is the region where the FET structure is formed and is the main region through which the drain current of the vertical transistor 2 flows. The active region 3 roughly coincides with the region covered by the main surface source electrode 55. The inactive region 4 is the region other than the active region 3. The region where the main surface gate electrode 50 is located and the voltage-bearing structure region on the outer periphery (peripheral side) are the inactive region 4.

[0130] In semiconductor devices, a gate pad 70 of a certain size is generally required for wire bonding of metal wires. If the main surface gate electrode 50 is formed to be approximately the same size as the gate pad 70, the main surface source electrode 55 will be formed to be relatively small. Since the size of the active region 3 is approximately the same as the size of the main surface source electrode 55, increasing the size of the main surface gate electrode 50 will cause the main surface source electrode 55 to shrink, and the active region 3 to become smaller. As a result, the semiconductor layer 10 cannot be used effectively, which hinders the miniaturization and cost reduction of semiconductor devices.

[0131] In contrast, in semiconductor device 1, while a main surface gate electrode 50 is formed, a gate pad 70 (wide portion 72) that intersects the active region 3 in three dimensions is provided. With this structure, the target of wire bonding is changed from the main surface gate electrode 50 to the gate pad 70. This makes it possible to reduce the size of the main surface gate electrode 50 and expand the active region 3. In other words, in semiconductor device 1, the gate pad 70 relaxes the design rules caused by the main surface gate electrode 50, increasing the degree of design freedom.

[0132] Specifically, a portion of the gate pad 70 (the wider portion 72) overlaps the main surface source electrode 55 in a plan view. More specifically, in a plan view, the gate pad 70 has a width greater than the width of the main surface gate electrode 50 in the x-axis direction and overlaps a portion of the main surface source electrode 55. This reduces the area of ​​the main surface gate electrode 50 and expands the area of ​​the active region 3. Furthermore, the gate pad 70 can be formed to a certain size or larger while avoiding design rules caused by the main surface gate electrode 50. Therefore, by effectively utilizing the limited area of ​​the semiconductor layer 10, a semiconductor device 1 that is easily miniaturized and cost-effective can be realized.

[0133] Referring to Figure 3, the semiconductor device 1 includes a protective insulating layer 66 as an example of a second insulating layer (second insulator) formed on the upper insulating layer 63. The protective insulating layer 66 covers the boundary portion 80 (gap) between the gate pad 70 and the source pad 75. That is, the protective insulating layer 66 includes a portion that covers the upper insulating layer 63 within the boundary portion 80 between the gate pad 70 and the source pad 75 above the main surface source electrode 55. The protective insulating layer 66 has a portion that faces the main surface source electrode 55 with the upper insulating layer 63 in between within the boundary portion 80.

[0134] The boundary portion 80 is formed in a rectangular annular shape in a plan view. Therefore, the protective insulating layer 66 is formed in a rectangular annular shape in the portion that covers the boundary portion 80. Furthermore, the protective insulating layer 66 covers the entire outer periphery (peripheral edge) of the semiconductor device 1 (first main surface 11). The protective insulating layer 66 may contain an organic insulating material. The protective insulating layer 66 may contain polyimide, PBO, or the like.

[0135] Figure 12 is an enlarged cross-sectional view of the outer periphery of the semiconductor device 1 (first main surface 11), and shows region XII of Figure 2 in more detail. Referring to Figure 12, in the outer periphery of the semiconductor device 1 (first main surface 11), the positive end of the end insulating layer 65 in the x-axis direction overlaps the main surface source electrode 55 so that it is located on the main surface source electrode 55. The negative end of the source pad 75 in the x-axis direction is located on the positive end of the end insulating layer 65 in the x-axis direction. The protective insulating layer 66 covers the positive end of the end insulating layer 65 in the x-axis direction and the negative end of the source pad 75 in the x-axis direction.

[0136] Under conditions that satisfy at least one of high voltage, high temperature, and high humidity, migration of impurities within the module gel and infiltration of water into the module gel may occur. If the structure of the outer periphery (periphery) of the semiconductor layer 10 deteriorates due to the effects of temperature cycling or humidity, the above-mentioned substances (elements) may enter the device starting from the deteriorated area, potentially causing problems such as short circuits, discharges, and failures.

[0137] In semiconductor device 1, the outer periphery of the semiconductor layer 10 is covered in a predetermined pattern by a lower insulating layer 61, a protective insulating layer 66, and an end insulating layer 65 (upper insulating layer 63). Therefore, compared to the case where the outer periphery of the semiconductor layer 10 is covered by the lower insulating layer 61 and the protective insulating layer 66, deterioration of the outer periphery is suppressed. In other words, the intrusion of moisture and other substances originating from deteriorated areas is suppressed, and the reliability of semiconductor device 1 is improved.

[0138] Figures 13A to 13E are cross-sectional views showing each step in the manufacturing process of the semiconductor device 1. The following description mainly focuses on the manufacturing method of the upper structure of the semiconductor layer 10. Known methods are used to form the trench gate structure 21, the trench source structure 31, and various semiconductor regions (each well region) on the semiconductor layer 10.

[0139] First, referring to Figure 13A, a lower insulating layer 61 having a plurality of source contact holes 61b is formed on the first main surface 11 of the semiconductor layer 10. The process for forming the lower insulating layer 61 includes, for example, a step of depositing an insulating film such as silicon oxide by plasma CVD (Chemical Vapor Deposition), and a step of removing a portion of the deposited insulating film (silicon oxide) by photolithography and etching. As a result, the insulating film is patterned, and a lower insulating layer 61 having a predetermined pattern is formed.

[0140] Next, referring to Figure 13B, the main surface gate electrode 50 and the main surface source electrode 55 are formed on the lower insulating layer 61 with a gap between them. The process for forming the main surface gate electrode 50 and the main surface source electrode 55 includes, for example, a step of depositing a metal film over the entire surface of the first main surface 11 by vapor deposition or sputtering so as to cover the lower insulating layer 61, and a step of removing a portion of the metal film after deposition by photolithography and etching.

[0141] This process patterns the metal film, forming a main surface gate electrode 50 having a predetermined pattern and a main surface source electrode 55 having a predetermined pattern. The main surface gate electrode 50 and the main surface source electrode 55 may be formed through different processes by repeating the metal film deposition process and the patterning process using different materials.

[0142] Next, referring to Figure 13C, an upper insulating layer 63 and an end insulating layer 65 having through holes 64 are formed on the lower insulating layer 61. The process for forming the upper insulating layer 63 and the end insulating layer 65 includes, for example, a step of depositing an insulating film such as silicon oxide by plasma CVD, and a step of removing a portion of the deposited insulating film (silicon oxide) by photolithography and etching.

[0143] The upper insulating layer 63 and the end insulating layer 65 may be formed from an organic insulating material (for example, a photosensitive resin material such as polyimide). In this case, the process for forming the upper insulating layer 63 and the end insulating layer 65 includes, for example, the steps of applying a liquid photosensitive resin material, which will be the basis of each insulating layer, to the upper surface 52 of the main surface gate electrode 50 and the upper surface 56 of the main surface source electrode 55 by a spin coating method, and curing the applied photosensitive resin material by exposure, and then removing the cured photosensitive resin material by development (for example, a wet etching method).

[0144] Next, referring to Figure 13D, a metal film 78 is formed over the entire surface of the first main surface 11 so as to cover the upper insulating layer 63. The metal film 78 is formed, for example, by vapor deposition or sputtering.

[0145] Next, referring to Figure 13E, a portion of the metal film 78 after deposition is removed by photolithography and etching. This patterns the metal film 78, forming a gate pad 70 and a source pad 75 having a predetermined pattern. The gate pad 70 and source pad 75 may be formed through different processes by repeating the metal film deposition process and patterning process using different materials.

[0146] Next, a liquid organic insulating material (photosensitive resin material) that will form the protective insulating layer 66 is applied to the upper surface of the semiconductor layer 10 in the state shown in Figure 13E by spin coating. Then, the applied photosensitive resin material is cured by exposure, and the cured photosensitive resin material is removed by development (for example, wet etching). This forms a protective insulating layer 66 having a predetermined pattern.

[0147] Next, a drain electrode 40 covering the second main surface 12 is formed. The drain electrode 40 is formed (film-formed) by, for example, a vapor deposition method or a sputtering method. Subsequently, the semiconductor layer 10 is cut by a dicing blade or a laser irradiation method, and the semiconductor device 1 is cut out from the semiconductor layer 10. The semiconductor device 1 is manufactured through the above process.

[0148] Figure 14 is a cross-sectional view showing a modified example of the structure of the outer periphery (periphery) of the semiconductor device 1 (semiconductor layer 10). In Figure 12, an example is shown in which the protective insulating layer 66 rests on top of the source pad 75. However, the protective insulating layer 66 may be spaced apart from the source pad 75 so that the end insulating layer 65 is exposed in the region between it and the source pad 75. In this case, the end insulating layer 65 may be an inorganic insulating film. The source pad 75 may also be made of an aluminum-based metal. In this case, a bonding wire may be bonded to the source pad 75.

[0149] When a metal plate is joined to the source pad 75 by solder, a nickel / gold plating layer or a nickel / palladium / gold plating layer may be laminated on the source pad 75. The dashed line in Figure 14 shows the plating layer when the plating layer is laminated on the source pad 75. According to the configuration in Figure 14, the plating layer can be formed more stably compared to the configuration in Figure 12.

[0150] As described above, the semiconductor device 1 includes a vertical transistor 2. The semiconductor device 1 includes a semiconductor layer 10, a main surface gate electrode 50, a main surface source electrode 55, a gate pad 70, and a drain electrode 40. The semiconductor layer 10 mainly contains SiC and has a first main surface 11 and a second main surface 12 opposite to the first main surface 11. The main surface gate electrode 50 covers a portion of the first main surface 11.

[0151] The main surface source electrode 55 covers a portion of the first main surface 11 at a distance from the main surface gate electrode 50. The gate pad 70 is provided on the side opposite to the semiconductor layer 10 relative to the main surface gate electrode 50 such that at least a portion of it overlaps with the main surface gate electrode 50 in a plan view, and is electrically connected to the main surface gate electrode 50. The gate pad 70 also overlaps a portion of the main surface source electrode 55 in a plan view.

[0152] From another perspective, the semiconductor device 1 includes a semiconductor layer 10, a vertical transistor 2 (switching element), a main surface gate electrode 50 (first electrode), a main surface source electrode 55 (second electrode), a gate pad 70 (first terminal electrode), a source pad 75 (second terminal electrode), and a drain electrode 40. The semiconductor layer 10 has a first main surface 11 (main surface). The vertical transistor 2 is formed on the semiconductor layer 10. The main surface gate electrode 50 is positioned on the first main surface 11 and is electrically connected to the vertical transistor 2.

[0153] The main surface source electrode 55 is positioned on the first main surface 11 at a distance from the main surface gate electrode 50 and is electrically connected to the vertical transistor 2. The gate pad 70 has a portion that overlaps with the main surface gate electrode 50 and a portion that overlaps with the main surface source electrode 55 in a plan view, and is electrically connected to the main surface gate electrode 50. The source pad 75 has a portion that overlaps with the main surface source electrode 55 in a plan view and is electrically connected to the main surface source electrode 55. The drain electrode 40 is electrically connected to the second main surface 12.

[0154] If, for example, the main surface gate electrode 50 is used as the electrode pad for wire bonding instead of the gate pad 70 according to the above embodiment (i.e., in the conventional configuration), then a main surface gate electrode 50 having the same size as the gate pad 70 is required. Since the region of the semiconductor layer 10 covered by the main surface gate electrode 50 becomes an inactive region 4, the area available for use as an active region 3 is reduced. As a result, the effective use of the semiconductor layer 10 is hindered, which is detrimental to miniaturization and cost reduction.

[0155] In contrast, semiconductor device 1 has a gate pad 70 that overlaps the main surface gate electrode 50 and the main surface source electrode 55 in a plan view. With this structure, the design rules for the main surface gate electrode 50 are relaxed by the gate pad 70, and the area of ​​the main surface gate electrode 50 can be reduced. This allows the active region 3 to be expanded. Furthermore, with this structure, the gate pad 70 on which wire bonding is performed can be formed to a certain size or larger while avoiding the design rule limitations caused by the main surface gate electrode 50.

[0156] In other words, in semiconductor device 1, the design rules related to the main surface gate electrode 50, etc., are relaxed, increasing the degree of design freedom. With this configuration, it becomes unnecessary to increase the chip size in order to expand the active region 3. That is, the active region 3 can be expanded while avoiding an increase in chip size. Therefore, it is possible to provide a semiconductor device 1 that can be miniaturized and cost-reduced by effectively utilizing the semiconductor layer 10.

[0157] The vertical transistor 2 may include a source, a gate, and a drain. Specifically, the vertical transistor 2 may include a source region 17 formed on the surface of the semiconductor layer 10 on the first main surface 11 side, a gate insulating layer 23 (gate insulating film) covering the source region 17, a gate electrode 20 facing the source region 17 across the gate insulating layer 23, and a drain region formed within the semiconductor layer 10. In such a structure, the main surface gate electrode 50 is electrically connected to the gate electrode 20, the main surface source electrode 55 is electrically connected to the source region 17, and the drain electrode 40 is electrically connected to the drain region.

[0158] The semiconductor device 1 may include an upper insulating layer 63 located between the gate pad 70 and the main surface source electrode 55 in a direction perpendicular to the first main surface 11. This structure allows the upper insulating layer 63 to realize a configuration in which the gate pad 70 overlaps a portion of the main surface source electrode 55 in a plan view. The side surface 63a of the upper insulating layer 63 may be a plane extending along a direction perpendicular to the first main surface 11. This structure allows the upper insulating layer 63 to be formed by an etching method.

[0159] When the source pad 75 is electrically connected to the main surface source electrode 55, it is preferable that the end portion 79 of the source pad 75 on the gate pad 70 side is located on the upper insulating layer 63. This structure allows for stable formation of the source pad 75. Specifically, the shape of the source pad 75 can be easily adjusted.

[0160] The semiconductor device 1 may include a protective insulating layer 66 that covers the boundary portion 80 (gap) between the gate pad 70 and the source pad 75. This structure suppresses the intrusion of moisture and other substances into the boundary portion 80. Therefore, the reliability of the semiconductor device 1 is improved. In this case, the portion of the protective insulating layer 66 located at the boundary portion 80 may face the main surface source electrode 55 with an upper insulating layer 63 in between.

[0161] The method for manufacturing the semiconductor device 1 includes a first step, a second step, and a third step. The semiconductor layer 10, which mainly contains SiC, is prepared in the first step, having a first main surface 11 and a second main surface 12 opposite to the first main surface 11. The semiconductor layer 10 includes a vertical transistor 2. In the second step, a main surface gate electrode 50 and a main surface source electrode 55 are formed on the first main surface 11 with a gap between them.

[0162] In the third step, a gate pad 70 is formed in the region opposite to the semiconductor layer 10 relative to the main surface gate electrode 50 so as to be electrically connected to the main surface gate electrode 50. The gate pad 70 is formed so as to overlap at least a portion of the main surface gate electrode 50 and a portion of the main surface source electrode 55 in a plan view. This manufacturing method makes it possible to manufacture and provide a semiconductor device 1 that can expand the active region 3 while avoiding an increase in chip size.

[0163] In Embodiment 1, an example was shown in which the wide portion 72 spreads out in an umbrella shape on both the negative and positive sides in the x-axis direction (see Figure 3, etc.). However, the wide portion 72 may also have a configuration in which it spreads out in an umbrella shape only on the positive side in the x-axis direction (see Figure 10). In this configuration as well, the gate pad 70 (wide portion 72) is provided so as to overlap the active region 3 (main surface source electrode 55) in a plan view.

[0164] In Embodiment 1, an example was shown in which the main surface gate electrode 50 extends from the power receiving portion 50a in the y-axis direction (see Figure 3, etc.). However, the main surface gate electrode 50 may also have a configuration that extends from the power receiving portion 50a in the x-axis direction in addition to the y-axis direction (see Figure 11). In this configuration as well, the gate pad 70 (wide portion 72) is provided so as to overlap the active region 3 (main surface source electrode 55) in a plan view.

[0165] Figure 15 is a cross-sectional view of the semiconductor device 101 according to Embodiment 2. Figure 15 shows a cross-section along the line XV-XV in Figure 16. Figure 16 is a plan view of the semiconductor device 101 according to Embodiment 2. In Figure 16, the outer edge 70b of the gate pad, the outer edge 75a of the source pad 75, the inner edge 75b of the source pad 75, and the outer edge 170b of the current sensing pad 170 are shown by dashed lines.

[0166] Figure 17 is a plan view obtained by removing the protective insulating layer 66 from the plan view shown in Figure 16. In Figure 17, the main surface source electrode 55 is shown by a dashed line. Figure 18 is a plan view of the electrode top surface of the semiconductor device 101 in a plane parallel to the substrate surface, as seen from the position of line XVIII-XVIII in Figure 15. Figure 18 is a plan view of the semiconductor device 101 as seen from the positive z-axis side, with the gate pad 70, source pad 75, and current sensing pad 170 shown in Figure 16 visible through them.

[0167] Although not shown in Figures 15 to 18, the semiconductor device 101, like Embodiment 1, includes a vertical transistor 2 that conducts current in the thickness direction of the semiconductor layer 10. The semiconductor device 101 (Embodiment 2) differs from the semiconductor device 1 (Embodiment 1) mainly in that it further includes an electrode for current detection and an electrode pad connected to the current detection electrode. In the semiconductor device 101, the current detection electrode is formed to be smaller than the electrode pad. In the following, the differences from Embodiment 1 will be explained in detail, and the explanation of common points will be omitted or simplified.

[0168] Referring to Figures 15 to 18, the semiconductor device 101 includes a main surface gate electrode 50 (first electrode), a main surface source electrode 55 (second electrode), and a current sensing electrode 150 as an example of a third electrode. The arrangement or shape of the main surface gate electrode 50 and the main surface source electrode 55 differs from that of Embodiment 1, but are substantially the same. A description of the main surface gate electrode 50 and the main surface source electrode 55 is omitted.

[0169] The current sensing electrode 150 is positioned at a distance from the main surface gate electrode 50 and the main surface source electrode 55 in a plan view. The current sensing electrode 150 may be positioned on the outer periphery (periphery) of the semiconductor layer 10 (first main surface 11) in a plan view. The current sensing electrode 150 may be positioned in a region including the center of the semiconductor layer 10 (first main surface 11) in a plan view. The current sensing electrode 150 may be positioned in a region surrounded by the main surface source electrode 55 in a plan view. In other words, the main surface source electrode 55 may be positioned to surround the current sensing electrode 150 in a plan view.

[0170] The current sensing electrode 150 corresponds to a portion of the main surface source electrode 55 that has been separated according to Embodiment 1. Although not shown in the figures, an FET structure is formed below the current sensing electrode 150. The FET structure on the current sensing electrode 150 side is formed in the same manner as the FET structure formed below the main surface source electrode 55 (see also Figures 1 and 2).

[0171] In other words, in this configuration, the FET structure includes a main cell region located below the main surface source electrode 55, and a current sensing cell region (sense cell region) located below the current sensing electrode 150. The main cell region conducts the drain current. The current sensing cell region is formed to detect the drain current. In other words, the semiconductor device 101 includes a main cell region provided on the first main surface 11, and a current sensing cell region provided on the first main surface 11 in a region different from the main cell region.

[0172] The FET structure is formed in the main cell region and the current sensing cell region, respectively. The FET structure in the main cell region is formed as the main FET structure (main element) that generates the drain current as the main current. The FET structure in the current sensing cell region is formed as the sense FET structure (sense element) that generates a sense current to detect the drain current. In this configuration, the FET structure in the main cell region and the FET structure in the current sensing cell region have the same structure.

[0173] The main surface source electrode 55 is positioned in a region that overlaps with the main cell region (main FET structure) in a plan view and is electrically connected to the source region 17 of the main cell region (main FET structure). The current sensing electrode 150 is positioned in a region that overlaps with the current sensing cell region (sense FET structure) in a plan view and is electrically connected to the source region 17 of the current sensing cell region (sense FET structure).

[0174] In the vertical transistor 2 of the semiconductor device 101, a drain current flows from the drain electrode 40 towards the source region 17 on the main cell side, and a sense current flows from the drain electrode 40 towards the source region 17 on the sense cell side. As a result, the drain current is extracted from the main surface source electrode 55, and the sense current is extracted from the current sensing electrode 150.

[0175] The sense FET structure may be configured to generate a sense current linked to the drain current by being controlled on and off simultaneously with the main FET structure. In other words, the same gate voltage may be applied simultaneously to the main cell region and the current sensing cell region. The main cell region has a larger area than the current sensing cell region. In this configuration, the only difference between the main cell region and the current sensing cell region is the area. Therefore, a current flows through the current sensing cell region in proportion to the area ratio of the main cell region and the current sensing cell region.

[0176] In other words, the sense current of the sense FET structure may be less than the main current of the main FET structure. The area of ​​the main cell region may be 100 times or more but not exceeding 10,000 times the area of ​​the current sensing cell region. In this case, a current of 1 / 10,000 to 1 / 100 of the current (drain current) flowing through the main surface source electrode 55 flows through the current sensing electrode 150.

[0177] This allows the current flowing through the current sensing electrode 150 to be reduced even if a relatively large drain current is generated due to some factor. For example, the maximum amount of current flowing through the current sensing electrode 150 can be limited to about 1A. This makes it possible to appropriately detect an increase in current within a predetermined current detection range using the current sensing electrode 150.

[0178] The current sensing electrode 150 may contain a non-metallic conductor or a metal. Preferably, the current sensing electrode 150 is formed from an aluminum-based metal material. Examples of aluminum-based metal materials for the current sensing electrode 150 include aluminum, aluminum-silicon (Al-Si) alloys, aluminum-copper (Al-Cu) alloys, etc. Of course, the current sensing electrode 150 may also be formed from conductive polysilicon, tungsten, titanium, nickel, copper, silver, gold, titanium nitride (metal nitride), etc. The current sensing electrode 150 may be formed from the same material as the main surface gate electrode 50 and the main surface source electrode 55.

[0179] Referring to Figure 15, the current sensing electrode 150 is provided on a lower insulating layer 61 having one or more source contact holes 61b. The current sensing electrode 150 is electrically connected to the source region 17 of the current sensing cell region via the source contact holes 61b.

[0180] The current sensing electrode 150 is smaller than the current sensing pad 170, which will be described later, in a plan view. The planar shape of the current sensing electrode 150 may be square or rectangular. The length of one side of the current sensing electrode 150 may be between 5 μm and 50 μm. For example, the planar shape of the current sensing electrode 150 may be a square of about 20 μm × 20 μm. Referring to Figure 18, in this configuration, the current sensing electrode 150 has the same size as the current receiving portion 50a of the main surface gate electrode 50.

[0181] Of course, the size of the current sensing electrode 150 may be smaller than the size of the power receiving section 50a. The size of the current sensing electrode 150 may be larger than the size of the power receiving section 50a. The current sensing electrode 150 may have an area of ​​20% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. Preferably, the current sensing electrode 150 has an area of ​​10% or less of the area of ​​the semiconductor layer 10 (first main surface 11).

[0182] Referring to Figures 15 to 17, the semiconductor device 101 includes a gate pad 70 (first electrode pad), a source pad 75 (second electrode pad), and a current sensing pad 170 as an example of a third electrode pad. The arrangement and shape of the gate pad 70 and the source pad 75 differ from those in Embodiment 1, but are substantially the same. A description of the gate pad 70 and the source pad 75 is omitted.

[0183] The current sensing pad 170 overlaps the current sensing electrode 150 in a plan view and is electrically connected to the current sensing electrode 150. The current sensing pad 170 is spaced apart from the gate pad 70 and the source pad 75. The current sensing pad 170 may be located in a region that includes the center of the semiconductor layer 10 (first main surface 11) in a plan view. The current sensing pad 170 may be located in a region surrounded by the source pad 75. In other words, the source pad 75 may be located so as to surround the current sensing pad 170.

[0184] In this embodiment, the current sensing pad 170 has a configuration similar to that of the gate pad 70. Referring to Figure 15, the current sensing pad 170 specifically includes a columnar portion 171 as an example of a lower conductive layer, and a wide portion 172 as an example of an upper conductive layer. The columnar portion 171 is provided on the current sensing electrode 150. The columnar portion 171 is connected to the upper surface 152 of the current sensing electrode 150 and is formed in a columnar shape extending in the direction normal to the upper surface 152 (in the z-axis direction). The columnar portion 171 is connected to the current sensing electrode 150 via a through hole 164 provided in the upper insulating layer 63.

[0185] The height (length in the z-axis direction) of the columnar portion 171 is greater than the thickness (length in the z-axis direction) of the upper insulating layer 63. Specifically, the height of the columnar portion 171 is equal to the thickness of the portion of the upper insulating layer 63 located on the current sensing electrode 150. The side surface 174 of the columnar portion 171 may be flush with the side surface 153 of the current sensing electrode 150. The side surface 174 of the columnar portion 171 may be located inside the current sensing electrode 150 relative to the side surface 153 of the current sensing electrode 150.

[0186] The wide portion 172 is provided at the upper end of the columnar portion 171. The wide portion 172 is an extended portion of the upper end of the columnar portion 171. In other words, the wide portion 172 has a larger area than the columnar portion 171 in a plan view. The wide portion 172 is formed such that, in a plan view, the columnar portion 171 is located inside the wide portion 172. In a plan view, the size and shape of the wide portion 172 match the size and shape of the current sensing pad 170. In a plan view, the portion of the upper surface 173 of the wide portion 172 that overlaps with the columnar portion 171 is recessed toward the current sensing electrode 150.

[0187] The upper surface 173 of the wide portion 172 is used for electrical connections between the semiconductor device 101 and other circuits. For example, the upper surface 173 of the wide portion 172 is connected to a control circuit that controls the semiconductor device 101 based on the detected current. Metal wires may be connected to the upper surface 173 of the wide portion 172 by wire bonding. The metal wires may include at least one of aluminum, copper, and gold. In this embodiment, an aluminum wire is wedge-bonded to the current sensing pad 170 (upper surface 173 of the wide portion 172). Instead of wire bonding, a metal plate may be connected to the upper surface 173 of the wide portion 172 by solder.

[0188] The current sensing pad 170 has an area of ​​20% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. Preferably, the current sensing pad 170 has an area of ​​10% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. The wide portion 172 (i.e., the current sensing pad 170) has a larger area than the area of ​​the current sensing electrode 150 in a plan view. The area of ​​the wide portion 172 may be 200 times or more and 40,000 times or less of the area of ​​the current sensing electrode 150. The area of ​​the wide portion 172 may be 400 times or more of the area of ​​the current sensing electrode 150. For example, the area of ​​the wide portion 172 may be about 2,500 times the area of ​​the current sensing electrode 150.

[0189] For proper wire bonding, the wide portion 172 (current sensing pad 170) must have a certain minimum size. Preferably, the wide portion 172 has an area of ​​800 μm × 800 μm or more and 1 mm × 1 mm or less in plan view. In this case, the wide portion 172 may be formed in a square shape in plan view. In this case, the orientation of the metal wire connection can be set to any direction.

[0190] Of course, the wide portion 172 may be formed in a square shape larger than 1 mm × 1 mm in plan view. Alternatively, the wide portion 172 may be formed in a rectangular shape of 400 μm × 800 μm or larger in plan view. In this embodiment, the size of the wide portion 172 is the same as the size of the wide portion 72 of the gate pad 70. Of course, the size of the wide portion 172 may be less than the size of the wide portion 72, or it may be greater than the size of the wide portion 72.

[0191] The columnar portion 171 and the wide portion 172 may be formed from the same conductive material. The columnar portion 171 and the wide portion 172 may be formed from an aluminum-based metal material. Of course, the columnar portion 171 and the wide portion 172 may be formed from titanium, nickel, copper, silver, gold, tungsten, etc. The columnar portion 171 and the wide portion 172 may be formed from different conductive materials. The current sensing pad 170 may be formed from the same material as the gate pad 70 and the source pad 75. This allows the current sensing pad 170, the gate pad 70 and the source pad 75 to be formed in the same process.

[0192] The height (length in the z-axis direction) of the current sensing pad 170 is the sum of the height (length in the z-axis direction) of the columnar portion 171 and the thickness (length in the z-axis direction) of the wide portion 172. The height of the current sensing pad 170 may be, for example, several tens of μm to several hundred μm (i.e., 20 μm to less than 1000 μm). Figure 15 shows an example where the height of the columnar portion 171 is equal to the thickness of the wide portion 172, but the height of the columnar portion 171 may be greater than or less than the thickness of the wide portion 172.

[0193] Referring to Figure 15, the semiconductor device 101 includes an active region 103 and an inactive region 104. The active region 103 is the main region through which the drain current of the vertical transistor 2 flows. Specifically, the active region 103 is the region that overlaps the main surface source electrode 55 in a plan view, but does not include the region that overlaps the main surface gate electrode 50 (not shown in Figure 15) and the current sensing electrode 150. In other words, the active region 103 includes the main cell region in which the main FET structure is formed, but does not include the region outside the main cell region.

[0194] The inactive region 104 is the region other than the active region 103, and is the region where no drain current flows through the vertical transistor 2. Specifically, the inactive region 104 is the region that overlaps the main plane gate electrode 50 and the current sensing electrode 150 in a plan view, but does not include the region that overlaps the main plane source electrode 55. In other words, the inactive region 104 includes the current sensing cell region where the sense FET structure is formed, but does not include the main cell region. Referring to Figure 15, the inactive region 104 includes the current sensing region 102. The current sensing region 102 includes the region that overlaps the current sensing electrode 150 in a plan view (i.e., the current sensing cell region).

[0195] In the semiconductor device 101, a current sensing electrode 150 is formed, while a current sensing pad 170 (wide portion 172) is provided that intersects the active region 103 in three dimensions. With this structure, the target of wire bonding is changed from the current sensing electrode 150 to the current sensing pad 170. This allows the current sensing electrode 150 to be reduced in size and the active region 103 to be expanded. In other words, in the semiconductor device 101, the design rules related to the current sensing electrode 150 are relaxed by the current sensing pad 170, increasing the degree of design freedom.

[0196] Specifically, the current sensing pad 170 has a width greater than the width of the current sensing electrode 150 in both the x-axis and y-axis directions, and overlaps with a portion of the main surface source electrode 55 in a plan view. This allows the current sensing pad 170 to be formed to a certain size or larger while avoiding design rules caused by the current sensing electrode 150. Furthermore, the area of ​​the main surface gate electrode 50 can be reduced, and the area of ​​the active region 103 can be expanded. Therefore, by effectively utilizing the limited area of ​​the semiconductor layer 10, a semiconductor device 101 that is easily miniaturized and cost-effective can be realized.

[0197] The current sensing pad 170 may be configured in a similar manner to the modified examples used in the gate pad 70. For example, the configurations shown in Figures 8 and 9 (including the arrangement and number of through holes, their positional relationship with the bonding wires, etc.) may be applied to the current sensing pad 170.

[0198] In this embodiment, a configuration was described in which the current sensing pad 170 overlaps the current sensing electrode 150 in a plan view. However, the current sensing pad 170 does not have to overlap the current sensing electrode 150 in a plan view. In this case, a connecting wiring section (not shown) may be provided, extending from the current sensing pad to a position above the current sensing electrode, so as to be electrically connected to the current sensing electrode 150 through a through hole. In this case, the main surface source electrode 55 may be positioned in a region below the current sensing pad and the connecting wiring section.

[0199] As described above, the semiconductor device 101 includes a vertical transistor 2. The semiconductor device 101 includes an active region 103, an inactive region 104, a main surface gate electrode 50 (first electrode), a main surface source electrode 55 (second electrode), a current sensing electrode 150 (third electrode), a gate pad 70 (first electrode pad), a source pad 75 (second electrode pad), and a current sensing pad 170 (third electrode pad).

[0200] The active region 103 is provided in the semiconductor layer 10. The active region 103 includes a main cell region that conducts drain current. The inactive region 104 is provided in a region of the semiconductor layer 10 that is different from the active region 103. The inactive region 104 includes a current sensing cell region (sense cell region) that conducts a sense current for detecting drain current. The main surface gate electrode 50 is positioned so as to overlap the region outside the main cell region in a plan view. The main surface source electrode 55 is positioned so as to overlap the main cell region with a gap between it and the main surface gate electrode 50 in a plan view.

[0201] The gate pad 70 is positioned on the side opposite the semiconductor layer 10 to the main surface gate electrode 50 such that at least a portion of it overlaps the main surface gate electrode 50 in a plan view, and is electrically connected to the main surface gate electrode 50. The gate pad 70 also overlaps a portion of the main surface source electrode 55 in a plan view. The source pad 75 is positioned at a distance from the gate pad 70. The source pad 75 is positioned on the side opposite the semiconductor layer 10 to the main surface source electrode 55 such that at least a portion of it overlaps the main surface source electrode 55 in a plan view, and is electrically connected to the main surface source electrode 55.

[0202] The current sensing pad 170 is positioned at a distance from the gate pad 70 and the source pad 75 in a plan view. The current sensing pad 170 is positioned on the side opposite to the semiconductor layer 10 relative to the current sensing electrode 150 such that at least a portion of it overlaps with the current sensing electrode 150 in a plan view, and is electrically connected to the current sensing electrode 150. In this embodiment, the current sensing pad 170 further overlaps a portion of the main surface source electrode 55 in a plan view.

[0203] If, for example, the current sensing electrode 150 is used as the electrode pad for wire bonding instead of the current sensing pad 170 according to the above embodiment, then the current sensing electrode 150 would need to be the same size as the current sensing pad 170. Since the area of ​​the semiconductor layer 10 covered by the current sensing electrode 150 becomes an inactive area 104, the area available as an active area 103 is reduced. Therefore, the effective use of the semiconductor layer 10 is hindered, which is detrimental to miniaturization and cost reduction.

[0204] In contrast, the semiconductor device 101 has a current sensing pad 170 that overlaps the current sensing electrode 150 and the main surface source electrode 55 in a plan view. With this structure, the design rules for the current sensing electrode 150 are relaxed by the current sensing pad 170, and the area of ​​the current sensing electrode 150 can be reduced. This allows the active region 103 to be expanded. Furthermore, with this structure, the current sensing pad 170 on which wire bonding is performed can be formed to a size greater than a certain size while avoiding the design rule limitations caused by the current sensing electrode 150.

[0205] In other words, the design rules related to the current sensing electrode 150, etc., are relaxed in the semiconductor device 101, increasing the degree of design freedom. With this configuration, it becomes unnecessary to increase the chip size in order to expand the active region 103. That is, the active region 103 can be expanded while avoiding an increase in chip size. Therefore, it is possible to provide a semiconductor device 101 that can make effective use of the semiconductor layer 10 and achieve miniaturization and cost reduction.

[0206] The semiconductor device 101 is manufactured using the same manufacturing method as the semiconductor device 1. Specifically, the semiconductor device 101 is manufactured by modifying the patterning process for the main surface gate electrode 50, the main surface source electrode 55, and the current sensing electrode 150, the patterning process for the insulating layer 60, and the patterning process for the gate pad 70, the source pad 75, and the current sensing pad 170 in the manufacturing method of the semiconductor device 1, so that they correspond to the semiconductor device 101.

[0207] Figure 19 is a plan view of a semiconductor device 101a according to a modified example of Embodiment 2 (the protective insulating layer 66 is not shown). Figure 20 is a plan view of the upper electrode surface of the semiconductor device 101a according to a modified example of Embodiment 2. Figures 19 and 20 correspond to Figures 17 and 18, respectively. In the above-described Embodiment 2, an example was described in which the gate pad 70 has a wide portion 72 and the current sensing pad 170 has a wide portion 172. However, as shown in Figures 19 and 20, a configuration in which the gate pad 70 does not have a wide portion 72 and the current sensing pad 170 has a wide portion 172 may also be adopted.

[0208] Specifically, in semiconductor device 101a, the gate pad 70a has the same size and shape as the main surface gate electrode 50A in a plan view. In other words, the main surface gate electrode 50A of semiconductor device 101a is larger in size than the current receiving portion 50a of the main surface gate electrode 50 of semiconductor device 101 in a plan view. The configuration of the current sensing electrode 150 and the current sensing pad 170 is the same as in the case of semiconductor device 101. In other words, semiconductor device 101a includes a current sensing electrode 150 as an example of a first electrode, and a current sensing pad 170 as an example of a first electrode pad.

[0209] In semiconductor device 101a, a configuration that increases the area in a plan view (specifically, a current sensing pad 170) is applied only to the current sensing electrode 150. In other words, the current sensing electrode 150 of semiconductor device 101a overlaps with a part of the main surface source electrode 55 in a plan view and is electrically connected to one of the multiple source electrodes 30. In this case, the current sensing electrode is considered an example of a first electrode, and the current sensing pad 170 is considered an example of a first electrode pad.

[0210] Thus, in semiconductor device 101a, a current sensing pad 170 is formed that overlaps the current sensing electrode 150 and the main surface source electrode 55 in a plan view. With this structure, the design rules of the current sensing electrode 150 are relaxed by the current sensing pad 170, and the area of ​​the current sensing electrode 150 can be reduced. This allows the active region 103 to be expanded. Furthermore, with this structure, the current sensing pad 170 on which wire bonding is performed can be formed to a size greater than a certain size while avoiding the design rule limitations caused by the current sensing electrode 150.

[0211] In other words, in semiconductor device 101a, the design rules related to the current sensing electrode 150, etc., are relaxed, increasing the degree of design freedom. With this configuration, it is not necessary to increase the chip size in order to expand the active region 103. That is, the active region 103 can be expanded while avoiding an increase in chip size. Therefore, it is possible to provide semiconductor device 101a that can make effective use of the semiconductor layer 10 and achieve miniaturization and cost reduction.

[0212] Figure 21 is a cross-sectional view of the semiconductor device 201 according to Embodiment 3. Figure 21 shows a cross-section along the line XXI-XXI in Figure 22. Figure 22 is a plan view of the semiconductor device 201 according to Embodiment 3. In Figure 22, the outer edge 70b of the gate pad, the outer edge 75a of the source pad 75, the inner edge 75b of the source pad 75, the outer edge 270a of the anode electrode pad 270, and the outer edge 275a of the cathode electrode pad 275 are shown by dashed lines. Figure 23 is a plan view of Figure 22 with the protective insulating layer 66 removed. In Figure 23, the main surface source electrode 55 is shown by a dashed line.

[0213] Figure 24 is a plan view of the semiconductor device 201 in a plane parallel to the substrate surface, as seen from the position of line XXIV-XXIV in Figure 21. Specifically, Figure 24 is a plan view of the semiconductor device 201 as seen from the positive z-axis side, with a transparent view through the gate pad 70, source pad 75, anode electrode pad 270, and cathode electrode pad 275 shown in Figure 23.

[0214] Referring to Figures 21 to 24, semiconductor device 201 (Embodiment 3) differs from semiconductor device 1 (Embodiment 1) mainly in that it includes a diode 290 (first conductive layer). In the following, the differences from Embodiment 1 will be mainly described, and the descriptions of common points will be omitted or simplified. Specifically, semiconductor device 201 includes an insulating layer 260 that covers a part of the first main surface 11 of the semiconductor layer 10, and a diode 290 provided on the insulating layer 260.

[0215] In this embodiment, the diode 290 is a pn diode comprising polysilicon, a p-type semiconductor layer 291 formed on the polysilicon, and an n-type semiconductor layer 292 formed on the polysilicon. For example, the p-type semiconductor layer 291 is polysilicon doped with p-type impurities, and the n-type semiconductor layer 292 is polysilicon doped with n-type impurities. The n-type semiconductor layer 292 is connected to the p-type semiconductor layer 291, forming a pn junction (pn diode) with the p-type semiconductor layer 291.

[0216] Diode 290 is used as a temperature sensor (thermosensitive diode) to detect the temperature of the semiconductor device 201 (semiconductor layer 10) by the magnitude of the voltage between the p-type semiconductor layer 291 and the n-type semiconductor layer 292. In other words, diode 290 may have a forward voltage characteristic that changes linearly with respect to temperature changes. The temperature of the semiconductor layer 10 is indirectly detected from the voltage characteristics of diode 290.

[0217] The semiconductor device 201 includes a gate pad 70, a source pad 75, an anode electrode pad 270 (first polarity terminal electrode), and a cathode electrode pad 275 (second polarity terminal electrode). The anode electrode pad 270 and the cathode electrode pad 275 are formed as examples of diode electrode pads (polarity terminal electrodes), respectively. The arrangement and shape of the gate pad 70 and the source pad 75 differ from those in Embodiment 1, but are substantially the same. A description of the gate pad 70 and the source pad 75 is omitted.

[0218] In a plan view, the anode electrode pad 270 is positioned in a region overlapping the p-type semiconductor layer 291, spaced apart from the gate pad 70 and source pad 75, and is electrically connected to the p-type semiconductor layer 291. In this embodiment, the anode electrode pad 270 has the same configuration as the gate pad 70.

[0219] Referring to Figure 21, the anode electrode pad 270 specifically includes a columnar portion 271 as an example of a lower conductive layer, and a wide portion 272 as an example of an upper conductive layer. The columnar portion 271 is provided on the p-type semiconductor layer 291. The columnar portion 271 is connected to the upper surface of the p-type semiconductor layer 291 and is formed in a columnar shape extending in the direction normal to the upper surface of the p-type semiconductor layer 291 (in the z-axis direction).

[0220] The wide portion 272 is provided at the upper end of the columnar portion 271. The wide portion 272 is an extended portion of the upper end of the columnar portion 271. In other words, the wide portion 272 is formed with a larger area than the columnar portion 271 in a plan view. The wide portion 272 is formed such that, in a plan view, the columnar portion 271 is located inside the wide portion 272. In a plan view, the size and shape of the wide portion 272 match the size and shape of the anode electrode pad 270.

[0221] The upper surface 273 of the wide portion 272 is used for electrical connections of the semiconductor device 201 and other circuits. Metal wires may be connected to the upper surface 273 of the wide portion 272 by wire bonding. The metal wires may include at least one of aluminum, copper, and gold. In this embodiment, an aluminum wire is wedge-bonded to the anode electrode pad 270 (upper surface 273 of the wide portion 272).

[0222] In order to perform wire bonding properly, the wide portion 272 (anode electrode pad 270) must have a certain size or larger. The planar shape and size of the wide portion 272 may be the same as the planar shape and size of the wide portion 72 of the gate pad 70. Of course, either or both of the planar shape and size of the wide portion 272 may differ from those of the wide portion 72.

[0223] The columnar portion 271 and the wide portion 272 may be formed from the same conductive material. The columnar portion 271 and the wide portion 272 may be formed from an aluminum-based metal material. Of course, the columnar portion 271 and the wide portion 272 may be formed from titanium, nickel, copper, silver, gold, tungsten, etc. The columnar portion 271 and the wide portion 272 may be formed from different conductive materials.

[0224] The height (length in the z-axis direction) of the anode electrode pad 270 is the sum of the height (length in the z-axis direction) of the columnar portion 271 and the thickness (length in the z-axis direction) of the wide portion 272. The height of the anode electrode pad 270 may be, for example, several tens of μm or more and several hundred μm or less (i.e., 20 μm or more and less than 1000 μm). The height of the columnar portion 271 may exceed the thickness of the wide portion 272, or it may be less than the thickness of the wide portion 272. Of course, the height of the columnar portion 271 may be equal to the thickness of the wide portion 272.

[0225] The cathode electrode pad 275 is positioned in a region overlapping the n-type semiconductor layer 292, spaced apart from the gate pad 70, source pad 75, and anode electrode pad 270, and is electrically connected to the n-type semiconductor layer 292. In this embodiment, the cathode electrode pad 275 has the same configuration as the gate pad 70 and anode electrode pad 270.

[0226] Referring to Figure 21, the cathode electrode pad 275 specifically includes a columnar portion 276 as an example of a lower conductive layer and a wide portion 277 as an example of an upper conductive layer. The columnar portion 276 is provided on the n-type semiconductor layer 292. The columnar portion 276 is connected to the upper surface of the n-type semiconductor layer 292 and is formed in a columnar shape extending in the direction normal to the n-type semiconductor layer 292 (z-axis direction).

[0227] The wide portion 277 is provided at the upper end of the columnar portion 276. The wide portion 277 is an extended portion of the upper end of the columnar portion 276. In other words, the wide portion 277 is formed with a larger area than the columnar portion 276 in a plan view. The wide portion 277 is formed such that, in a plan view, the columnar portion 276 is located inside the wide portion 277.

[0228] In a plan view, the size and shape of the wide portion 277 match the size and shape of the cathode electrode pad 275. The upper surface 278 of the wide portion 277 is used for electrical connections of the semiconductor device 201 and other circuits. In this configuration, the upper surface 278 of the wide portion 277 is connected to a voltmeter or the like. Metal wires may be connected to the upper surface 278 of the wide portion 277 by wire bonding.

[0229] The anode electrode pad 270 and the cathode electrode pad 275 may each have an area of ​​20% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view. Preferably, the anode electrode pad 270 and the cathode electrode pad 275 each have an area of ​​10% or less of the area of ​​the semiconductor layer 10 (first main surface 11) in a plan view.

[0230] Either or both of the anode electrode pad 270 and the cathode electrode pad 275 may be located on the outer periphery (periphery) of the semiconductor layer 10 (first main surface 11) in a plan view. Either or both of the anode electrode pad 270 and the cathode electrode pad 275 may be located in a region that includes the center of the semiconductor layer 10 (first main surface 11) in a plan view.

[0231] Either or both of the anode electrode pad 270 and the cathode electrode pad 275 may be located in the region surrounded by the source pad 75. In other words, the source pad 75 may be formed to surround either or both of the anode electrode pad 270 and the cathode electrode pad 275.

[0232] The anode electrode pad 270 and the cathode electrode pad 275 are formed from the same material as, for example, the gate pad 70 and the source pad 75. This allows the anode electrode pad 270, the cathode electrode pad 275, the gate pad 70, and the source pad 75 to be formed in the same process. The shape and material of the columnar portion 276 and the wide portion 277 of the cathode electrode pad 275 may be the same as those of the columnar portion 276 and the wide portion 277 of the anode electrode pad 270. A description of the shape and material of the columnar portion 276 and the wide portion 277 of the cathode electrode pad 275 is omitted.

[0233] Referring to Figure 21, the semiconductor device 201 includes an active region 203 and an inactive region 204. The active region 203 is the main region through which the drain current of the vertical transistor 2 flows. In a plan view, the active region 203 is the region that overlaps with the main surface source electrode 55.

[0234] The inactive region 204 is the region other than the active region 203 in a plan view, and is the region that does not operate as a vertical transistor 2 (the region where drain current does not flow). The aforementioned diode 290 is located in the inactive region 204. In other words, in this configuration, the anode electrode pad 270 and the cathode electrode pad 275 are located in the region that overlaps the inactive region 204, overlapping a part of the active region 203 in a plan view.

[0235] In semiconductor device 201, a portion of the anode electrode pad 270 (the wide portion 272) overlaps with the main surface source electrode 55 in a plan view. This allows the anode electrode pad 270 to be formed to a certain size or larger while avoiding design rules caused by the diode 290. Furthermore, the area of ​​the diode 290 can be reduced, and the area of ​​the active region 203 can be expanded. Therefore, by effectively utilizing the limited area of ​​the semiconductor layer 10, a semiconductor device 201 that is easily miniaturized and cost-effective can be realized.

[0236] Furthermore, in semiconductor device 201, a portion of the cathode electrode pad 275 (the wide portion 277) overlaps with the main surface source electrode 55 in a plan view. This allows the cathode electrode pad 275 to be formed to a certain size or larger while avoiding design rules caused by the diode 290. In addition, the area of ​​the diode 290 can be reduced, and the area of ​​the active region 203 can be expanded. Therefore, by effectively utilizing the limited area of ​​the semiconductor layer 10, a semiconductor device 201 that is easily miniaturized and cost-effective can be realized.

[0237] As described above, the semiconductor device 201 includes an insulating layer 260, a diode 290, an anode electrode pad 270 (first polarity terminal electrode), and a cathode electrode pad 275 (second polarity terminal electrode). The insulating layer 260 covers a portion of the first main surface 11. The diode 290 is disposed on the insulating layer 260. The diode 290 includes a p-type semiconductor layer 291 (first polarity layer) and an n-type semiconductor layer 292 (second polarity layer) that forms a pn junction with the p-type semiconductor layer.

[0238] The anode electrode pad 270 has a portion that overlaps with the p-type semiconductor layer 291 in a plan view and is electrically connected to the p-type semiconductor layer 291. The cathode electrode pad 275 has a portion that overlaps with the n-type semiconductor layer 292 in a plan view and is electrically connected to the n-type semiconductor layer 292. In this structure, either or both of the anode electrode pad 270 and the cathode electrode pad 275 overlap a portion of the main surface source electrode 55 in a plan view.

[0239] This structure allows either the anode electrode pad 270 or the cathode electrode pad 275, or both, to be formed to a certain size or larger while avoiding design rules imposed by the diode 290. Furthermore, this structure allows for a reduction in the area of ​​the diode 290 and an expansion of the area of ​​the active region 203. Therefore, by effectively utilizing the limited area of ​​the semiconductor layer 10, a semiconductor device 201 that is easily miniaturized and cost-effective can be realized.

[0240] The semiconductor device 201 is manufactured using the same manufacturing method as the semiconductor device 1. Specifically, the semiconductor device 201 is manufactured by modifying the patterning process of the main surface gate electrode 50 and the main surface source electrode 55, the patterning process of the insulating layer 60, and the patterning process of the gate pad 70, source pad 75, anode electrode pad 270 and cathode electrode pad 275, respectively, to suit the semiconductor device 201.

[0241] Figure 25 is a plan view of a semiconductor device 201a according to a modified example of Embodiment 3 (the protective insulating layer 66 is not shown). Figure 26 is a plan view of the upper electrode surface of the semiconductor device 201a according to a modified example of Embodiment 3. Figures 25 and 26 correspond to Figures 23 and 24 of Embodiment 3, respectively. In Figure 25, the main surface source electrode 55 is shown by a dashed line.

[0242] In the semiconductor device 201, an example was described in which the gate pad 70 has a wide portion 72, the anode electrode pad 270 has a wide portion 272, and the cathode electrode pad 275 has a wide portion 277. However, as shown in Figures 25 and 26, an example may be adopted in which the gate pad 70 does not have a wide portion 72, the anode electrode pad 270 has a wide portion 272, and the cathode electrode pad 275 has a wide portion 277.

[0243] The gate pad 70a of the semiconductor device 201a has the same size and shape as the main gate electrode 50A in a plan view. In other words, the main gate electrode 50A of the semiconductor device 201a is larger in size than the power receiving portion 50a of the main gate electrode 50 of the semiconductor device 201 in a plan view.

[0244] As described above, the semiconductor device 201a also reduces the area of ​​the diode 290 and expands the area of ​​the active region 203. Therefore, by effectively utilizing the limited area of ​​the semiconductor layer 10, a semiconductor device 201a that is easily miniaturized and cost-effective can be realized.

[0245] Figures 27 and 28 show a semiconductor device 201b according to another modification of Embodiment 3. Figure 27 is a plan view of the semiconductor device 200b (protective insulating layer 66 is not shown). Figure 28 is a plan view of the electrode top surface in the semiconductor device 201b. In Figure 27, the main surface source electrode 55 is shown by a dashed line. In Figure 28, the arrangement of the diode 290 on the main surface source electrode 55 is shown.

[0246] Referring to Figures 27 and 28, semiconductor device 201b, like semiconductor device 201, includes a diode 290, an anode electrode pad 270, and a cathode electrode pad 275. In this embodiment, the diode 290 is located near the center of the chip (near the center of the first main surface 11) in a plan view.

[0247] In this embodiment, the anode electrode pad 270 and the cathode electrode pad 275 are positioned on the periphery of the chip (the periphery of the first main surface 11) in a plan view. Either one or both (both in this embodiment) of the anode electrode pad 270 and the cathode electrode pad 275 are positioned at a distance from the diode 290 so as not to overlap the diode 290 in a plan view. In this embodiment, the entire anode electrode pad 270 overlaps the main surface source electrode 55 in a plan view. Similarly, the entire cathode electrode pad 275 overlaps the main surface source electrode 55 in a plan view.

[0248] The semiconductor device 201b includes a first connection portion 250a, a first finger portion 250, a second connection portion 255a, and a second finger portion 255. The first connection portion 250a is located directly above the p-type semiconductor layer 291 of the diode 290. The first finger portion 250 is interposed between the anode electrode pad 270 and the first connection portion 250a, connecting the anode electrode pad 270 and the first connection portion 250a.

[0249] The first finger portion 250 extends in a line (strip) shape in a plan view in the region between the anode electrode pad 270 and the first connection portion 250a. In this embodiment, the first finger portion 250 extends in the x-axis direction in a plan view. At least a portion of the first finger portion 250 overlaps the main surface source electrode 55 in a plan view.

[0250] The second connection portion 255a is located directly above the n-type semiconductor layer 292 of the diode 290. The second finger portion 255 is interposed between the cathode electrode pad 275 and the second connection portion 255a, connecting the cathode electrode pad 275 and the second connection portion 255a. In a plan view, the second finger portion 255 extends in a line (strip) shape through the region between the cathode electrode pad 275 and the second connection portion 255a.

[0251] In this configuration, the second finger portion 255 is provided at a distance from the first finger portion 250 in the y-axis direction in a plan view, and extends in the x-axis direction. In other words, the second finger portion 255 extends parallel to the first finger portion 250 in a plan view. At least a portion of the second finger portion 255 overlaps the main surface source electrode 55 in a plan view.

[0252] The central part of the chip (semiconductor layer 10) tends to get hotter than the peripheral part of the chip (semiconductor layer 10). Therefore, when a diode 290 that functions as a temperature sensor is provided, it is preferable to place the diode 290 in the central part of the chip (semiconductor layer 10) in a plan view. On the other hand, from the viewpoint of mountability such as wire bonding, it is preferable to place the electrode pad at the edge (periphery) of the chip where there are fewer obstacles.

[0253] Conventionally, the area directly beneath multiple electrode pads for a temperature sensor located at the edge (periphery) of the chip (semiconductor layer 10), and the area directly beneath the wiring from these electrode pads to the center of the chip (semiconductor layer 10), are formed as inactive areas. In this respect, according to the structure of semiconductor device 201b, in addition to the area directly beneath the anode electrode pad 270 and the cathode electrode pad 275, the area directly beneath the first finger portion 250 and the second finger portion 255 can also be used as an active area 203.

[0254] Figures 29 and 30 show a semiconductor package 300 according to Embodiment 4. Figure 30 shows the internal structure of the semiconductor package 300 shown in Figure 29, viewed from the opposite side from Figure 29.

[0255] The semiconductor package 300 is a so-called TO (Transistor Outline) type semiconductor package. The semiconductor package 300 includes the package body 301, terminals 302d, 302g, 302s, bonding wire 303g, bonding wire 303s, and semiconductor device 1. Hereinafter, terminals 302d, 302g, and 302s may be collectively referred to simply as "terminals 302d-302s".

[0256] The package body 301 is formed in the shape of a rectangular parallelepiped. The package body 301 is formed of an epoxy resin containing, for example, carbon and glass fibers. Each of the terminals 302d to 302s protrudes from the bottom of the package body 301 and is arranged in a row. The terminals 302d to 302s may be formed of aluminum. The terminals 302d to 302s may be formed of other metallic materials such as copper.

[0257] The semiconductor device 1 is housed within the package body 301. In other words, the package body 301 is configured as a encapsulant that seals the semiconductor device 1. The gate pad 70 related to the semiconductor device 1 is electrically connected to the terminal 302g within the package body 301 via bonding wires 303g, etc.

[0258] The source pad 75 of the semiconductor device 1 is electrically connected to the terminal 302s via a bonding wire 303s or the like. The drain electrode 40 of the semiconductor device 1 is joined to the terminal 302d via a solder, a sintered layer, or the like. The sintered layer may contain silver, copper, or the like. In this form, the drain electrode 40 is joined to the wide portion located within the package body 301 of the terminal 302d.

[0259] The semiconductor package 300 may include the semiconductor devices 101, 101a, 201, 201a, or 201b instead of the semiconductor device 1. In this case, the semiconductor package 300 may further include at least one terminal other than the terminals 302d to 302s. For example, when the semiconductor device 101 is mounted, the semiconductor package 300 may further include a terminal connected to the current detection pad 170. Also, when the semiconductor device 201 is mounted, the semiconductor package 300 may further include a terminal to which the anode electrode pad 270 is connected and a terminal to which the cathode electrode pad 275 is connected.

[0260] As described above, the semiconductor package 300 includes the semiconductor devices 1, 101, 101a, 201, 201a, or 201b. As described above, according to the semiconductor device 1 or the like, miniaturization can be achieved by effectively using the semiconductor layer 10. Therefore, according to the semiconductor package 300, it can be easily miniaturized in response to the miniaturization of the semiconductor device 1 or the like.

[0261] Also, according to the semiconductor device 1 or the like, the active regions 3, 103, and 203 can be expanded. Therefore, according to the semiconductor package 300, the allowable current amount can be increased compared to a general semiconductor package of the same size. In the semiconductor package 300, an example in which the semiconductor device 1 or the like is electrically connected to the terminal via a bonding wire is shown. However, in the semiconductor package 300, the semiconductor device 1 or the like may be electrically connected to the terminal by a bonding material.

[0262] Figure 31 shows a semiconductor package 400 according to Embodiment 4. Referring to Figure 31, the semiconductor package 400 is a so-called DIP (Dual In-line Package) type semiconductor package. The semiconductor package 400 includes a package body 401, a plurality of terminals 402, and a semiconductor device 1.

[0263] The package body 401 is formed in the shape of a rectangular parallelepiped. The package body 401 is formed of an epoxy resin containing, for example, carbon or glass fiber. The multiple terminals 402 are arranged in a line along the long side of the package body 401. The multiple terminals 402 protrude outward from the long side of the package body 401. The multiple terminals 402 may be formed of, for example, aluminum. The multiple terminals 402 may be formed of other metallic materials such as copper.

[0264] The semiconductor device 1 is housed within the package body 401. In other words, the package body 401 is configured as a encapsulant that seals the semiconductor device 1. The gate pad 70, source pad 75, and drain electrode 40 related to the semiconductor device 1 are electrically connected to the corresponding terminals 402 within the package body 401 via bonding wires or the like. The semiconductor package 400 may contain multiple semiconductor devices 1. In other words, multiple semiconductor devices 1 may be housed within the package body 401.

[0265] Of course, the semiconductor package 400 may include at least one of the semiconductor devices 101, 101a, 201, 201a, and 201b in place of or in addition to the semiconductor device 1. When semiconductor device 101 is mounted, the current sensing pad 170 is electrically connected to the corresponding terminal 402 inside the package body 401 via bonding wires or the like. When semiconductor device 201 is mounted, the anode electrode pad 270 and cathode electrode pad 275 are electrically connected to the corresponding terminal 402 inside the package body 401 via bonding wires or the like.

[0266] As described above, the semiconductor package 400 includes at least one of the semiconductor devices 1, 101, 101a, 201, 201a, and 201b. As described above, with the semiconductor device 1, miniaturization can be achieved by effectively utilizing the semiconductor layer 10. Therefore, with the semiconductor package 300, miniaturization can be easily achieved in accordance with the miniaturization of the semiconductor device 1, etc.

[0267] Furthermore, the semiconductor device 1, etc., allows for the expansion of the active regions 3, 103, and 104. Therefore, the semiconductor package 300 allows for an increase in the allowable current compared to a typical semiconductor package of the same size. In the semiconductor package 400, an example was shown in which the semiconductor device 1, etc., is electrically connected to the terminals via bonding wires. However, in the semiconductor package 400, the semiconductor device 1, etc., may also be electrically connected to the terminals by a bonding material.

[0268] Figure 32 is a cross-sectional view of a modified semiconductor device 501. Referring to Figure 32, a plating layer 90 (metal plating layer) as an example of a metal layer may be formed on the upper surface 73 of the gate pad 70 and the upper surface 76 of the source pad 75. In Figure 32, in addition to the plating layer 90, a bonding wire 303g, a bonding material 502, and a metal plate 503 are shown as an example of a connecting member (bonding means) to an external terminal.

[0269] In the semiconductor device 501, a bonding wire 303g is connected to the gate pad 70, and a bonding material 502 is bonded to the source pad 75. The bonding material 502 is interposed between the metal plate 503 and the source pad 75 to bond the metal plate 503 and the source pad 75. Examples of bonding material 502 include solder and sintered metal members. The sintered metal member may contain silver, copper, or the like.

[0270] The plating layer 90 is formed from a different metallic material than the metallic material forming the gate pad 70 and source pad 75. The plating layer 90 is, for example, a metallic layer mainly composed of nickel. Specifically, the plating layer 90 is a metallic layer made of pure nickel.

[0271] The plating layer 90 may have a two-layer structure (i.e., a NiPd layer) including a nickel layer and a palladium layer laminated on the nickel layer. The plating layer 90 may have a three-layer structure (i.e., a NiPdAu layer) including a nickel layer, a palladium layer laminated on the nickel layer, and a gold (Au) layer laminated on the palladium layer. Of course, the plating layer 90 may have a laminated structure including another metal layer instead of the gold (Au) layer. The NiPd layer and NiPdAu layer are suitable not only when bonding wires are joined, but also when external terminals are joined by silver sintering or soldering.

[0272] The plating layer 90 may be applied to semiconductor devices 101, 101a, 201, 201a, and 201b. In other words, the plating layer 90 may be provided on the upper surfaces of the current sensing pad 170, the anode electrode pad 270, and the cathode electrode pad 275.

[0273] Although embodiments have been described above, the embodiments described above can be implemented in other forms. For example, the form of the semiconductor package on which semiconductor devices 1, 101, 101a, 201, 201a, 201b, and 501 are mounted is not limited to forms such as semiconductor package 300 and semiconductor package 400. As the semiconductor package, SOP (Small Outline Package), QFN (Quad Flat Non Lead Package), DFP (Dual Flat Package), QFP (Quad Flat Package), SIP (Single Inline Package), or SOJ (Small Outline J-leaded Package) may be used. Of course, various semiconductor packages similar to these may be used.

[0274] In the embodiments 1 to 4 described above, an example was explained in which the "first conductivity type" is "n-type" and the "second conductivity type" is "p-type." However, the "first conductivity type" may also be "p-type" and the "second conductivity type" may be "n-type." The specific configuration in this case can be obtained by replacing the "n-type region" with the "p-type region" and the "p-type region" with the "n-type region" in the above description and attached drawings. The terms "first conductivity type" and "second conductivity type" are merely descriptive forms to clarify the order of explanation, and "n-type" may be expressed as the "second conductivity type" and "p-type" as the "first conductivity type."

[0275] In the embodiments 1 to 4 described above, n + Instead of the type semiconductor substrate 13, p + A SiC semiconductor substrate of type 1 may be used. In this case, a semiconductor device including an IGBT (Insulated Gate Bipolar Transistor) as the vertical transistor 2 can be provided. In this case, in the specification and drawings, the "source" of the MISFET is replaced with the "emitter" of the IGBT, and the "drain" of the MISFET is replaced with the "collector" of the IGBT. The emitter (emitter electrode) of the IGBT is an example of a first main electrode, and the collector (collector electrode) of the IGBT is an example of a second main electrode. According to the semiconductor devices of each embodiment described above, even when an IGBT is included instead of a MISFET, the same effects as described above are achieved.

[0276] The configurations of Embodiments 1 to 4 described above and the configurations of modified examples of Embodiments 1 to 4 can be combined as appropriate. For example, in a semiconductor device including a gate pad, a current sensing pad, and a temperature sensing pad, the configurations described in the above embodiments may be applied to each of the gate pad, current sensing pad, and temperature sensing pad. This makes it possible to provide a high-performance semiconductor device equipped with current sensing and temperature sensing functions without reducing the area of ​​the active region.

[0277] The following are examples of features extracted from this specification and drawings. The alphanumeric characters in parentheses below represent the corresponding components in the embodiments described above, but this is not intended to limit the scope of each item to the embodiments. The term "semiconductor device" in the following items may be replaced with "wide bandgap semiconductor device," "SiC semiconductor device," "wide bandgap semiconductor switching device," or "SiC semiconductor switching device."

[0278] Conventional semiconductor devices include a gate pad and a source pad where wire bonding takes place. Below the source pad is an active region containing an FET structure. Below the gate pad is a non-active region that does not contain an FET structure. The gate pad needs to be formed to a certain size or larger to ensure sufficient bonding area with the wires. Therefore, if the active region is to be expanded without changing the size of the gate pad, the size of the chip itself must be increased.

[0279] Therefore, one objective of the following items is to provide a semiconductor device that can relax design rules related to electrodes. Another objective of the following items is to provide a semiconductor device that can expand the active area without increasing the chip size.

[0280] [A1]A semiconductor device (1, 101, 101a, 201, 201a, 201b, 501; hereinafter simply referred to as "semiconductor device (1, etc.)") including a semiconductor layer (10) containing SiC and having a first main surface (11) on one side and a second main surface (12) on the other side, a vertical transistor (2) formed in the semiconductor layer (10), a first electrode (50 / 150) disposed on the first main surface (11), a second electrode (55) disposed on the first main surface (11) at a distance from the first electrode (50 / 150), a first electrode pad (70 / 170) disposed on the opposite side of the semiconductor layer (10) with respect to the first electrode (50 / 150) so as to overlap at least a part of the first electrode (50 / 150) in plan view and electrically connected to the first electrode (50 / 150), and an electrode (40) disposed on the second main surface (12), wherein the first electrode pad (70 / 170) overlaps a part of the second electrode (55) in plan view.

[0281] [A2]The semiconductor device (1, etc.) according to A1, further including a first insulating layer (63) interposed between the first electrode pad (70 / 170) and the second electrode (55) in a direction (z) perpendicular to the first main surface (11).

[0282] [A3]The semiconductor device (1, etc.) according to A2, wherein a side surface of the first insulating layer (63) is formed in a plane extending in the perpendicular direction (z).

[0283] [A4]The semiconductor device (1, etc.) according to A2 or A3, further including a second electrode pad (75) electrically connected to the second electrode (55), wherein an end portion of the second electrode pad (75) on the side of the first electrode pad (70 / 170) is located on the first insulating layer (63).

[0284] [A5]The semiconductor device (1, etc.) according to A4, further including a second insulating layer (66) covering a boundary portion (80) between the first electrode pad (70 / 170) and the second electrode pad (75).

[0285] [A6] The vertical transistor (2) includes a source region (17) formed on the surface of the first main surface (11), a gate insulating film (23) covering the source region (17), a gate electrode (20) facing the source region (17) with the gate insulating film (23) in between, and drain regions (10, 13, 14) formed within the semiconductor layer (10), wherein the first electrode (50 / 150) is electrically connected to the gate electrode (20), the second electrode (55) is electrically connected to the source region (17), and the electrode (40) is electrically connected to the drain regions (10, 13, 14), as described in any one of A1 to A5 (1, etc.).

[0286] [A7] The semiconductor device (1, etc.) described in A6, wherein the vertical transistor (2) includes a main cell region (103) that generates a drain current in a plan view, and a current sensing cell region (104) that generates a sense current for detecting the drain current, and the second electrode (55) is arranged in a region that overlaps with the main cell region (103) in a plan view.

[0287] [A8] The semiconductor device (1, etc.) according to A7, further comprising: a third electrode (150) positioned in a region overlapping the current sensing cell region (104) at a distance from the first electrode (50) and the second electrode (55) in a plan view; and a third electrode pad (170) positioned on the opposite side of the semiconductor layer (10) from the third electrode (150) and electrically connected to the third electrode (150) such that at least a portion of it overlaps the third electrode (150) in a plan view.

[0288] [A9] The semiconductor device (1, etc.) described in A8, wherein the third electrode pad (170) overlaps a portion of the second electrode (55) in a plan view.

[0289] [A10] A semiconductor device (1, etc.) according to any one of A1 to A9, further comprising: an insulating layer (260) covering a part of the first main surface (11); a diode (290) disposed on the insulating layer (260) and having a first polarity portion (291) and a second polarity portion (292) forming a pn junction with the first polarity portion (291); a first polarity electrode pad (270) electrically connected to the first polarity portion (291) on the diode (290); and a second polarity electrode pad (275) electrically connected to the second polarity portion (292) on the diode (290).

[0290] [A11] The semiconductor device (1, etc.) according to A10, wherein at least one of the first polar electrode pad (270) and the second polar electrode pad (275) overlaps a portion of the second electrode (55) in a plan view.

[0291] [A12] A method for manufacturing a semiconductor device (1, etc.), comprising the steps of: preparing a semiconductor layer (10) containing SiC and having a first main surface (11) on one side and a second main surface (12) on the other side, and including a vertical transistor (2); forming a first electrode (50 / 150) and a second electrode (55) on the first main surface (11) with a gap between them; and forming a first electrode pad (70 / 170) at a position opposite to the semiconductor layer (10) relative to the first electrode (50 / 150) such that at least a portion of it overlaps the first electrode (50 / 150) in a plan view and is electrically connected to the first electrode (50 / 150), wherein in the step of forming the first electrode pad (70 / 170), the first electrode pad (70 / 170) is formed to overlap a portion of the second electrode (55).

[0292] [B1] A semiconductor device (1, etc.) comprising: a semiconductor layer (10) having a main surface (11); a switching element (2) formed on the semiconductor layer (10); a first electrode (50 / 150) disposed on the main surface (11) and electrically connected to the switching element (2); a second electrode (55) disposed on the main surface (11) at a distance from the first electrode (50 / 150) and electrically connected to the switching element (2); a first terminal electrode (70 / 170) having a portion that overlaps with the first electrode (50 / 150) and a portion that overlaps with the second electrode (55) in a plan view, and electrically connected to the first electrode (50 / 150); and a second terminal electrode (75) having a portion that overlaps with the second electrode (55) in a plan view, and electrically connected to the second electrode (55).

[0293] [B2] The semiconductor layer (10) is a semiconductor device (1, etc.) as described in B1, comprising SiC.

[0294] [B3] The semiconductor device (1, etc.) according to B1 or B2, wherein the first terminal electrode (70 / 170) is connected to the first electrode (50 / 150) over a first area and has an electrode surface (73) exceeding the first area.

[0295] [B4] The semiconductor device (1, etc.) described in any one of B1 to B3, wherein the second terminal electrode (75) has an area of ​​the first terminal electrode (70 / 170) or more in a plan view.

[0296] [B5] The semiconductor device (1, etc.) according to any one of B1 to B4, wherein the first terminal electrode (70 / 170) intersects with at least a portion of the first electrode (50 / 150) in a plan view.

[0297] [B6] The semiconductor device (1, etc.) according to any one of B1 to B5, wherein the second terminal electrode (75) has a portion that overlaps with the first electrode (50 / 150) in a plan view.

[0298] [B7] The semiconductor device (1, etc.) described in any one of B1 to B6, wherein the first electrode (50 / 150) is a control electrode that transmits a control signal of the switching element (2), and the second electrode (55) is a non-control electrode.

[0299] [B8] The semiconductor device (1, etc.) according to any one of B1 to B7, wherein the switching element (2) includes a gate (20) and a source (17), the first electrode (50 / 150) is electrically connected to the gate (20), and the second electrode (55) is electrically connected to the source (17).

[0300] [B9] A semiconductor device (1, etc.) according to any one of B1 to B8, further comprising a first insulator (63) covering the second electrode (55), wherein the first terminal electrode (70 / 170) has a portion facing the second electrode (55) with the first insulator (63) in between, and the second terminal electrode (75) has a portion facing the second electrode (55) with the first insulator (63) in between.

[0301] [B10] The semiconductor device (1, etc.) according to B9, wherein the first terminal electrode (70 / 170) has a side surface positioned above the second electrode (55) so as to face the second electrode (55) with the first insulator (63) in between, and the second terminal electrode (75) has a side surface positioned above the second electrode (55) so as to face the second electrode (55) with the first insulator (63) in between, and forms a gap (80) between itself and the side surface of the first terminal electrode (70 / 170) that exposes the first insulator (63).

[0302] [B11] The semiconductor device (1, etc.) according to B10, further comprising a second insulator (66) that covers the first insulator (63) within the gap (80) and faces the second electrode (55) with the first insulator (63) in between.

[0303] [B12] A semiconductor device (1, etc.) according to any one of B9 to B11, wherein the first insulator (63) covers the first electrode (50 / 150), the first terminal electrode (70 / 170) has a portion facing the first electrode (50 / 150) with the first insulator (63) in between, and the second terminal electrode (75) has a portion facing the first electrode (50 / 150) with the first insulator (63) in between.

[0304] [B13] The switching element (2) is formed in the active region (3, 103, 203) and the first electrode (50 / 150) is arranged in a region that overlaps the inactive region (4, 104, 204) in a plan view. A semiconductor device (e.g., 1) according to any one of B1 to B12, wherein the second electrode (55) is arranged in a region that overlaps with the active region (3, 103, 203) in a plan view, the first terminal electrode (70 / 170) is arranged in a region that overlaps with the active region (3, 103, 203) and the inactive region (4, 104, 204) in a plan view, and the second terminal electrode (75) is arranged in a region that overlaps with the active region (3, 103, 203) in a plan view.

[0305] [B14] The semiconductor device (1, etc.) according to B13, wherein the active regions (3, 103, 203) include a main cell region (103) provided in the semiconductor layer (10), the inactive regions (4, 104, 204) include a sense cell region (104) provided in a region different from the main cell region (103) in the semiconductor layer (10), and the switching element (2) includes a main switching element (2) formed in the main cell region (103) to generate a main current, and a sense switching element (2) formed in the sense cell region (104) to generate a monitor current for detecting the main current.

[0306] [B15] The semiconductor device (1, etc.) according to B14, wherein the first electrode (50 / 150) is electrically connected to the main switching element (2), the second electrode (55) is located in a region that overlaps with the main cell region (103) in a plan view and is electrically connected to the main switching element (2), the first terminal electrode (70 / 170) is located in a region that overlaps with the main cell region (103) and the inactive regions (4, 104, 204) in a plan view, and the second terminal electrode (75) is located in a region that overlaps with the main cell region (103) in a plan view.

[0307] [B16] The first electrode (50 / 150) is electrically connected to the sense switching element (2) in the semiconductor device (1, etc.) described in B14 or B15.

[0308] [B17] A semiconductor device (1, etc.) according to any one of B14 to B16, further comprising: a third electrode (150) arranged in a region overlapping the sense cell region (104) at a distance from the first electrode (50) and the second electrode (55) in a plan view, and electrically connected to the sense switching element (2); and a third terminal electrode (170) having a portion overlapping the third electrode (150) in a plan view and electrically connected to the third electrode (150).

[0309] [B18] A semiconductor device (1, etc.) according to any one of B13 to B17, further comprising a diode (290) formed in the inactive region (4, 104, 204), and polar terminal electrodes (270, 275) having a portion that overlaps with the diode (290) in a plan view and being electrically connected to the diode (290).

[0310] [B19] A semiconductor layer (10) having a main surface (11), a main element (2) formed in the semiconductor layer (10) that generates a main current, a sense element (2) formed in the semiconductor layer (10) in a region different from the main element (2) that generates a monitor current to monitor the main current, a first electrode (50) disposed on the main surface (11) and electrically connected to the main element (2), a second electrode (55) disposed on the main surface (11) at a distance from the first electrode (50) and electrically connected to the main element (2), and the first electrode (50 and A semiconductor device (1, etc.) comprising: a third electrode (150) positioned on the main surface (11) at a distance from the second electrode (55) and electrically connected to the sense element (2); a first terminal electrode (70) on the first electrode (50) and electrically connected to the first electrode (50); a second terminal electrode (75) on the second electrode (55) and electrically connected to the second electrode (55); and a third terminal electrode (170) having a portion that overlaps with the third electrode (150) and a portion that overlaps with the second electrode (55) in a plan view, and electrically connected to the third electrode (150).

[0311] [B20] A semiconductor layer (10) having a main surface (11), a switching element (2) formed on the semiconductor layer (10), a diode (290) formed in a region of the semiconductor layer (10) different from the switching element (2), a first electrode (50 / 150) disposed on the main surface (11) and electrically connected to the switching element (2), and a component disposed on the main surface (11) at a distance from the first electrode (50 / 150) and electrically connected to the switching element (2). A semiconductor device (1, etc.) comprising: a second electrode (55); a first terminal electrode (70 / 170) electrically connected to the first electrode (50 / 150) on the first electrode (50 / 150); a second terminal electrode (75) electrically connected to the second electrode (55) on the second electrode (55); and polar terminal electrodes (270, 275) electrically connected to the diode (290), having a portion that overlaps with the diode (290) and a portion that overlaps with the second electrode (55) in a plan view.

[0312] [C1] A semiconductor layer (10) containing SiC, having a first main surface (11) on one side and a second main surface (12) on the other side; active regions (3, 103, 203) provided on the first main surface (11); inactive regions (4, 104, 204) provided outside the active regions (3, 103, 203) on the first main surface (11); a first insulating layer (61) covering the first main surface (11); a first main electrode layer (55) disposed on the first insulating layer (61) so as to overlap the active regions (3, 103, 203) in a plan view; and the first main electrode layer (55) so as to overlap the inactive regions (4, 104, 204) in a plan view. A semiconductor device (e.g.) comprising: a first conductive layer (50 / 150 / 290) disposed on the first insulating layer (61) at a distance from the electrode layer (55) and electrically separated from the first main electrode layer (55); a second insulating layer (63) covering the first main electrode layer (55) and the first conductive layer (50 / 150 / 290); a second conductive layer (70 / 170 / 270 / 275) disposed on the second insulating layer (63) so as to overlap the first main electrode layer (55) in a plan view, electrically separated from the first main electrode layer (55) and electrically connected to the first conductive layer (50 / 150 / 290); and an electrode (40) covering the second main surface (12).

[0313] [C2] The semiconductor device (1, etc.) according to C1, further comprising a switching element (2) formed on the semiconductor layer (10) in the active region (3, 103, 203), wherein the first conductive layer (50 / 150 / 290) and the second conductive layer (70 / 170 / 270 / 275) are electrically connected to the switching element (2).

[0314] [C3] The switching element (2) is a semiconductor device (1, etc.) according to C2, which includes at least one of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) and an IGBT (Insulated Gate Bipolar Transistor).

[0315] [C4] The semiconductor device (1, etc.) described in C3, wherein the first conductive layer (50 / 150) and the second conductive layer (70 / 170) are electrically connected to the gate of the switching element (2) and form a first transmission path for the gate voltage.

[0316] [C5] The semiconductor device (1, etc.) according to C1, further comprising a current sensing element (2) formed on the semiconductor layer (10), wherein the first conductive layer (150) and the second conductive layer (170) are electrically connected to the current sensing element (2) and form a second transmission path for the signal generated by the current sensing element (2).

[0317] [C6] The current sensing element (2) is a semiconductor device (1, etc.) as described in C5, formed in the inactive region (4, 104, 204).

[0318] [C7] The semiconductor device (1, etc.) according to C1, wherein the first conductive layer (290) is composed of a diode (290) and forms a third transmission path for the current flowing through the diode (290) between it and the second conductive layer (270 / 275).

[0319] [C8] The diode (290) is a temperature-sensitive diode (290), and the third transmission line transmits a signal for detecting the temperature of the semiconductor layer (10), as described in C7 (1, etc.).

[0320] [C9] The diode (290) is a semiconductor device (1, etc.) described in C7 or C8, formed in the inactive region (4, 104, 204).

[0321] [C10] The semiconductor device (1, etc.) according to any one of C1 to C9, wherein the first conductive layer (50 / 150 / 290) is made of substantially the same thickness and substantially the same material as the first main electrode layer (55). Herein, "substantially the same" means that the first main electrode layer (55) and the first conductive layer (50 / 150 / 290) have the same configuration (thickness and material) by being formed through the same process (manufacturing process).

[0322] [C11] A semiconductor device (1, etc.) according to any one of C1 to C10, further comprising a second main electrode layer (75) disposed on the second insulating layer (63) at a distance from the second conductive layer (70 / 170 / 270 / 275) so as to overlap the first main electrode layer (55) in a plan view.

[0323] [C12] The semiconductor device (1, etc.) according to C11, wherein the second main electrode layer (75) is substantially the same thickness and made of substantially the same material as the second conductive layer (70 / 170 / 270 / 275). Herein, "substantially the same" means that the second main electrode layer (75) and the second conductive layer (70 / 170 / 270 / 275) have the same configuration (thickness and material) because they are formed through the same process (manufacturing process).

[0324] [C13] A semiconductor device (e.g., 1) according to C11 or C12, wherein at least one of the second conductive layer (70 / 170 / 270 / 275) and the second main electrode layer (75) is exposed to the outside so as to be electrically connected to external terminals (302d, 302g, 302s, 402).

[0325] [C14] The semiconductor device (1, etc.) according to C13, wherein at least one of the second conductive layer (70 / 170 / 270 / 275) and the second main electrode layer (75) is configured to be electrically connected to the external terminals (302d, 302g, 302s, 402) via bonding wire (303g, 303s), solder (502), or sintered metal (502).

[0326] [C15] The external terminals (302d, 302g, 302s, 402) are lead frames, as described in C13 or C14 (e.g., semiconductor device 1).

[0327] [C16] The semiconductor device (1, etc.) described in any one of C1 to C10, wherein the first main electrode layer (55) is exposed to the outside so as to be electrically connected to external terminals (302d, 302g, 302s, 402).

[0328] [C17] The semiconductor device (1, etc.) according to C16, wherein the first main electrode layer (55) is configured to be electrically connected to the external terminals (302d, 302g, 302s, 402) via bonding wires (303g, 303s), solder (502), or sintered metal (502).

[0329] [C18] The external terminals (302d, 302g, 302s, 402) are lead frames, as described in C16 or C17 (e.g., semiconductor device 1).

[0330] A semiconductor device relating to [C1] to [C18] may include at least one of the first transmission line, second transmission line, and third transmission line relating to [C4] to [C8]. In other words, in a semiconductor device, the first transmission line, second transmission line, and third transmission line may be provided individually or in combination. Specifically, a semiconductor device that includes only one of the first transmission line, second transmission line, and third transmission line may be used.

[0331] Furthermore, a semiconductor device including only two of the first, second, and third transmission lines may be used. Alternatively, a semiconductor device including all of the first, second, and third transmission lines may be used. When multiple transmission lines are provided, it is preferable that at least one transmission line has the configuration described in [C1] above. In this case, it is particularly preferable that all of the multiple transmission lines have the configuration described in [C1] above.

[0332] [D1] A semiconductor device including a vertical transistor, comprising: a semiconductor layer having a first main surface and a second main surface opposite to the first main surface, and mainly composed of SiC; a first electrode covering a part of the first main surface; a second electrode spaced apart from the first electrode in a plan view, and covering a part of the first main surface; a first electrode pad provided on the side opposite to the semiconductor layer with respect to the first electrode, with at least a part of it overlapping the first electrode in a plan view and electrically connected to the first electrode; and an electrode provided on the second main surface, wherein the first electrode pad overlaps a part of the second electrode in a plan view.

[0333] [D2] The semiconductor device according to D1, further comprising a first insulating layer located between the first electrode pad and the second electrode in a direction perpendicular to the first main surface.

[0334] [D3] The semiconductor device according to D2, wherein the side surface of the first insulating layer is a plane along a direction perpendicular to the first main surface.

[0335] [D4] The semiconductor device according to D2 or D3, further comprising a second electrode pad electrically connected to the second electrode, wherein the end of the second electrode pad on the first electrode pad side is located on the first insulating layer.

[0336] [D5] The semiconductor device according to D4, further comprising a second insulating layer covering the boundary between the first electrode pad and the second electrode pad.

[0337] [D6] The vertical transistor includes a source region formed on the first main surface side of the semiconductor layer, a gate electrode adjacent to the source region via a gate insulating film, and a drain region formed in the semiconductor layer, wherein the first electrode is electrically connected to the gate electrode and the second electrode is electrically connected to the source region, according to any one of D1 to D5.

[0338] [D7] The semiconductor device according to D6, wherein the vertical transistor has, in a plan view, a main cell region for conducting drain current and a current sensing cell region for detecting drain current, the second electrode is arranged in correspondence with the main cell region, the semiconductor device further comprises, in a plan view, a third electrode provided at a distance from the first electrode and the second electrode and arranged in correspondence with the current sensing cell region, and a third electrode pad provided on the side of the semiconductor layer opposite to the third electrode, in a plan view at least a portion of which overlaps with the third electrode and is electrically connected to the third electrode, the third electrode pad overlaps a portion of the second electrode in a plan view.

[0339] [D8] The semiconductor device according to D6 or D7, further comprising a diode provided on an insulating layer covering a part of the first main surface, an anode electrode pad electrically connected to the p-type semiconductor layer of the diode, and a cathode electrode pad electrically connected to the n-type semiconductor layer of the diode, wherein at least one of the anode electrode pad and the cathode electrode pad overlaps a part of the second electrode in a plan view.

[0340] [D9] A method for manufacturing a semiconductor device including a vertical transistor, comprising: a first step of forming a first electrode and a second electrode, which are spaced apart from each other, on a semiconductor layer having a first main surface and a second main surface opposite to the first main surface, and covering a part of the first main surface of the semiconductor layer mainly composed of SiC; and a second step of forming a first electrode pad electrically connected to the first electrode on the side opposite to the semiconductor layer of the first electrode, such that in a plan view at least a part of the first electrode pad overlaps the first electrode, wherein in a plan view the first electrode pad overlaps a part of the second electrode.

[0341] [E1] A semiconductor device comprising: a semiconductor layer having a first main surface having an active region and an inactive region, and a second main surface opposite to the first main surface, and mainly composed of SiC; a first insulating layer formed on the first main surface; a first main electrode layer formed on the first insulating layer and in a region corresponding to the active region; a first conductive layer formed on the first insulating layer, electrically separated from the first main electrode layer and in a region corresponding to the inactive region; a second insulating layer formed on the first main electrode layer and the first conductive layer; a second conductive layer formed on the second insulating layer, electrically connected to the first conductive layer and electrically separated from the first main electrode layer, and in a region in which a part overlaps with the first main electrode layer in the thickness direction of the semiconductor layer; and an electrode formed on the second main surface.

[0342] [E2] The semiconductor device includes an insulated gate-driven switching element, which is a MOSFET or IGBT, and the first and second conductive layers constitute a transmission path for control signals used to control the insulated gate-driven switching element.

[0343] [E3] That is, the first conductive layer and the second conductive layer may be connected to the gate electrode of the switching element to constitute a first transmission path, which is a transmission path for a gate voltage control signal.

[0344] [E4] In addition, the first conductive layer and the second conductive layer may be connected to the source electrode (emitter electrode) of the current sensing element to form a second transmission path, which is a transmission path for a detection signal for detecting the current flowing through the semiconductor device.

[0345] [E5] In addition, the first conductive layer and the second conductive layer may be connected to the electrodes of a diode for temperature detection of the semiconductor device to constitute a third transmission path, which is a transmission path for a detection signal for detecting the temperature of the semiconductor device.

[0346] [E6] The first, second, and third transmission lines may be provided individually or in combination in the semiconductor device.

[0347] [E7] Specifically, the configuration may include only the first transmission line, or it may include the first transmission line plus a second or third transmission line, or it may be a semiconductor device that includes the first, second, and third transmission lines.

[0348] [E8] When multiple transmission lines are provided, it is preferable that all of the transmission lines satisfy the above-mentioned configuration, but it is also acceptable for at least one transmission line to satisfy the above-mentioned configuration.

[0349] [E9] The first main electrode layer and the first conductive layer may be made of substantially the same thickness and material. "Substantially the same" means that the first main electrode layer and the first conductive layer have the same composition as a result of being formed by the same process.

[0350] [E10] Alternatively, a second main electrode layer may be formed so as to overlap the first main electrode layer.

[0351] [E11] In this case, the second main electrode layer and the second conductive layer may be made of substantially the same thickness and material.

[0352] [E12] The second conductive layer and the second main electrode layer are exposed on the surface of the semiconductor device and are used for connection to the corresponding external terminals.

[0353] [E13] If the second main electrode layer is not provided, the first main electrode layer is exposed on the surface of the semiconductor device and may be used for connection to external terminals.

[0354] [E14] The second conductive layer and the second main electrode layer are bonded to the corresponding external terminals such as lead frames by wire bonding, but the second conductive layer and the second main electrode layer may also be joined to the external terminals by solder or sintered metal.

[0355] [E15] The bond between the second conductive layer and the external terminal may be formed by wire bonding, and the bond between the second main electrode layer and the external terminal may be formed by solder or sintered metal.

[0356] Although semiconductor devices and methods for manufacturing semiconductor devices according to one or more embodiments have been described above based on embodiments, the present invention is not limited to these embodiments. Various modifications, substitutions, additions, omissions, etc., can be made to each of the above embodiments within the scope of the claims or equivalents. As long as they do not depart from the spirit of the present invention, forms in which various modifications that can be conceived by those skilled in the art are applied to each embodiment, and combinations of various components in different embodiments are also included within the scope of the present invention. The present invention has industrial applicability and can be used in semiconductor devices and semiconductor packages, etc. [Explanation of Symbols]

[0357] 1 Semiconductor device 2 Vertical Transistors 3 Active Area 4. Inactive areas 10 Semiconductor layer 11. First Main Surface 12 Second Main Surface 13 Semiconductor substrates 14 Epitaxial layer 17 Source Area 20 gates 23 Gate Insulation Layer 40 Drain electrode 50 Main surface gate electrode 55 Main surface source electrode 63 Upper insulating layer 66 Protective insulating layer 70 Gate Pad 75 Sourcepad 80 Boundary 101 Semiconductor Equipment 101a Semiconductor 103 Active Area 104 Inactive Area 150 Current sensing electrodes 170 Current-Sensing Pads 201 Semiconductor Equipment 201a Semiconductor 201b Semiconductor equipment 203 Active Area 204 Inactive Area 260 Insulating layer 270 Anode Electrode Pads 275 Cathode Electrode Pads 290 diodes 291 p-type semiconductor layer 292 n-type semiconductor layer 302d terminal 302g terminal 302s terminal 402 terminal 303g bonding wire 303s bonding wire 501 Semiconductor Equipment 502 Bonding material

Claims

1. A semiconductor layer having a main surface, A switching element formed on the semiconductor layer, A first electrode is placed on the main surface and electrically connected to the switching element, A second electrode is positioned on the main surface at a distance from the first electrode and electrically connected to the switching element, A first terminal electrode has a portion that overlaps with the first electrode and a portion that overlaps with the second electrode in a plan view, and is electrically connected to the first electrode, A semiconductor device comprising a second terminal electrode having a portion that overlaps with the second electrode in a plan view and being electrically connected to the second electrode.

2. The semiconductor device according to claim 1, wherein the semiconductor layer includes SiC.

3. The semiconductor device according to claim 1 or 2, wherein the first terminal electrode is connected to the first electrode over a first area and has an electrode surface exceeding the first area.

4. The semiconductor device according to any one of claims 1 to 3, wherein the second terminal electrode has an area greater than or equal to that of the first terminal electrode in a plan view.

5. The semiconductor device according to any one of claims 1 to 4, wherein the first terminal electrode intersects at least a portion of the first electrode in a plan view.

6. The semiconductor device according to any one of claims 1 to 5, wherein the second terminal electrode has a portion that overlaps with the first electrode in a plan view.

7. The first electrode is a control electrode that transmits the control signal of the switching element, The semiconductor device according to any one of claims 1 to 6, wherein the second electrode is a non-controlled electrode.

8. The switching element includes a gate and a source, The first electrode is electrically connected to the gate, The semiconductor device according to any one of claims 1 to 7, wherein the second electrode is electrically connected to the source.

9. The first insulator further comprises covering the second electrode, The first terminal electrode has a portion that faces the second electrode with the first insulator in between, The semiconductor device according to any one of claims 1 to 8, wherein the second terminal electrode has a portion that faces the second electrode with the first insulator in between.

10. The first terminal electrode has a side surface positioned above the second electrode so as to face the second electrode with the first insulator in between, The semiconductor device according to claim 9, wherein the second terminal electrode is positioned above the second electrode so as to face the first insulator across it, and has a side surface that forms a gap between it and the side surface of the first terminal electrode, exposing the first insulator.

11. The semiconductor device according to claim 10, further comprising a second insulator that covers the first insulator within the gap and faces the second electrode with the first insulator in between.

12. The first insulator covers the first electrode, The first terminal electrode has a portion that faces the first electrode across the first insulator, The semiconductor device according to any one of claims 9 to 11, wherein the second terminal electrode has a portion that faces the first electrode across the first insulator.

13. An active region provided in the semiconductor layer, The semiconductor layer further includes an inactive region provided in a region outside the active region, The switching element is formed in the active region, The first electrode is positioned in a region that overlaps with the inactive region in a plan view. The second electrode is positioned in a region that overlaps with the active region in a plan view. The first terminal electrode is positioned in a region that overlaps the active region and the inactive region in a plan view. The semiconductor device according to any one of claims 1 to 12, wherein the second terminal electrode is arranged in a region that overlaps with the active region in a plan view.

14. The active region includes the main cell region provided in the semiconductor layer, The inactive region includes a sense cell region provided in the semiconductor layer in a region different from the main cell region. The semiconductor device according to claim 13, wherein the switching element includes a main switching element formed in the main cell region to generate a main current, and a sense switching element formed in the sense cell region to generate a monitor current for detecting the main current.

15. The first electrode is electrically connected to the main switching element, The second electrode is positioned in a region that overlaps with the main cell region in a plan view, and is electrically connected to the main switching element. The first terminal electrode is positioned in a region that overlaps the main cell region and the inactive region in a plan view. The semiconductor device according to claim 14, wherein the second terminal electrode is arranged in a region that overlaps with the main cell region in a plan view.

16. The semiconductor device according to claim 14 or 15, wherein the first electrode is electrically connected to the sense switching element.

17. A third electrode is positioned in a region overlapping the sense cell region, spaced apart from the first and second electrodes in a plan view, and electrically connected to the sense switching element. The semiconductor device according to any one of claims 14 to 16, further comprising a third terminal electrode having a portion that overlaps with the third electrode in a plan view and being electrically connected to the third electrode.

18. A diode formed in the inactive region, A semiconductor device according to any one of claims 13 to 17, further comprising a polarity terminal electrode having a portion that overlaps with the diode in a plan view and being electrically connected to the diode.

19. A semiconductor layer having a main surface, A main element formed in the semiconductor layer and generating a main current, A sense element formed in a region different from the main element in the semiconductor layer, which generates a monitor current to monitor the main current, A first electrode is placed on the main surface and electrically connected to the main element, A second electrode is positioned on the main surface at a distance from the first electrode and electrically connected to the main element, A third electrode is positioned on the main surface at a distance from the first and second electrodes and electrically connected to the sense element, A first terminal electrode electrically connected to the first electrode is located on the first electrode, A second terminal electrode electrically connected to the second electrode is located on the second electrode, A semiconductor device comprising a third terminal electrode having a portion that overlaps with the third electrode and a portion that overlaps with the second electrode in a plan view, and which is electrically connected to the third electrode.

20. A semiconductor layer having a main surface, A switching element formed on the semiconductor layer, A diode formed in a region different from the switching element in the semiconductor layer, A first electrode is placed on the main surface and electrically connected to the switching element, A second electrode is positioned on the main surface at a distance from the first electrode and electrically connected to the switching element, A first terminal electrode electrically connected to the first electrode is located on the first electrode, A second terminal electrode electrically connected to the second electrode is located on the second electrode, A semiconductor device comprising a polarity terminal electrode having a portion that overlaps with the diode in a plan view and a portion that overlaps with the second electrode, and which is electrically connected to the diode.

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