Processing methods

Abstract

To provide a processing method that can suppress the peeling of the filler material. [Solution] The processing method comprises a stacking step 102 in which a plurality of chips are stacked on a substrate to form a stacked wafer, a filling step 103 in which the spaces between the stacked chips on the substrate are filled with a filler, a chip processing step in which at least an inclined portion is formed on the side surface of the chip before the filling step 103 is performed, and a chip forming step 101 in which the wafer is divided along a planned division line to form a plurality of chips before the stacking step 102 is performed, wherein the chip forming step 101 also serves as the chip processing step.

Description

Technical Field

[0001] The present invention relates to a processing method for laminating a plurality of chips on a substrate.

Background Art

[0002] After forming a stacked wafer in which a plurality of device chips are stacked on a wafer, the stacked chips are manufactured by dividing the stacked wafer (see, for example, Patent Document 1). <>

[0003] In the method disclosed in Patent Document 1, before further stacking another device chip on the stacked device chips, the spaces between the device chips of the stacked wafer are filled with a filler. Generally, an oxide film is used as the filler, which fills the spaces between the device chips and covers the exposed surfaces of the device chips.

[0004] Then, thereafter, the upper surface of the oxide film is planarized or grinding is performed to reduce the thickness of the device chips.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, in the method disclosed in Patent Document 1, the filler may be peeled off from the side surfaces of the chips due to grinding, and improvement is eagerly desired.

[0007] An object of the present invention is to provide a processing method capable of suppressing the peeling of the filler.

Means for Solving the Problems

[0008] To solve the above-mentioned problems and achieve the objective, the processing method of the present invention is characterized by comprising: a stacking step of stacking a plurality of chips on a substrate to form a stacked wafer; a filling step of filling the spaces between the stacked chips on the substrate with a filler material; and a chip processing step of forming inclined portions on at least the sides of the chips before performing the filling step.

[0009] In the above-described processing method, before performing the stacking step, a chip forming step is provided in which the wafer is divided along a planned division line to form a plurality of chips, and the chip forming step includes cutting along the planned division line with a cutting blade having a tapered shape at the leading edge of the cross section to form an inclined portion on the side surface of the chip, and the chip forming step may also serve as the chip processing step.

[0010] The above processing method includes a chip formation step in which, before performing the stacking step, the wafer is divided along a planned division line to form a plurality of chips, and the chip formation step includes plasma etching along the planned division line of the wafer to form an inclined portion on the side surface of the chip, and the chip formation step may also serve as the chip processing step.

[0011] In the above processing method, the chip processing step may be performed after the stacking step and before the filling step, by cutting a plurality of the chips of the stacked wafer with a cutting blade having a tapered cross-sectional tip to form inclined portions on the sides of the chips.

[0012] The above processing method may include a filling step in which the spaces between the chips are filled with a filler and the exposed surfaces of the chips are covered with the filler, and a planaring step in which the filler of the laminated wafer is planar after the filling step has been performed. [Effects of the Invention]

[0013] This invention has the effect of suppressing the peeling of the filler material. [Brief explanation of the drawing]

[0014] [Figure 1] Figure 1 is a flowchart showing the flow of the processing method according to Embodiment 1. [Figure 2] Figure 2 is a schematic perspective view showing the wafer being divided into chips in the chip formation step of the processing method shown in Figure 1. [Figure 3] Figure 3 is a schematic side view showing a partial cross-section of the wafer being divided during the chip formation step of the processing method shown in Figure 1. [Figure 4] Figure 4 is a schematic cross-sectional view showing a chip formed in the chip formation step of the processing method shown in Figure 1. [Figure 5] Figure 5 is a schematic cross-sectional view showing the stacked wafer after the stacking step of the processing method shown in Figure 1. [Figure 6] Figure 6 is a schematic cross-sectional view showing the filling step of the processing method shown in Figure 1. [Figure 7] Figure 7 is a schematic side view showing a partial cross-section of the planarization step of the processing method shown in Figure 1. [Figure 8] Figure 8 is a schematic cross-sectional view showing the state in which a protective film is applied to the surface of a wafer during the chip formation step of the processing method according to Embodiment 2. [Figure 9] Figure 9 is a schematic cross-sectional view showing the state in which a laser beam is irradiated onto a protective film covering the surface of a wafer during the chip formation step of the processing method according to Embodiment 2. [Figure 10] Figure 10 is a schematic cross-sectional view showing the main part of the wafer surface in the chip formation step of the processing method according to Embodiment 2. [Figure 11] Figure 11 is a schematic cross-sectional view showing the state in which a wafer with a protective film formed on its surface is being plasma-etched during the chip formation step of the processing method according to Embodiment 2. [Figure 12]FIG. 12 is a cross-sectional view schematically showing a state in which a wafer is divided into chips in the chip formation step of the processing method according to Embodiment 2. [Figure 13] FIG. 13 is a cross-sectional view schematically showing a state in which a protective film is removed in the chip formation step of the processing method according to Embodiment 2. [Figure 14] FIG. 14 is a flowchart showing the flow of the processing method according to Embodiment 3. [Figure 15] FIG. 15 is a cross-sectional view schematically showing a stacked wafer after the stacking step of the processing method shown in FIG. 14. [Figure 16] FIG. 16 is a cross-sectional view of a main part of a stacked wafer schematically showing the chip processing step of the processing method shown in FIG. 14.

Mode for Carrying Out the Invention

[0015] The mode (embodiment) for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited by the content described in the following embodiments. Further, the constituent elements described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Furthermore, the configurations described below can be combined as appropriate. Also, various omissions, substitutions, or changes in the configuration can be made without departing from the gist of the present invention.

[0016] 〔Embodiment 1〕 The processing method according to Embodiment 1 of the present invention will be described based on the drawings. FIG. 1 is a flowchart showing the flow of the processing method according to Embodiment 1.

[0017] As shown in FIG. 1, the processing method according to Embodiment 1 includes a chip formation step 101, a stacking step 102, a filling step 103, and a planarization step 104.

[0018] (Chip Formation Step) Figure 2 is a schematic perspective view showing a wafer being divided into chips in the chip formation step of the processing method shown in Figure 1. Figure 3 is a schematic side view showing a partial cross-section of the wafer being divided in the chip formation step of the processing method shown in Figure 1. Figure 4 is a schematic cross-sectional view showing a chip formed in the chip formation step of the processing method shown in Figure 1.

[0019] The chip formation step 101 is a step in which, before performing the stacking step 102, the wafer 1 shown in Figure 2 is divided along the planned division line 4 to form multiple chips 10. In the chip formation step 101, the wafer 1 to be divided into chips 10 is, as shown in Figure 2, a disc-shaped semiconductor wafer or an optical device wafer, for example, with silicon, sapphire, gallium, or SiC as the base material 2.

[0020] As shown in Figure 2, wafer 1 is divided into a grid-like region by multiple intersecting division lines 4 on its surface 3, with devices 5 formed in each region. Devices 5 are, for example, integrated circuits such as ICs (Integrated Circuits) or LSIs (Large Scale Integrations), or memory (semiconductor memory devices). Wafer 1 is divided into individual chips 10 along the division lines 4. In the following description, the same reference numerals are used for the same parts of wafer 1 and chip 10.

[0021] In Embodiment 1, in the chip formation step 101, a disc-shaped adhesive tape 20 with a diameter larger than the outer diameter of the wafer 1 is attached to the surface 3 of the wafer 1, and an annular frame 21 with an inner diameter larger than the wafer 1 is attached to the outer edge of the adhesive tape 20. In Embodiment 1, in the chip formation step 101, the cutting device 30 holds the surface 3 side of the wafer 1 to the holding surface 32 of the chuck table 31 by suction via the adhesive tape 20, and clamps the frame 21 with the clamping part 33.

[0022] In Embodiment 1, in the chip formation step 101, the cutting device 30, as shown in Figure 3, moves the wafer 1 relative to the tapered portion 36 of the cutting blade 34, which has a mountain-shaped cross-section, as well as the cutting edge 35 of the cutting blade 34, which has a tapered cross-section, as shown in Figure 3, and cuts the wafer 1 by cutting the tapered portion 36 of the cutting blade 34 into the tapered portion 36 of the cutting edge 35 of the wafer 1 until it reaches the adhesive tape 20. In Embodiment 1, in the chip formation step 101, the wafer 1 is cut along the tapered portion 36 of the cutting edge 35 of the cutting blade 34, which has a tapered cross-section, as shown in Figure 3.

[0023] In Embodiment 1, in the chip formation step 101, the cutting apparatus 30 cuts along all the planned division lines 4 of the wafer 1 to divide the wafer 1 into individual chips 10 (shown in Figure 4). In Embodiment 1, in the chip formation step 101, the wafer 1 is cut along the planned division lines 4 to form an inclined portion 12 on the side surface 11 of the chip 10, as shown in Figure 4. The side surface 11 of the chip 10 is the surface that connects the outer edge of the surface 3 and the outer edge of the back surface 6 on the back side of the surface 3. Furthermore, the inclined portion 12 is inclined with respect to both the surface 3 and the back surface 6, and to a surface perpendicular to both the surface 3 and the back surface 6, so that the planar shape of the chip 10 gradually shrinks as it approaches the back surface 6.

[0024] Thus, in Embodiment 1, the chip formation step 101 also serves as a chip processing step that forms an inclined portion 12 on at least the side surface 11 of the chip 10 before performing the filling step 103.

[0025] (Lamination step) Figure 5 is a schematic cross-sectional view showing a laminated wafer after the lamination step of the processing method shown in Figure 1. Lamination step 102 is a step in which a plurality of chips 10 are stacked on a substrate 22 to form a laminated wafer 23.

[0026] In Embodiment 1, in the lamination step 102, as shown in Figure 5, the device 5 side of the chip 10 formed in the chip formation step 101 is laminated onto the substrate 22. In Embodiment 1, the substrate 22 has the same configuration as the wafer 1 shown in Figure 2. Therefore, the same reference numerals are used to denote the same parts of the substrate 22 as those of the wafer 1.

[0027] In Embodiment 1, in the lamination step 102, as shown in Figure 5, the device 5 of the chip 10 is laminated onto the device 5 of the substrate 22, and the devices 5, 5 are directly bonded to each other. In addition, in the lamination step 102, the substrate 22 may be a disc-shaped support wafer having the same outer diameter as the wafer 1 on which the device 5 is not formed.

[0028] Furthermore, in the lamination step 102, the present invention may involve laminating the chip 10 onto the device 5 of the substrate 22 and directly bonding the devices 5, 5 together. Alternatively, the chip 10 may be directly bonded to the substrate 22 in a orientation where the back surface 6 of the chip 10 abuts against the device 5 of the substrate 22. In this case, an inclined portion may be formed on the back surface 6 of the chip 10 such that its planar shape is larger than that of the front surface 3.

[0029] Thus, in the lamination step 102, inclined portions 12 are formed on the side surfaces 11 of the chips 10 such that the spacing between the chips 10 stacked on the substrate 22 gradually narrows as it approaches the substrate 22. Furthermore, in Embodiment 1, the stacked wafer 23 formed in the lamination step 102 is a so-called COW (Chip On Wafer) in which the chips 10 are stacked on the surface 3 of the substrate 22.

[0030] (Filling step) Figure 6 is a schematic cross-sectional view showing the filling step of the processing method shown in Figure 1. The filling step 103 is a step in which the spaces between the chips 10 stacked on the substrate 22 are filled with an oxide film 24, which is a filler material.

[0031] In Embodiment 1, in the filling step 103, an oxide film 24, which is a filler, is formed on the surface 3 side of the substrate 22 on the chip 10 side of the stacked wafer 23, thereby filling the spaces between the chips 10 with the oxide film 24 and stacking the oxide film 24 on the chips 10 (back surface 6 in Embodiment 1). In Embodiment 1, in the filling step 103, for example, the oxide film 24 is formed on the surface 3 side of the substrate 22 of the stacked wafer 23 by CVD (Chemical Vapor Deposition).

[0032] In Embodiment 1, as shown in Figure 6, in the filling step 103, the spaces between the chips 10 of the stacked wafer 23 are filled with an oxide film 24, which is a filler material, and the exposed surface of the chip 10 on the substrate 22 (exposed surface) is covered with the oxide film 24. In Embodiment 1, in the filling step 103, since an inclined portion 12 is formed on the side surface 11 of the chip 10, vaporized gas of CVD can easily enter between the chips 10, and for example, even if the thickness of the chip 10 is thick, it is possible to prevent the formation of areas where no film has been deposited.

[0033] In Embodiment 1, in the filling step 103, an oxide film 24 is formed in order to further stack chips 10 on the aforementioned COW stacked wafer 23. As shown in Figure 6, irregularities occur between the oxide film 24 formed on the chips 10 and the oxide film 24 formed between the chips.

[0034] (Flattening step) Figure 7 is a schematic side view showing a partial cross-section of the planarization step of the processing method shown in Figure 1. The planarization step 104 is a step in which the surface of the oxide film 24 of the stacked wafer 23 is planarized after the filling step 103 has been performed.

[0035] In Embodiment 1, in the planarization step 104, the grinding apparatus 40 shown in Figure 7 holds the back surface 6 side of the substrate 22 of the stacked wafer 23 by suction to the holding surface 42 of the holding table 41. In Embodiment 1, in the planarization step 104, as shown in Figure 7, the grinding apparatus 40 rotates the grinding wheel 43 around its axis with the spindle 45 and rotates the holding table 41 around its axis while supplying grinding water, and brings the grinding wheel 44 into contact with the surface of the oxide film 24 of the stacked wafer 23 and brings it close to the holding table 41 at a predetermined feed rate, thereby grinding the surface of the oxide film 24 of the stacked wafer 23 with the grinding wheel 44 and planarizing the surface of the oxide film 24 of the stacked wafer 23.

[0036] In Embodiment 1, in the planarization step 104, in addition to planarizing only the oxide film 24, the oxide film 24 covering the chip 10 may be removed, or the chip 10 may be thinned to the finishing thickness. Furthermore, in the planarization step 104, the oxide film 24 of the stacked wafer 23 may be polished instead of being ground. Furthermore, in the planarization step 104, the oxide film 24 of the stacked wafer 23 may be ground and then polished. Furthermore, in the planarization step 104, only a portion of the oxide film 24 may be planarized, leaving a residual portion of the oxide film 24.

[0037] Conventionally, when grinding the surface 3 of the oxide film 24 filling the space between the chips 10, peeling of the oxide film 24 occurred during grinding. In contrast, the processing method according to Embodiment 1 forms an inclined portion 12 on the side surface 11 of the chip 10, increasing the adhesion area between the oxide film 24 and the chip 10 compared to when the side surface 11 is perpendicular to the surface 3 and back surface 6. Therefore, peeling of the oxide film 24 during the planarization step 104 can be suppressed.

[0038] As a result, the processing method according to Embodiment 1 has the effect of suppressing the peeling of the oxide film 24, which is a filler, because it includes a chip forming step 101 in which an inclined portion 12 is formed on the side surface 11 of the chip 10.

[0039] Furthermore, the processing method according to Embodiment 1 includes a chip forming step 101 in which an inclined portion 12 is formed on the side surface 11 of the chip 10. As a result, the cross-sectional shape of the outer edge of the chip 10 becomes obtuse on the back surface 6 side of the chip 10, making it less likely for the outer edge of the chip 10 to chip during grinding.

[0040] [Embodiment 2] Next, a processing method according to Embodiment 2 will be described. Figure 8 is a schematic cross-sectional view showing the state in which a protective film is coated on the surface of the wafer during the chip formation step of the processing method according to Embodiment 2. Figure 9 is a schematic cross-sectional view showing the state in which a laser beam is irradiated onto the protective film covering the surface of the wafer during the chip formation step of the processing method according to Embodiment 2. Figure 10 is a schematic cross-sectional view showing the main part of the state in which a mask is formed on the surface of the wafer during the chip formation step of the processing method according to Embodiment 2. Figure 11 is a schematic cross-sectional view showing the state in which a wafer with a protective film formed on its surface is being plasma-etched during the chip formation step of the processing method according to Embodiment 2. Figure 12 is a schematic cross-sectional view showing the state in which the wafer has been divided into chips during the chip formation step of the processing method according to Embodiment 2. Figure 13 is a schematic cross-sectional view showing the state in which the protective film has been removed during the chip formation step of the processing method according to Embodiment 2.

[0041] Note that in Figures 8, 9, 10, 11, 12, and 13, the same reference numerals are used for the same parts as in Embodiment 1, and their descriptions are omitted. The processing method according to Embodiment 2 is the same as in Embodiment 1, except that the chip formation step 101 is different.

[0042] The processing method according to Embodiment 2 is the same as that of Embodiment 1, except that the chip formation step 101 is different. In Embodiment 2, in the chip formation step 101, the back surface 6 of the wafer 1 is held by suction on the holding surface of a spinner table (not shown), and a liquid protective film agent is applied to the surface 3 of the wafer 1 from a coating nozzle (not shown) while the spinner table is rotated around its axis. The protective film agent applied to the surface 3 of the wafer 1 is then spread outwards towards the outer edge of the wafer 1 by the centrifugal force generated by the rotation of the spinner table, covering the entire surface 3 of the wafer 1, and gradually dries as it is exposed to the atmosphere by the rotation of the spinner table.

[0043] In Embodiment 2, the protective film agent includes, for example, a water-soluble resin such as polyvinyl alcohol (PVA) or polyvinylpyrrolidone (PVP). In Embodiment 1, the protective film material is resistant to plasma-induced etching gas. Thus, in Embodiment 2, in the chip formation step 101, the protective film agent covering the entire surface 3 of the wafer 1 is dried to cover the entire surface 3 of the wafer 1 with a protective film 25 made of a water-soluble resin, as shown in Figure 8.

[0044] In Embodiment 2, in the chip formation step 101, the laser processing apparatus 50 shown in Figure 9 holds the back surface 6 of the wafer 1 by suction to the holding surface 52 of the chuck table 51, and as shown in Figure 9, moves the chuck table 51 and the laser beam irradiation unit 53 relative to each other along the division line 4, while the oscillator 54 oscillates and irradiates the protective film 25 on each division line 4 with a laser beam 55 of a wavelength that is absorbed by the protective film 25 through the focusing lens 56, thereby removing the protective film 25 on each division line 4. In Embodiment 2, in the chip formation step 101, as shown in Figure 10, the laser processing apparatus 50 forms an opening 26 along the division line 4 over the entire length of each division line 4, and forms the protective film 25 on the mask 27 on which the opening 26 is formed.

[0045] The opening 26 exposes the surface 3 of the division line 4 at its bottom. In this invention, instead of a water-soluble resin, a resist film used in etching may be exposed to form the mask 27.

[0046] In Embodiment 2, in the chip formation step 101, an etching apparatus (not shown) adsorbs and holds the back side 6 of the wafer 1 to the holding surface of an electrostatic chuck in a vacuum chamber. In Embodiment 2, in the chip formation step 101, an etching apparatus (not shown) reduces the pressure inside the vacuum chamber and supplies plasma-formed etching gas into the vacuum chamber while applying high-frequency power to attract ions to the electrostatic chuck.

[0047] In Embodiment 2, in the chip formation step 101, an etching apparatus (not shown) supplies, for example, plasma-formed SF6 into a vacuum chamber at a predetermined flow rate to form etching grooves 7 on the surface 3 of the division line 4 exposed from the opening 26 of the mask 27, as shown in Figure 11. This etching step alternately repeats the following steps: an etching step in which plasma-formed C4F8 into a vacuum chamber at a predetermined flow rate to deposit a protective film (fluorocarbon film) on the inner wall of the etching grooves 7. This Bosch method is used to plasma etch the wafer 1 and form etching grooves 7 from the surface 3 side of the division line 4 of the wafer 1.

[0048] Furthermore, in Embodiment 2, in the chip formation step 101, when an etching apparatus (not shown) alternately repeats the etching step and the protective film deposition step, the time spent performing the protective film deposition step is kept constant, but the time spent performing the etching step is gradually increased. For this purpose, in Embodiment 2, in the chip formation step 101, the etching apparatus (not shown) gradually widens the etching groove 7 as it approaches the back surface 6. Also, in Embodiment 2, in the chip formation step 101, the etching apparatus (not shown) plasma etches the wafer 1 using the Bosch method, so a step 8 is formed on the inner wall of the etching groove 7 that occurs when performing the etching step and the protective film deposition step.

[0049] In Embodiment 2, in the chip formation step 101, an etching apparatus (not shown) moves the etching groove 7 to the back surface 6 of the wafer 1, as shown in Figure 12, and alternately repeats the etching step and the protective film deposition step until the wafer 1 is divided into individual chips 10. In Embodiment 2, in the chip formation step 101, as shown in Figure 12, when the etching groove 7 reaches the back surface 6 of the wafer 1, the wafer 1, i.e., the chip 10, is removed from the vacuum chamber of the etching apparatus, and the surface 3 of the wafer 1 is washed with cleaning water such as pure water to remove the mask 27 from the surface 3 of the wafer 1, i.e., the chip 10, as shown in Figure 13.

[0050] Thus, in Embodiment 2, the chip formation step 101 performs plasma etching along the planned division line 4 of the wafer 1 to divide the wafer 1 into chips 10, and forms inclined portions 12 (including multiple steps 8 in Embodiment 2) on the side surface 11 of the chips 10. In Embodiment 2, the chip formation step 101 also serves as a chip processing step that forms inclined portions 12 on at least the side surface 11 of the chips 10 before performing the filling step 103, similar to Embodiment 1.

[0051] The processing method according to Embodiment 2 involves forming an inclined portion 12 on the side surface 11 of the chip 10, thereby increasing the bonding area between the oxide film 24 and the chip 10, similar to Embodiment 1. This has the effect of suppressing peeling of the oxide film 24 during the planarization step 104.

[0052] [Embodiment 3] Next, the processing method according to Embodiment 3 will be described. Figure 14 is a flowchart showing the flow of the processing method according to Embodiment 3. Figure 15 is a schematic cross-sectional view showing the stacked wafer after the stacking step of the processing method shown in Figure 14. Figure 16 is a schematic cross-sectional view of the main part of the stacked wafer showing the chip processing step of the processing method shown in Figure 14.

[0053] Note that in Figures 14, 15, and 16, the same reference numerals are used for the same parts as in Embodiment 1, and their descriptions are omitted. The processing method according to Embodiment 3, as shown in Figure 14, comprises a chip formation step 101-3, a lamination step 102, a chip processing step 105, a filling step 103, and a planarization step 104, and is the same as Embodiment 1 except that the chip formation step 101-3, the lamination step 102, and the chip processing step 105 are performed in order before the filling step 103 and the planarization step 104.

[0054] In Embodiment 3, the chip formation step 101-3 is a step in which the wafer 1 is divided along the division line 4 to form a plurality of chips 10-3 (shown in Figure 15) before performing the stacking step 102. In Embodiment 3, in the chip formation step 101-3, the wafer 1 is divided into individual chips 10-3 by cutting along the division line 4 with a cutting blade of constant thickness. In Embodiment 3, after the chip formation step 101, the side surface 11 of the chip 10-3 is perpendicular to the front surface 3 and back surface 6.

[0055] The lamination step 102 is a step in which a plurality of chips 10-3 are stacked on a substrate 22 to form a laminated wafer 23, similar to Embodiment 1. In Embodiment 3, in the lamination step 102, similar to Embodiment 1, as shown in Figure 15, the devices 5 of the chips 10-3 are stacked on the devices 5 of the substrate 22 and the devices 5, 5 are directly bonded to each other to form a laminated wafer 23.

[0056] The chip processing step 105 is a step in which an inclined portion 12 is formed on at least the side surface 11 of the chip 10 before the filling step 103 is performed, and in Embodiment 3, it is performed after the lamination step 102 and before the filling step 103 is performed.

[0057] In Embodiment 3, in the chip processing step 105, the cutting apparatus 30 shown in Figure 16 holds the back surface 6 side of the substrate 22 of the stacked wafer 23 by suction to the holding surface 32 of the chuck table 31. As shown in Figure 16, the thickness of the outer edge of the cutting blade 34 is gradually formed to become thinner towards the outer edge, and the tapered portion 36 with a mountain-shaped cross-section is moved relative to the wafer 1 along the planned division line 4. The tapered portion 36 of the cutting blade 34 cuts into the corner on the back surface 6 side of the chip 10-3 of the stacked wafer 23, chamfering the corner on the back surface 6 side of the chip 10-3 and forming an inclined portion 12 on the side surface 11.

[0058] In Embodiment 3, in the chip processing step 105, the cutting device 30 chamfers the corners on the back surface 6 side of all the chips 10-3 on the stacked wafer 23. In this way, in Embodiment 3, the chip processing step 105 cuts the corners on the back surface 6 side of multiple chips 10-3 on the stacked wafer 23 with the tapered portion 36 of the cutting edge 35 of the cutting blade 34, which has a tapered shape at the tip of its cross-section, thereby forming an inclined portion 12 on the side surface 11 of the chip 10-3.

[0059] The processing method according to Embodiment 3 involves forming an inclined portion 12 on the side surface 11 of the chip 10-3, thereby increasing the bonding area between the oxide film 24 and the chip 10-3, similar to Embodiment 1. This has the effect of suppressing peeling of the oxide film 24 during the planarization step 104.

[0060] It should be noted that the present invention is not limited to the embodiments described above. That is, it can be implemented with various modifications without departing from the core principles of the present invention. [Explanation of Symbols]

[0061] 1 wafer 4 planned division lines 10,10-3 tip 11 Side view 12 Slope 22 circuit boards 23. Multilayer wafer 24. Oxide film (filler) 34 cutting blades 101, 101-3 Chip formation step (chip processing step) 102 Lamination Step 103 Filling step 104 Flattening step 105 Chip machining steps

Claims

1. A stacking step in which multiple chips are stacked on a substrate to form a stacked wafer, A filling step in which the spaces between the chips stacked on the substrate are filled with a filler material, A machining method comprising a chip machining step of forming an inclined portion on at least the side surface of the chip before performing the filling step.

2. Prior to performing the stacking step, the process includes a chip forming step in which the wafer is divided along a planned division line to form a plurality of chips. The machining method according to claim 1, wherein the chip forming step includes cutting along the planned division line with a cutting blade having a tapered cross-section at the leading edge to form an inclined portion on the side surface of the chip, and the chip forming step also serves as the chip machining step.

3. Prior to performing the stacking step, the process includes a chip forming step in which the wafer is divided along a planned division line to form a plurality of chips. The processing method according to claim 1, wherein the chip formation step includes plasma etching along the planned division line of the wafer to form an inclined portion on the side surface of the chip, and the chip formation step also serves as the chip processing step.

4. The chip processing step is performed after the lamination step and before the filling step. The processing method according to claim 1, wherein a cutting blade having a tapered cross-section at the leading edge cuts a plurality of the chips of the stacked wafer to form an inclined portion on the side surface of the chips.

5. In the filling step, the space between the chips is filled with filler and the exposed surface of the chips is covered with filler. A processing method according to any one of claims 1 to 4, comprising a planarization step of planarizing the filler material of the stacked wafer after performing the filling step.

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